summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2021-04-08pinctrl: ti: fix error return code of ti_iodelay_dt_node_to_map()Junlin Yang
when devm_kcalloc fails, use -ENOMEM instead of -EINVAL, and consistent with other devm_kcalloc return values. Signed-off-by: Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210330062655.1027-1-angkery@163.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-08pinctrl: rockchip: add support for rk3568Jianqun Xu
RK3568 SoCs have 5 gpio controllers, each gpio has 32 pins. GPIO supports set iomux, pull, drive strength and schmitt. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210319081441.368358-1-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-08pinctrl: stm32: Print invalid AF warning inside stm32_pctrl_is_function_valid()Marek Vasut
The "invalid function %d on pin %d .\n" message is triplicated in the driver in different variants, just pull it into the function and have it once in the driver. The bonus is that all variants of the message now print the pin number and AF consistently, so it is easier to debug such pinmux problems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabien Dessenne <fabien.dessenne@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Acked-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20210406180035.279249-1-marex@denx.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-08pinctrl: bcm63xx: Fix More dependenciesRandy Dunlap
The additional patch below fixes all of the kconfig warnings and build errors for me. Link: https://lore.kernel.org/r/9e1cec76-1c0a-9203-7995-4c2d09b711d8@infradead.org Signed-off-by: Randy Dunlap <rdunlap@infradead.org> [Tweaked some other line in the BCMxxx] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-04-07Merge tag 'renesas-pinctrl-for-v5.13-tag2' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.13 (take two) - Add bias support for the R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N SoCs, - Miscellaneous cleanups and improvements.
2021-03-31pinctrl: bcm63xx: Fix dependenciesLinus Walleij
Add depends on OF so we don't get weird build errors on randconfig. Also order selects the same as the other drivers for pure aestetic reasons. Reported-by: Randy Dunlap <rdunlap@infradead.org> Cc: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-31pinctrl: bcm: bcm6362: fix warningÁlvaro Fernández Rojas
The current implementation of bcm6362_set_gpio() produces the following warning on x86_64: drivers/pinctrl/bcm/pinctrl-bcm6362.c: In function 'bcm6362_set_gpio': drivers/pinctrl/bcm/pinctrl-bcm6362.c:503:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 503 | (uint32_t) desc->drv_data, 0); | ^ Modify the code to make it similar to bcm63268_set_gpio() in order to fix the warning. Fixes: 705791e23ecd ("pinctrl: add a pincontrol driver for BCM6362") Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210330103225.3949-1-noltari@gmail.com Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-30Merge branch 'ib-bcm63xx' into develLinus Walleij
2021-03-30Merge tag 'intel-pinctrl-v5.13-1' of ↵Linus Walleij
gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.13-1 * Don't disable disabled IRQs in the handler * Fix the base calculation for groups defined by size The following is an automated git shortlog grouped by driver: intel: - No need to disable IRQs in the handler - Show the GPIO base calculation explicitly
2021-03-30drivers: pinctrl: Remove duplicate include of io.hWan Jiabing
linux/io.h has been included at line 6, so remove the duplicate include at line 18. Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com> Link: https://lore.kernel.org/r/20210323013727.135571-1-wanjiabing@vivo.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-29pinctrl: add a pincontrol driver for BCM6318Álvaro Fernández Rojas
Add a pincontrol driver for BCM6318. BCM6318 allows muxing most GPIOs to different functions. BCM6318 is similar to BCM6328 with the addition of a pad register, and the GPIO meaning of the mux register changes based on the GPIO number. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-23-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-29pinctrl: add a pincontrol driver for BCM63268Álvaro Fernández Rojas
Add a pincontrol driver for BCM63268. BCM63268 allows muxing GPIOs to different functions. Depending on the mux, these are either single pin configurations or whole pin groups. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-20-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-29pinctrl: add a pincontrol driver for BCM6368Álvaro Fernández Rojas
Add a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32 GPIOs onto alternative functions. Not all are documented. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-17-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-29pinctrl: add a pincontrol driver for BCM6362Álvaro Fernández Rojas
Add a pincotrol driver for BCM6362. BCM6362 allows muxing individual GPIO pins to the LED controller, to be available by the integrated wifi, or other functions. It also supports overlay groups, of which only NAND is documented. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-14-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-29pinctrl: add a pincontrol driver for BCM6358Álvaro Fernández Rojas
Add a pincotrol driver for BCM6358. BCM6358 allow overlaying different functions onto the GPIO pins. It does not support configuring individual pins but only whole groups. These groups may overlap, and still require the directions to be set correctly in the GPIO register. In addition the functions register controls other, not directly mux related functions. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-11-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-29pinctrl: add a pincontrol driver for BCM6328Álvaro Fernández Rojas
Add a pincontrol driver for BCM6328. BCM6328 supports muxing 32 pins as GPIOs, as LEDs for the integrated LED controller, or various other functions. Its pincontrol mux registers also control other aspects, like switching the second USB port between host and device mode. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-8-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-29pinctrl: bcm: add bcm63xx base codeÁlvaro Fernández Rojas
Add a helper for registering BCM63XX pin controllers. Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210324081923.20379-5-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-29gpio: regmap: set gpio_chip of_nodeÁlvaro Fernández Rojas
This is needed for properly registering GPIO regmap as a child of a regmap pin controller. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Link: https://lore.kernel.org/r/20210324081923.20379-3-noltari@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-25pinctrl: intel: No need to disable IRQs in the handlerAndy Shevchenko
In IRQ handler interrupts are already disabled, hence no need to repeat it. Even in the threaded case, which is disabled here, it is not a problem because IRQ framework serializes descriptor handling. Remove disabling IRQ part in the handler. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-03-25pinctrl: PINCTRL_ROCKCHIP should depend on ARCH_ROCKCHIPGeert Uytterhoeven
The Rockchip GPIO and pin control modules are only present on Rockchip SoCs. Hence add a dependency on ARCH_ROCKCHIP, to prevent asking the user about this driver when configuring a kernel without Rockchip platform support. Note that before, the PINCTRL_ROCKCHIP symbol was not visible, and automatically selected when needed. By making it tristate and user-selectable, it became visible for everyone. Fixes: be786ac5a6c4bf4e ("pinctrl: rockchip: make driver be tristate module") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210316134059.2377081-1-geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-25pinctrl: add lock in mtk_rmw function.Zhiyong Tao
When multiple threads operate on the same register resource which include multiple pin, It will make the register resource wrong to control. So we add lock to avoid the case. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Link: https://lore.kernel.org/r/20210321033150.15380-2-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-25Merge tag 'renesas-pinctrl-for-v5.13-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.13 - Add pin groups for the green and high8 subsets of the Video IN (VIN) pins on R-Car H3 ES2.0+, R-Car M3-W/M3-W+, R-Car M3-N, and R-Car E3.
2021-03-25pinctrl: pinctrl-single: fix pcs_pin_dbg_show() when bits_per_mux is not zeroHanna Hawa
A System Error (SError, followed by kernel panic) was detected when trying to print the supported pins in a pinctrl device which supports multiple pins per register. This change fixes the pcs_pin_dbg_show() in pinctrl-single driver when bits_per_mux is not zero. In addition move offset calculation and pin offset in register to common function. Fixes: 4e7e8017a80e ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") Signed-off-by: Hanna Hawa <hhhawa@amazon.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Drew Fustini <drew@beagleboard.org> Link: https://lore.kernel.org/r/20210319152133.28705-4-hhhawa@amazon.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-25pinctrl: pinctrl-single: remove unused parameterHanna Hawa
Remove unused parameter 'pin_pos' from pcs_add_pin(). Signed-off-by: Hanna Hawa <hhhawa@amazon.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Drew Fustini <drew@beagleboard.org> Link: https://lore.kernel.org/r/20210319152133.28705-3-hhhawa@amazon.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-25pinctrl: pinctrl-single: remove unused variableHanna Hawa
Remove unused parameter 'num_pins_in_register' from pcs_allocate_pin_table(). Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Hanna Hawa <hhhawa@amazon.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Drew Fustini <drew@beagleboard.org> Link: https://lore.kernel.org/r/20210319152133.28705-2-hhhawa@amazon.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-24pinctrl: renesas: r8a7791: Add bias pinconf supportGeert Uytterhoeven
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N SoCs, using the common R-Car bias handling. Note that on RZ/G1 SoCs, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-7-geert+renesas@glider.be
2021-03-24pinctrl: renesas: Add support for R-Car SoCs with pull-down only pinsGeert Uytterhoeven
Currently, the common R-Car bias handling supports pin controllers with either: 1. Separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers, for controlling both pin pull-up and pin pull-down, 2. A single pin Pull-Up control register (PUPR), for controlling pin pull-up. Add support for a variant of #2, where some bits in the single pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up. This is the case for the "ASEBRK#/ACK" pin on R-Car M2-W, M2-N, and E2, and the "ACK" pin on RZ/G1M, RZ/G1N, RZ/G1E, and RZ/G1C. To describe such a register, SoC-specific drivers need to provide two instances of pinmux_bias_reg: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-6-geert+renesas@glider.be
2021-03-24pinctrl: renesas: Add PORT_GP_CFG_7 macrosGeert Uytterhoeven
Add PORT_GP_CFG_7() and PORT_GP_7() helper macros, to be used by the r8a7791 subdriver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-5-geert+renesas@glider.be
2021-03-24pinctrl: renesas: Factor out common R-Mobile bias handlingGeert Uytterhoeven
The pin control sub-drivers for SH/R-Mobile SoCs contain almost identical bias handling. The only SoC-specific part is the mapping from pin numbers to PORTnCR registers. Reduce code duplication by factoring out the bias handling to the common pinctrl.c code. Use a callback to handle the pin/register mapping. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-4-geert+renesas@glider.be
2021-03-24pinctrl: renesas: Move R-Car bias helpers to sh_pfc.hGeert Uytterhoeven
The Renesas Pin Function Controller driver uses two header files: - sh_pfc.h, for use by both core code and SoC-specific drivers, - core.h, for internal use by the core code only. Hence move the R-Car bias helper declarations from core.h to sh_pfc.h, and drop the inclusion of core.h from SoC-specific drivers that no longer need it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-3-geert+renesas@glider.be
2021-03-24pinctrl: renesas: Make sh_pfc_pin_to_bias_reg() staticGeert Uytterhoeven
Now all R-Car pin control drivers have been converted to the common R-Car bias handling, sh_pfc_pin_to_bias_reg() is only called from a single place. Move it from core.c to pinctrl.c, make it static, and rename it to rcar_pin_to_bias_reg(), as it is specific to R-Car SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-2-geert+renesas@glider.be
2021-03-15pinctrl: qcom: sc8180x: add ACPI probe supportShawn Guo
It adds ACPI probe support for pinctrl-sc8180x driver. We have one problem with ACPI table, i.e. GIO0 (TLMM) block has one single memory resource to cover 3 tiles defined by SC8180X. To follow the hardware layout of 3 tiles which is already supported DT probe, it adds one function to replace the original single memory resource with 3 named ones for tiles. With that, We can map memory for ACPI in the same way as DT. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/20210311024102.15450-1-shawn.guo@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-15pinctrl: qcom: sm8350: add GPIO wakeup interrupt mapLina Iyer
GPIOs that can be configured as wakeup sources, have their interrupt lines routed to PDC interrupt controller. Provide the interrupt map of the GPIO to its wakeup capable interrupt parent. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312034218.3324410-1-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-15pinctrl: core: Set ret to 0 when group is skippedMichal Simek
Static analyzer tool found that the ret variable is not initialized but code expects ret value >=0 when pinconf is skipped in the first pinmux loop. The same expectation is for pinmux in a pinconf loop. That's why initialize ret to 0 to avoid uninitialized ret value in first loop or reusing ret value from first loop in second. Addresses-Coverity: ("Uninitialized variables") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Cc: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/e5203bae68eb94b4b8b4e67e5e7b4d86bb989724.1615534291.git.michal.simek@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-15pinctrl: ti: fix error return code of ti_iodelay_probe()Jia-Ju Bai
When ti_iodelay_pinconf_init_dev() fails, no error return code of ti_iodelay_probe() is assigned. To fix this bug, ret is assigned with the return value of ti_iodelay_pinconf_init_dev(), and then ret is checked. Reported-by: TOTE Robot <oslab@tsinghua.edu.cn> Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com> Link: https://lore.kernel.org/r/20210306125122.15043-1-baijiaju1990@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-15pinctrl: rockchip: make driver be tristate moduleJianqun Xu
Make pinctrl-rockchip driver to be tristate module, support to build as a module, this is useful for GKI. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210305003907.1692515-3-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-15arm64: remove select PINCTRL_ROCKCHIP from ARCH_ROCKCHIPJianqun Xu
Prepare to make pinctrl driver of rockchip to be module able, this patch remove the select of PINCTRL_ROCKCHIP from ARCH_ROCKCHIP. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210305003907.1692515-2-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-15pinctrl: core: Handling pinmux and pinconf separatelyMichal Simek
Right now the handling order depends on how entries are coming which is corresponding with order in DT. We have reached the case with DT overlays where conf and mux descriptions are exchanged which ends up in sequence that firmware has been asked to perform configuration before requesting the pin. The patch is enforcing the order that pin is requested all the time first followed by pin configuration. This change will ensure that firmware gets requests in the right order. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/cfbe01f791c2dd42a596cbda57e15599969b57aa.1615364211.git.michal.simek@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-15pinctrl: qcom: spmi-gpio: Add support for PM8350 and friendsVinod Koul
Add support for the PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B GPIO support to the Qualcomm PMIC GPIO driver. Signed-off-by: Vinod Koul <vkoul@kernel.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210308164845.3210393-2-vkoul@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-10pinctrl: pinmux: Add pinmux-select debugfs fileDrew Fustini
Add "pinmux-select" to debugfs which will activate a pin function for a given pin group: echo "<group-name function-name>" > pinmux-select The write operation pinmux_select() handles this by checking that the names map to valid selectors and then calling ops->set_mux(). The existing "pinmux-functions" debugfs file lists the pin functions registered for the pin controller. For example: function: pinmux-uart0, groups = [ pinmux-uart0-pins ] function: pinmux-mmc0, groups = [ pinmux-mmc0-pins ] function: pinmux-mmc1, groups = [ pinmux-mmc1-pins ] function: pinmux-i2c0, groups = [ pinmux-i2c0-pins ] function: pinmux-i2c1, groups = [ pinmux-i2c1-pins ] function: pinmux-spi1, groups = [ pinmux-spi1-pins ] To activate function pinmux-i2c1 on group pinmux-i2c1-pins: echo "pinmux-i2c1-pins pinmux-i2c1" > pinmux-select Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Drew Fustini <drew@beagleboard.org> Link: https://lore.kernel.org/r/20210302053059.1049035-3-drew@beagleboard.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-10pinctrl: use to octal permissions for debugfs filesDrew Fustini
Switch over pinctrl debugfs files to use octal permissions as they are preferred over symbolic permissions. Refer to commit f90774e1fd27 ("checkpatch: look for symbolic permissions and suggest octal instead"). Note: S_IFREG flag is added to the mode by __debugfs_create_file() in fs/debugfs/inode.c Suggested-by: Joe Perches <joe@perches.com> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Drew Fustini <drew@beagleboard.org> Link: https://lore.kernel.org/r/20210302053059.1049035-2-drew@beagleboard.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-10pinctrl: ingenic: add missing call to of_node_put()Yang Li
In one of the error paths of the for_each_child_of_node() loop in ingenic_gpio_probe, add missing call to of_node_put(). Fix the following coccicheck warning: ./drivers/pinctrl/pinctrl-ingenic.c:2485:1-23: WARNING: Function "for_each_child_of_node" should have of_node_put() before return around line 2489. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/1614303297-24178-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-10pinctrl: rockchip: clear int status when driver probedJianqun Xu
Some devices may do gpio interrupt trigger and make an int status before pinctrl driver probed, then the gpio handler will keep complain untill the device driver works to stop trigger. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210223101937.273085-1-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-10pinctrl: qcom: sc7280: Add GPIO wakeup interrupt mapMaulik Shah
GPIOs that can be configured as wakeup sources, have their interrupt lines routed to PDC interrupt controller. Provide the interrupt map of the GPIO to its wakeup capable interrupt parent. Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1613105974-28181-1-git-send-email-rnayak@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-10pinctrl: stm32: add missing of_node_putJunlin Yang
Fix OF node leaks by calling of_node_put in for_each_available_child_of_node when the cycle returns. Generated by: scripts/coccinelle/iterators/for_each_child.cocci Signed-off-by: Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210215103643.898-1-angkery@163.com Acked-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-10pinctrl: armada-cp110 - fix MPP54/MPP55 functionsKonstantin Porotchkin
The function name is used for selecting MPP functionality and should be unique within function names of the same pin. This patch fixes function names for MPP54 and MPP55 that have two different functions named the same. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Link: https://lore.kernel.org/r/20210216113118.17484-3-kostap@marvell.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-10pinctrl: equilibrium: add missing of_node_putJunlin Yang
Fix OF node leaks by calling of_node_put in for_each_child_of_node when the cycle returns. Generated by: scripts/coccinelle/iterators/for_each_child.cocci Signed-off-by: Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210216080231.1303-1-angkery@163.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-03-10pinctrl: renesas: r8a77965: Add vin4_g8 and vin5_high8 pinsNiklas Söderlund
This patch adds vin4_g8 and vin5_high8 support to the R8A77965 SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20210309114930.2433711-5-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-03-10pinctrl: renesas: r8a77990: Add vin4_g8 and vin5_high8 pinsNiklas Söderlund
This patch adds vin4_g8 and vin5_high8 support to the R8A77990 SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20210309114930.2433711-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-03-10pinctrl: renesas: r8a7796: Add vin4_g8 and vin5_high8 pinsNiklas Söderlund
This patch adds vin4_g8 and vin5_high8 support to the R8A7796 SoC. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20210309114930.2433711-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit (git 2.34.1) at 2025-04-06 04:46:10 +0000