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2019-08-18net: hns3: add phy_attached_info() to the hns3 driverYonglong Liu
This patch adds the call to phy_attached_info() to the hns3 driver to identify which exact PHY drivers and models is in use. Signed-off-by: Yonglong Liu <liuyonglong@huawei.com> Reviewed-by: Yunsheng Lin <linyunsheng@huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-18net: hns3: prevent unnecessary MAC TNL interruptHuazhong Tan
MAC TNL interrupt is used to collect statistic info about link status changing suddenly when netdev is running. But when stopping netdev, the enabled MAC TNL interrupt is unnecessary, and may add some noises to the statistic info. So this patch disables it before stopping MAC. Fixes: a63457878b12 ("net: hns3: Add handling of MAC tunnel interruption") Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Reviewed-by: Yunsheng Lin <linyunsheng@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-18net: hns3: change print level of RAS error log from warning to errorXiaofei Tan
This patch changes print level of RAS error log from warning to error. Because RAS error and its recovery process could cause application failure. Also uses %u instead of %d when the parameter is unsigned. Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by: Weihang Li <liweihang@hisilicon.com> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-18net: hns3: fix error and incorrect formatGuojia Liao
The pointer type parameter should be declare as const for preventing from its pointed value being unexpected modified. The uninitialized variable can not be return directly. The default return value is 0 if no abnormal result. This patch fixes the preceding two errors, deletes redundant declaration of a function and align one parameter. Signed-off-by: Guojia Liao <liaoguojia@huawei.com> Signed-off-by: Weihang Li <liweihang@hisilicon.com> Signed-off-by: Jian Shen <shenjian15@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-18net: hns3: modify redundant initialization of variableGuojia Liao
Some temporary variables do not need to be initialized that they will be set before used, so this patch deletes the initialization value of these temporary variables. Signed-off-by: Guojia Liao <liaoguojia@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Huzhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-18net: hns3: add or modify commentsGuojia Liao
To explain some code, this patch adds some comments, and modifies or merges some comments to make them more neat. Signed-off-by: Guojia Liao <liaoguojia@huawei.com> Signed-off-by: Zhongzhu Liu <liuzhongzhu@huawei.com> Signed-off-by: Weihang Li <liweihang@hisilicon.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: stmmac: selftests: Add selftest for VLAN TX OffloadJose Abreu
Add 2 new selftests for VLAN Insertion offloading. Tests are for inner and outer VLAN offloading. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: stmmac: Add support for VLAN Insertion OffloadJose Abreu
Adds the logic to insert a given VLAN ID in a packet. This is offloaded to HW and its descriptor based. For now, only XGMAC implements the necessary callbacks. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: stmmac: xgmac: Add EEE supportJose Abreu
Add support for EEE in XGMAC cores by implementing the necessary callbacks. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: stmmac: selftests: Add tests for SA Insertion/ReplacementJose Abreu
Add 4 new tests: - SA Insertion (register based) - SA Insertion (descriptor based) - SA Replacament (register based) - SA Replacement (descriptor based) Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: stmmac: Add support for SA Insertion/Replacement in XGMAC coresJose Abreu
Add the support for Source Address Insertion and Replacement in XGMAC cores. Two methods are supported: Descriptor based and register based. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: stmmac: Add ethtool register dump for XGMAC coresJose Abreu
Add the ethtool interface to dump the register map in XGMAC cores. Changes from v2: - Remove uneeded memset (Jakub) Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: stmmac: dwxgmac: Add Flexible PPS supportJose Abreu
Add the support for Flexible PPS in XGMAC cores. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: stmmac: Add a counter for Split Header packetsJose Abreu
Add a counter that increments each time a packet with split header is received. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: stmmac: Add Split Header support and enable it in XGMAC coresJose Abreu
Add the support for Split Header feature in the RX path and enable it in XGMAC cores. This does not impact neither beneficts bandwidth but it does reduces CPU usage because without the feature all the entire packet is memcpy'ed, while that with the feature only the header is. With Split Header disabled 'perf stat -d' gives: 86870.624945 task-clock (msec) # 0.429 CPUs utilized 1073352 context-switches # 0.012 M/sec 1 cpu-migrations # 0.000 K/sec 213 page-faults # 0.002 K/sec 327113872376 cycles # 3.766 GHz (62.53%) 56618161216 instructions # 0.17 insn per cycle (75.06%) 10742205071 branches # 123.658 M/sec (75.36%) 584309242 branch-misses # 5.44% of all branches (75.19%) 17594787965 L1-dcache-loads # 202.540 M/sec (74.88%) 4003773131 L1-dcache-load-misses # 22.76% of all L1-dcache hits (74.89%) 1313301468 LLC-loads # 15.118 M/sec (49.75%) 355906510 LLC-load-misses # 27.10% of all LL-cache hits (49.92%) With Split Header enabled 'perf stat -d' gives: 49324.456539 task-clock (msec) # 0.245 CPUs utilized 2542387 context-switches # 0.052 M/sec 1 cpu-migrations # 0.000 K/sec 213 page-faults # 0.004 K/sec 177092791469 cycles # 3.590 GHz (62.30%) 68555756017 instructions # 0.39 insn per cycle (75.16%) 12697019382 branches # 257.418 M/sec (74.81%) 442081897 branch-misses # 3.48% of all branches (74.79%) 20337958358 L1-dcache-loads # 412.330 M/sec (75.46%) 3820210140 L1-dcache-load-misses # 18.78% of all L1-dcache hits (75.35%) 1257719198 LLC-loads # 25.499 M/sec (49.73%) 685543923 LLC-load-misses # 54.51% of all LL-cache hits (49.86%) Changes from v2: - Reword commit message (Jakub) Changes from v1: - Add performance info (David) - Add misssing dma_sync_single_for_device() Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: stmmac: xgmac: Correctly return that RX descriptor is not last oneJose Abreu
Return the correct value when RX descriptor is not the last one. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: stmmac: Prepare to add Split Header supportJose Abreu
In order to add Split Header support, stmmac_rx() needs to take into account that packet may be split accross multiple descriptors. Refactor the logic of this function in order to support this scenario. Changes from v2: - Fixup if condition detection (Jakub) - Don't stop NAPI with unfinished packet (Jakub) - Use napi_alloc_skb() (Jakub) Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: stmmac: Get correct timestamp values from XGMACJose Abreu
TX Timestamp in XGMAC comes from MAC instead of descriptors. Implement this in a new callback. Also, RX Timestamp in XGMAC must be cheked against corruption and we need a barrier to make sure that descriptor fields are read correctly. Changes from v2: - Rework return code check (Jakub) Changes from v1: - Rework the get timestamp function (David) Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17Documentation: Add description of netdevsim trapsIdo Schimmel
Signed-off-by: Ido Schimmel <idosch@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17netdevsim: Add devlink-trap supportIdo Schimmel
Have netdevsim register its trap groups and traps with devlink during initialization and periodically report trapped packets to devlink core. Since netdevsim is not a real device, the trapped packets are emulated using a workqueue that periodically reports a UDP packet with a random 5-tuple from each active packet trap and from each running netdev. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Acked-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: phy: remove genphy_config_initHeiner Kallweit
Now that all users have been removed we can remove genphy_config_init. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-17net: phy: remove calls to genphy_config_initHeiner Kallweit
Supported PHY features are either auto-detected or explicitly set. In both cases calling genphy_config_init isn't needed. All that genphy_config_init does is removing features that are set as supported but can't be auto-detected. Basically it duplicates the code in genphy_read_abilities. Therefore remove such calls from all PHY drivers. v2: - remove call also from new adin PHY driver v3: - pass NULL as config_init function pointer for dp83848 Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16ipvlan: set hw_enc_features like macvlanBill Sommerfeld
Allow encapsulated packets sent to tunnels layered over ipvlan to use offloads rather than forcing SW fallbacks. Since commit f21e5077010acda73a60 ("macvlan: add offload features for encapsulation"), macvlan has set dev->hw_enc_features to include everything in dev->features; do likewise in ipvlan. Signed-off-by: Bill Sommerfeld <wsommerfeld@google.com> Acked-by: Mahesh Bandewar <maheshb@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: dsa: mv88e6xxx: check for mode change in port_setup_macMarek Behún
The mv88e6xxx_port_setup_mac checks if the requested MAC settings are different from the current ones, and if not, does nothing (since chaning them requires putting the link down). In this check it only looks if the triplet [link, speed, duplex] is being changed. This patch adds support to also check if the mode parameter (of type phy_interface_t) is requested to be changed. The current mode is computed by the ->port_link_state() method, and if it is different from PHY_INTERFACE_MODE_NA, we check for equality with the requested mode. In the implementations of the mv88e6250_port_link_state() method we set the current mode to PHY_INTERFACE_MODE_NA - so the code does not check for mode change on 6250. In the mv88e6352_port_link_state() method, we use the cached cmode of the port to determine the mode as phy_interface_t (and if it is not enough, eg. for RGMII, we also look at the port control register for RX/TX timings). Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: add ethtool get_stats supportAlexandru Ardelean
This change implements retrieving all the error counters from the PHY. The counters require that the RxErrCnt register (0x0014) be read first, after which copies of the counters are latched into the registers. This ensures that all registers read after RxErrCnt are synchronized at the moment that they are read. The counter values need to be accumulated by the driver, as each time that RxErrCnt is read, the values that are latched are the ones that have incremented from the last read. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: implement downshift configuration via phy-tunableAlexandru Ardelean
Down-speed auto-negotiation may not always be enabled, in which case the PHY won't down-shift to 100 or 10 during auto-negotiation. This change enables downshift and configures the number of retries to default 4 (which is also in the datasheet The downshift control mechanism can also be controlled via the phy-tunable interface (ETHTOOL_PHY_DOWNSHIFT control). The change has been adapted from the Aquantia PHY driver. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: implement PHY subsystem software resetAlexandru Ardelean
The ADIN PHYs supports 4 types of reset: 1. The standard PHY reset via BMCR_RESET bit in MII_BMCR reg 2. Reset via GPIO 3. Reset via reg GeSftRst (0xff0c) & reload previous pin configs 4. Reset via reg GeSftRst (0xff0c) & request new pin configs Resets 2, 3 & 4 are almost identical, with the exception that the crystal oscillator is available during reset for 2. This change implements subsystem software reset via the GeSftRst and reloading the previous pin configuration (so reset number 3). This will also reset the PHY core regs (similar to reset 1). Since writing bit 1 to reg GeSftRst is self-clearing, the only thing that can be done, is to write to that register, wait a specific amount of time (10 milliseconds should be enough) and try to read back and check if there are no errors on read. A busy-wait-read won't work well, and may sometimes work or not work. In case phylib is configured to also do a reset via GPIO, the ADIN PHY may be reset twice when the PHY device registers, but that isn't a problem, since it's being done on boot (or PHY device register). Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: add EEE translation layer from Clause 45 to Clause 22Alexandru Ardelean
The ADIN1200 & ADIN1300 PHYs support EEE by using standard Clause 45 access to access MMD registers for EEE. The EEE register addresses (when using Clause 22) are available at different addresses (than Clause 45), and since accessing these regs (via Clause 22) needs a special mechanism, a translation table is required to convert these addresses. For Clause 45, this is not needed since the driver will likely never use this access mode. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: add support MDI/MDIX/Auto-MDI selectionAlexandru Ardelean
The ADIN PHYs support automatic MDI/MDIX negotiation. By default this is disabled, so this is enabled at `config_init`. This is controlled via the PHY Control 1 register. The supported modes are: 1. Manual MDI 2. Manual MDIX 3. Auto MDIX - prefer MDIX 4. Auto MDIX - prefer MDI The phydev mdix & mdix_ctrl fields include modes 3 & 4 into a single auto-mode. So, the default mode this driver enables is 4 when Auto-MDI mode is used. When detecting MDI/MDIX mode, a combination of the PHY Control 1 register and PHY Status 1 register is used to determine the correct MDI/MDIX mode. If Auto-MDI mode is not set, then the manual MDI/MDIX mode is returned. If Auto-MDI mode is set, then MDIX mode is returned differs from the preferred MDI/MDIX mode. This covers all cases where: 1. MDI preferred & Pair01Swapped == MDIX 2. MDIX preferred & Pair01Swapped == MDI 3. MDI preferred & ! Pair01Swapped == MDIX 4. MDIX preferred & ! Pair01Swapped == MDI The preferred MDI/MDIX mode is not configured via SW, but can be configured via HW pins. Note that the `Pair01Swapped` is the Green-Yellow physical pairs. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: make RMII fifo depth configurableAlexandru Ardelean
The FIFO depth can be configured for the RMII mode. This change adds support for doing this via device-tree (or ACPI). Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: make RGMII internal delays configurableAlexandru Ardelean
The internal delays for the RGMII are configurable for both RX & TX. This change adds support for configuring them via device-tree (or ACPI). Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: configure RGMII/RMII/MII modes on configAlexandru Ardelean
The ADIN1300 chip supports RGMII, RMII & MII modes. Default (if unconfigured) is RGMII. This change adds support for configuring these modes via the device registers. For RGMII with internal delays (modes RGMII_ID,RGMII_TXID, RGMII_RXID), the default delay is 2 ns. This can be configurable and will be done in a subsequent change. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: add {write,read}_mmd hooksAlexandru Ardelean
Both ADIN1200 & ADIN1300 support Clause 45 access for some registers. The Extended Management Interface (EMI) registers are accessible via both Clause 45 (at register MDIO_MMD_VEND1) and using Clause 22. The Clause 22 access for MMD regs differs from the standard one defined by 802.3. The ADIN PHYs use registers ExtRegPtr (0x0010) and ExtRegData (0x0011) to access Clause 45 & EMI registers. The indirect access is done via the following mechanism (for both R/W): 1. Write the address of the register in the ExtRegPtr 2. Read/write the value of the register via reg ExtRegData This mechanism is needed to manage configuration of chip settings and to access EEE registers via Clause 22. Since Clause 45 access will likely never be used, it is not implemented via this hook. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: add support for interruptsAlexandru Ardelean
This change hooks link-status-change interrupts to phylib. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: hook genphy_{suspend, resume} into the driverAlexandru Ardelean
The chip supports standard suspend/resume via BMCR reg. Hook these functions into the `adin` driver. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-16net: phy: adin: add support for Analog Devices PHYsAlexandru Ardelean
This change adds support for Analog Devices Industrial Ethernet PHYs. Particularly the PHYs this driver adds support for: * ADIN1200 - Robust, Industrial, Low Power 10/100 Ethernet PHY * ADIN1300 - Robust, Industrial, Low Latency 10/100/1000 Gigabit Ethernet PHY The 2 chips are register compatible with one another. The main difference being that ADIN1200 doesn't operate in gigabit mode. The chips can be operated by the Generic PHY driver as well via the standard IEEE PHY registers (0x0000 - 0x000F) which are supported by the kernel as well. This assumes that configuration of the PHY has been done completely in HW, according to spec. Configuration can also be done via registers, which will be supported by this driver. Datasheets: https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1300.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1200.pdf Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: mscc: PTP Hardware Clock (PHC) supportAntoine Tenart
This patch adds support for PTP Hardware Clock (PHC) to the Ocelot switch for both PTP 1-step and 2-step modes. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: mscc: remove the frame_info cpuq memberAntoine Tenart
In struct frame_info, the cpuq member is never used. This cosmetic patch removes it from the structure, and from the parsing of the frame header as it's only set but never used. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: mscc: improve the frame header parsing readabilityAntoine Tenart
This cosmetic patch improves the frame header parsing readability by introducing a new macro to access and mask its fields. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: mscc: describe the PTP register rangeAntoine Tenart
This patch adds support for using the PTP register range, and adds a description of its registers. This bank is used when configuring PTP. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15qed: Add driver API for flashing the config attributes.Sudarsana Reddy Kalluru
The patch adds driver interface for reading the config attributes from user provided buffer, and updates these values on nvm config flash partition. This is basically an expansion of our existing ethtool -f implementation. The management FW has exposed an additional method of configuring some of the nvram options, and this makes use of that. This implementation will come into use when newer FW files which contain configuration directives employing this API will be provided to ethtool -f. Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15qed: Add API for configuring NVM attributes.Sudarsana Reddy Kalluru
The patch adds API for configuring the NVM config attributes using Management FW (MFW) interfaces. Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15Merge tag 'linux-can-next-for-5.4-20190814' of ↵David S. Miller
git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next Marc Kleine-Budde says: ==================== pull-request: can-next 2019-08-14 this is a pull request for net-next/master consisting of 41 patches. The first two patches are for the kvaser_pciefd driver: Christer Beskow removes unnecessary code in the kvaser_pciefd_pwm_stop() function, YueHaibing removes the unused including of <linux/version.h>. In the next patch YueHaibing also removes the unused including of <linux/version.h> in the f81601 driver. In the ti_hecc driver the next 6 patches are by me and fix checkpatch warnings. YueHaibing's patch removes an unused variable in the ti_hecc_mailbox_read() function. The next 6 patches all target the xilinx_can driver. Anssi Hannula's patch fixes a chip start failure with an invalid bus. The patch by Venkatesh Yadav Abbarapu skips an error message in case of a deferred probe. The 3 patches by Appana Durga Kedareswara rao fix the RX and TX path for CAN-FD frames. Srinivas Neeli's patch fixes the bit timing calculations for CAN-FD. The next 12 patches are by me and several checkpatch warnings in the af_can, raw and bcm components. Thomas Gleixner provides a patch for the bcm, which switches the timer to HRTIMER_MODE_SOFT and removes the hrtimer_tasklet. Then 6 more patches by me for the gw component, which fix checkpatch warnings, followed by 2 patches by Oliver Hartkopp to add CAN-FD support. The vcan driver gets 3 patches by me, fixing checkpatch warnings. And finally a patch by Andre Hartmann to fix typos in CAN's netlink header. ====================
2019-08-15netdevsim: implement support for devlink region and snapshotsJiri Pirko
Implement dummy region of size 32K and allow user to create snapshots or random data using debugfs file trigger. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15r8169: sync EEE handling for RTL8168h with vendor driverHeiner Kallweit
Sync EEE init for RTL8168h with vendor driver and add two writes to vendor-specific registers. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15r8169: use the generic EEE management functionsHeiner Kallweit
Now that the Realtek PHY driver maps the vendor-specific EEE registers to the standard MMD registers, we can remove all special handling and use the generic functions phy_ethtool_get/set_eee. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: phy: realtek: add support for EEE registers on integrated PHY'sHeiner Kallweit
EEE-related registers on newer integrated PHY's have the standard layout, but are accessible not via MMD but via vendor-specific registers. Emulating the standard MMD registers allows to use the generic functions for EEE control. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: phy: swphy: emulate register MII_ESTATUSHeiner Kallweit
When the genphy driver binds to a swphy it will call genphy_read_abilites that will try to read MII_ESTATUS if BMSR_ESTATEN is set in MII_BMSR. So far this would read the default value 0xffff and 1000FD and 1000HD are reported as supported just by chance. Better add explicit support for emulating MII_ESTATUS. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-15net: phy: read MII_CTRL1000 in genphy_read_status only if neededHeiner Kallweit
Value of MII_CTRL1000 is needed only if LPA_1000MSFAIL is set. Therefore move reading this register. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-08-14net/mvpp2: Replace tasklet with softirq hrtimerThomas Gleixner
The tx_done_tasklet tasklet is used in invoke the hrtimer (mvpp2_hr_timer_cb) in softirq context. This can be also achieved without the tasklet but with HRTIMER_MODE_SOFT as hrtimer mode. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
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