summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Expand)Author
2017-06-12drm/i915/cnl: Implement voltage swing sequence.Rodrigo Vivi
2017-06-12drm/i915/cnl: Add DDI Buffer translation tables for Cannonlake.Rodrigo Vivi
2017-06-12drm/i915/cnl: Add registers related to voltage swing sequences.Rodrigo Vivi
2017-06-12drm/i915: Add MMIO helper for 6 ports with different offsets.Rodrigo Vivi
2017-06-12drm/i915/cnl: Initialize PLLsRodrigo Vivi
2017-06-12drm/i915: Configure DPLL's for CannonlakeKahola, Mika
2017-06-12drm/i915/cnl: DDI - PLL mappingRodrigo Vivi
2017-06-12drm/i915/cnl: Allow dynamic cdclk changes on CNLRodrigo Vivi
2017-06-12drm/i915/cnl: Implement CNL display init/unit sequenceVille Syrjälä
2017-06-12drm/i915/cnl: Implement .set_cdclk() for CNLVille Syrjälä
2017-06-12drm/i915/cnl: Implement .get_display_clock_speed() for CNLVille Syrjälä
2017-06-12drm/i915: Pass atomic state to backlight enable/disable/set callbacks.Maarten Lankhorst
2017-06-12drm/i915: Pass connector state to intel_panel_set_backlight_acpiMaarten Lankhorst
2017-06-12drm/i915: Pass crtc_state and connector state to backlight enable/disable fun...Maarten Lankhorst
2017-06-12drm/i915: Fix GVT-g PVINFO version compatibility checkZhenyu Wang
2017-06-09drm/i915/cfl: Coffee Lake reuses Kabylake DMC.Rodrigo Vivi
2017-06-09drm/i915/huc: Load HuC on Coffee LakeAnusha Srivatsa
2017-06-09drm/i915/guc: Load GuC on Coffee LakeAnusha Srivatsa
2017-06-09drm/i915/cfl: Add Coffee Lake PCI IDs for U Sku.Anusha Srivatsa
2017-06-09drm/i915/cfl: Add Coffee Lake PCI IDs for H Sku.Anusha Srivatsa
2017-06-09drm/i915/cfl: Add Coffee Lake PCI IDs for S Skus.Anusha Srivatsa
2017-06-09drm/i915/glk: Remove the alpha_support flagAnder Conselvan de Oliveira
2017-06-08drm/i915/cfl: Introduce Display workarounds for Coffee Lake.Rodrigo Vivi
2017-06-08drm/i915/cfl: Coffee Lake uses CNP PCH.Rodrigo Vivi
2017-06-08drm/i915/cfl: Introduce Coffee Lake platform definition.Rodrigo Vivi
2017-06-08drm/i915: Remove the spin-request during execbuf await_requestChris Wilson
2017-06-08drm/i915: Skip adding the request to the signal tree is completeChris Wilson
2017-06-08drm/i915: Report back whether the irq was armed when adding the waiterChris Wilson
2017-06-08drm/i915: Check signaled state after enabling signalingChris Wilson
2017-06-08drm/i915/guc: Clear enable_guc_loading in case of init failureMichel Thierry
2017-06-08drm/i915: Move the unclaimed mmio detection into the powerwell for KMSChris Wilson
2017-06-07drm/i915: Unify GT* and GT3 definitionsRodrigo Vivi
2017-06-07drm/i915: Remove unnecessary PORT3 definition.Rodrigo Vivi
2017-06-07drm/i915/cnl: Also need power well sanitize.Rodrigo Vivi
2017-06-07drm/i915/cnl: Add power wells for CNLVille Syrjälä
2017-06-07drm/i915/gen10: Set value of Indirect Context Offset for gen10Michel Thierry
2017-06-07drm/i915/cnl: Cannonlake has same MOCS table than Skylake.Rodrigo Vivi
2017-06-07drm/i915/cnl: Configure EU slice power gating.Rodrigo Vivi
2017-06-07drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipeJames Irwin
2017-06-07drm/i915/cnl: add IS_CNL_REVID macroPaulo Zanoni
2017-06-07drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.Rodrigo Vivi
2017-06-07drm/i915/cnl: Cannonlake uses CNP PCH.Rodrigo Vivi
2017-06-07drm/i915/cnl: Introduce Cannonlake platform defition.Rodrigo Vivi
2017-06-06drm/i915: Fix 90/270 rotated coordinates for FBCVille Syrjälä
2017-06-06drm/i915: Fix SKL+ watermarks for 90/270 rotationVille Syrjälä
2017-06-06drm/i915: Fix scaling check for 90/270 degree plane rotationVille Syrjälä
2017-06-06drm/i915: Restore has_fbc=1 for ILK-MVille Syrjälä
2017-06-06drm/i915: s/fbc_fc/fbc_false_color/Ville Syrjälä
2017-06-06drm/i915: Implement fbc_status "Compressing" info for all platformsVille Syrjälä
2017-06-06drm/i915: Workaround VLV/CHV DSI scanline counter hardware failVille Syrjälä
generated by cgit (git 2.34.1) at 2025-05-09 06:29:09 +0000