summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Expand)Author
2018-12-04drm/i915: Verify GT workaround state after GPU initTvrtko Ursulin
2018-12-04drm/i915: Introduce per-engine workaroundsTvrtko Ursulin
2018-12-04drm/i915: Record GT workarounds in a listTvrtko Ursulin
2018-12-04drm/i915: change i915_sw_fence license to MITJonathan Gray
2018-12-04drm/i915: Complete the fences as they are cancelled due to wedgingChris Wilson
2018-12-04drm/i915/dp: Fix inconsistent indentingChris Wilson
2018-12-03drm/i915: Move display device info capabilities to its own structJosé Roberto de Souza
2018-12-03drm/i915: Add HAS_DISPLAY() and use itJosé Roberto de Souza
2018-12-03drm/i915/dp: Fix link compute m_n calc for DSCManasi Navare
2018-12-03drm/i915/sysfs: make attrs arrays constJani Nikula
2018-12-03drm/i915/vgpu: Disallow loading on old vGPU hostsChris Wilson
2018-12-03drm/i915/breadcrumbs: Reduce missed-breadcrumb false positive rateChris Wilson
2018-12-03drm/i915/icl: add pll mapping for DSIJani Nikula
2018-12-03drm/i915/icl: Ungate DSI clocksMadhav Chauhan
2018-12-03drm/i915/icl: Gate clocks for DSIMadhav Chauhan
2018-12-03drm/i915/icl: add dummy DSI GPIO element execution functionJani Nikula
2018-12-03drm/i915/icl: Define display GPIO pins for DSIMadhav Chauhan
2018-12-03drm/i915/icl: Define Panel power ctrl registerMadhav Chauhan
2018-12-03drm/i915/icl: Define missing bitfield for shortplug regMadhav Chauhan
2018-12-03drm/i915/icl: Get pipe timings for DSIMadhav Chauhan
2018-12-03drm/i915/icl: Consider DSI for getting transcoder stateMadhav Chauhan
2018-12-03drm/i915/icl: Configure DSI Dual link modeMadhav Chauhan
2018-12-03drm/i915/icl: Add DSI encoder compute config hookMadhav Chauhan
2018-12-03drm/i915/icl: Get HW state for DSI encoderMadhav Chauhan
2018-12-03drm/i915/icl: Add get config functionality for DSIVandita Kulkarni
2018-12-03drm/i915/icl: Allocate DSI hosts and imlement host transferMadhav Chauhan
2018-12-03drm/i915/icl: Fill DSI ports infoMadhav Chauhan
2018-12-03drm/i915/icl: Use the same pll functions for dsiVandita Kulkarni
2018-12-03drm/i915/icl: Allocate DSI encoder/connectorMadhav Chauhan
2018-12-03drm/i915/icl: Calculate DPLL params for DSIMadhav Chauhan
2018-12-03drm/i915/icl: Sanitize DDI port clock gating for DSI portsImre Deak
2018-12-03drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooksJani Nikula
2018-12-03drm/i915/selftests: Terminate hangcheck sanitycheck forciblyChris Wilson
2018-12-03drm/i915/ringbuffer: Clear semaphore sync registers on ring initChris Wilson
2018-11-30drm/i915/psr: Get pipe id following atomic guidelinesJosé Roberto de Souza
2018-11-30drm/i915/selftests: Fix live_workarounds to actually do resetsTvrtko Ursulin
2018-11-30drm/i915/selftests: Extract spinner codeTvrtko Ursulin
2018-11-30drm/i915/icl: Remove Wa_1604302699Tvrtko Ursulin
2018-11-30drm/i915: Remove whitelist application from ringbuffer backendTvrtko Ursulin
2018-11-30drm/i915: Fixup stub definitions for intel_opregion_suspend|resumeChris Wilson
2018-11-29drm/i915/fec: Disable FEC state.Anusha Srivatsa
2018-11-29i915/dp/fec: Configure the Forward Error Correction bits.Anusha Srivatsa
2018-11-29drm/i915/fec: Set FEC_READY in FEC_CONFIGURATIONAnusha Srivatsa
2018-11-29i915/dp/fec: Add fec_enable to the crtc state.Anusha Srivatsa
2018-11-29drm/i915/dsc: Enable and disable appropriate power wells for VDSCManasi Navare
2018-11-29drm/i915/dp: Disable DSC in source by disabling DSS CTL bitsManasi Navare
2018-11-29drm/i915/dp: Configure Display stream splitter registers during DSC enableManasi Navare
2018-11-29drm/i915/dp: Populate DSC PPS SDP and send PPS infoframesManasi Navare
2018-11-29drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPsManasi Navare
2018-11-29drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enablingManasi Navare
generated by cgit (git 2.34.1) at 2024-07-06 11:11:33 +0000