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2020-01-08bus: moxtet: declare moxtet_bus_type as staticMarek Behún
This symbol is not meant to be used from elsewhere. Cc: Ben Dooks <ben.dooks@codethink.co.uk> Cc: Christoph Hellwig <hch@infradead.org> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-01-08firmware: turris-mox-rwtm: small white space cleanupDan Carpenter
This patch deletes a stray tab. Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Colin King <colin.king@canonical.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-01-08reset: qcom-aoss: Allow CONFIG_RESET_QCOM_AOSS to be a tristateJohn Stultz
Allow CONFIG_RESET_QCOM_AOSS to be set as as =m to allow for the driver to be loaded from a modules. Also replaces the builtin_platform_driver() line with module_platform_driver() and adds a MODULE_DEVICE_TABLE() entry. Cc: Todd Kjos <tkjos@google.com> Cc: Alistair Delva <adelva@google.com> Cc: Amit Pundir <amit.pundir@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-01-07firmware: qcom_scm: Dynamically support SMCCC and legacy conventionsElliot Berman
Dynamically support SMCCCC and legacy conventions by detecting which convention to use at runtime. qcom_scm_call_atomic and qcom_scm_call can then be moved in qcom_scm.c and use underlying convention backend as appropriate. Thus, rename qcom_scm-64,-32 to reflect that they are backends for -smc and -legacy, respectively. Also add support for making SCM calls earlier than when SCM driver probes to support use cases such as qcom_scm_set_cold_boot_addr. Support is added by lazily initializing the convention and guarding the query with a spin lock. The limitation of these early SCM calls is that they cannot use DMA, as in the case of >4 arguments for SMC convention and any non-atomic call for legacy convention. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-18-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm: Remove thin wrappersElliot Berman
qcom_scm-32 and qcom_scm-64 implementations are nearly identical, so make qcom_scm_call and qcom_scm_call_atomic unique to each and the SCM descriptor creation common to each. There are the following catches: - __qcom_scm_is_call_available is still in each -32,-64 implementation as the argument is unique to each convention - For some functions, only one implementation was provided in -32 or -64. The actual implementation was moved into qcom_scm.c - io_writel and io_readl in -64 were non-atomic calls and in -32 they were. Atomic is the better option, so use it. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-17-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm: Order functions, definitions by service/commandElliot Berman
Definitions throughout qcom_scm are loosely grouped and loosely ordered. Sort all the functions/definitions by service ID/command ID to improve sanity when needing to add new functionality to this driver. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-16-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm-32: Add device argument to atomic callsElliot Berman
Add unused "device" parameter to reduce merge friction between SMCCC and legacy based conventions in an upcoming patch. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-15-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm-32: Create common legacy atomic callElliot Berman
Per [1], legacy calling convention supports up to 5 arguments and 3 return values. Create one function to support this combination, and remove the original "atomic1" and "atomic2" variants for 1 and 2 arguments. This more closely aligns scm_legacy implementation with scm_smc implementation. [1]: https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/soc/qcom/scm.c?h=kernel.lnx.4.9.r28-rel#n1024 Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-14-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_callElliot Berman
Move SMCCC register filling to qcom_scm_call so that __scm_legacy_do only needs to concern itself with retry mechanism. qcom_scm_call then is responsible for translating qcom_scm_desc into the complete set of register arguments and passing onto qcom_scm_call_do. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-13-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic callsElliot Berman
Use qcom_scm_desc in non-atomic calls to remove legacy convention details from every SCM wrapper function. Implementations were copied from qcom_scm-64 and are functionally equivalent when using the qcom_scm_desc and qcom_scm_res structs. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-12-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm-32: Add funcnum IDsElliot Berman
Add SCM_LEGACY_FNID macro to qcom_scm-32. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-11-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm-32: Use SMC arch wrappersElliot Berman
Use SMC arch wrappers instead of inline assembly. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-10-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm-64: Improve SMC convention detectionElliot Berman
Improve the calling convention detection to use __qcom_scm_is_call_available() and not blindly assume 32-bit mode if the checks fails. BUG() if neither 32-bit or 64-bit mode works. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-9-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm-64: Move SMC register filling to qcom_scm_call_smcccElliot Berman
qcom_scm_call_smccc should be responsible for converting qcom_scm_desc into arguments for smc call. Consolidate the dispersed logic to convert qcom_scm_desc into smc arguments inside qcom_scm_call_smccc. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-8-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm-64: Add SCM results structElliot Berman
Remove knowledge of arm_smccc_res struct from client wrappers so that client wrappers only work QCOM SCM data structures. SCM calls may have up to 3 arguments, so qcom_scm_call_smccc is responsible now for filling those 3 arguments accordingly. This is necessary to support merging legacy and SMC conventions in an upcoming patch. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-7-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_descElliot Berman
Service, command, and owner IDs are all part of qcom_scm_desc struct and have no special reason to be a function argument (or hard-coded in the case of owner [1]). Moving them to be part of qcom_scm_desc struct improves readability. [1]: Example of SCM function using owner vale other than hard-coded SIP value: https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/soc/qcom/smcinvoke.c?h=kernel.lnx.4.9.r28-rel#n35 Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-6-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm-64: Make SMC macros less magicalElliot Berman
Improve understandability of SMC macros by reversing the logic as they are all functions of how many arguments can be shoved in registers and how many SCM arguments are supported. There aren't 4 register arguments because are 7 arguments that go into a buffer - there are up to 7 arguments that are overflowed into a buffer because only 4 registers are allocated for arguments. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-5-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm: Remove unused qcom_scm_get_versionElliot Berman
Remove unused qcom_scm_get_version. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-4-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm: Apply consistent naming scheme to command IDsElliot Berman
Create a consistent naming scheme for command IDs. The scheme is QCOM_SCM_##svc_##cmd. Remove unused macros QCOM_SCM_FLAG_HLOS, QCOM_SCM_FLAG_COLDBOOT_MC, QCOM_SCM_FLAG_WARMBOOT_MC, QCOM_SCM_CMD_CORE_HOTPLUGGED, and QCOM_SCM_BOOT_ADDR_MC. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-3-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07firmware: qcom_scm: Rename macros and structuresElliot Berman
Rename legacy-specific structures and macros with legacy prefix; rename smc-specific structures and macros with smc prefix. This should make it clearer which structures are generic to "SCM" and which are specfically for implementing the convention. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-2-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07soc: qcom: rpmhpd: Set 'active_only' for active only power domainsDouglas Anderson
The 'active_only' attribute was accidentally never set to true for any power domains meaning that all the code handling this attribute was dead. NOTE that the RPM power domain code (as opposed to the RPMh one) gets this right. Acked-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: 279b7e8a62cc ("soc: qcom: rpmhpd: Add RPMh power domain driver") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20190214173633.211000-1-dianders@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-01-07memory: samsung: Rename Exynos to lowercaseKrzysztof Kozlowski
Fix up inconsistent usage of upper and lowercase letters in "Exynos" name. "EXYNOS" is not an abbreviation but a regular trademarked name. Therefore it should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-01-07soc: samsung: Rename Samsung and Exynos to lowercaseKrzysztof Kozlowski
Fix up inconsistent usage of upper and lowercase letters in "Samsung" and "Exynos" names. "SAMSUNG" and "EXYNOS" are not abbreviations but regular trademarked names. Therefore they should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Although advertisement materials usually use uppercase "SAMSUNG", the lowercase version is used in all legal aspects (e.g. on Wikipedia and in privacy/legal statements on https://www.samsung.com/semiconductor/privacy-global/). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-01-06Merge tag 'renesas-drivers-for-v5.6-tag1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v5.6 - Remove now unused ARCH_R8A7796 config symbol, - Fix a sparse warning, - Add split R-Car H3 ES1.x and ES2.0+ config symbols. * tag 'renesas-drivers-for-v5.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: Add ARCH_R8A7795[01] for existing R-Car H3 soc: renesas: rcar-rst: Fix __iomem on configure call soc: renesas: Remove ARCH_R8A7796 Link: https://lore.kernel.org/r/20200106104857.8361-5-geert+renesas@glider.be Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06Merge tag 'tee-optee-pldrv-for-5.6' of ↵Olof Johansson
git://git.linaro.org:/people/jens.wiklander/linux-tee into arm/drivers Model OP-TEE as a platform device/driver * tag 'tee-optee-pldrv-for-5.6' of git://git.linaro.org:/people/jens.wiklander/linux-tee: optee: model OP-TEE as a platform device/driver Link: https://lore.kernel.org/r/20200103090025.GA11243@jax Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06Merge tag 'scmi-updates-5.6' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers ARM SCMI updates for v5.6 1. Addition of multiple device support per protocol to enable use of some procotols by multiple kernel subsystems simultaneously and corresponding updates to the existing scmi drivers 2. Addition of trace events around the scmi transfer code to measure any delays and capture anomalies that can also be used during investigation of some platform firmware related issues * tag 'scmi-updates-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: drivers: firmware: scmi: Extend SCMI transport layer by trace events include: trace: Add SCMI header with trace events reset: reset-scmi: Match scmi device by both name and protocol id hwmon: (scmi-hwmon) Match scmi device by both name and protocol id cpufreq: scmi: Match scmi device by both name and protocol id clk: scmi: Match scmi device by both name and protocol id firmware: arm_scmi: Skip protocol initialisation for additional devices firmware: arm_scmi: Stash version in protocol init functions firmware: arm_scmi: Match scmi device by both name and protocol id firmware: arm_scmi: Add versions and identifier attributes using dev_groups firmware: arm_scmi: Add names to scmi devices created firmware: arm_scmi: Skip scmi mbox channel setup for addtional devices firmware: arm_scmi: Add support for multiple device per protocol Link: https://lore.kernel.org/r/20191230182956.GA29349@bogus Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06soc: renesas: Add ARCH_R8A7795[01] for existing R-Car H3Geert Uytterhoeven
Despite using the same compatible values ("r8a7795"-based) because of historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+ (R8A77951) are really different SoCs, with different part numbers. Reflect this in the SoC configuration, by adding CONFIG_ARCH_R8A77950 and CONFIG_ARCH_R8A77951 as new config symbols. These are intended to replace CONFIG_ARCH_R8A7795, and will allow making support for early SoC revisions optional. Note that for now, CONFIG_ARCH_R8A7795 is retained, and just selects CONFIG_ARCH_R8A77950 and CONFIG_ARCH_R8A77951. This relaxes dependencies of other subsystems on the SoC configuration symbol, and provides a smooth transition path for config files through "make oldconfig". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191217183841.432-6-geert+renesas@glider.be
2020-01-06soc: renesas: rcar-rst: Fix __iomem on configure callBen Dooks (Codethink)
The configure call back takes a register pointer, so should have been marked with __iomem. Add this to silence the following sparse warnings: drivers/soc/renesas/rcar-rst.c:33:22: warning: incorrect type in initializer (incompatible argument 1 (different address spaces)) drivers/soc/renesas/rcar-rst.c:33:22: expected int ( *configure )( ... ) drivers/soc/renesas/rcar-rst.c:33:22: got int ( * )( ... ) drivers/soc/renesas/rcar-rst.c:97:40: warning: incorrect type in argument 1 (different address spaces) drivers/soc/renesas/rcar-rst.c:97:40: expected void *base drivers/soc/renesas/rcar-rst.c:97:40: got void [noderef] <asn:2> *[assigned] base Signed-off-by: Ben Dooks (Codethink) <ben.dooks@codethink.co.uk> Link: https://lore.kernel.org/r/20191218135230.2610161-1-ben.dooks@codethink.co.uk Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-01-06reset: Add Broadcom STB RESCAL reset controllerJim Quinlan
On BCM7216 there is a special purpose reset controller named RESCAL (reset calibration) which is necessary for SATA and PCIe0/1 to operate correctly. This commit adds support for such a reset controller to be available. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-01-05soc: bcm: brcmstb: biuctrl: Update programming for 7211Florian Fainelli
Add a matching entry for 7211 which can be programmed with the same BIUCTRL settings as other Brahma-B53 based SoCs. While at it, rename the function to include a72 in the name to reflect this applies to both types of 64-bit capable CPUs that we support (Brahma-B53 and Cortex-A72). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-01-05soc: bcm: brcmstb: biuctrl: Update layout for A72 on 7211Florian Fainelli
The BIUCTRL layout is a little different on 7211 which is equipped with a Cortex-A72, account for those register offset differences. We will match 7211 specifically in a subsequent commit. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-01-05soc: bcm: brcmstb: biuctrl: Tune interface for 7255 and 7216Florian Fainelli
7255 and 7216 are some of the latest chips that were produced and support the full register range configuration for the BIU, add the two entries to get the expected programming. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-01-05soc: bcm: brcmstb: biuctrl: Tune 7260 BIU interfaceFlorian Fainelli
7260A0 and B0 are both supported, and 7260A0 has a small difference in that it does not support the write-back control register, which is why we have a different array of registers. Update the comment above b53_cpubiuctrl_no_wb_regs to denote that difference. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-01-03reset: intel: Add system reset controller driverDilip Kota
Add driver for the reset controller present on Intel Gateway SoCs for performing reset management of the devices present on the SoC. Driver also registers a reset handler to peform the entire device reset. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-01-03optee: model OP-TEE as a platform device/driverArd Biesheuvel
To simplify adding ACPI support to the OP-TEE driver, model it as a platform driver. This will permit us to use the generic device property layer for parsing additional properties, regardless of whether DT or ACPI is being used. Note that this change will result in the OP-TEE driver to be loaded automatically on systems that advertise the presence of OP-TEE via the device tree. Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2020-01-02cpuidle: psci: Add support for PM domains by using genpdUlf Hansson
When the hierarchical CPU topology layout is used in DT and the PSCI OSI mode is supported by the PSCI FW, let's initialize a corresponding PM domain topology by using genpd. This enables a CPU and a group of CPUs, when attached to the topology, to be power-managed accordingly. To trigger the attempt to initialize the genpd data structures let's use a subsys_initcall, which should be early enough to allow CPUs, but also other devices to be attached. The initialization consists of parsing the PSCI OF node for the topology and the "domain idle states" DT bindings. In case the idle states are compatible with "domain-idle-state", the initialized genpd becomes responsible of selecting an idle state for the PM domain, via assigning it a genpd governor. Note that, a successful initialization of the genpd data structures, is followed by a call to psci_set_osi_mode(), as to try to enable the OSI mode in the PSCI FW. In case this fails, we fall back into a degraded mode rather than bailing out and returning error codes. Co-developed-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
2020-01-02PM / Domains: Introduce a genpd OF helper that removes a subdomainUlf Hansson
We already have the of_genpd_add_subdomain() helper, but no corresponding of_genpd_remove_subdomain(), so let's add it. Subsequent changes starts to make use of it. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
2020-01-02cpuidle: psci: Support CPU hotplug for the hierarchical modelUlf Hansson
When the hierarchical CPU topology is used and when a CPU is put offline, that CPU prevents its PM domain from being powered off, which is because genpd observes the corresponding attached device as being active from a runtime PM point of view. Furthermore, any potential master PM domains are also prevented from being powered off. To address this limitation, let's add add a new CPU hotplug state (CPUHP_AP_CPU_PM_STARTING) and register up/down callbacks for it, which allows us to deal with runtime PM accordingly. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
2020-01-02cpuidle: psci: Manage runtime PM in the idle pathUlf Hansson
In case we have succeeded to attach a CPU to its PM domain, let's deploy runtime PM support for the corresponding attached device, to allow the CPU to be powered-managed accordingly. The triggering point for when runtime PM reference counting should be done, has been selected to the deepest idle state for the CPU. However, from the hierarchical point view, there may be good reasons to do runtime PM reference counting even on shallower idle states, but at this point this isn't supported, mainly due to limitations set by the generic PM domain. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
2020-01-02cpuidle: psci: Prepare to use OS initiated suspend mode via PM domainsUlf Hansson
The per CPU variable psci_power_state, contains an array of fixed values, which reflects the corresponding arm,psci-suspend-param parsed from DT, for each of the available CPU idle states. This isn't sufficient when using the hierarchical CPU topology in DT, in combination with having PSCI OS initiated (OSI) mode enabled. More precisely, in OSI mode, Linux is responsible of telling the PSCI FW what idle state the cluster (a group of CPUs) should enter, while in PSCI Platform Coordinated (PC) mode, each CPU independently votes for an idle state of the cluster. For this reason, introduce a per CPU variable called domain_state and implement two helper functions to read/write its value. Then let the domain_state take precedence over the regular selected state, when entering and idle state. To avoid executing the above OSI specific code in the ->enter() callback, while operating in the default PSCI Platform Coordinated mode, let's also add a new enter-function and use it for OSI. Co-developed-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
2020-01-02cpuidle: psci: Attach CPU devices to their PM domainsUlf Hansson
In order to enable a CPU to be power managed through its PM domain, let's try to attach it by calling psci_dt_attach_cpu() during the cpuidle initialization. psci_dt_attach_cpu() returns a pointer to the attached struct device, which later should be used for runtime PM, hence we need to store it somewhere. Rather than adding yet another per CPU variable, let's create a per CPU struct to collect the relevant per CPU variables. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
2020-01-02cpuidle: psci: Add a helper to attach a CPU to its PM domainUlf Hansson
Introduce a PSCI DT helper function, psci_dt_attach_cpu(), which takes a CPU number as an in-parameter and tries to attach the CPU's struct device to its corresponding PM domain. Let's makes use of dev_pm_domain_attach_by_name(), as it allows us to specify "psci" as the "name" of the PM domain to attach to. Additionally, let's also prepare the attached device to be power managed via runtime PM. Note that, the implementation of the new helper function is in a new separate c-file, which may seems a bit too much at this point. However, subsequent changes that implements the remaining part of the PM domain support for cpuidle-psci, helps to justify this split. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
2020-01-02cpuidle: psci: Support hierarchical CPU idle statesUlf Hansson
Currently CPU's idle states are represented using the flattened model. Let's add support for the hierarchical layout, via converting to use of_get_cpu_state_node(). Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
2020-01-02cpuidle: psci: Simplify OF parsing of CPU idle state nodesUlf Hansson
Iterating through the idle state nodes in DT, to find out the number of states that needs to be allocated is unnecessary, as it has already been done from dt_init_idle_driver(). Therefore, drop the iteration and use the number we already have at hand. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
2020-01-02cpuidle: dt: Support hierarchical CPU idle statesLina Iyer
Currently CPU's idle states are represented using the flattened model. Let's add support for the hierarchical layout, via converting to use of_get_cpu_state_node(). Suggested-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Co-developed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
2020-01-02of: base: Add of_get_cpu_state_node() to get idle states for a CPU nodeUlf Hansson
The CPU's idle state nodes are currently parsed at the common cpuidle DT library, but also when initializing data for specific CPU idle operations, as in the PSCI cpuidle driver case and qcom-spm cpuidle case. To avoid open-coding, let's introduce of_get_cpu_state_node(), which takes the device node for the CPU and the index to the requested idle state node, as in-parameters. In case a corresponding idle state node is found, it returns the node with the refcount incremented for it, else it returns NULL. Moreover, for PSCI there are two options to describe the CPU's idle states [1], either via a flattened description or a hierarchical layout. Hence, let's take both options into account. [1] Documentation/devicetree/bindings/arm/psci.yaml Suggested-by: Sudeep Holla <sudeep.holla@arm.com> Co-developed-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
2020-01-02firmware: psci: Export functions to manage the OSI modeUlf Hansson
To allow subsequent changes to implement support for OSI mode through the cpuidle-psci driver, export the existing psci_has_osi_support(). Export also a new function, psci_set_osi_mode(), that allows its caller to enable the OS-initiated CPU-suspend mode in the PSCI FW. To deal with backwards compatibility for a kernel started through a kexec call, default to set the CPU-suspend mode to the Platform Coordinated mode during boot. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
2020-01-02cpuidle: psci: Align psci_power_state count with idle state countSudeep Holla
Instead of allocating 'n-1' states in psci_power_state to manage 'n' idle states which include "ARM WFI" state, it would be simpler to have 1:1 mapping between psci_power_state and cpuidle driver states. ARM WFI state(i.e. idx == 0) is handled specially in the generic macro CPU_PM_CPU_IDLE_ENTER_PARAM and hence state[-1] is not possible. However for sake of code readability, it is better to have 1:1 mapping and not use [idx - 1] to access psci_power_state corresponding to driver cpuidle state for idx. psci_power_state[0] is default initialised to 0 and is never accessed while entering WFI state. Reported-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rafael J. Wysocki <rafael@kernel.org>
2020-01-02reset: uniphier: Add SCSSI reset control for each channelKunihiko Hayashi
SCSSI has reset controls for each channel in the SoCs newer than Pro4, so this adds missing reset controls for channel 1, 2 and 3. And more, this moves MCSSI reset ID after SCSSI. Fixes: 6b39fd590aeb ("reset: uniphier: add reset control support for SPI") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-01-02reset: Align logic and flow in managed helpersGeert Uytterhoeven
__devm_reset_control_get() and devm_reset_control_array_get() are very similar, but they do not look similar, due to inverted logic. Make them more similar, following the "bail out early" paradigm. Adjust the logic and flow in devm_reset_controller_register() to match the two other functions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
generated by cgit (git 2.34.1) at 2025-04-28 22:44:56 +0000