summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2024-01-09Merge branches 'clk-zynq', 'clk-xilinx' and 'clk-stm' into clk-nextStephen Boyd
- Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP * clk-zynq: drivers: clk: zynqmp: update divider round rate logic drivers: clk: zynqmp: calculate closest mux rate * clk-xilinx: clocking-wizard: Add support for versal clocking wizard dt-bindings: clock: xilinx: add versal compatible * clk-stm: dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform clk: stm32mp1: use stm32mp13 reset driver clk: stm32mp1: move stm32mp1 clock driver into stm32 directory
2024-01-09Merge branches 'clk-imx', 'clk-qcom', 'clk-amlogic' and 'clk-mediatek' into ↵Stephen Boyd
clk-next * clk-imx: clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() dt-bindings: clock: support i.MX93 ANATOP clock module * clk-qcom: (41 commits) clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings clk: qcom: gcc-sm8550: Mark RCGs shared where applicable clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag clk: qcom: camcc-sc8280xp: Prevent error pointer dereference clk: qcom: videocc-sm8150: Add runtime PM support clk: qcom: videocc-sm8150: Add missing PLL config property clk: qcom: videocc-sm8150: Update the videocc resets dt-bindings: clock: Update the videocc resets for sm8150 clk: qcom: rpmh: Add support for X1E80100 rpmh clocks clk: qcom: Add Global Clock controller (GCC) driver for X1E80100 dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for X1E80100 dt-bindings: clock: qcom: Add X1E80100 GCC clocks clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000 clk: qcom: branch: Add mem ops support for branch2 clocks ... * clk-amlogic: clk: meson: g12a: add CSI & ISP gates clocks clk: meson: g12a: add MIPI ISP clocks dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids * clk-mediatek: clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: brcm,kona-ccu: convert to YAML dt-bindings: arm: mediatek: move ethsys controller & convert to DT schema dt-bindings: Remove alt_ref from versal
2024-01-09Merge branches 'clk-versa', 'clk-silabs', 'clk-samsung', 'clk-starfive' and ↵Stephen Boyd
'clk-sophgo' into clk-next - Add glitch free PLL setting support to si5351 clk driver * clk-versa: clk: versaclock3: Drop ret variable clk: versaclock3: Add missing space between ')' and '{' clk: versaclock3: Use u8 return type for get_parent() callback clk: versaclock3: Avoid unnecessary padding clk: versaclock3: Update vc3_get_div() to avoid divide by zero * clk-silabs: clk: si5351: allow PLLs to be adjusted without reset dt-bindings: clock: si5351: add PLL reset mode property dt-bindings: clock: si5351: convert to yaml * clk-samsung: clk: samsung: Improve kernel-doc comments clk: samsung: Fix kernel-doc comments * clk-starfive: clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro * clk-sophgo: dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC
2024-01-09Merge branches 'clk-renesas', 'clk-rockchip', 'clk-allwinner' and ↵Stephen Boyd
'clk-cleanup' into clk-next * clk-renesas: clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1 clk: renesas: rzg2l: Check reset monitor registers clk: renesas: r9a08g045: Add IA55 pclk and its reset clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset() clk: renesas: r8a779g0: Add PCIe clocks clk: renesas: r8a779g0: Add EtherTSN clock * clk-rockchip: clk: rockchip: rk3568: Mark pclk_usb as critical clk: rockchip: rk3568: Add PLL rate for 126.4MHz clk: rockchip: rk3568: Add PLL rate for 115.2MHz * clk-allwinner: clk: sunxi-ng: nkm: remove redundant initialization of tmp_parent * clk-cleanup: clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw clk: si5341: fix an error code problem in si5341_output_clk_set_rate clk: microchip: mpfs-ccc: replace include of asm-generic/errno-base.h clk: rs9: Fix DIF OEn bit placement on 9FGV0241 clk: mmp: pxa168: Fix memory leak in pxa168_clk_init() clk: hi3620: Fix memory leak in hi3620_mmc_clk_init() clk: sp7021: fix return value check in sp7021_clk_probe()
2024-01-03clk: mediatek: add drivers for MT7988 SoCSam Shih
Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are typical MediaTek designs. Also add driver for XFIPLL clock generating the 156.25MHz clock for the XFI SerDes. It needs an undocumented software workaround and has an unknown internal design. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org [sboyd@kernel.org: Add module license to infracfg file] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03clk: mediatek: add pcw_chg_bit control for PLLs of MT7988Sam Shih
Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead of the previously hardcoded PCW_CHG_MASK macro if set. This will needed for clocks on the MT7988 SoC. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxesAngeloGioacchino Del Regno
The top_dp and top_edp muxes can be both parented to either TVDPLL1 or TVDPLL2, two identically specced PLLs for the specific purpose of giving out pixel clock: this becomes a problem when the MediaTek DisplayPort Interface (DPI) driver tries to set the pixel clock rate. In the usecase of two simultaneous outputs (using two controllers), it was seen that one of the displays would sometimes display garbled output (if any at all) and this was because: - top_edp was set to TVDPLL1, outputting X GHz - top_dp was set to TVDPLL2, outputting Y GHz - mtk_dpi calls clk_set_rate(top_edp, Z GHz) - top_dp is switched to TVDPLL1 - TVDPLL1 changes its rate, top_edp outputs the wrong rate. - eDP display is garbled To solve this issue, remove all TVDPLL1 parents from `top_dp` and all TVDPLL2 parents from `top_edp`, plus, necessarily switch both clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be able to use the right bit index for the new parents list. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231103102533.69280-4-angelogioacchino.delregno@collabora.com Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Fei Shao <fshao@chromium.org> Reviewed-by: Fei Shao <fshao@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxesAngeloGioacchino Del Regno
The top_dp and top_edp muxes can be both parented to either TVDPLL1 or TVDPLL2, two identically specced PLLs for the specific purpose of giving out pixel clock: this becomes a problem when the MediaTek DisplayPort Interface (DPI) driver tries to set the pixel clock rate. In the usecase of two simultaneous outputs (using two controllers), it was seen that one of the displays would sometimes display garbled output (if any at all) and this was because: - top_edp was set to TVDPLL1, outputting X GHz - top_dp was set to TVDPLL2, outputting Y GHz - mtk_dpi calls clk_set_rate(top_edp, Z GHz) - top_dp is switched to TVDPLL1 - TVDPLL1 changes its rate, top_edp outputs the wrong rate. - eDP display is garbled To solve this issue, remove all TVDPLL1 parents from `top_dp` and all TVDPLL2 parents from `top_edp`, plus, necessarily switch both clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be able to use the right bit index for the new parents list. Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231103102533.69280-3-angelogioacchino.delregno@collabora.com Reviewed-by: Fei Shao <fshao@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03clk: mediatek: clk-mux: Support custom parent indices for muxesAngeloGioacchino Del Regno
Add support for customized parent indices for MediaTek muxes: this is necessary for the case in which we want to exclude some clocks from a mux's parent clocks list, where the exclusions are not from the very bottom of the list but either in the middle or the beginning. Example: - MUX1 (all parents) - parent1; idx=0 - parent2; idx=1 - parent3; idx=2 - MUX1 (wanted parents) - parent1; idx=0 - parent3; idx=2 To achieve that add a `parent_index` array pointer to struct mtk_mux, then in .set_parent(), .get_parent() callbacks check if this array was populated and eventually get the index from that. Also, to avoid updating all clock drivers for all SoCs, rename the "main" macro to __GATE_CLR_SET_UPD_FLAGS (so, `__` was added) and add the new member to it; furthermore, GATE_CLK_SET_UPD_FLAGS has been reintroduced as being fully compatible with the older version. The new parent_index can be specified with the new `_INDEXED` variants of the MUX_GATE_CLR_SET_UPD_xxxx macros. Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231103102533.69280-2-angelogioacchino.delregno@collabora.com Tested-by: Fei Shao <fshao@chromium.org> Reviewed-by: Fei Shao <fshao@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_txEmil Renner Berthing
This is needed by the dwmac-starfive ethernet driver to set the clock for 1000, 100 and 10 Mbps links properly. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Link: https://lore.kernel.org/r/20231219232442.2460166-3-cristian.ciocaltea@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03clk: starfive: Add flags argument to JH71X0__MUX macroEmil Renner Berthing
This flag is needed to add the CLK_SET_RATE_PARENT flag on the gmac_tx clock on the JH7100, which in turn is needed by the dwmac-starfive driver to set the clock properly for 1000, 100 and 10 Mbps links. This change was mostly made using coccinelle: @ match @ expression idx, name, nparents; @@ JH71X0__MUX( -idx, name, nparents, +idx, name, 0, nparents, ...) Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Link: https://lore.kernel.org/r/20231219232442.2460166-2-cristian.ciocaltea@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-21clk: imx: pll14xx: change naming of fvco to foutShengjiu Wang
pll14xx_calc_rate() output the fout clock not the fvco clock The relation of fvco and fout is: fout = fvco / (1 << sdiv) So use correct naming for the clock. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.kernel.org/r/1703068389-6130-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-12-20clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocksAlexander Stein
To be compatible with SCU firmware based on 1.15 a different clock routing for LVDS is needed. Signed-off-by: Oliver F. Brown <oliver.brown@oss.nxp.com> Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20231218122407.2757175-1-alexander.stein@ew.tq-group.com/ Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-12-20clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu()Kuan-Wei Chiu
In cases where imx_clk_is_resource_owned() returns false, the code path does not handle the failure gracefully, potentially leading to a memory leak. This fix ensures proper cleanup by freeing the allocated memory for 'clk_node' before returning. Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/all/20231210171907.3410922-1-visitorckw@gmail.com/ Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-12-19clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL configKonrad Dybcio
These values were missing. Add them. Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231219-topic-8650_clks-v1-2-5672bfa0eb05@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL configKonrad Dybcio
These values were missing. Add them. Fixes: 8676fd4f3874 ("clk: qcom: add the SM8650 GPU Clock Controller driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231219-topic-8650_clks-v1-1-5672bfa0eb05@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: dispcc-sm8550: Use the correct PLL configuration functionKonrad Dybcio
To ensure that all fields (particularly CAL_L and CAL_L_RINGOSC) are filled properly, use the correct prepare function for OLE PLLs. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-9-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: dispcc-sm8550: Update disp PLL settingsKonrad Dybcio
The settings in the driver seem to have been taken from an older release. Update them to match the latest values. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-8-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gpucc-sm8550: Update GPU PLL settingsKonrad Dybcio
The settings in the driver seem to have been taken from an older release. Update them to match the latest values. Fixes: bfae40744b33 ("clk: qcom: gpucc-sm8550: Add support for graphics clock controller") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-7-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gcc-sm8550: Mark RCGs shared where applicableKonrad Dybcio
The vast majority of shared RCGs were not marked as such. Fix it. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-6-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCsKonrad Dybcio
The PCIe GDSCs can be shared with other masters and should use the APCS collapse-vote register when updating the power state. This is specifically also needed to be able to disable power domains that have been enabled by boot firmware using the vote register. Following other recent Qualcomm platforms, describe this register and the corresponding mask for the PCIe (and _phy) GDSCs. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-5-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votableKonrad Dybcio
The PCIe GDSCs on most Qualcomm platforms expect the OS to always consider collapse requests as successful. This also concerns SM8550. Add the VOTABLE flag to the GDSCs in question to comply with these expectations. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-4-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flagKonrad Dybcio
All of the 8550's GCC GDSCs can and should use the retain registers so as not to lose their state when entering lower power modes. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-3-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-17clk: si5351: allow PLLs to be adjusted without resetAlvin Šipraga
Introduce a new PLL reset mode flag which controls whether or not to reset a PLL after adjusting its rate. The mode can be configured through platform data or device tree. Since commit 6dc669a22c77 ("clk: si5351: Add PLL soft reset"), the driver unconditionally resets a PLL whenever its rate is adjusted. The rationale was that a PLL reset was required to get three outputs working at the same time. Before this change, the driver never reset the PLLs. Commit b26ff127c52c ("clk: si5351: Apply PLL soft reset before enabling the outputs") subsequently introduced an option to reset the PLL when enabling a clock output that sourced it. Here, the rationale was that this is required to get a deterministic phase relationship between multiple output clocks. This clearly shows that it is useful to reset the PLLs in applications where multiple clock outputs are used. However, the Si5351 also allows for glitch-free rate adjustment of its PLLs if one avoids resetting the PLL. In our audio application where a single Si5351 clock output is used to supply a runtime adjustable bit clock, this unconditional PLL reset behaviour introduces unwanted glitches in the clock output. It would appear that the problem being solved in the former commit may be solved by using the optional device tree property introduced in the latter commit, obviating the need for an unconditional PLL reset after rate adjustment. But it's not OK to break the default behaviour of the driver, and it cannot be assumed that all device trees are using the property introduced in the latter commit. Hence, the new behaviour is made opt-in. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Jacob Siverskog <jacob@teenage.engineering> Cc: Sergej Sawazki <sergej@taudac.com> Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lore.kernel.org/r/20231124-alvin-clk-si5351-no-pll-reset-v6-3-69b82311cb90@bang-olufsen.dk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: si5341: fix an error code problem in si5341_output_clk_set_rateSu Hui
regmap_bulk_write() return zero or negative error code, return the value of regmap_bulk_write() rather than '0'. Fixes: 3044a860fd09 ("clk: Add Si5341/Si5340 driver") Acked-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Su Hui <suhui@nfschina.com> Link: https://lore.kernel.org/r/20231101031633.996124-1-suhui@nfschina.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: versaclock3: Drop ret variableBiju Das
Drop ret variable from vc3_clk_mux_determine_rate(). While at it, return the value returned by regmap_* wherever possible instead of returning 0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-6-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: versaclock3: Add missing space between ')' and '{'Biju Das
Add missing space between ')' and '{' for hw.init initialization. While at it, update the macro VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a->0xa. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-5-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: versaclock3: Use u8 return type for get_parent() callbackBiju Das
The return type of get_parent() member in struct clk_ops is u8. Use same return type for corresponding callback function as well. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-4-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: versaclock3: Avoid unnecessary paddingBiju Das
Move long/pointer variables at the beginning of struct to avoid unnecessary padding. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-3-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: versaclock3: Update vc3_get_div() to avoid divide by zeroBiju Das
Update vc3_get_div() to avoid divide by zero operation on vc3_div_round_rate() by returning1, if there is no table match found. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-2-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: stm32mp1: use stm32mp13 reset driverGabriel Fernandez
STM32MP15 is now using the same reset driver as STM32MP13 as they have the same binding requirement. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20231208143700.354785-3-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: stm32mp1: move stm32mp1 clock driver into stm32 directoryGabriel Fernandez
Move all STM32MP clock drivers into same directory (stm32). Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20231208143700.354785-2-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clocking-wizard: Add support for versal clocking wizardShubhrajyoti Datta
Add support for Clocking Wizard for Versal adaptive compute acceleration platforms. The Versal clocking wizard differs in the programming model and the register layout. The CLKFBOUT_1 registers are at offset of 0x200 instead of the 0x330 in Versal. In Versal clocking wizard the low and high time is programmed instead of the divisor. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Link: https://lore.kernel.org/r/20231214105125.26919-3-shubhrajyoti.datta@amd.com [sboyd@kernel.org: Stop initializing spinlock flags] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: microchip: mpfs-ccc: replace include of asm-generic/errno-base.hConor Dooley
As evidenced by the fact that only 2 other drivers include this header, it is not a normal thing to do. Including the regular version of this header is far more conventional for drivers. Acked-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231214-dipper-earshot-72eef3059961@spud Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-17clk: rs9: Fix DIF OEn bit placement on 9FGV0241Marek Vasut
On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE1 is BIT(2), on the other chips like 9FGV0441 and 9FGV0841 DIF OE0 is BIT(0) and so on. Increment the index in BIT() macro instead of the result of BIT() macro to shift the bit correctly on 9FGV0241. Fixes: 603df193ec51 ("clk: rs9: Support device specific dif bit calculation") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/r/20231105200642.62792-1-marek.vasut+renesas@mailbox.org Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-16drivers: clk: zynqmp: update divider round rate logicJay Buddhabhatti
Currently zynqmp divider round rate is considering single parent and calculating rate and parent rate accordingly. But if divider clock flag is set to SET_RATE_PARENT then its not trying to traverse through all parent rate and not selecting best parent rate from that. So use common divider_round_rate() which is traversing through all clock parents and its rate and calculating proper parent rate. Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Link: https://lore.kernel.org/r/20231129112916.23125-3-jay.buddhabhatti@amd.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-16drivers: clk: zynqmp: calculate closest mux rateJay Buddhabhatti
Currently zynqmp clock driver is not calculating closest mux rate and because of that Linux is not setting proper frequency for CPU and not able to set given frequency for dynamic frequency scaling. E.g., In current logic initial acpu clock parent and frequency as below apll1 0 0 0 2199999978 0 0 50000 Y acpu0_mux 0 0 0 2199999978 0 0 50000 Y acpu0_idiv1 0 0 0 2199999978 0 0 50000 Y acpu0 0 0 0 2199999978 0 0 50000 Y After changing acpu frequency to 549999994 Hz using CPU freq scaling its selecting incorrect parent which is not closest frequency. rpll_to_xpd 0 0 0 1599999984 0 0 50000 Y acpu0_mux 0 0 0 1599999984 0 0 50000 Y acpu0_div1 0 0 0 533333328 0 0 50000 Y acpu0 0 0 0 533333328 0 0 50000 Y Parent should remain same since 549999994 = 2199999978 / 4. So use __clk_mux_determine_rate_closest() generic function to calculate closest rate for mux clock. After this change its selecting correct parent and correct clock rate. apll1 0 0 0 2199999978 0 0 50000 Y acpu0_mux 0 0 0 2199999978 0 0 50000 Y acpu0_div1 0 0 0 549999995 0 0 50000 Y acpu0 0 0 0 549999995 0 0 50000 Y Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Link: https://lore.kernel.org/r/20231129112916.23125-2-jay.buddhabhatti@amd.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-16clk: mmp: pxa168: Fix memory leak in pxa168_clk_init()Kuan-Wei Chiu
In cases where mapping of mpmu/apmu/apbc registers fails, the code path does not handle the failure gracefully, potentially leading to a memory leak. This fix ensures proper cleanup by freeing the allocated memory for 'pxa_unit' before returning. Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Link: https://lore.kernel.org/r/20231210175232.3414584-1-visitorckw@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-16clk: hi3620: Fix memory leak in hi3620_mmc_clk_init()Kuan-Wei Chiu
In cases where kcalloc() fails for the 'clk_data->clks' allocation, the code path does not handle the failure gracefully, potentially leading to a memory leak. This fix ensures proper cleanup by freeing the allocated memory for 'clk_data' before returning. Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com> Link: https://lore.kernel.org/r/20231210165040.3407545-1-visitorckw@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-16clk: sp7021: fix return value check in sp7021_clk_probe()Yang Yingliang
devm_platform_ioremap_resource() never returns NULL pointer, it will return ERR_PTR() when it fails, so replace the check with IS_ERR(). Fixes: d54c1fd4a51e ("clk: Add Sunplus SP7021 clock driver") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20231128133016.2494699-1-yangyingliang@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-12-15clk: qcom: camcc-sc8280xp: Prevent error pointer dereferenceDan Carpenter
If "regmap" is an error pointer then calling regmap_update_bits() will crash. We only need to call regmap_update_bits() if we had written to it earlier. Fixes: ff93872a9c61 ("clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/210d48ce-6ebc-4a6b-b30f-866d10d41a16@moroto.mountain Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15clk: qcom: videocc-sm8150: Add runtime PM supportSatya Priya Kakitapalli
Add runtime PM support to ensure the supply rails are enabled when necessary. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-4-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15clk: qcom: videocc-sm8150: Add missing PLL config propertySatya Priya Kakitapalli
When the driver was ported upstream, PLL test_ctl_hi1 register value was omitted. Add it to ensure the PLLs are fully configured. Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-3-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15clk: qcom: videocc-sm8150: Update the videocc resetsSatya Priya Kakitapalli
Add all the available resets for the video clock controller on sm8150. Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-2-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-13clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1Claudiu Beznea
RZ/G3S has 2 Gigabit Ethernet interfaces available. Add clock and reset support for both of them. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-13clk: renesas: rzg2l: Check reset monitor registersClaudiu Beznea
The hardware manual of both RZ/G2L and RZ/G3S specifies that the reset monitor registers need to be interrogated when the reset signals are toggled (chapters "Procedures for Supplying and Stopping Reset Signals" and "Procedure for Activating Modules"). Without this, there is a chance that different modules (e.g. Ethernet) are not ready after their reset signal is toggled, leading to failures (on probe or resume from deep sleep states). The same indications are available for RZ/V2M for TYPE-B reset controls. Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC") Fixes: 8090bea32484 ("clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg") Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-13clk: renesas: r9a08g045: Add IA55 pclk and its resetClaudiu Beznea
An IA55 interrupt controller is available on the RZ/G3S SoC. Add the IA55 pclk and its reset. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231120111820.87398-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-07clk: qcom: rpmh: Add support for X1E80100 rpmh clocksRajendra Nayak
Adds the RPMH clocks present in X1E80100 SoC Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231205061002.30759-5-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: Add Global Clock controller (GCC) driver for X1E80100Rajendra Nayak
Add support for the global clock controller found on X1E80100 based devices. Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231205061002.30759-3-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000Imran Shaik
Add ECPRI Clock Controller (ECPRICC) support for QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231123064735.2979802-4-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit (git 2.34.1) at 2025-05-11 23:00:11 +0000