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path: root/include/drm/i915_pciids.h
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2024-02-14drm/i915: Update ADL-N PCI IDsGustavo Sousa
Extend the list of ADL-N PCI IDs to contain two new entries. Bspec: 68397 Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240214144629.106702-2-gustavo.sousa@intel.com
2024-01-18drm/i915: Add additional ARL PCI IDsMatt Roper
Our existing MTL driver handling is also sufficient to handle ARL, so these IDs are simply added to the MTL ID list. Bspec: 55420 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240108122738.14399-2-haridhar.kalvala@intel.com
2023-11-21drm/i915: ATS-M device ID updateHaridhar Kalvala
ATS-M device ID update. BSpec: 44477 Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231120113731.1570589-1-haridhar.kalvala@intel.com
2023-10-12drm/i915: Add new DG2 PCI IDsShekhar Chauhan
Add recently added PCI IDs for DG2 BSpec: 44477 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231011080039.2781048-1-shekhar.chauhan@intel.com
2023-10-04Merge drm/drm-next into drm-intel-nextJani Nikula
Backmerge to sync up with drm-intel-gt-next and drm-misc-next. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2023-08-24drm/i915/rpl: Update pci ids for RPL P/UDnyaneshwar Bhadane
Update pci device ids as per bspec for RPL P/U. v2: - Append new id's instead of replacing the existing in device id list define v3: - Fixed the commit messege with revision details. Bpsec: 55376 Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230824062840.2372872-1-dnyaneshwar.bhadane@intel.com
2023-08-23drm/i915/mtl: Adding DeviceID for Arrowlake-S under MTLNemesa Garg
Arrowlake-S graphics is similar enough to Meteorlake that we can treat them as the same platform Signed-off-by: Nemesa Garg <nemesa.garg@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230822172743.2113377-1-nemesa.garg@intel.com
2023-08-21drm/i915/mtl: Eliminate subplatformsMatt Roper
Now that we properly match the Xe_LPG IP versions associated with various workarounds, there's no longer any need to define separate MTL subplatform in the driver. Nothing in the code is conditional on MTL-M or MTL-P base platforms. Furthermore, I'm not sure the "M" and "P" designations are even an accurate representation of which specific platforms would have which IP versions; those were mostly just placeholders from a long time ago. The reality is that the IP version present on a platform gets read from a fuse register at driver init; we shouldn't be trying to guess which IP is present based on PCI ID anymore. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Nemesa Garg <nemesa.garg@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-18-matthew.d.roper@intel.com
2023-02-16drm/i915: Add RPL-U sub platformChaitanya Kumar Borah
Separate out RPLU device ids and add them to both RPL and newly created RPL-U subplatforms. v2: (Matt) - Sort PCI-IDs numerically - Name the sub-platform to accurately depict what it is for - Make RPL-U part of RPL subplatform v3: revert to RPL-U subplatform (Jani) v4: (Jani) - Add RPL-U ids to RPL-P platform - Remove redundant comment Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230130100806.1373883-2-chaitanya.kumar.borah@intel.com
2023-02-08drm/i915/dg2: Drop one PCI IDMatt Roper
The bspec was recently updated to remove PCI ID 0x5698; this ID is actually reserved for future use and should not be treated as DG2-G11. Bspec: 44477 Fixes: 8618b8489ba6 ("drm/i915: DG2 and ATS-M device ID updates") Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230208200905.680865-1-matthew.d.roper@intel.com
2023-02-06drm/i915: Add another EHL pci idJonathan Gray
described as "32 Execution Unit (EU) Super SKU" in: Intel Atom x6000E Series, and Intel Pentium and Celeron N and J Series Processors for IoT Applications Datasheet, Volume 1 Document Number: 636112-1.6 Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230206043727.46069-1-jsg@jsg.id.au
2022-08-26drm/i915: Add new ADL-S pci idJosé Roberto de Souza
New PCI id recently added. BSpec: 53655 Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220824133935.51560-1-jose.souza@intel.com
2022-07-08drm/i915/mtl: Add MeteorLake PCI IDsRadhakrishna Sripada
Add Meteorlake PCI IDs. Split into M, and P subplatforms. v2: Update PCI id's v3: Move id 7d60 under MTL_M(MattR) Bspec: 55420 Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220708000335.2869311-3-radhakrishna.sripada@intel.com
2022-07-01drm/i915: DG2 and ATS-M device ID updatesMatt Roper
Small BAR support has now landed, which allows us to add the PCI IDs that correspond to add-in card designs of DG2 and ATS-M. There's also one additional MB-down PCI ID that recently appeared (0x5698) so we add it too. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220701152231.529511-2-matthew.d.roper@intel.com
2022-04-27drm/i915: Add first set of DG2 PCI IDsMatt Roper
The IDs added here are the subset reserved for 'motherboard down' designs of DG2. We have all the necessary support upstream to enable these now (although they'll continue to require force_probe until the usual requirements are met). The remaining DG2 IDs for add-in cards will come in a future patch once some additional required functionality has fully landed. Bspec: 44477 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220425211251.77154-3-matthew.d.roper@intel.com
2022-04-19drm/i915/rpl-p: Add PCI IDsMatt Atwood
Adding initial PCI ids for RPL-P. RPL-P behaves identically to ADL-P from i915's point of view. Changes since V1 : - SUBPLATFORM ADL_N and RPL_P clash as both are ADLP based - Matthew R Bspec: 55376 Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> [mattrope: Corrected comment formatting to match coding style] Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220418062157.2974665-1-tejaskumarx.surendrakumar.upadhyay@intel.com
2022-03-29drm/i915: Add RPL-S PCI IDsTejas Upadhyay
Add couple of RPL-S device ids Bspec : 53655 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220322040616.1078009-1-tejaskumarx.surendrakumar.upadhyay@intel.com
2021-12-20drm/i915/adl-n: Enable ADL-N platformTejas Upadhyay
Adding PCI device ids and enabling ADL-N platform. ADL-N from i915 point of view is subplatform of ADL-P. BSpec: 68397 Changes since V2: - Added version log history Changes since V1: - replace IS_ALDERLAKE_N with IS_ADLP_N - Jani Nikula Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211210051802.4063958-1-tejaskumarx.surendrakumar.upadhyay@intel.com
2021-12-08drm/i915/rpl-s: Add PCI IDS for Raptor Lake SAnusha Srivatsa
Raptor Lake S(RPL-S) is a version 12 Display, Media and Render. For all i915 purposes it is the same as Alder Lake S (ADL-S). Introduce RPL-S as a subplatform of ADL-S. This patch adds PCI ids for RPL-S. BSpec: 53655 Cc: x86@kernel.org Cc: dri-devel@lists.freedesktop.org Cc: Ingo Molnar <mingo@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> # arch/x86 Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211203063545.2254380-2-anusha.srivatsa@intel.com
2021-09-14drm/i915/dg1: Add new PCI idJosé Roberto de Souza
New DG1 PCI id. BSpec: 44463 Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210913181909.35237-1-jose.souza@intel.com
2021-08-23drm/i915/adl_s: Update ADL-S PCI IDsTejas Upadhyay
Sync PCI IDs with Bspec. Bspec:53655 Changes since V2: - Upstream devices which are "POR" yes and "Ok to upstream" yes - James Asmus Changes since V1: - All POR and Non POR Ids needs to be upstreamed - James Asmus Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210818050116.1116237-1-tejaskumarx.surendrakumar.upadhyay@intel.com
2021-05-07drm/i915/adl_p: Add PCI Devices IDsClinton Taylor
Add 18 known PCI device IDs Bspec: 55376 Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210506161930.309688-3-imre.deak@intel.com
2021-04-29drm/i915/adl_s: ADL-S platform Update PCI ids for Mobile BGAAnand Moon
As per Bspec: 53655 Update PCI ids for Mobile BGA. Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Anand Moon <anandx.ram.moon@intel.com> Reviewed-by: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210203091029.2089-1-anandx.ram.moon@intel.com
2021-01-20drm/i915/adl_s: Add ADL-S platform info and PCI idsCaz Yokoyama
- Add the initial platform information for Alderlake-S. - Specify ppgtt_size value - Add dma_mask_size - Add ADLS REVIDs - HW tracking(Selective Update Tracking Enable) has been removed from ADLS. Disable PSR2 till we enable software/ manual tracking. v2: - Add support for different ADLS SOC steppings to select correct GT/DISP stepping based on Bspec 53655 based on feedback from Matt Roper.(aswarup) v3: - Make display/gt steppings info generic for reuse with TGL and ADLS. - Modify the macros to reuse tgl_revids_get() - Add HTI support to adls device info.(mdroper) v4: - Rebase on TGL patch for applying WAs based on stepping info from Matt Roper's feedback.(aswarup) v5: - Replace macros with PCI IDs in revid to stepping table. v6: remove stray adls_revids (Lucas) Bspec: 53597 Bspec: 53648 Bspec: 53655 Bspec: 48028 Bspec: 53650 BSpec: 50422 Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210119192931.1116500-2-lucas.demarchi@intel.com
2020-11-06drm/i915: Sort EHL/JSL PCI IDsVille Syrjälä
Sort the EHL/JSL PCI IDs numerically. Some order seems better than randomness. v2: Deal with the JSL vs. EHL split v3: Rebase due to 0x4500 removal Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201030164124.16922-1-ville.syrjala@linux.intel.com
2020-11-03drm/i915/ehl: Remove invalid PCI IDAnusha Srivatsa
Update the EHL PCI IDs from BSpec. Remove the invalid ones. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201102193034.28055-1-anusha.srivatsa@intel.com
2020-10-20drm/i915: Sort ICL PCI IDsVille Syrjälä
Sort the ICL PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov <apodtele@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-14-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-20drm/i915: Sort CNL PCI IDsVille Syrjälä
Sort the CNL PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov <apodtele@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-13-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-20drm/i915: Sort CFL PCI IDsVille Syrjälä
Sort the CFL PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov <apodtele@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-12-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-20drm/i915: Sort CML PCI IDsVille Syrjälä
Sort the CML PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov <apodtele@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-11-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-20drm/i915: Sort KBL PCI IDsVille Syrjälä
Sort the KBL PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov <apodtele@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-10-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-20drm/i915: Sort SKL PCI IDsVille Syrjälä
Sort the SKL PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov <apodtele@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-9-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-20drm/i915: Sort HSW PCI IDsVille Syrjälä
Sort the HSW PCI IDs numerically. Some order seems better than randomness. Cc: Alexei Podtelezhnikov <apodtele@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-8-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-20drm/i915: Ocd the HSW PCI ID hex numbersVille Syrjälä
Most of the HSW PCI IDs are upper case hex numbers, but a few are lower case. Make it consistent so these don't stick out like a sore thumb. Cc: Alexei Podtelezhnikov <apodtele@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-7-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-20drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e commentsVille Syrjälä
Bunch of the SKL SKUs currently documented as GT3/4 seem to actually be GT3e/4e. Fix up the comments. Cc: Alexei Podtelezhnikov <apodtele@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-6-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-20drm/i915: Add SKL GT1.5 PCI IDsAlexei Podtelezhnikov
Add three new devices 0x1913, 0x1915, and 0x1917 also known as iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15. Signed-off-by: Alexei Podtelezhnikov <apodtele@gmail.com> [vsyrjala: Split separate changes into separate patchs, Sort the IDs] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-5-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-20drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULTAlexei Podtelezhnikov
Reclassify 0x1923, 0x1927 according to specifications. Of note, the second to last digit seems to correspond to GT#. Signed-off-by: Alexei Podtelezhnikov <apodtele@gmail.com> [vsyrjala: Split separate changes into separate patches, Sort the IDs] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-4-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-20drm/i915: Reclassify SKL 0x192a as GT3Alexei Podtelezhnikov
Reclassify 0x192A according to specifications. Of note, the second to last digit seems to correspond to GT#. Signed-off-by: Alexei Podtelezhnikov <apodtele@gmail.com> [vsyrjala: Split separate changes into separate patches] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-3-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-20drm/i915: Update Haswell PCI IDsAlexei Podtelezhnikov
Reclassify 0x0426 as GT3 (GT2+) according to specifications and the second least significant digit. Signed-off-by: Alexei Podtelezhnikov <apodtele@gmail.com> [vsyrjala: s/GT2/GT3/ in the comment] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200716172106.2656-2-ville.syrjala@linux.intel.com Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2020-10-14drm/i915/jsl: Split EHL/JSL platform info and PCI idsTejas Upadhyay
Recently we came across requirement to identify EHL and JSL platform to program them differently. Thus Split the basic platform definition, macros, and PCI IDs to differentiate between EHL and JSL platforms. Also, IS_ELKHARTLAKE is replaced with IS_JSL_EHL everywhere. Changes since V1 : - Rebased to avoid merge conflicts - Added missed check for jasperlake in intel_uc_fw.c Cc : Matt Roper <matthew.d.roper@intel.com> Cc : Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201013192948.63470-1-tejaskumarx.surendrakumar.upadhyay@intel.com
2020-10-07drm/i915/dg1: add more PCI idsLucas De Marchi
Synchronize with the current list of DG1 PCI IDs. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201007002210.3678024-1-lucas.demarchi@intel.com
2020-08-31drm/i915: break TGL pci-ids in GT 1 & 2Lionel Landwerlin
I'll need this in IGT to identify the different kind of GTs and apply the right performance query configuration. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200828133125.157171-1-lionel.g.landwerlin@intel.com
2020-08-17drm/i915: Remove dubious Valleyview PCI IDsAlexei Podtelezhnikov
0x0155 is rather Ivy Bridge PCI-E Root Port. 0x0157 from the same commit ff049b6ce21d ("drm/i915: bind driver to ValleyView chipsets") is likely wrong too. Nowhere is it independetly confirmed or mentioned. Signed-off-by: Alexei Podtelezhnikov <apodtele@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200428034752.3975-1-apodtele@gmail.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2020-07-14drm/i915/dg1: Add DG1 PCI IDsAbdiel Janulgue
Add the PCI ID for DG1, but keep it out of the table we use to register the driver. At this point we can't consider the driver ready to bind to the device since we basically miss support for everything. When more support is merged we can enable it to work partially for example as a display-only driver. v2: remove DG1 from the pci table and reword commit message (Lucas) Bspec: 44463 Cc: Matthew Auld <matthew.auld@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> # v1 Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20200713182321.12390-3-lucas.demarchi@intel.com
2020-07-07drm/i915/ehl: Add new PCI idsJosé Roberto de Souza
Two new PCI ids added to ehl. v2: added two additional PCI ids BSpec: 29153 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200707204530.42289-1-jose.souza@intel.com
2020-05-19drm/i915/rkl: Add RKL platform info and PCI idsMatt Roper
Introduce the basic platform definition, macros, and PCI IDs. Bspec: 44501 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Caz Yokoyama <caz.yokoyama@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200504225227.464666-2-matthew.d.roper@intel.com
2020-03-18drm/i915/tgl: Add new PCI IDs to TGLSwathi Dhanavanthri
Adding 4 new PCI IDs to TGL Bspec: 44455 Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200318221240.8180-1-swathi.dhanavanthri@intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
2019-12-12drm/i915/cml: Separate U series pci id from origianl list.Lee Shawn C
U series device need different DDI buffer setup for eDP and DP. If driver did not recognize ULT id proerply. The setting for H and S series would be used. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191210150415.10705-2-shawn.c.lee@intel.com
2019-12-12drm/i915/cml: Remove unsupport PCI IDLee Shawn C
commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)' introduced new PCI ID that CML support. But some PCI IDs were removed in BSpec for CML. This patch is used to eliminate the unsed ID. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191210150415.10705-1-shawn.c.lee@intel.com
2019-12-06drm/i915: Add new EHL/JSL PCI idsJosé Roberto de Souza
Adding the recently added EHL/JSL PCI ids. BSpec: 29153 Cc: James Ausmus <james.ausmus@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191203211308.109703-1-jose.souza@intel.com
generated by cgit (git 2.34.1) at 2024-05-25 09:53:41 +0000