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2019-05-21treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13Thomas Gleixner
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details [based] [from] [clk] [highbank] [c] you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 355 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154041.837383322@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 4Thomas Gleixner
Based on 1 normalized pattern(s): licensed under gplv2 or later extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 118 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154040.961286471@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 1Thomas Gleixner
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin street fifth floor boston ma 02110 1301 usa this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option [no]_[pad]_[ctrl] any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin street fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 176 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190519154040.652910950@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-16Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM Device-tree updates from Olof Johansson: "Besides new bindings and additional descriptions of hardware blocks for various SoCs and boards, the main new contents here is: SoCs: - Intel Agilex (SoCFPGA) - NXP i.MX8MM (Quad Cortex-A53 with media/graphics focus) New boards: - Allwinner: + RerVision H3-DVK (H3) + Oceanic 5205 5inMFD (H6) + Beelink GS2 (H6) + Orange Pi 3 (H6) - Rockchip: + Orange Pi RK3399 + Nanopi NEO4 + Veyron-Mighty Chromebook variant - Amlogic: + SEI Robotics SEI510 - ST Micro: + stm32mp157a discovery1 + stm32mp157c discovery2 - NXP: + Eckelmann ci4x10 (i.MX6DL) + i.MX8MM EVK (i.MX8MM) + ZII i.MX7 RPU2 (i.MX7) + ZII SPB4 (VF610) + Zii Ultra (i.MX8M) + TQ TQMa7S (i.MX7Solo) + TQ TQMa7D (i.MX7Dual) + Kobo Aura (i.MX50) + Menlosystems M53 (i.MX53)j - Nvidia: + Jetson Nano (Tegra T210)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (593 commits) arm64: dts: bitmain: Add UART pinctrl support for Sophon Edge arm64: dts: bitmain: Add pinctrl support for BM1880 SoC arm64: dts: bitmain: Add GPIO Line names for Sophon Edge board arm64: dts: bitmain: Add GPIO support for BM1880 SoC ARM: dts: gemini: Indent DIR-685 partition table dt-bindings: hwmon (pwm-fan) Remove dead "cooling-*-state" properties ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20 arm64: dts: msm8998: thermal: Fix number of supported sensors arm64: dts: msm8998-mtp: thermal: Remove skin and battery thermal zones arm64: dts: exynos: Move fixed-clocks out of soc arm64: dts: exynos: Move pmu and timer nodes out of soc ARM: dts: s5pv210: Fix camera clock provider on Goni board ARM: dts: exynos: Properly override node to use MDMA0 on Universal C210 ARM: dts: exynos: Move fixed-clocks out of soc on Exynos3250 ARM: dts: exynos: Remove unneeded address/size cells from fixed-clock on Exynos3250 ARM: dts: exynos: Move pmu and timer nodes out of soc arm64: dts: rockchip: fix IO domain voltage setting of APIO5 on rockpro64 arm64: dts: db820c: Add sound card support arm64: dts: apq8096-db820c: Add HDMI display support ...
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' ↵Stephen Boyd
and 'clk-spdx' into clk-next - Support for STM32F769 - Rework AT91 sckc DT bindings - Fix slow RC oscillator issue on sama5d3 - AT91 sam9x60 PMC support - SiFive FU540 PRCI and PLL support * clk-stm32f4: clk: stm32mp1: Add ddrperfm clock clk: stm32: Introduce clocks of STM32F769 board * clk-tegra: clk: tegra: divider: Mark Memory Controller clock as read-only clk: tegra: emc: Replace BUG() with WARN_ONCE() clk: tegra: emc: Fix EMC max-rate clamping clk: tegra: emc: Support multiple RAM codes clk: tegra: emc: Don't enable EMC clock manually clk: tegra124: Remove lock-enable bit from PLLM clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider clk: tegra: Don't enable already enabled PLLs * clk-at91: clk: at91: Mark struct clk_range as const clk: at91: add sam9x60 pmc driver dt-bindings: clk: at91: add bindings for SAM9X60 pmc clk: at91: add sam9x60 PLL driver clk: at91: master: Add sam9x60 support clk: at91: usb: Add sam9x60 support clk: at91: allow configuring generated PCR layout clk: at91: allow configuring peripheral PCR layout clk: at91: sckc: handle different RC startup time clk: at91: modernize sckc binding dt-bindings: clock: at91: new sckc bindings * clk-sifive-fu540: clk: sifive: add a driver for the SiFive FU540 PRCI IP block clk: analogbits: add Wide-Range PLL library dt-bindings: clk: add documentation for the SiFive PRCI driver * clk-spdx: clk: sunxi-ng: Use the correct style for SPDX License Identifier clk: sprd: Use the correct style for SPDX License Identifier clk: renesas: Use the correct style for SPDX License Identifier clk: qcom: Use the correct style for SPDX License Identifier clk: davinci: Use the correct style for SPDX License Identifier clk: actions: Use the correct style for SPDX License Identifier
2019-05-07Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' ↵Stephen Boyd
and 'clk-qoriq' into clk-next - Mark UFS clk as critical on Hi-Silicon hi3660 SoCs - Support for Cirrus Logic Lochnagar clks * clk-hisi: clk: hi3660: Mark clk_gate_ufs_subsys as critical * clk-lochnagar: clk: lochnagar: Add support for the Cirrus Logic Lochnagar clk: lochnagar: Add initial binding documentation * clk-allwinner: clk: sunxi-ng: sun5i: Export the MBUS clock clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate clk: sunxi-ng: h6: Preset hdmi-cec clock parent clk: sunxi: Add Kconfig options clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset clk: sunxi-ng: Allow DE clock to set parent rate * clk-rockchip: clk: rockchip: undo several noc and special clocks as critical on rk3288 clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288 clk: rockchip: Limit use of USB PHY clock to USB on rk3288 clk: rockchip: Fix video codec clocks on rk3288 clk: rockchip: Make rkpwm a critical clock on rk3288 clk: rockchip: fix wrong clock definitions for rk3328 * clk-qoriq: clk: qoriq: increase array size of cmux_to_group dt-bindings: qoriq-clock: Add ls1028a chip compatible string clk: qoriq: Add ls1028a clock configuration clk: qoriq: add more PLL divider clocks support dt-bindings: qoriq-clock: add more PLL divider clocks support
2019-05-07Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and ↵Stephen Boyd
'clk-zynq' into clk-next - Various static analysis fixes/finds - Video Engine (ECLK) support on Aspeed SoCs - Xilinx ZynqMP Versal platform support - Convert Xilinx ZynqMP driver to be struct oriented * clk-sa: clk: mvebu: fix spelling mistake "gatable" -> "gateable" clk: ux500: add range to usleep_range clk: tegra: Make tegra_clk_super_mux_ops static clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5 * clk-aspeed: clk: Aspeed: Setup video engine clocking * clk-samsung: clk: samsung: exynos5410: Add gate clock for ADC clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410 clk: samsung: dt-bindings: Put CLK_UART3 in order * clk-ingenic: clk: ingenic: jz4725b: Add UDC PHY clock dt-bindings: clock: jz4725b-cgu: Add UDC PHY clock * clk-zynq: clk: zynqmp: use structs for clk query responses clk: zynqmp: fix check for fractional clock clk: zynqmp: do not export zynqmp_clk_register_* functions clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parents drivers: clk: Update clock driver to handle clock attribute drivers: clk: zynqmp: Allow zero divisor value
2019-05-07Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and ↵Stephen Boyd
'clk-basic-be' into clk-next - Remove clk_readl() and introduce BE versions of basic clk types * clk-doc: clk: Drop duplicate clk_register() documentation clk: Document and simplify clk_core_get_rate_nolock() clk: Remove 'flags' member of struct clk_fixed_rate clk: nxp: Drop 'flags' on fixed_rate clk macro clk: Document __clk_mux_determine_rate() clk: Document CLK_MUX_READ_ONLY mux flag clk: Document deprecated things clk: Collapse gpio clk kerneldoc * clk-more-critical: clk: highbank: Convert to CLK_IS_CRITICAL * clk-meson: (21 commits) clk: meson: axg-audio: add g12a support clk: meson: axg-audio: don't register inputs in the onecell data clk: meson: axg_audio: replace prefix axg by aud dt-bindings: clk: axg-audio: add g12a support clk: meson: meson8b: add the video decoder clock trees clk: meson: meson8b: add the VPU clock trees clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2 clk: meson: meson8b: use a separate clock table for Meson8m2 dt-bindings: clock: meson8b: export the video decoder clocks clk: meson-g12a: add video decoder clocks dt-bindings: clock: meson8b: export the VPU clock clk: meson-g12a: add PCIE PLL clocks dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL dt-bindings: clock: meson8b: drop the "ABP" clock definition clk: meson: g12a: add cpu clocks dt-bindings: clk: g12a-clkc: add VDEC clock IDs dt-bindings: clock: axg-audio: unexpose controller inputs dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id ... * clk-basic-be: clk: core: replace clk_{readl,writel} with {readl,writel} clk: core: remove powerpc special handling powerpc/512x: mark clocks as big endian clk: mux: add explicit big endian support clk: multiplier: add explicit big endian support clk: gate: add explicit big endian support clk: fractional-divider: add explicit big endian support clk: divider: add explicit big endian support
2019-05-07Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and ↵Stephen Boyd
'clk-imx' into clk-next - Qualcomm QCS404 CDSP clk support - Qualcomm QCS404 Turing clk support - Mediatek MT8183 clock support - Mediatek MT8516 clock support - Milbeaut M10V clk controller support * clk-renesas: clk: renesas: rcar-gen3: Remove unused variable clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value clk: renesas: r8a77980: Fix RPC-IF module clock's parent clk: renesas: rcar-gen3: Rename DRIF clocks clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC clk: renesas: rcar-gen3: Correct parent clock of HS-USB clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI clk: renesas: r8a774c0: Add Z2 clock clk: renesas: r8a77990: Add Z2 clock clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents math64: New DIV64_U64_ROUND_CLOSEST helper clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor clk: renesas: r9a06g032: Add missing PCI USB clock clk: renesas: r7s9210: Always use readl() clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() * clk-qcom: clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998 clk: qcom: Add QCS404 TuringCC clk: qcom: branch: Add AON clock ops dt-bindings: clock: Introduce Qualcomm Turing Clock controller clk: qcom: gcc-qcs404: Add CDSP related clocks and resets * clk-mtk: clk: mediatek: add clock driver for MT8516 dt-bindings: mediatek: apmixedsys: add support for MT8516 dt-bindings: mediatek: infracfg: add support for MT8516 dt-bindings: mediatek: topckgen: add support for MT8516 clk: mediatek: Allow changing PLL rate when it is off clk: mediatek: Add MT8183 clock support clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data clk: mediatek: Add dt-bindings for MT8183 clocks dt-bindings: ARM: Mediatek: Document bindings for MT8183 clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data clk: mediatek: Add new clkmux register API clk: mediatek: Disable tuner_en before change PLL rate * clk-milbeaut: clock: milbeaut: Add Milbeaut M10V clock controller dt-bindings: clock: milbeaut: add Milbeaut clock description * clk-imx: clk: imx: correct pfdv2 gate_bit/vld_bit operations clk: imx: clk-pllv3: mark expected switch fall-throughs clk: imx8mq: Add dsi_ipg_div clk: imx: pllv4: add fractional-N pll support clk: imx: keep uart clock on during system boot clk: imx: correct i.MX7D AV PLL num/denom offset clk: imx6sll: Fix mispelling uart4_serial as serail clk: imx: pll14xx: drop unused variable clk: imx: rename clk-imx51-imx53.c to clk-imx5.c clk: imx5: Fix i.MX50 ESDHC clock registers clk: imx5: Fix i.MX50 mainbus clock registers clk: imx: Remove unused imx_get_clk_hw_fixed dt-bindings: clock: imx7ulp: remove SNVS clock clk: imx7ulp: remove snvs clock
2019-04-28Merge tag 'amlogic-dt64-2' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.2, round 2 - add display/gfx support for G12a boards - enable USB for g12a boards * tag 'amlogic-dt64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (26 commits) arm64: dts: meson-g12a-u200: Add support for Video Display arm64: dts: meson-g12a-sei510: Add support for Video Display arm64: dts: meson-g12a-x96-max: Add support for Video Display arm64: dts: meson-g12a: Add AO-CEC nodes arm64: dts: meson-g12a: Add VPU and HDMI related nodes arm64: dts: meson-g12a-x96-max: Enable USB arm64: dts: meson-g12a-u200: Enable USB arm64: dts: meson-g12a-sei510: Enable USB arm64: dts: meson-g12a-sei510: Add ADC Key and BT support arm64: dts: meson-g12a-u200: add regulators arm64: dts: meson: g12a: Add mali-g31 gpu node arm64: dts: meson: g12a: Add G12A USB nodes arm64: dts: meson: g12a: Add SAR ADC node dt-bindings: power: amlogic, meson-gx-pwrc: Add G12A compatible arm64: dts: meson-gxm: Add Mali-T820 node dt-bindings: gpu: mali-midgard: Add resets property dt-bindings: clock: meson8b: export the video decoder clocks dt-bindings: clock: meson8b: export the VPU clock dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN dt-bindings: clock: meson8b: drop the "ABP" clock definition ... Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-25dt-bindings: mediatek: apmixedsys: add support for MT8516Fabien Parent
Add binding documentation of apmixedsys for MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-25dt-bindings: mediatek: infracfg: add support for MT8516Fabien Parent
Add binding documentation of infracfg for MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-25dt-bindings: mediatek: topckgen: add support for MT8516Fabien Parent
Add binding documentation of topckgen for MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-25clk: stm32: Introduce clocks of STM32F769 boardGabriel Fernandez
STM32F769 clocks are derived from STM32746 clocks. main differences are: - new source clock for SAI1 and SAI2 (HSI or HSE) - Add DFSDM & DSI clocks Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11dt-bindings: clock: jz4725b-cgu: Add UDC PHY clockPaul Cercueil
Add macro for the UDC PHY clock of the JZ4725B. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11dt-bindings: clock: Introduce Qualcomm Turing Clock controllerBjorn Andersson
Add devicetree binding for the turing clock controller found in QCS404. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11clk: qcom: gcc-qcs404: Add CDSP related clocks and resetsBjorn Andersson
Add the clocks and resets need in order to control the Turing remoteproc. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11clk: mediatek: Add dt-bindings for MT8183 clocksWeiyi Lu
Add MT8183 clock dt-bindings, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-10clk: sunxi-ng: sun5i: Export the MBUS clockMaxime Ripard
The MBUS clock is used by the MBUS controller, so let's export it so that we can use it in our DT node. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-09dt-bindings: clock: sifive: add FU540-C000 PRCI clock constantsPaul Walmsley
Add preprocessor macros for the important PRCI output clocks that are needed by both the FU540 PRCI driver and DT data. Details are available in the FU540 manual in Chapter 7 of https://static.dev.sifive.com/FU540-C000-v1.0.pdf Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-04-08dt-bindings: clk: axg-audio: add g12a supportJerome Brunet
Add a new compatible string and additional clock ids for audio clock controller of the g12a SoC family. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190329160649.31603-2-jbrunet@baylibre.com
2019-04-01dt-bindings: clock: meson8b: export the video decoder clocksMartin Blumenstingl
Export the four video decoder clocks so they can be used by the video decoder driver: - VDEC_1 - VDEC_HCODEC - VDEC_2 - VDEC_HEVC Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190324151423.19063-2-martin.blumenstingl@googlemail.com
2019-04-01dt-bindings: clock: meson8b: export the VPU clockMartin Blumenstingl
The VPU clock is an input the the "VPU" (Video Processing Unit), which is one of the components of the display controller. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190324151104.18397-2-martin.blumenstingl@googlemail.com
2019-04-01dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCINNeil Armstrong
When submitted v2 of the G12A AO-CLK IDs, the CLKID_AO_CTS_OSCIN was moved to the internal non-exported bindings, but this clock is necessary for the second AO-CEC-B module since it embeds the 32768Hz dual-divider clock generator unlike the AO-CEC-A module. Export it back to the public bindings. Fixes: be3d960b0aeb ("dt-bindings: clk: add G12A AO Clock and Reset Bindings") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20190321092010.14382-1-narmstrong@baylibre.com
2019-04-01dt-bindings: clock: meson8b: drop the "ABP" clock definitionMartin Blumenstingl
Commit 8e1dd17c8b0e3f ("dt-bindings: clock: meson8b: export the CPU post dividers") added a new clock ID "CLKID_ABP" which contains a typo. This was fixed by adding a new (typo-free) #define CLKID_APB in commit 40d08f774c17ad ("dt-bindings: clock: meson8b: add APB clock definition"). Now that the new #define is used by the driver we can remove the old one (because the old one is not used anywhere). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190319214123.27219-2-martin.blumenstingl@googlemail.com
2019-04-01dt-bindings: clk: g12a-clkc: add VDEC clock IDsMaxime Jourdan
Expose the three clocks related to the video decoder. Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190319101138.27520-2-mjourdan@baylibre.com
2019-04-01dt-bindings: clock: axg-audio: unexpose controller inputsJerome Brunet
Remove the bindings ID of the clock input of the controller. These clocks are purely internal to the controller, exposing them was a mistake. Actually, these should not even be in the provider and have IDs to begin with. Unexpose these IDs before: * someone starts using them (even if there no valid reason to do so) * the actual clocks are removed. The fact that they exist is just the result of an ugly hack. This will be resolved in CCF when we can reference DT directly in parent table. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Maxime Jourdan <mjourdan@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190213095835.17448-1-jbrunet@baylibre.com
2019-03-22clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410Krzysztof Kozlowski
Add ID for TSADC clock to Exynos5410. Choose the same value of ID as in Exynos5420 to make it simpler/compatible in future (although clock driver code is not shared). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-03-22clk: samsung: dt-bindings: Put CLK_UART3 in orderKrzysztof Kozlowski
Order the CLK_UART3 by ID. No change in functionality. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-03-20dt-bindings: clock: imx7ulp: remove SNVS clockAnson Huang
Since i.MX7ULP B0 chip, SNVS module is moved into M4 domain, so remove it from Linux clock table. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-03-19dt-bindings: clk: g12a-clkc: add PCIE PLL clock IDNeil Armstrong
Add a clock ID for the reference clock feeding the USB3+PCIe Combo PHY. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190307141455.23879-3-narmstrong@baylibre.com
2019-03-19clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock idNeil Armstrong
When submitted v2 of the G12A AO-CLK IDs, the SAR_ADC_SEL ID was moved to the internal non-exported bindings, but this clock is necessary and mandatory for the SAR ADC bindings. Export it back to the public bindings. Fixes: be3d960b0aeb ("dt-bindings: clk: add G12A AO Clock and Reset Bindings") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190304105358.4987-1-narmstrong@baylibre.com
2019-03-19clk: meson-g12a: add cpu clock bindingsNeil Armstrong
Add Amlogic G12A Family CPU clocks bindings, only export CPU_CLK since it should be the only ID used. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190304131129.7762-2-narmstrong@baylibre.com
2019-03-18include: dt-binding: clock: Rename zynqmp header fileJolly Shah
Rename file name of ZynqMP clk dt-bindings to align with file name of reset and power dt-bindings. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-03-14Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk subsystem updates from Stephen Boyd: "We have a fairly balanced mix of clk driver updates and clk framework updates this time around. It's the usual pile of new drivers for new hardware out there and the normal small fixes and updates, but then we have some core framework changes too. In the core framework, we introduce support for a clk_get_optional() API to get clks that may not always be populated and a way to devm manage clkdev lookups registered by provider drivers. We also do some refactoring to simplify the interface between clkdev and the common clk framework so we can reuse the DT parsing and clk_get() path in provider drivers in the future. This work will continue in the next few cycles while we convert how providers specify clk parents. On the driver side, the biggest part of the dirstat is the Amlogic clk driver that got support for the G12A SoC. It dominates with almost half the overall diff, while the second largest part of the diff is in the i.MX clk driver that gained support for imx8mm SoCs. After that, we have the Actions Semiconductor and Qualcomm drivers rounding out the big part of the dirstat because they both got new hardware support for SoCs. The rest is just various updates and non-critical fixes for existing drivers. Core: - Convert a few clk bindings to JSON schema format - Add a {devm_}clk_get_optional() API - Add devm_clk_hw_register_clkdev() API to manage clkdev lookups - Start rewriting clk parent registration and supporting device links by moving around code that supports clk_get() and DT parsing of the 'clocks' property New Drivers: - Add Qualcomm MSM8998 RPM managed clks - IPA clk support on Qualcomm RPMh clk controllers - Actions Semi S500 SoC clk support - Support for fixed rate clks populated from an MMIO register - Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car V3H - Add TMU (timer) clocks on Renesas RZ/G2E - Add Amlogic G12A Always-On Clock Controller - Add 32k clock generation for Amlogic AXG - Add support for the Mali GPU clocks on Amlogic Meson8 - Add Amlogic G12A EE clock controller driver - Add missing CANFD clocks on Renesas RZ/G2M and RZ/G2E - Add i.MX8MM SoC clk driver support Removed Drivers: - Remove clps711x driver as the board support is gone Updates: - 3rd ECO fix for Mediatek MT2712 SoCs - Updates for Qualcomm MSM8998 GCC clks - Random static analysis fixes for clk drivers - Support for sleeping gpios in the clk-gpio type - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.) - Split LCDC into two clks on the Marvell MMP2 SoC - Various DT of_node refcount fixes - Get rid of CLK_IS_BASIC from TI code (yay!) - TI Autoidle clk support - Fix Amlogic Meson8 APB clock ID name - Claim input clocks through DT for Amlogic AXG and GXBB - Correct the DU (display unit) parent clock on Renesas RZ/G2E - Exynos5433 IMEM CMU crypto clk support (SlimSS) - Fix for the PLL-MIPI on the Allwinner A23 - Fix Rockchip rk3328 PLL rate calculation - Add SET_RATE_PARENT flag on display clk of Rockhip rk3066 - i.MX SCU clk driver clk_set_parent() and cpufreq support" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits) dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps clk: ti: clkctrl: Fix clkdm_name regression for TI_CLK_CLKCTRL_COMPAT clk: fixup default index for of_clk_get_by_name() clk: Move of_clk_*() APIs into clk.c from clkdev.c clk: Inform the core about consumer devices clk: Introduce of_clk_get_hw_from_clkspec() clk: core: clarify the check for runtime PM clk: Combine __clk_get() and __clk_create_clk() clk: imx8mq: add GPIO clocks to clock tree clk: mediatek: correct cpu clock name for MT8173 SoC clk: imx: Refactor entire sccg pll clk clk: imx: scu: add cpu frequency scaling support clk: mediatek: Mark bus and DRAM related clocks as critical clk: mediatek: Add flags to mtk_gate clk: mediatek: Add MUX_FLAGS macro clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks clk: ingenic: Remove set but not used variable 'enable' clk: at91: programmable: remove unneeded register read clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel clk: mediatek: add MUX_GATE_FLAGS_2 ...
2019-03-12dt-bindings: clock: imx8mq: Fix numbering overlaps and gapsAbel Vesa
IMX8MQ_CLK_USB_PHY_REF changes from 163 to 153, this way removing the gap. All the following clock ids are now decreased by 10 to keep the numbering right. Doing this, the IMX8MQ_CLK_CSI2_CORE is not overlapped with IMX8MQ_CLK_GPT1 anymore. IMX8MQ_CLK_GPT1_ROOT changes from 193 to 183 and all the following ids are updated accordingly. Reported-by: Patrick Wildt <patrick@blueri.se> Fixes: 1cf3817b ("dt-bindings: Add binding for i.MX8MQ CCM") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-03-08Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and ↵Stephen Boyd
'clk-rockchip' into clk-next - Convert a few clk bindings to JSON schema format - 3rd ECO fix for Mediatek MT2712 SoCs * clk-typo: clk: samsung: fix typo * clk-json-schema: dt-bindings: clock: Convert fixed-factor-clock to json-schema dt-bindings: clock: Convert fixed-clock binding to json-schema * clk-mtk-2712-eco: clk: mediatek: update clock driver of MT2712 dt-bindings: clock: add clock for MT2712 * clk-rockchip: clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks clk: rockchip: fix frac settings of GPLL clock for rk3328
2019-03-08Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', ↵Stephen Boyd
'clk-mtk-crit' and 'clk-mtk' into clk-next * clk-ingenic: clk: ingenic: Remove set but not used variable 'enable' clk: ingenic: Fix doc of ingenic_cgu_div_info clk: ingenic: Fix round_rate misbehaving with non-integer dividers clk: ingenic: jz4740: Fix gating of UDC clock * clk-mtk-mux: clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel clk: mediatek: add MUX_GATE_FLAGS_2 * clk-qcom-sdm845-pcie: clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks * clk-mtk-crit: clk: mediatek: Mark bus and DRAM related clocks as critical clk: mediatek: Add flags to mtk_gate clk: mediatek: Add MUX_FLAGS macro * clk-mtk: clk: mediatek: correct cpu clock name for MT8173 SoC
2019-03-08Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ↵Stephen Boyd
'clk-SA-fixes' into clk-next - Updates for qcom MSM8998 GCC clks - qcom MSM8998 RPM managed clks - Random static analysis fixes for clk drivers * clk-qcom-msm8998: clk: qcom: Make common clk_hw registrations clk: qcom: smd: Add support for MSM8998 rpm clocks clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998 clk: qcom: Add missing freq for usb30_master_clk on 8998 clk: qcom: Add CLK_SET_RATE_PARENT for 8998 branch clocks * clk-fractional-parent: clk: fractional-divider: check parent rate only if flag is set * clk-x86-mv: clk: x86: Move clk-lpss.h to platform_data/x86 * clk-SA-fixes: clk: mediatek: fix platform_no_drv_owner.cocci warnings clk: tegra: dfll: Fix debugfs_simple_attr.cocci warnings clk: qoriq: Improve an error message
2019-03-08Merge branches 'clk-qcom-rpmh', 'clk-gpio-sleep', 'clk-stm32mp1', ↵Stephen Boyd
'clk-qcom-qcs404' and 'clk-actions-s500' into clk-next - IPA clk support on Qualcomm RPMh clk controllers - Support sleeping gpios in clk-gpio type - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.) - Actions Semi S500 SoC clk support * clk-qcom-rpmh: clk: qcom: clk-rpmh: Add IPA clock support * clk-gpio-sleep: clk: clk-gpio: add support for sleeping GPIOs in gpio-gate-clk * clk-stm32mp1: dt-bindings: clock: remove unused definition for stm32mp1 clk: stm32mp1: fix bit width of hse_rtc divider clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flag clk: stm32mp1: fix HSI divider flag clk: stm32mp1: fix mcu divider table clk: stm32mp1: set ck_csi as critical clock clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocks clk: stm32mp1: parent clocks update * clk-qcom-qcs404: clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs clk: qcom: remove empty lines in clk-rcg.h * clk-actions-s500: clk: actions: Add clock driver for S500 SoC dt-bindings: clock: Add DT bindings for Actions Semi S500 CMU clk: actions: Add configurable PLL delay
2019-03-08Merge branches 'clk-imx', 'clk-samsung', 'clk-ti', 'clk-uniphier-gear' and ↵Stephen Boyd
'clk-mmp2-lcdc' into clk-next - Split LCDC into two clks on the Marvell MMP2 SoC * clk-imx: clk: imx8mq: add GPIO clocks to clock tree clk: imx: Refactor entire sccg pll clk clk: imx: scu: add cpu frequency scaling support clk: imx: imx8mm: Mark init function __init clk: imx8mq: Add the missing ARM clock dt-bindings: imx8mq-clock: Add the missing ARM clock clk: imx: imx8mq: Fix the rate propagation for arm pll clk: imx8mq: Add support for the CLKO1 clock clk: imx8mq: Fix the CLKO2 source select list clk: imx8mq: Add missing M4 clocks clk: imx: Add clock driver support for imx8mm dt-bindings: imx: Add clock binding doc for imx8mm clk: imx: Add PLLs driver for imx8mm soc clk: imx5: add imx5_SCC2_IPG_GATE clk: imx: scu: add set parent support clk: imx: scu: add fallback compatible string support clk: imx8mq: Make parent names arrays const pointers clk: imx: Make parents const pointer in mux wrappers clk: imx: Make parent_names const pointer in composite-8m * clk-samsung: clk: samsung: s3c2443: Mark expected switch fall-through clk: samsung: exynos5: Fix kfree() of const memory on setting driver_override clk: samsung: exynos5: Fix possible NULL pointer exception on platform_device_alloc() failure clk: samsung: exynos5433: Add selected IMEM clocks clk: samsung: dt-bindings: Document Exynos5433 IMEM CMU clk: samsung: exynos5433: Fix name typo in sssx clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocks clk: samsung: dt-bindings: Add Exynos5433 IMEM CMU clock IDs * clk-ti: clk: clk-twl6040: Fix imprecise external abort for pdmclk ARM: OMAP2+: hwmod: disable ick autoidling when a hwmod requires that clk: ti: check clock type before doing autoidle ops clk: ti: add a usecount for autoidle clk: ti: generalize the init sequence of clk_hw_omap clocks clk: ti: remove usage of CLK_IS_BASIC clk: ti: add new API for checking if a provided clock is an OMAP clock clk: ti: move clk_hw_omap list handling under generic part of the driver * clk-uniphier-gear: clk: uniphier: Fix update register for CPU-gear * clk-mmp2-lcdc: clk: mmp2: separate LCDC peripheral clk form the display clock dt-bindings: marvell,mmp2: Add clock id for the LCDC clock
2019-03-08Merge branches 'clk-optional', 'clk-devm-clkdev-register', 'clk-allwinner', ↵Stephen Boyd
'clk-meson' and 'clk-renesas' into clk-next - Add a {devm_}clk_get_optional() API - Add devm_clk_hw_register_clkdev() API to manage clkdev lookups * clk-optional: clk: Add (devm_)clk_get_optional() functions clk: Add comment about __of_clk_get_by_name() error values * clk-devm-clkdev-register: clk: clk-st: avoid clkdev lookup leak at remove clk: clk-max77686: Clean clkdev lookup leak and use devm clkdev: add managed clkdev lookup registration * clk-allwinner: clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it * clk-meson: (22 commits) clk: meson: meson8b: fix the naming of the APB clocks dt-bindings: clock: meson8b: add APB clock definition clk: meson: Add G12A AO Clock + Reset Controller dt-bindings: clk: add G12A AO Clock and Reset Bindings clk: meson: factorise meson64 peripheral clock controller drivers clk: meson: g12a: add peripheral clock controller dt-bindings: clk: meson: add g12a periph clock controller bindings clk: meson: pll: update driver for the g12a clk: meson: rework and clean drivers dependencies clk: meson: axg-audio does not require syscon clk: meson: use CONFIG_ARCH_MESON to enter meson clk directory clk: export some clk_hw function symbols for module drivers clk: meson: ao-clkc: claim clock controller input clocks from DT clk: meson: axg: claim clock controller input clock from DT clk: meson: gxbb: claim clock controller input clock from DT clk: meson: meson8b: add the GPU clock tree clk: meson: meson8b: use a separate clock table for Meson8 clk: meson: axg-ao: add 32k generation subtree clk: meson: gxbb-ao: replace cec-32k with the dual divider clk: meson: add dual divider clock driver ... * clk-renesas: clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLK clk: renesas: r8a774c0: Add TMU clock clk: renesas: r8a77980: Add RPC clocks clk: renesas: rcar-gen3: Add RPC clocks clk: renesas: rcar-gen3: Add spinlock clk: renesas: rcar-gen3: Factor out cpg_reg_modify() clk: renesas: r8a774c0: Correct parent clock of DU clk: renesas: r8a774a1: Add missing CANFD clock clk: renesas: r8a774c0: Add missing CANFD clock
2019-03-06Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull ARM SoC device tree updates from Arnd Bergmann: "This is a smaller update than the past few times, but with just over 500 non-merge changesets still dwarfes the rest of the SoC tree. Three new SoC platforms get added, each one a follow-up to an existing product, and added here in combination with a reference platform: - Renesas RZ/A2M (R7S9210) 32-bit Cortex-A9 Real-time imaging processor: https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza2m.html - Renesas RZ/G2E (r8a774c0) 64-bit Cortex-A53 SoC "for Rich Graphics Applications": https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg2e.html - NXP i.MX8QuadXPlus 64-bit Cortex-A35 SoC: https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X These are actual commercial products we now support with an in-kernel device tree source file: - Bosch Guardian is a product made by Bosch Power Tools GmbH, based on the Texas Instruments AM335x chip - Winterland IceBoard is a Texas Instruments AM3874 based machine used in telescopes at the south pole and elsewhere, see commit d031773169df2 for some pointers: - Inspur on5263m5 is an x86 server platform with an Aspeed ast2500 baseboard management controller. This is for running on the BMC. - Zodiac Digital Tapping Unit, apparently a kind of ethernet switch used in airplanes. - Phicomm K3 is a WiFi router based on Broadcom bcm47094 - Methode Electronics uDPU FTTdp distribution point unit - X96 Max, a generic TV box based on Amlogic G12a (S905X2) - NVIDIA Shield TV (Darcy) based on Tegra210 And then there are several new SBC, evaluation, development or modular systems that we add: - Three new Rockchips rk3399 based boards: - FriendlyElec NanoPC-T4 and NanoPi M4 - Radxa ROCK Pi 4 - Five new i.MX6 family SoM modules and boards for industrial products: - Logic PD i.MX6QD SoM and evaluation baseboad - Y Soft IOTA Draco/Hydra/Ursa family boards based on i.MX6DL - Phytec phyCORE i.MX6 UltraLite SoM and evaluation module - MYIR Tech MYD-LPC4357 development based on the NXP lpc4357 microcontroller - Chameleon96, an Intel/Altera Cyclone5 based FPGA development system in 96boards form factor - Arm Fixed Virtual Platforms(FVP) Base RevC, a purely virtual platform for corresponding to the latest "fast model" - Another Raspberry Pi variant: Model 3 A+, supported both in 32-bit and 64-bit mode. - Oxalis Evalkit V100 based on NXP Layerscape LS1012a, in 96Boards enterprise form factor - Elgin RV1108 R1 development board based on 32-bit Rockchips RV1108 For already supported boards and SoCs, we often add support for new devices after merging the drivers. This time, the largest changes include updates for - STMicroelectronics stm32mp1, which was now formally launched last week - Qualcomm Snapdragon 845, a high-end phone and low-end laptop chip - Action Semi S700 - TI AM654x, their recently merged 64-bit SoC from the OMAP family - Various Amlogic Meson SoCs - Mediatek MT2712 - NVIDIA Tegra186 and Tegra210 - The ancient NXP lpc32xx family - Samsung s5pv210, used in some older mobile phones Many other chips see smaller updates and bugfixes beyond that" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (506 commits) ARM: dts: exynos: Fix max voltage for buck8 regulator on Odroid XU3/XU4 dt-bindings: net: ti: deprecate cpsw-phy-sel bindings ARM: dts: am335x: switch to use phy-gmii-sel ARM: dts: am4372: switch to use phy-gmii-sel ARM: dts: dm814x: switch to use phy-gmii-sel ARM: dts: dra7: switch to use phy-gmii-sel arch: arm: dts: kirkwood-rd88f6281: Remove disabled marvell,dsa reference ARM: dts: exynos: Add support for secondary DAI to Odroid XU4 ARM: dts: exynos: Add support for secondary DAI to Odroid XU3 ARM: dts: exynos: Disable ARM PMU on Odroid XU3-lite ARM: dts: exynos: Add stdout path property to Arndale board ARM: dts: exynos: Add minimal clkout parameters to Exynos3250 PMU ARM: dts: exynos: Enable ADC on Odroid HC1 arm64: dts: sprd: Remove wildcard compatible string arm64: dts: sprd: Add SC27XX fuel gauge device arm64: dts: sprd: Add SC2731 charger device arm64: dts: sprd: Add ADC calibration support arm64: dts: sprd: Remove PMIC INTC irq trigger type arm64: dts: rockchip: Enable tsadc device on rock960 ARM: dts: rockchip: add chosen node on veyron devices ...
2019-03-05Merge tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds
Pull MIPS updates from Paul Burton: - Support for the MIPSr6 MemoryMapID register & Global INValidate TLB (GINVT) instructions, allowing for more efficient TLB maintenance when running on a CPU such as the I6500 that supports these. - Enable huge page support for MIPS64r6. - Optimize post-DMA cache sync by removing that code entirely for kernel configurations in which we know it won't be needed. - The number of pages allocated for interrupt stacks is now calculated correctly, where before we would wastefully allocate too much memory in some configurations. - The ath79 platform migrates to devicetree. - The bcm47xx platform sees fixes for the Buffalo WHR-G54S board. - The ingenic/jz4740 platform gains support for appended devicetrees. - The cavium_octeon, lantiq, loongson32 & sgi-ip27 platforms all see cleanups as do various pieces of core architecture code. * tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (66 commits) MIPS: lantiq: Remove separate GPHY Firmware loader MIPS: ingenic: Add support for appended devicetree MIPS: SGI-IP27: rework HUB interrupts MIPS: SGI-IP27: do boot CPU init later MIPS: SGI-IP27: do xtalk scanning later MIPS: SGI-IP27: use pr_info/pr_emerg and pr_cont to fix output MIPS: SGI-IP27: clean up bridge access and header files MIPS: SGI-IP27: get rid of volatile and hubreg_t MIPS: irq: Allocate accurate order pages for irq stack MIPS: dma-noncoherent: Remove bogus condition in dma_sync_phys() MIPS: eBPF: Remove REG_32BIT_ZERO_EX MIPS: eBPF: Always return sign extended 32b values MIPS: CM: Fix indentation MIPS: BCM47XX: Fix/improve Buffalo WHR-G54S support MIPS: OCTEON: program rx/tx-delay always from DT MIPS: OCTEON: delete board-specific link status MIPS: OCTEON: don't lie about interface type of CN3005 board MIPS: OCTEON: warn if deprecated link status is being used MIPS: OCTEON: add fixed-link nodes to in-kernel device tree MIPS: Delete unused flush_cache_sigtramp() ...
2019-02-28clk: imx8mq: add GPIO clocks to clock treeAnson Huang
i.MX8MQ has clock gate for each GPIO bank, add them into clock tree for GPIO driver to manage. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-26clk: mediatek: correct cpu clock name for MT8173 SoCSeiya Wang
Correct cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72. Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-22dt-bindings: clock: Add DT bindings for Actions Semi S500 CMUEdgar Bernardi Righi
Add devicetree bindings for Actions Semi S500 Clock Management Unit. Signed-off-by: Edgar Bernardi Righi <edgar.righi@lsitec.org.br> [Mani: Documented S500 CMU compatible] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> [sboyd@kernel.org: Fix SPDX comment style in header file] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21dt-bindings: clock: remove unused definition for stm32mp1Gabriel Fernandez
A copy of LTDC_PX and ETHCK_K (LTDC_K and ETHMAC_K) was introduced in stm32mp1 dt-bindings file by mistake. These bindings are not used and shouldn't be use to be conform with convention name of the stm32mp1 clock IP. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: qcom: clk-rpmh: Add IPA clock supportDavid Dai
The clk-rpmh driver only supports on and off RPMh clock resources. Let's extend the driver by adding support for clocks that are managed by a different type of RPMh resource known as Bus Clock Manager(BCM). The BCM is a configurable shared resource aggregator that scales performance based on a set of frequency points. The Qualcomm IP Accelerator (IPA) clock is an example of a resource that is managed by the BCM and this a requirement from the IPA driver in order to scale its core clock. Signed-off-by: David Dai <daidavid1@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21dt-bindings: marvell,mmp2: Add clock id for the LCDC clockLubomir Rintel
The peripheral clock is required for access the the LCDC registers. It is in fact separate from the "AXI clock" that is optionally used to generate the pixel clock and as such requires a separate clock id. Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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