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clk-next
- Add support for the AP sub-system clock controller in the T-Head TH1520
* clk-qcom: (71 commits)
clk: qcom: Park shared RCGs upon registration
clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks
clk: qcom: common: Add interconnect clocks support
interconnect: icc-clk: Add devm_icc_clk_register
interconnect: icc-clk: Specify master/slave ids
dt-bindings: clock: qcom: Add AHB clock for SM8150
clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks
dt-bindings: interconnect: Add Qualcomm IPQ9574 support
clk: qcom: kpss-xcc: Return of_clk_add_hw_provider to transfer the error
clk: qcom: lpasscc-sc8280xp: Constify struct regmap_config
clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocks
clk: qcom: gcc-ipq6018: update sdcc max clock frequency
clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver
dt-bindings: clock: qcom: Add SM8650 camera clock controller
dt-bindings: clock: qcom: Update the order of SC8280XP camcc header
clk: qcom: videocc-sm8550: Add SM8650 video clock controller
clk: qcom: videocc-sm8550: Add support for videocc XO clk ares
dt-bindings: clock: qcom: Add SM8650 video clock controller
dt-bindings: clock: qcom: Update SM8450 videocc header file name
clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's
...
* clk-rockchip:
dt-bindings: clock: rk3188-cru-common: remove CLK_NR_CLKS
clk: rockchip: rk3188: Drop CLK_NR_CLKS usage
clk: rockchip: Switch to use kmemdup_array()
clk: rockchip: rk3128: Add HCLK_SFC
dt-bindings: clock: rk3128: Add HCLK_SFC
dt-bindings: clock: rk3128: Drop CLK_NR_CLKS
clk: rockchip: rk3128: Drop CLK_NR_CLKS usage
clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocks
clk: rockchip: rk3128: Export PCLK_MIPIPHY
dt-bindings: clock: rk3128: Add PCLK_MIPIPHY
* clk-sophgo:
clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate()
clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id()
clk: sophgo: Add SG2042 clock driver
dt-bindings: clock: sophgo: add clkgen for SG2042
dt-bindings: clock: sophgo: add RP gate clocks for SG2042
dt-bindings: clock: sophgo: add pll clocks for SG2042
* clk-thead:
clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks
dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller
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'clk-samsung' into clk-next
* clk-renesas:
clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C
clk: renesas: r8a779h0: Add Audio clocks
clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP
dt-bindings: clock: rcar-gen2: Remove obsolete header files
dt-bindings: clock: r8a7779: Remove duplicate newline
clk: renesas: Drop "Renesas" from individual driver descriptions
clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments
clk: renesas: r8a779h0: Add VIN clocks
dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells
clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock
clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock
clk: renesas: r8a77970: Use common cpg_lock
clk: renesas: r8a779h0: Add CSI-2 clocks
clk: renesas: r8a779h0: Add ISPCS clocks
* clk-amlogic:
clk: meson: add missing MODULE_DESCRIPTION() macros
dt-bindings: clock: meson: a1: peripherals: support sys_pll input
dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL
clk: meson: c3: add c3 clock peripherals controller driver
clk: meson: c3: add support for the C3 SoC PLL clock
dt-bindings: clock: add Amlogic C3 peripherals clock controller
dt-bindings: clock: add Amlogic C3 SCMI clock controller support
dt-bindings: clock: add Amlogic C3 PLL clock controller
dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format
clk: meson: s4: fix pwm_j_div parent clock
clk: meson: s4: fix fixed_pll_dco clock
* clk-allwinner:
clk: sunxi-ng r40: Constify struct regmap_config
clk: sunxi-ng: h616: Add clock/reset for GPADC
dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks
clk: sunxi: Remove unused struct 'gates_data'
clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros
* clk-samsung:
clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical
clk: samsung: Switch to use kmemdup_array()
clk: samsung: exynos-clkout: Remove misleading of_match_table/MODULE_DEVICE_TABLE
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git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
Pull pmdomain updates from Ulf Hansson:
"pmdomain core:
- Add support for HW-managed devices
pmdomain providers:
- amlogic: Add support for the A5 and the A4 power domains
- arm: Enable system wakeups for the SCMI PM domain
- qcom/clk: Add HW-mode callbacks to allow switching of GDSC mode
pmdomain consumers:
- qcom/media/venus: Enable support for switching GDSC HW-mode on V6"
* tag 'pmdomain-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm:
pmdomain: amlogic: Constify struct meson_secure_pwrc_domain_desc
venus: pm_helpers: Use dev_pm_genpd_set_hwmode to switch GDSC mode on V6
clk: qcom: videocc: Use HW_CTRL_TRIGGER for SM8250, SC7280 vcodec GDSC's
clk: qcom: gdsc: Add set and get hwmode callbacks to switch GDSC mode
PM: domains: Add the domain HW-managed mode to the summary
PM: domains: Allow devices attached to genpd to be managed by HW
pmdomain: amlogic: Add support for A5 power domains controller
dt-bindings: power: add Amlogic A5 power domains
pmdomain: amlogic: add missing MODULE_DESCRIPTION() macros
pmdomain: arm: scmi_pm_domain: set flag GENPD_FLAG_ACTIVE_WAKEUP
pmdomain: renesas: rmobile-sysc: Use for_each_child_of_node_scoped()
pmdomain: core: Use genpd_is_irq_safe() helper
pmdomain: amlogic: Add support for A4 power domains controller
dt-bindings: power: add Amlogic A4 power domains
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git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux
Pull chrome platform updates from Tzung-Bi Shih:
"New code:
- Add "cros_ec_hwmon" driver to expose fan speed and temperature
- Add "cros_charge-control" driver to control charge thresholds and
behaviour
- Add module parameter "log_poll_period_ms" in cros_ec_debugfs for
tuning the poll period
- Support version 3 of EC_CMD_GET_NEXT_EVENT and keyboard matrix
Fixes:
- Fix a race condition in accessing MEC (Microchip EC) memory between
ACPI and kernel. Serialize the memory access by an AML (ACPI
Machine Language) mutex
- Fix an issue of wrong EC message version in cros_ec_debugfs
Misc:
- Fix kernel-doc errors and cleanups"
* tag 'tag-chrome-platform-for-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux: (28 commits)
power: supply: cros_charge-control: Fix signedness bug in charge_behaviour_store()
power: supply: cros_charge-control: Avoid accessing attributes out of bounds
power: supply: cros_charge-control: don't load if Framework control is present
power: supply: add ChromeOS EC based charge control driver
platform/chrome: cros_ec_proto: Introduce cros_ec_get_cmd_versions()
platform/chrome: Update binary interface for EC-based charge control
ACPI: battery: add devm_battery_hook_register()
dt-bindings: input: cros-ec-keyboard: Add keyboard matrix v3.0
platform/chrome: cros_ec_lpc: Handle zero length read/write
platform/chrome: cros_ec_lpc: Fix error code in cros_ec_lpc_mec_read_bytes()
platform/chrome: cros_ec_debugfs: fix wrong EC message version
platform/chrome: cros_ec_proto: update Kunit test for get_next_data_v3
platform/chrome: cros_ec_proto: add missing MODULE_DESCRIPTION() macro
hwmon: (cros_ec) Fix access to restricted __le16
hwmon: (cros_ec) Prevent read overflow in probe()
platform/chrome: cros_ec_lpc: Add quirks for Framework Laptop
platform/chrome: cros_ec_lpc: Add a new quirk for AML mutex
platform/chrome: cros_ec_lpc: Add a new quirk for ACPI id
platform/chrome: cros_ec_lpc: MEC access can use an AML mutex
platform/chrome: cros_ec_lpc: MEC access can return error code
...
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Fix thermal zone names for consistency with the other SoCs:
- GPU0 must be used as the first GPU item.
- SOCx deal with audio DSP, video, and infra subsystems.
The naming must be fixed "atomically" so compilation does not break.
As a result, the change is made in the dt-bindings and in the LVTS
driver within a single commit, despite the checkpatch warning.
The definitions can be safely modified here because they are used only
in the LVTS driver, which is modified accordingly, and have not yet
been included in a released kernel.
Fixes: 78c88534e5e1 ("dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for MT8188")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Link: https://lore.kernel.org/r/20240603-mtk-thermal-mt818x-dtsi-v7-2-8c8e3c7a3643@baylibre.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Fix a thermal zone name for consistency with the other SoCs:
MFG contains GPU, the latter is more specific and must be used here.
The naming must be fixed "atomically" so compilation does not break.
As a result, the change is made in the dt-bindings and in the LVTS
driver within a single commit, despite the checkpatch warning.
The definition can be safely modified here because it is used only
in the LVTS driver, which is modified accordingly, and has not yet
been included in a released kernel.
Fixes: a2ca202350f9 ("dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for MT8186")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Link: https://lore.kernel.org/r/20240603-mtk-thermal-mt818x-dtsi-v7-1-8c8e3c7a3643@baylibre.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Document bindings for the T-Head TH1520 AP sub-system clock controller.
Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
Co-developed-by: Yangtao Li <frank.li@vivo.com>
Signed-off-by: Yangtao Li <frank.li@vivo.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Link: https://lore.kernel.org/r/20240623-th1520-clk-v2-1-ad8d6432d9fb@tenstorrent.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
A few more Arm64 DeviceTree updates for v6.11
This introduces support for Lenovo Thinkpad Yoga slim 7x, LG Leon LTE,
and LG K10 (K420n).
In addition to this, all Gen-1 platforms gets the DWC3 quirk to disable
"SuperSpeed in park mode", which resolves an instabliity issue seen in
host mode.
For Fairphone 4, PM6150L and PMK8003 thermal sensors are added and
thermal zones defined.
Two fastrpc contexts on SM6350 are marked as non-secure, to allow
non-secure usage.
The video clock controller on SM8150 is introduced. IPQ9574 GCC is
marked as a interconnect provider. The vibrator block in the PM6150 is
described.
On SC7280 the download mode register is defined for SCM, allowing it to
enable/disable the ramdump support during a system crash.
Lastly, add a mailmap entry for Luca Weiss.
* tag 'qcom-arm64-for-6.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (22 commits)
mailmap: Update Luca Weiss's email address
arm64: dts: qcom: msm8916-lg-c50: add initial dts for LG Leon LTE
arm64: dts: qcom: msm8916-lg-m216: Add initial device tree
dt-bindings: arm: qcom: Add msm8916 based LG devices
arm64: dts: qcom: ipq9574: Add icc provider ability to gcc
dt-bindings: interconnect: Add Qualcomm IPQ9574 support
arm64: dts: qcom: sm8150: Add video clock controller node
arm64: dts: qcom: pm6150: Add vibrator
arm64: dts: qcom: sc7280: Enable download mode register write
arm64: dts: qcom: sm7225-fairphone-fp4: Add PM6150L thermals
arm64: dts: qcom: sm7225-fairphone-fp4: Add PMK8003 thermals
arm64: dts: qcom: sm6350: Add missing qcom,non-secure-domain property
arm64: dts: qcom: sdm845: Disable SS instance in Parkmode for USB
arm64: dts: qcom: msm8996: Disable SS instance in Parkmode for USB
arm64: dts: qcom: sm6350: Disable SS instance in Parkmode for USB
arm64: dts: qcom: sm6115: Disable SS instance in Parkmode for USB
arm64: dts: qcom: sdm630: Disable SS instance in Parkmode for USB
arm64: dts: qcom: msm8998: Disable SS instance in Parkmode for USB
arm64: dts: qcom: ipq8074: Disable SS instance in Parkmode for USB
arm64: dts: qcom: ipq6018: Disable SS instance in Parkmode for USB
...
Link: https://lore.kernel.org/r/20240709193406.3966-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
Georgi writes:
interconnect changes for 6.11
This pull request contains the interconnect changes for the 6.11-rc1 merge
window. It contains just driver changes with the following highlights:
Driver changes:
- New driver for MediaTek MT8183/8195 platforms
- New driver for MSM8953 platforms
- New QoS support for RPMh-based platforms with SC7280 being the
first one to benefit from it.
- Fix incorrect master-id value in qcm2290 driver
- Add missing MODULE_DESCRIPTION in a few drivers
Signed-off-by: Georgi Djakov <djakov@kernel.org>
* tag 'icc-6.11-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
interconnect: qcom: Fix DT backwards compatibility for QoS
interconnect: qcom: Add MSM8953 driver
dt-bindings: interconnect: qcom: Add Qualcomm MSM8953 NoC
interconnect: qcom: qcm2290: Fix mas_snoc_bimc RPM master ID
interconnect: qcom: sc7280: enable QoS configuration
interconnect: qcom: icc-rpmh: Add QoS configuration support
dt-bindings: interconnect: add clock property to enable QOS on SC7280
interconnect: mediatek: remove unneeded semicolon
interconnect: qcom: add missing MODULE_DESCRIPTION() macros
interconnect: imx: add missing MODULE_DESCRIPTION() macros
interconnect: mediatek: Add MediaTek MT8183/8195 EMI Interconnect driver
dt-bindings: interconnect: Add MediaTek EMI Interconnect bindings
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Add devicetree binding document and related header file for
Amlogic A5 secure power domains.
Signed-off-by: Hongyu Chen <hongyu.chen1@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240627-a5_secpower-v1-1-1f47dde1270c@amlogic.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
Qualcomm driver updates for v6.11
Support for Shared Memory (shm) Bridge is added, which provides a
stricter interface for handling of buffers passed to TrustZone.
The X1Elite platform is added to uefisecapp allow list, to instantiate
the efivars implementation.
A new in-kernel implementation of the pd-mapper (or servreg) service is
introduced, to replace the userspace dependency for USB Type-C and
battery management.
Support for sharing interrupts across multiple bwmon instances is added,
and a refcount imbalance issue is corrected.
The LLCC support for recent platforms is corrected, and SA8775P support
is added.
A new interface is added to SMEM, to expose "feature codes". One example
of the usecase for this is to indicate to the GPU driver which
frequencies are available on the given device.
The interrupt consumer and provider side of SMP2P is updated to provide
more useful names in interrupt stats.
Support for using the mailbox binding and driver for outgoing IPC
interrupt in the SMSM driver is introduced.
socinfo driver learns about SDM670 and IPQ5321, as well as get some
updates to the X1E PMICs.
pmic_glink is bumped to now support managing 3 USB Type-C ports.
* tag 'qcom-drivers-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (48 commits)
soc: qcom: smp2p: Use devname for interrupt descriptions
soc: qcom: smsm: Add missing mailbox dependency to Kconfig
soc: qcom: add missing pd-mapper dependencies
soc: qcom: icc-bwmon: Allow for interrupts to be shared across instances
dt-bindings: interconnect: qcom,msm8998-bwmon: Add X1E80100 BWMON instances
dt-bindings: interconnect: qcom,msm8998-bwmon: Remove opp-table from the required list
firmware: qcom: tzmem: export devm_qcom_tzmem_pool_new()
soc: qcom: add pd-mapper implementation
soc: qcom: pdr: extract PDR message marshalling data
soc: qcom: pdr: fix parsing of domains lists
soc: qcom: pdr: protect locator_addr with the main mutex
firmware: qcom: scm: clarify the comment in qcom_scm_pas_init_image()
firmware: qcom: scm: add support for SHM bridge memory carveout
firmware: qcom: tzmem: enable SHM Bridge support
firmware: qcom: scm: add support for SHM bridge operations
firmware: qcom: qseecom: convert to using the TZ allocator
firmware: qcom: scm: make qcom_scm_qseecom_app_get_id() use the TZ allocator
firmware: qcom: scm: make qcom_scm_lmh_dcvsh() use the TZ allocator
firmware: qcom: scm: make qcom_scm_ice_set_key() use the TZ allocator
firmware: qcom: scm: make qcom_scm_assign_mem() use the TZ allocator
...
Link: https://lore.kernel.org/r/20240705034410.13968-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Introduce reset capability to EN7581 device-tree clock binding
documentation. Add reset register mapping between misc scu and pb scu
ones in order to follow the memory order. This change is not
introducing any backward compatibility issue since the EN7581 dts is not
upstream yet.
Fixes: 0a382be005cf ("dt-bindings: clock: airoha: add EN7581 binding")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/28fef3e83062d5d71e7b4be4b47583f851a15bf8.1719485847.git.lorenzo@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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clk-for-6.11
Merge the IPQ9574 interconnect binding through a topic branch, to make
it possible to use the constants in the DeviceTree source branch as
well.
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v6.11
This introduces 11 new boards, namely:
* ASUS Vivobook S 15
* Lenovo Smart Tab M10 DTS
* Motorola Moto E 2015 LTE (surnia)
* Motorola Moto G 2015 (osprey)
* Motorola Moto G4 Play (harpia)
* Qualcomm AIM300 AIoT development board
* Qualcomm SM8650 Hardware Development Kit (HDK)
* SHIFTphone 8
* Samsung Galaxy Z Fold5
* Schneider HMIBSC board DTS
* TP-Link Archer AX55 v1
Of particular interest here is the Asus Vivobook, the first supported X1
Elite consumer laptop.
For IPQ6018 an SDHCI controller is added and on IPQ9574 an MDIO bus is
described.
The improvements to MSM8916-based devices continues, with sound and
mdoem support added to Acer Iconia Talk S and GPLUS FL8005A, the latter
also gaining BMS support. Samsung Galaxy devices gains PMIC and charger
definitions, NFC support and MUIC. Accelerometer and magnetometer
support is added to the Samsung Galaxy Grand Prime devices.
On MSM8976 definitions for IOMMU, the display subsystem, wifi subsystem,
and Adreno GPU are added.
On MSM8996 UFS core clock frequencies are specified, FastRPC nodes are
added for the audio DSP, glink-edges are described where available, the
display subsystem reset is added.
Venus is introduced on MSM8998 and the "No MSA Ready" quirk is added to
allow ath10k to come up.
GPU support is added to QCM2290 and enabled on the RB1 development
board.
The I2C controller used for communicating with the LT9611UXC HDMI
bridge is temporarily replaced with i2c-gpio while issues with the
builtin controller is diagnosed. The same is done for RB2, on the
QRB4210 platform.
On RB2 TCPM max current draw is corrected and the vreg_l9a regulator is
marked as always on to match expectations.
On the QDU1000 platform, USB is added, secure QFPROM is introduced to
allow LLCC to access OTP data. USB is enabled on the two IDP boards.
SA8775p gains PCIe endpoint definitions, LLCCC support, IMEM and PIL
info regions. Nodes are marked as dma-coherent as needed, a dedicated
carveout for shared memory bridge allocations is introduced.
The SA8775P ride device is split in the two versions r2 and r3.
The SC7180 Trogdor clamshell/detachable fragments are refactored for
convenience, and pwmleds are disabled where unused.
On SC7280 the APR nodes for interfacing with the audio services in audio
DSP firmware are introduced. The Qualcomm SMMU TBUs are described, to
enable improved debug support. QoS clocks are added to interconnects, as
needed in order to operate the QoS settings on some buses.
SuperSpeed in park is disabled for the primary DWC3 instance to address
host controller issues under load.
The PM8008 (camera PMIC) is introduced in Fairphone 5, regulators are
named for better output, and firmware name for IPA is adjusted to the
preferred file format.
The HDMI bridge on Rb3gen2 is described, rtc, gpi-dma and qup nodes are
enabled.
The Type-C port manager found in PM7250b is enabled, for targets not
using pmic-glink firmware for Type-C management.
SC8180X gets a number of smaller corrections, and some cleanups -
related to both functional issues and DeviceTree validation.
The PSHOLD node is marked reserved, after reports that this causes
issues during shutdown. Description of the USB signals are updated to
match the signal path. The PM8008 camera PMIC is added to Lenovo
ThinkPad X13s.
The PM660 PMIC is extended with charger and rradc definitions, and the
SDM670 gains a SMEM region definition.
On SDM845 the Qualcomm SMMU TBU nodes are described, to enable improved
debug output during faults etc. The UFS PHY is associated with its GDSC,
and the DisplayPort controller is wired up to the QMP PHY.
The Lenovo Yoga C630 Embedded Controller is introduced, adding battery
and Type-C port management and altmode support. The C630 also gains WiFI
calibration variant information, to cause selection of the right data.
The missing IPA firmware path is corrected.
For the SDX75 platform, AOSS, IPCC, SDHCI, TCSR, modem SMP2P, I2C and
SPI nodes are introduced. SD-card support is added to the IDP board.
CPUfreq support is introduced for the SM4450 platform.
Missing reset is added to the SDHC controller of SM6115. The UFS PHY
is associated with its GDSC, so is the PHY on SM6350.
On Fairphone 4, the camera pmic (PM8008) is introduced, regulators are
named for more informative debug output, and USB role switching is
enabled.
On the Fairphone 3, vibrator support is added and enabled.
On SM8250, the USB signal paths are properly described in the OF graph,
the UFS PHY gains its required power-domains description.
Thanks to the introduction of PCI power sequence support, the QRB5165
RB5 WiFi chip can now be powered up, so this is added.
Touchscreen interrupt flags are corrected accross a number of Sony
Xperia devices, to remove the unexpected traces from downstream.
On SM8450 an OPP-table is introduced for the PCIe controllers, to
specify the bandwidth and performance state requirements for the
different genrations and link widths. For this the PCIe controllers also
gains interconnect path definitions. The LLCC register layout is
corrected, and the UFS PHY is associated with its GDSC.
On the SM8550 development boards speaker port mapping is added. WiFi
support is finally enabled on the QRD board.
The new AIM300 development platform/board is introduced.
For SM8650 video and camera clock controller are introduced. SCM node
gains details necessary to trigger USB ramdump (download mode) upon a
system crash.
WiFi support and speaker port mapping is added to the QRD and the newly
introduced HDK. On the MTP the USB Type-C connector is describe to be
routed to the PHY.
In addition to the base HDK, a Display Card overlay is also introduced.
For X1 Elite bwmon, fastrpc and GPU support, tsens, and the missing PCIe
6a instance are added. Thermal zones are described. Pmic-glink is
introduced for both CRD and QCP devices, and remaining PMICs are
described. Audio support is also added to the QCP.
An explicit, larger, chunk of CMA memory is added to the various
devices, in order to compensate for the lack of IOMMU for PCIe.
Across a wide range of platforms, the thermal zone polling delays are
removed as supplies are interrupt driven anyways. Also thermal related
is the introduction of GPU thermal throttling, across many SoCs.
The old SMSM implementation is finally transitioned to using the
mailbox-based description and implementation for invoking interrupts on
remote processors. As such interrupt-triggering is converted to use this
mechanism on related platforms.
The usb-role-switch property is removed for all USB instances hard coded
to either host or peripheral across a range of boards.
* tag 'qcom-arm64-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (279 commits)
dt-bindings: arm: qcom: Document samsung,ms013g
arm64: dts: qcom: Add device tree for ASUS Vivobook S 15
dt-bindings: arm: qcom: Add ASUS Vivobook S 15
arm64: dts: qcom: qrb4210-rb2: Correct max current draw for VBUS
arm64: dts: qcom: msm8998: add venus node
arm64: dts: qcom: sa8775p-ride-r3: add new board file
arm64: dts: qcom: move common parts for sa8775p-ride variants into a .dtsi
dt-bindings: arm: qcom: add sa8775p-ride Rev 3
arm64: dts: qcom: sm8550-qrd: add port mapping to speakers
arm64: dts: qcom: sm8550-mtp: add port mapping to speakers
arm64: dts: qcom: sm8550-hdk: add port mapping to speakers
arm64: dts: qcom: sm8650-qrd: add port mapping to speakers
arm64: dts: qcom: sm8650-mtp: add port mapping to speakers
arm64: dts: qcom: sm8650-hdk: add port mapping to speakers
arm64: dts: qcom: sm7225-fairphone-fp4: Name the regulators
arm64: dts: qcom: pm8916: correct thermal zone name
arm64: dts: qcom: x1e80100: Add gpu support
arm64: dts: qcom: x1e80100: Fix USB HS PHY 0.8V supply
arm64: dts: qcom: qcs6490-rb3gen2: enable hdmi bridge
arm64: dts: qcom: sm6115: add resets for sdhc_1
...
Link: https://lore.kernel.org/r/20240706173140.18887-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.11, round 1
Highlights:
----------
-MCU:
- Add syscfg missing clock on stm32f429.
- MPU:
- STM32MP13:
- Add camera support on stm32mp135f-dk bord using DCMIPP and
GC2145 sensor.
- Document PWM output for stm32mp135f-dk
- Add goodix touchscreen support on stm32mp135f-dk board.
- Add new DH DHCOR / DHSBC board (Som + carrier board) based on
STM32MP135F SoC.
SOM part contains: STM32MP135F SoC, 512MB DDR2L RAM and
eMMC/SDIO wifi module.
The carrier boards embedds 2 RGMII ETH ports, USB-A,USB-C
and an extansion connector.
- Add Ethernet controller support on stm32mp135f-dk.
It uses LAN8742A PHY based on RMII.
- STMP32MP15:
- Rework Octavo OSD32MP1 split for USB phy.
- Add OP-TEE IRQ for asynchronous notification support.
It allows OP-TEE to trig Linux.
- STM32MP25:
- Add OP-TEE IRQ for asynchronous notification support.
It allows OP-TEE to trig Linux.
- Enable firewall for RCC.
- Add all U(s)ART nodes for stm32mp25.
- Add 3 power domains for low power modes.
- Add HPDMA support.
- Add Ethernet controller (ETH2) support on stm32mp257f-ev1.
It uses Realtek PHY based on RGMII.
- Add and enable SCMI regulator support.
* tag 'stm32-dt-for-v6.11-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (31 commits)
arm64: dts: st: describe power supplies for stm32mp257f-ev1 board
arm64: dts: st: add scmi regulators on stm32mp25
regulator: Add STM32MP25 regulator bindings
ARM: dts: stm32: omit unused pinctrl groups from stm32mp13 dtb files
arm64: dts: st: enable Ethernet2 on stm32mp257f-ev1 board
arm64: dts: st: add eth2 pinctrl entries in stm32mp25-pinctrl.dtsi
arm64: dts: st: add ethernet1 and ethernet2 support on stm32mp25
arm64: dts: st: add HPDMA nodes on stm32mp251
ARM: dts: stm32: Add ethernet support for DH STM32MP13xx DHCOR DHSBC board
ARM: dts: stm32: order stm32mp13-pinctrl nodes
ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board
ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13
ARM: dts: stm32: Document output pins for PWMs on stm32mp135f-dk
ARM: dts: stm32: OP-TEE async notif interrupt for ST STM32MP15x boards
ARM: dts: stm32: Missing clocks for stm32f429's syscfg.
ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board
ARM: dts: stm32: Add pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board
dt-bindings: arm: stm32: Add compatible string for DH electronics STM32MP13xx DHCOR DHSBC board
ARM: dts: stm32: osd32: move pwr_regulators to common
...
Link: https://lore.kernel.org/r/8f10bd29-d067-4060-89ff-2e1a605f3141@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
Allwinner SoC device tree changes for 6.11
This includes a commit shared with the clk tree. This commit adds clock
and reset indices to the device tree binding, and thus is needed for
both the device tree and driver changes.
ARM64 device tree and binding-only changes
- Add LRADC (low resolution ADC for resistor network based keys) for H616 SoC
- Add cache information for A64, H6, and H616 SoCs
- Correct model names and descriptions for Pine64 boards
- Add GPADC (general purpose ADC) for H616 SoC
- Add ADC joysticks based on GPADC for anbernic-rg35xx-h board
- Add additional CPU OPPs for the H700 on top of existing H616 ones
- Enable DVFS for rg35xx boards
- Add IOMMU for H616 SoC
RISC-V device tree changes
- Add system LDOs to D1s/T113 SoC
- Add ClockworkPi and DevTerm device trees
* tag 'sunxi-dt-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees
riscv: dts: allwinner: d1s-t113: Add system LDOs
arm64: dts: allwinner: h616: add IOMMU node
arm64: dts: allwinner: rg35xx: Enable DVFS CPU frequency scaling
arm64: dts: allwinner: h616: add additional CPU OPPs for the H700
arm64: dts: allwinner: anbernic-rg35xx-h: Add ADC joysticks
arm64: dts: allwinner: h616: Add GPADC device node
dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks
ARM: dts: sunxi: remove duplicated entries in makefile
arm64: dts: allwinner: Add cache information to the SoC dtsi for H616
arm64: dts: allwinner: Add cache information to the SoC dtsi for A64
arm64: dts: allwinner: Correct the model names for Pine64 boards
dt-bindings: arm: sunxi: Correct the descriptions for Pine64 boards
arm64: dts: allwinner: Add cache information to the SoC dtsi for H6
ARM: dts: sun50i: Add LRADC node
dt-bindings: input: sun4i-lradc-keys: Add H616 compatible
Link: https://lore.kernel.org/r/ZoQa8r1N8yi7FlPV@wens.tw
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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arm64-for-6.11
Merge IPQ9574 interconnect clock DeviceTree binding to gain access to
the interconnect constants.
|
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Add interconnect-cells to clock provider so that it can be
used as icc provider.
Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
interfaces. This will be used by the gcc-ipq9574 driver
that will for providing interconnect services using the
icc-clk framework.
Acked-by: Georgi Djakov <djakov@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20240430064214.2030013-3-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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These bindings will be used for the SCMI voltage domain.
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add interconnect driver for MSM8953-based devices.
* icc-msm8953
dt-bindings: interconnect: qcom: Add Qualcomm MSM8953 NoC
interconnect: qcom: Add MSM8953 driver
Link: https://lore.kernel.org/r/20240628-msm8953-interconnect-v3-0-a70d582182dc@mainlining.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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CLK_NR_CLKS should not be part of the binding.
Remove since the kernel code no longer uses it.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/6f21c09b-e8d2-4749-aca6-572c79df775d@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Change include/dt-bindings/mfd/st,stpmic1.h license model from GPLv2.0
only to dual GPLv2.0 or BSD-2-Clause. I have every legitimacy to request
this change on behalf of STMicroelectronics. This change clarifies that
this DT binding header file can be shared with software components as
bootloaders and OSes that are not published under GPLv2 terms.
In CC are all the contributors to this header file.
Cc: Pascal Paillet <p.paillet@st.com>
Cc: Lee Jones <lee@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240617092016.2958046-1-etienne.carriere@foss.st.com
Signed-off-by: Lee Jones <lee@kernel.org>
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Add a new binding for the MT6350 Series (MT6357/8/9) PMIC AUXADC,
providing various ADC channels for both internal temperatures and
voltages, audio accessory detection (hp/mic/hp+mic and buttons,
usually on a 3.5mm jack) other than some basic battery statistics
on boards where the battery is managed by this PMIC.
Also add the necessary dt-binding headers for devicetree consumers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://patch.msgid.link/20240604123008.327424-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
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https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
Amlogic ARM64 DT changes for v6.11:
- New Boards:
- OSMC Vero 4K
- Dreambox One & Two
- GXLX/S905L p271 Reference Boards
- Amlogic A4 Power Domain
- A bunch of DT fixes to allmost solve all remaining check errors
- Amlogic S4 PWM
- Fixes for:
- SM1 SPDIF compatibles
- Bump G12 SPDIF driver strength
- Add power domain to HDMI TX
- Correct HDMI TX clocks
* tag 'amlogic-arm64-dt-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: (32 commits)
arm64: dts: amlogic: setup hdmi system clock
arm64: dts: amlogic: gx: correct hdmi clocks
arm64: dts: amlogic: Add Amlogic S4 PWM
arm64: dts: amlogic: add power domain to hdmitx
arm64: dts: amlogic: g12: bump spdif output drive strength
arm64: dts: amlogic: sm1: fix spdif compatibles
arm64: dts: amlogic: ad402: fix thermal zone node name
arm64: dts: meson: add initial support for Dreambox One/Two
dt-bindings: arm: amlogic: add support for Dreambox One/Two
dt-bindings: add dream vendor prefix
arm64: dts: meson: add support for OSMC Vero 4K
dt-bindings: arm: amlogic: add OSMC Vero 4K
arm64: dts: amlogic: gxbb-odroidc2: fix invalid reset-gpio property
arm64: dts: amlogic: a1: drop the invalid reset-name for usb@fe004400
arm64: dts: amlogic: a1: use correct node name for mmc controller
arm64: dts: amlogic: c3: use correct compatible for gpio_intc node
arm64: dts: amlogic: axg: fix tdm audio-controller clock order
arm64: dts: amlogic: g12a-u200: add missing AVDD-supply to acodec
arm64: dts: amlogic: g12a-u200: drop invalid sound-dai-cells
arm64: dts: amlogic: sm1: fix tdm controllers compatible
...
Link: https://lore.kernel.org/r/7f71e76c-c793-429a-b0ed-7296553a3eff@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
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Add support for keyboard matrix version 3.0, which reduces keyboard
ghosting.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Link: https://lore.kernel.org/r/9ae4d96cc2ce8c9de8755b9beffb78c641100fe7.1719531519.git.dnojiri@chromium.org
Signed-off-by: Tzung-Bi Shih <tzungbi@kernel.org>
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Add the device-tree bindings for interconnect providers
used on MSM8953 platform.
Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/r/20240628-msm8953-interconnect-v3-1-a70d582182dc@mainlining.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
More attention for the rk3128 soc (dsi, i2c, spdif, sfc), hdmi-sound
for a rk3066a board and some minor cleanups.
* tag 'v6.11-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add #sound-dai-cells to hdmi node on rk3128
ARM: dts: rockchip: add #sound-dai-cells to hdmi node no rk3036
ARM: dts: rockchip: enable hdmi_sound and i2s0 for mk808 hdmi
ARM: dts: rockchip: Add SFC for RK3128
ARM: dts: rockchip: add hdmi-sound node to rk3066a
ARM: dts: rockchip: Add spdif node for RK3128
ARM: dts: rockchip: Add i2s nodes for RK3128
ARM: dts: rockchip: Add DSI for RK3128
ARM: dts: rockchip: Add D-PHY for RK3128
dt-bindings: clock: rk3128: Add PCLK_MIPIPHY
Link: https://lore.kernel.org/r/2187283.irdbgypaU6@diego
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Sound Card need to consider/adjust HW control ordering based on the
combination of CPU/Codec. The controlling feature is already supported
on ASoC, but Simple Audio Card / Audio Graph Card still not support it.
Let's support it.
Cc: Maxim Kochetkov <fido_max@inbox.ru>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://patch.msgid.link/87sexizojx.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Merge the SM8650 video and clock controller drivers to gain access to
the constants from the DeviceTree binding.
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Merge SM8650 video and camera clock drivers through topic branch, to
make available the DeviceTree binding includes to the DeviceTree source
branches as well.
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Add device tree bindings for the camera clock controller on
Qualcomm SM8650 platform.
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240602114439.1611-7-quic_jkona@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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SM8650 video clock controller has most clocks same as SM8450,
but it also has few additional clocks and resets. Add device tree
bindings for the video clock controller on Qualcomm SM8650 platform
by defining these additional clocks and resets on top of SM8450.
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240602114439.1611-3-quic_jkona@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The clock definitions in <dt-bindings/clock/r8a779?-clock.h> were
superseded by those in <dt-bindings/clock/r8a779?-cpg-mssr.h> a long
time ago.
The last DTS user of these files was removed in commit 362b334b17943d84
("ARM: dts: r8a7791: Convert to new CPG/MSSR bindings") in v4.15.
Driver support for the old bindings was removed in commit
58256143cff7c2e0 ("clk: renesas: Remove R-Car Gen2 legacy DT clock
support") in v5.5, so there is no point to keep on carrying these.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/d4abb688d666be35e99577a25b16958cbb4c3c98.1718796005.git.geert+renesas@glider.be
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Drop duplicate newline. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240616160038.45937-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add a clock id for SFC's AHB clock.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240606143401.32454-5-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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CLK_NR_CLKS should not be part of the binding. Let's drop it, since
the kernel code no longer uses it either.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240606143401.32454-4-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add the required clock bindings for the GPADC.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240605172049.231108-2-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add bindings for the clock generator of divider/mux and gates working
for other subsystem than RP subsystem for Sophgo SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Rob Herring <robh@kernel.org>
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Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Rob Herring <robh@kernel.org>
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Add bindings for the pll clocks for Sophgo SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
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Rework the pm8008 driver to match the new devicetree binding which no
longer describes internal details like interrupts and register offsets
(including which of the two consecutive I2C addresses the registers
belong to).
Instead make the interrupt controller implementation internal and pass
interrupts to the subdrivers using MFD cell resources.
Note that subdrivers may either get their resources, like register block
offsets, from the parent MFD or this can be included in the subdrivers
directly.
In the current implementation, the temperature alarm driver is generic
enough to just get its base address and alarm interrupt from the parent
driver, which already uses this information to implement the interrupt
controller.
The regulator driver, however, needs additional information like parent
supplies and regulator characteristics so in that case it is easier to
just augment its table with the regulator register base addresses.
Similarly, the current GPIO driver already holds the number of pins and
that lookup table can therefore also be extended with register offsets.
Note that subdrivers can now access the two regmaps by name, even if the
primary regmap is registered last so that it is returned by default when
no name is provided in lookups.
Finally, note that the temperature alarm and GPIO subdrivers need some
minor rework before they can be used with non-SPMI devices like the
PM8008. The temperature alarm MFD cell name specifically uses a "qpnp"
rather than "spmi" prefix to prevent binding until the driver has been
updated.
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240608155526.12996-11-johan+linaro@kernel.org
Signed-off-by: Lee Jones <lee@kernel.org>
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Add bindings for the MediaTek External Memory Interface Interconnect,
which providers support system bandwidth requirements through Dynamic
Voltage Frequency Scaling Resource Collector (DVFSRC) hardware.
This adds bindings for MediaTek MT8183 and MT8195 SoCs.
Note that this is modeled as a subnode of DVFSRC for multiple reasons:
- Some SoCs have more than one interconnect on the DVFSRC (and two
different kinds of EMI interconnect, and also a SMI interconnect);
- Some boards will want to not enable the interconnect driver because
some of those are not battery powered (so they just keep the knobs
at full thrust from the bootloader and never care scaling busses);
- Some DVFSRC interconnect features may depend on firmware.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240610085735.147134-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
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clk-for-6.11
Merge the QCM2290 GPUCC binding through a topic branch to allow for it
to also be merged into the DeviceTree branch.
|
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Add device tree bindings for graphics clock controller for Qualcomm
Technology Inc's QCM2290 SoCs.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240606-topic-rb1_gpu-v4-1-4bc0c19da4af@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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QCA8386/QCA8084 includes the clock & reset controller that is
accessed by MDIO bus. Two work modes are supported, qca8386 works
as switch mode, qca8084 works as PHY mode.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20240605124541.2711467-3-quic_luoj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The 'sys_pll' input is an optional clock that can be used to generate
'sys_pll_div16', which serves as one of the sources for the GEN clock.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240515185103.20256-5-ddrokosov@salutedevices.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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The 'syspll' PLL is a general-purpose PLL designed specifically for the
CPU clock. It is capable of producing output frequencies within the
range of 768MHz to 1536MHz.
The 'syspll_in' source clock is an optional parent connection from the
peripherals clock controller.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240515185103.20256-3-ddrokosov@salutedevices.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Modify license to include dual licensing as GPL-2.0-only OR MIT
license for TI specific phy header files. This allows for Linux
kernel files to be used in other Operating System ecosystems
such as Zephyr or FreeBSD.
While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync
with latest SPDX conventions (GPL-2.0 is deprecated).
While at this, update the TI copyright year to sync with current year
to indicate license change.
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Trent Piepho <tpiepho@impinj.com>
Cc: Wadim Egorov <w.egorov@phytec.de>
Cc: Kip Broadhurst <kbroadhurst@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Acked-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add devicetree binding document and related header file for
Amlogic A4 secure power domains.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240529-a4_secpowerdomain-v2-1-47502fc0eaf3@amlogic.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add the peripherals clock controller dt-bindings for Amlogic C3 SoC family
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Co-developed-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240522082727.3029656-4-xianwei.zhao@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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