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2019-03-21ARM: at91: add sam9x60 SFR definitionsTudor Ambarus
Keep generic names, as there are no conflicts with previous SFR definitions. While touching bits, update AT91_OHCIICR_USB_SUSPEND to use GENMASK, replace unused AT91_OHCIICR_SUSPEND_A/B/C with a more generic macro, align values on tab-width. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2017-11-01clk: at91: utmi: set the mainck rateLudovic Desroches
By default, it is assumed that the UTMI clock is generated from a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ field of the SFR_UTMICKTRIM has to be updated to generate the UTMI clock in the proper way. The UTMI clock has a fixed rate of 480 MHz. In fact, there is no multiplier we can configure. The multiplier is managed internally, depending on the reference clock frequency, to achieve the target of 480 MHz. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by: Ingo van Lil <inguin@gmx.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-16ARM: at91: define LPDDR typesAlexandre Belloni
The Atmel MPDDR controller support LPDDR2 and LPDDR3 memories, add their types. Cc: <stable@vger.kernel.org> # 4.4+ Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Reichel <sre@kernel.org>
2016-11-07ARM: at91: add secumod register definitionsAlexandre Belloni
Add registers and bits definitions for the security module found on sama5d2. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-08-30usb: ohci-at91: Forcibly suspend ports while USB suspendWenyou Yang
The usb controller does not manage correctly the suspend mode for the ehci. In echi mode, there is no way to suspend without any device connected to it. This is why this specific control is added to fix this issue. Since the suspend mode works in ohci mode, this specific control works by suspend the usb controller in ohci mode. This specific control is by setting the SUSPEND_A/B/C fields of SFR_OHCIICR(OHCI Interrupt Configuration Register) in the SFR while the OHCI USB suspend. This set operation must be done before the USB clock disabled, clear operation after the USB clock enabled. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-03-29ARM: dts: at91: sama5d2: add SFR nodeCyrille Pitchen
This SFR node is looked up by the I2S controller driver to tune the SFR_I2SCLKSEL register. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-05-20ARM: at91: remove at91rm9200_sdramc.hAlexandre Belloni
include/soc/at91/at91rm9200_sdramc.h is replaced by include/linux/mfd/syscon/atmel-smc.h as this is actually a syscon device. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-03-03pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.Peter Rosin
The DDRSDR controller fails miserably to put LPDDR1 memories in self-refresh. Force the controller to think it has DDR2 memories during the self-refresh period, as the DDR2 self-refresh spec is equivalent to LPDDR1, and is correctly implemented in the controller. Assume that the second controller has the same fault, but that is untested. Signed-off-by: Peter Rosin <peda@axentia.se> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-11-13ARM: at91: move sdramc/ddrsdr header to include/soc/at91Alexandre Belloni
Move the (DDR) SDRAM controller headers to include/soc/at91 to remove the dependency on mach/ headers from the at91-reset driver. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>