From 0703146060786f972aaa22cad9c877a6067fd47d Mon Sep 17 00:00:00 2001 From: Julien Masson Date: Mon, 24 Jun 2019 16:49:04 +0200 Subject: drm: meson: add macro used to enable HDMI PLL This patch add new macro HHI_HDMI_PLL_CNTL_EN which is used to enable HDMI PLL. Signed-off-by: Julien Masson Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/86o92n82e1.fsf@baylibre.com --- drivers/gpu/drm/meson/meson_vclk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c index c11b55237917..869231c93617 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -97,6 +97,7 @@ #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ +#define HHI_HDMI_PLL_CNTL_EN BIT(30) #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ @@ -469,7 +470,7 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m, /* Enable and unreset */ regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, - 0x7 << 28, 0x4 << 28); + 0x7 << 28, HHI_HDMI_PLL_CNTL_EN); /* Poll for lock bit */ regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, -- cgit