From 082802a3ee09e764bc1513988d6f5889712fe88f Mon Sep 17 00:00:00 2001
From: Koby Elbaz <kelbaz@habana.ai>
Date: Tue, 28 Nov 2023 18:53:15 +0200
Subject: drm/xe: add skip_pcode flag
Per device, set this flag to enable access to the PCODE uC or to skip it.
Signed-off-by: Koby Elbaz <kelbaz@habana.ai>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 2 ++
drivers/gpu/drm/xe/xe_pci.c | 2 ++
drivers/gpu/drm/xe/xe_pcode.c | 9 +++++++++
3 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index c4b6aa8fcec1..1a95b1587c86 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -260,6 +260,8 @@ struct xe_device {
u8 enable_display:1;
/** @bypass_mtcfg: Bypass Multi-Tile configuration from MTCFG register */
u8 bypass_mtcfg:1;
+ /** @skip_pcode: skip access to PCODE uC */
+ u8 skip_pcode:1;
/** @supports_mmio_ext: supports MMIO extension/s */
u8 supports_mmio_ext:1;
/** @has_heci_gscfi: device has heci gscfi */
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 1c4f9081e84c..57eecaac53b5 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -63,6 +63,7 @@ struct xe_device_desc {
u8 has_llc:1;
u8 has_sriov:1;
u8 bypass_mtcfg:1;
+ u8 skip_pcode:1;
u8 supports_mmio_ext:1;
u8 skip_guc_pc:1;
};
@@ -581,6 +582,7 @@ static int xe_info_init(struct xe_device *xe,
xe->info.has_llc = desc->has_llc;
xe->info.has_sriov = desc->has_sriov;
xe->info.bypass_mtcfg = desc->bypass_mtcfg;
+ xe->info.skip_pcode = desc->skip_pcode;
xe->info.supports_mmio_ext = desc->supports_mmio_ext;
xe->info.tile_mmio_ext_size = graphics_desc->tile_mmio_ext_size;
diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
index 4a240acf7625..b324dc2a5deb 100644
--- a/drivers/gpu/drm/xe/xe_pcode.c
+++ b/drivers/gpu/drm/xe/xe_pcode.c
@@ -61,6 +61,9 @@ static int pcode_mailbox_rw(struct xe_gt *gt, u32 mbox, u32 *data0, u32 *data1,
{
int err;
+ if (gt_to_xe(gt)->info.skip_pcode)
+ return 0;
+
lockdep_assert_held(>->pcode.lock);
if ((xe_mmio_read32(gt, PCODE_MAILBOX) & PCODE_READY) != 0)
@@ -249,6 +252,9 @@ int xe_pcode_init(struct xe_gt *gt)
int timeout_us = 180000000; /* 3 min */
int ret;
+ if (gt_to_xe(gt)->info.skip_pcode)
+ return 0;
+
if (!IS_DGFX(gt_to_xe(gt)))
return 0;
@@ -280,6 +286,9 @@ int xe_pcode_probe(struct xe_gt *gt)
{
drmm_mutex_init(>_to_xe(gt)->drm, >->pcode.lock);
+ if (gt_to_xe(gt)->info.skip_pcode)
+ return 0;
+
if (!IS_DGFX(gt_to_xe(gt)))
return 0;
--
cgit