From 1b95c5a48f5ea3a23618b5894f44124bfa98171a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 26 Aug 2019 08:47:07 -0700 Subject: ARM: OMAP2+: Drop legacy platform data for omap4 gpu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I've tested that the interconnect target module enables and idles just fine when probed with ti-sysc with PM runtime control via sys: # echo on > $(find /sys -name control | grep \/5601) # rwmem 0x56000024 0x56000024 = 0x00010200 # SGX540 CORE_REVISION # echo auto > $(find /sys -name control | grep \/5601) # rwmem 0x56000024 And when idled, it will produce "Bus error" as expected. Cc: Adam Ford Cc: Filip Matijević Cc: "H. Nikolaus Schaller" Cc: Ivaylo Dimitrov Cc: moaz korena Cc: Merlijn Wajer Cc: Paweł Chmiel Cc: Philipp Rossak Cc: Tomi Valkeinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 1 - arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 53 ------------------------------ 2 files changed, 54 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index c43e52fd5f65..7cc95bc1598b 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -330,7 +330,6 @@ target-module@56000000 { compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "gpu"; reg = <0x5601fc00 0x4>, <0x5601fc10 0x4>; reg-names = "rev", "sysc"; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index a6f2a10cdc3e..559b205020c7 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1085,41 +1085,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = { }, }; -/* - * 'gpu' class - * 2d/3d graphics accelerator - */ - -static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { - .rev_offs = 0x1fc00, - .sysc_offs = 0x1fc10, - .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | - MSTANDBY_SMART | MSTANDBY_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type2, -}; - -static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { - .name = "gpu", - .sysc = &omap44xx_gpu_sysc, -}; - -/* gpu */ -static struct omap_hwmod omap44xx_gpu_hwmod = { - .name = "gpu", - .class = &omap44xx_gpu_hwmod_class, - .clkdm_name = "l3_gfx_clkdm", - .main_clk = "sgx_clk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* * 'hdq1w' class * hdq / 1-wire serial interface controller @@ -2596,14 +2561,6 @@ static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* gpu -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { - .master = &omap44xx_gpu_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* hsi -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { .master = &omap44xx_hsi_hwmod, @@ -3028,14 +2985,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3_main_2 -> gpu */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_gpu_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_per -> hdq1w */ static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { .master = &omap44xx_l4_per_hwmod, @@ -3450,7 +3399,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_debugss__l3_main_2, &omap44xx_dma_system__l3_main_2, &omap44xx_fdif__l3_main_2, - &omap44xx_gpu__l3_main_2, &omap44xx_hsi__l3_main_2, &omap44xx_ipu__l3_main_2, &omap44xx_iss__l3_main_2, @@ -3503,7 +3451,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_per__elm, &omap44xx_l4_cfg__fdif, &omap44xx_l3_main_2__gpmc, - &omap44xx_l3_main_2__gpu, &omap44xx_l4_per__hdq1w, &omap44xx_l4_cfg__hsi, &omap44xx_l3_main_2__ipu, -- cgit From fd5683749472bb3370487009c91c49182eb99694 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 26 Aug 2019 08:47:07 -0700 Subject: clk: ti: add clkctrl data omap5 sgx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Looks like we have sgx clock missing currently so let's add it. Cc: Adam Ford Cc: Filip Matijević Cc: "H. Nikolaus Schaller" Cc: Ivaylo Dimitrov Cc: moaz korena Cc: Merlijn Wajer Cc: Michael Turquette Cc: Paweł Chmiel Cc: Philipp Rossak Cc: Stephen Boyd Cc: Tero Kristo Cc: Tomi Valkeinen Cc: linux-clk@vger.kernel.org Acked-by: Stephen Boyd Signed-off-by: Tony Lindgren --- drivers/clk/ti/clk-54xx.c | 34 ++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/omap5.h | 3 +++ 2 files changed, 37 insertions(+) diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index dafef7e70ba8..e675e27f1203 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -314,6 +314,39 @@ static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = { 0 }, }; +static const char * const omap5_gpu_core_mux_parents[] __initconst = { + "dpll_core_h14x2_ck", + "dpll_per_h14x2_ck", + NULL, +}; + +static const char * const omap5_gpu_hyd_mux_parents[] __initconst = { + "dpll_core_h14x2_ck", + "dpll_per_h14x2_ck", + NULL, +}; + +static const char * const omap5_gpu_sys_clk_parents[] __initconst = { + "sys_clkin", + NULL, +}; + +static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = { + .max_div = 2, +}; + +static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL }, + { 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL }, + { 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = { + { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" }, + { 0 }, +}; + static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = { "func_128m_clk", "dpll_per_m2x2_ck", @@ -470,6 +503,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = { { 0x4a008e20, omap5_l3instr_clkctrl_regs }, { 0x4a009020, omap5_l4per_clkctrl_regs }, { 0x4a009420, omap5_dss_clkctrl_regs }, + { 0x4a009520, omap5_gpu_clkctrl_regs }, { 0x4a009620, omap5_l3init_clkctrl_regs }, { 0x4ae07920, omap5_wkupaon_clkctrl_regs }, { 0 }, diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h index f3283957f48d..e5411938983c 100644 --- a/include/dt-bindings/clock/omap5.h +++ b/include/dt-bindings/clock/omap5.h @@ -89,6 +89,9 @@ /* dss clocks */ #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +/* gpu clocks */ +#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) + /* l3init clocks */ #define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) #define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -- cgit From 394534cb07d8f89b6e621e8a1e6da23571725aef Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 26 Aug 2019 08:47:08 -0700 Subject: ARM: dts: Configure sgx for omap5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I've tested that the interconnect target module enables and idles just fine when probed with ti-sysc with PM runtime control via sys: # echo on > $(find /sys -name control | grep \/5600) # rwmem 0x5600fe00 # OCP Revision 0x5600fe00 = 0x40000000 # echo auto > $(find /sys -name control | grep \/5600) # rwmem 0x5600fe10 # rwmem 0x56000024 Cc: Adam Ford Cc: Filip Matijević Cc: "H. Nikolaus Schaller" Cc: Ivaylo Dimitrov Cc: moaz korena Cc: Merlijn Wajer Cc: Paweł Chmiel Cc: Philipp Rossak Cc: Tomi Valkeinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 23 +++++++++++++++++++++++ arch/arm/boot/dts/omap54xx-clocks.dtsi | 14 ++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index edfd26c03462..1fb7937638f0 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -257,6 +257,29 @@ ports-implemented = <0x1>; }; + target-module@56000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5600fe00 0x4>, + <0x5600fe10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x56000000 0x2000000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; + dss: dss@58000000 { compatible = "ti,omap5-dss"; reg = <0x58000000 0x80>; diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 33e8dd905bff..fac2e57dcca9 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -1146,6 +1146,20 @@ }; }; + gpu_cm: clock-controller@1500 { + compatible = "ti,omap4-cm"; + reg = <0x1500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1500 0x100>; + + gpu_clkctrl: clk@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; + l3init_cm: l3init_cm@1600 { compatible = "ti,omap4-cm"; reg = <0x1600 0x100>; -- cgit From 3b72fc895a2e57f70276b46f386f35d752adf555 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 26 Aug 2019 08:47:08 -0700 Subject: ARM: dts: Configure interconnect target module for omap3 sgx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Looks like omap34xx OCP registers are not readable unlike on omap36xx. We use SGX revision register instead of the OCP revision register for 34xx and do not configure any SYSCONFIG register unlike for 36xx. I've tested that the interconnect target module enables and idles just fine with PM runtime control via sys: # echo on > $(find /sys -name control | grep \/5000); rwmem 0x5000fe10 # rwmem 0x50000014 # SGX revision register on 36xx 0x50000014 = 0x00010205 # echo auto > $(find /sys -name control | grep \/5000) # rwmem 0x5000fe00 And when idled, it will produce "Bus error" as expected. Cc: Adam Ford Cc: Filip Matijević Cc: "H. Nikolaus Schaller" Cc: Ivaylo Dimitrov Cc: moaz korena Cc: Merlijn Wajer Cc: Paweł Chmiel Cc: Philipp Rossak Cc: Tomi Valkeinen Tested-by: Adam Ford #logicpd-torpedo-37xx-devkit Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap34xx.dtsi | 26 ++++++++++++++++++++++++++ arch/arm/boot/dts/omap36xx.dtsi | 28 ++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index f572a477f74c..7b09cbee8bb8 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -100,6 +100,32 @@ interrupts = <18>; }; }; + + /* + * On omap34xx the OCP registers do not seem to be accessible + * at all unlike on 36xx. Maybe SGX is permanently set to + * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is + * write-only at 0x50000e10. We detect SGX based on the SGX + * revision register instead of the unreadable OCP revision + * register. Also note that on early 34xx es1 revision there + * are also different clocks, but we do not have any dts users + * for it. + */ + sgx_module: target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000014 0x4>; + reg-names = "rev"; + clocks = <&sgx_fck>, <&sgx_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50000000 0x4000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; }; thermal_zones: thermal-zones { diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 6fb23ada1f64..1e552f08f120 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -139,6 +139,34 @@ interrupts = <18>; }; }; + + /* + * Note that the sysconfig register layout is a subset of the + * "ti,sysc-omap4" type register with just sidle and midle bits + * available while omap34xx has "ti,sysc-omap2" type sysconfig. + */ + sgx_module: target-module@50000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5000fe00 0x4>, + <0x5000fe10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + clocks = <&sgx_fck>, <&sgx_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50000000 0x2000000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; }; thermal_zones: thermal-zones { -- cgit From 6cb0ac0fb9786d01f140dcfcd3d09ce850dd0a64 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 26 Aug 2019 08:47:09 -0700 Subject: ARM: dts: ARM: dts: Configure interconnect target module for am3517sgx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on Tony Lindgren's work for omap34xx, this patch applies the same functionality to the AM3517. The following can be tested via sysfs with the following to ensure the SGX module gets enabled and disabled properly: 0x00010201 Bus error Cc: Filip Matijević Cc: "H. Nikolaus Schaller" Cc: Ivaylo Dimitrov Cc: moaz korena Cc: Merlijn Wajer Cc: Paweł Chmiel Cc: Philipp Rossak Cc: Tomi Valkeinen Signed-off-by: Adam Ford [tony@atomide.com: updated subject, dropped rstctrl info] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index 23ea381d363f..bf3002009b00 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -88,6 +88,30 @@ interrupts = <24>; clocks = <&hecc_ck>; }; + + /* + * On am3517 the OCP registers do not seem to be accessible + * similar to the omap34xx. Maybe SGX is permanently set to + * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is + * write-only at 0x50000e10. We detect SGX based on the SGX + * revision register instead of the unreadable OCP revision + * register. + */ + sgx_module: target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000014 0x4>; + reg-names = "rev"; + clocks = <&sgx_fck>, <&sgx_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50000000 0x4000>; + + /* + * Closed source PowerVR driver, no child device + * binding or driver in mainline + */ + }; }; }; -- cgit