From 736263d8aa20c99d5f40f129e4c9c28ddb3f95ef Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 13 Sep 2016 20:57:22 +0100 Subject: ARM: sa1100: switch to accurate MPLL calculation Switch SA1100 to the more accurate MPLL calculation. Table 8-1 in the SA1110 developers manual gives two sets of frequencies for two different crystals - 3.6864MHz and 3.5795MHz. Calculating the multiplication factor for each entry in the table shows that the clock rates given are are equal to the crystal frequency multiplied by 4(4 + PPCR), rounded to 100kHz. This equation holds for the higher frequencies up to 280.2MHz which have been omitted from the later manuals. Signed-off-by: Russell King --- arch/arm/mach-sa1100/clock.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c index e8691921c69a..c4356e620c0f 100644 --- a/arch/arm/mach-sa1100/clock.c +++ b/arch/arm/mach-sa1100/clock.c @@ -12,7 +12,6 @@ #include #include -#include static const char * const clk_tucr_parents[] = { "clk32768", "clk3686400", @@ -66,12 +65,12 @@ static const struct clk_init_data clk_gpio27_init_data __initconst = { * Derived from the table 8-1 in the SA1110 manual, the MPLL appears to * multiply its input rate by 4 x (4 + PPCR). This calculation gives * the exact rate. The figures given in the table are the rates rounded - * to 100kHz. Stick with sa11x0_getspeed() for the time being. + * to 100kHz. */ static unsigned long clk_mpll_recalc_rate(struct clk_hw *hw, unsigned long prate) { - return sa11x0_getspeed(0) * 1000; + return prate * 4 * (4 + (PPCR & 15)); } static const struct clk_ops clk_mpll_ops = { -- cgit