From 8f7e001e0325de63a42f23342ac3b8139150c5cf Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Mon, 12 Sep 2022 23:48:01 +0100 Subject: RISC-V: Clean up the Zicbom block size probing This fixes two issues: I truncated the warning's hart ID when porting to the 64-bit hart ID code, and the original code's warning handling could fire on an uninitialized hart ID. The biggest change here is that riscv_cbom_block_size is no longer initialized, as IMO the default isn't sane: there's nothing in the ISA that mandates any specific cache block size, so falling back to one will just silently produce the wrong answer on some systems. This also changes the probing order so the cache block size is known before enabling Zicbom support. CC: stable@vger.kernel.org CC: Andrew Jones CC: Heiko Stuebner CC: Atish Patra Fixes: 3aefb2ee5bdd ("riscv: implement Zicbom-based CMO instructions + the t-head variant") Fixes: 1631ba1259d6 ("riscv: Add support for non-coherent devices using zicbom extension") Reported-by: kernel test robot Reported-by: Conor Dooley Signed-off-by: Palmer Dabbelt [Conor: fixed the redefinition errors] Tested-by: Conor Dooley Signed-off-by: Conor Dooley Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220912224800.998121-1-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- arch/riscv/errata/thead/errata.c | 1 + arch/riscv/include/asm/cacheflush.h | 1 + arch/riscv/kernel/setup.c | 2 +- arch/riscv/mm/dma-noncoherent.c | 23 +++++++++++++---------- 4 files changed, 16 insertions(+), 11 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 202c83f677b2..96648c176f37 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -37,6 +37,7 @@ static bool errata_probe_cmo(unsigned int stage, if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return false; + riscv_cbom_block_size = L1_CACHE_BYTES; riscv_noncoherent_supported(); return true; #else diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index a60acaecfeda..a89c005b4bbf 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -43,6 +43,7 @@ void flush_icache_mm(struct mm_struct *mm, bool local); #endif /* CONFIG_SMP */ #ifdef CONFIG_RISCV_ISA_ZICBOM +extern unsigned int riscv_cbom_block_size; void riscv_init_cbom_blocksize(void); #else static inline void riscv_init_cbom_blocksize(void) { } diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 95ef6e2bf45c..2dfc463b86bb 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -296,8 +296,8 @@ void __init setup_arch(char **cmdline_p) setup_smp(); #endif - riscv_fill_hwcap(); riscv_init_cbom_blocksize(); + riscv_fill_hwcap(); apply_boot_alternatives(); } diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index cd2225304c82..e3f9bdf47c5f 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -12,7 +12,7 @@ #include #include -static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES; +unsigned int riscv_cbom_block_size; static bool noncoherent_supported; void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, @@ -79,38 +79,41 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, void riscv_init_cbom_blocksize(void) { struct device_node *node; + unsigned long cbom_hartid; + u32 val, probed_block_size; int ret; - u32 val; + probed_block_size = 0; for_each_of_cpu_node(node) { unsigned long hartid; - int cbom_hartid; ret = riscv_of_processor_hartid(node, &hartid); if (ret) continue; - if (hartid < 0) - continue; - /* set block-size for cbom extension if available */ ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); if (ret) continue; - if (!riscv_cbom_block_size) { - riscv_cbom_block_size = val; + if (!probed_block_size) { + probed_block_size = val; cbom_hartid = hartid; } else { - if (riscv_cbom_block_size != val) - pr_warn("cbom-block-size mismatched between harts %d and %lu\n", + if (probed_block_size != val) + pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", cbom_hartid, hartid); } } + + if (probed_block_size) + riscv_cbom_block_size = probed_block_size; } #endif void riscv_noncoherent_supported(void) { + WARN(!riscv_cbom_block_size, + "Non-coherent DMA support enabled without a block size\n"); noncoherent_supported = true; } -- cgit From 225e47ea20ea4f37031131f4fa7a6c281fac6657 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Fri, 8 Jul 2022 18:49:29 -0700 Subject: riscv: fix RISCV_ISA_SVPBMT kconfig dependency warning RISCV_ISA_SVPBMT selects RISCV_ALTERNATIVE which depends on !XIP_KERNEL. Therefore RISCV_ISA_SVPBMT should also depend on !XIP_KERNEL so quieten this kconfig warning: WARNING: unmet direct dependencies detected for RISCV_ALTERNATIVE Depends on [n]: !XIP_KERNEL [=y] Selected by [y]: - RISCV_ISA_SVPBMT [=y] && 64BIT [=y] && MMU [=y] Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") Signed-off-by: Randy Dunlap Cc: stable@vger.kernel.org Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20220709014929.14221-1-rdunlap@infradead.org/ Signed-off-by: Palmer Dabbelt --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ed66c31e4655..59d18881f35b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -386,6 +386,7 @@ config RISCV_ISA_C config RISCV_ISA_SVPBMT bool "SVPBMT extension support" depends on 64BIT && MMU + depends on !XIP_KERNEL select RISCV_ALTERNATIVE default y help -- cgit From 2a2018c3ac84c2dc7cfbad117ce9339ea0914622 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 7 Sep 2022 17:49:32 +0200 Subject: riscv: make t-head erratas depend on MMU Both basic extensions of SVPBMT and ZICBOM depend on CONFIG_MMU. Make the T-Head errata implementations of the similar functionality also depend on it to prevent build errors. Fixes: a35707c3d850 ("riscv: add memory-type errata for T-Head") Fixes: d20ec7529236 ("riscv: implement cache-management errata for T-Head SoCs") Reported-by: kernel test robot Signed-off-by: Heiko Stuebner Reviewed-by: Guo Ren Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220907154932.2858518-1-heiko@sntech.de Signed-off-by: Palmer Dabbelt --- arch/riscv/Kconfig.erratas | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index 6850e9389930..f3623df23b5f 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -46,7 +46,7 @@ config ERRATA_THEAD config ERRATA_THEAD_PBMT bool "Apply T-Head memory type errata" - depends on ERRATA_THEAD && 64BIT + depends on ERRATA_THEAD && 64BIT && MMU select RISCV_ALTERNATIVE_EARLY default y help @@ -57,7 +57,7 @@ config ERRATA_THEAD_PBMT config ERRATA_THEAD_CMO bool "Apply T-Head cache management errata" - depends on ERRATA_THEAD + depends on ERRATA_THEAD && MMU select RISCV_DMA_NONCOHERENT default y help -- cgit From 762df359aa5849e010ef04c3ed79d57588ce17d9 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Fri, 24 Sep 2021 01:55:27 +0000 Subject: riscv: fix a nasty sigreturn bug... riscv has an equivalent of arm bug fixed by 653d48b22166 ("arm: fix really nasty sigreturn bug"); if signal gets caught by an interrupt that hits when we have the right value in a0 (-513), *and* another signal gets delivered upon sigreturn() (e.g. included into the blocked mask for the first signal and posted while the handler had been running), the syscall restart logics will see regs->cause equal to EXC_SYSCALL (we are in a syscall, after all) and a0 already restored to its original value (-513, which happens to be -ERESTARTNOINTR) and assume that we need to apply the usual syscall restart logics. Signed-off-by: Al Viro Fixes: e2c0cdfba7f6 ("RISC-V: User-facing API") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/YxJEiSq%2FCGaL6Gm9@ZenIV/ Signed-off-by: Palmer Dabbelt --- arch/riscv/kernel/signal.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 5a2de6b6f882..5c591123c440 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -124,6 +124,8 @@ SYSCALL_DEFINE0(rt_sigreturn) if (restore_altstack(&frame->uc.uc_stack)) goto badframe; + regs->cause = -1UL; + return regs->a0; badframe: -- cgit From c589e3ca27c9f608004b155d3acb2fab6f7a9f26 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Thu, 15 Sep 2022 10:09:00 -0700 Subject: RISC-V: Avoid coupling the T-Head CMOs and Zicbom We could make the T-Head CMOs depend on a new-enough assembler to have Zicbom, but it's not strictly necessary because the T-Head CMOs circumvent the assembler. Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") Reported-by: kernel test robot Reported-by: Conor Dooley Signed-off-by: Palmer Dabbelt Reviewed-by: Heiko Stuebner Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20220915170900.22685-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt --- arch/riscv/include/asm/cacheflush.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index a89c005b4bbf..273ece6b622f 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -42,8 +42,12 @@ void flush_icache_mm(struct mm_struct *mm, bool local); #endif /* CONFIG_SMP */ -#ifdef CONFIG_RISCV_ISA_ZICBOM +/* + * The T-Head CMO errata internally probe the CBOM block size, but otherwise + * don't depend on Zicbom. + */ extern unsigned int riscv_cbom_block_size; +#ifdef CONFIG_RISCV_ISA_ZICBOM void riscv_init_cbom_blocksize(void); #else static inline void riscv_init_cbom_blocksize(void) { } -- cgit