From 1435696556e46a7dc22a4b2fb1a9a68ae75591c2 Mon Sep 17 00:00:00 2001 From: Suzuki K Poulose Date: Tue, 11 Sep 2018 11:17:12 +0100 Subject: ARM: dts: vexpress/TC2: Update entries to match latest coresight bindings Switch to the new coresight bindings Cc: Liviu Dudau Cc: Sudeep Holla Cc: Lorenzo Pieralisi Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose [sudeep.holla: updated title and fixed couple of remaining dtc warnings] Signed-off-by: Sudeep Holla --- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 94 ++++++++++++++++-------------- 1 file changed, 49 insertions(+), 45 deletions(-) diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index ac6b90e9d806..8b926c30ccd1 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -393,10 +393,11 @@ clocks = <&oscclk6a>; clock-names = "apb_pclk"; - port { - etb_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port0>; + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; }; }; }; @@ -407,10 +408,11 @@ clocks = <&oscclk6a>; clock-names = "apb_pclk"; - port { - tpiu_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; }; }; }; @@ -421,11 +423,10 @@ */ compatible = "arm,coresight-replicator"; - ports { + out-ports { #address-cells = <1>; #size-cells = <0>; - /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { @@ -439,12 +440,11 @@ remote-endpoint = <&tpiu_in_port>; }; }; + }; - /* replicator input port */ - port@2 { - reg = <0>; + in-ports { + port { replicator_in_port0: endpoint { - slave-mode; remote-endpoint = <&funnel_out_port0>; }; }; @@ -457,40 +457,36 @@ clocks = <&oscclk6a>; clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel output port */ - port@0 { - reg = <0>; + out-ports { + port { funnel_out_port0: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; + }; - /* funnel input ports */ - port@1 { + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { reg = <0>; funnel_in_port0: endpoint { - slave-mode; remote-endpoint = <&ptm0_out_port>; }; }; - port@2 { + port@1 { reg = <1>; funnel_in_port1: endpoint { - slave-mode; remote-endpoint = <&ptm1_out_port>; }; }; - port@3 { + port@2 { reg = <2>; funnel_in_port2: endpoint { - slave-mode; remote-endpoint = <&etm0_out_port>; }; }; @@ -500,7 +496,6 @@ port@4 { reg = <4>; funnel_in_port4: endpoint { - slave-mode; remote-endpoint = <&etm1_out_port>; }; }; @@ -508,7 +503,6 @@ port@5 { reg = <5>; funnel_in_port5: endpoint { - slave-mode; remote-endpoint = <&etm2_out_port>; }; }; @@ -522,9 +516,11 @@ cpu = <&cpu0>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; - port { - ptm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; }; }; }; @@ -536,9 +532,11 @@ cpu = <&cpu1>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; - port { - ptm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port1>; + out-ports { + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; }; }; }; @@ -550,9 +548,11 @@ cpu = <&cpu2>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; - port { - etm0_out_port: endpoint { - remote-endpoint = <&funnel_in_port2>; + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port2>; + }; }; }; }; @@ -564,9 +564,11 @@ cpu = <&cpu3>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; - port { - etm1_out_port: endpoint { - remote-endpoint = <&funnel_in_port4>; + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port4>; + }; }; }; }; @@ -578,9 +580,11 @@ cpu = <&cpu4>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; - port { - etm2_out_port: endpoint { - remote-endpoint = <&funnel_in_port5>; + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&funnel_in_port5>; + }; }; }; }; -- cgit From 69fd70c7ff31d3f00833c472c3994a02bb0ab287 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 31 Aug 2018 18:14:49 +0300 Subject: ARM: dts: am33xx: convert to use new clkctrl layout Convert AM33xx to use the new clockdomain based layout. Previously the clkctrl split was based on CM instance boundaries. The new layout helps with introducing the interconnect driver instances. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone-common.dtsi | 2 +- arch/arm/boot/dts/am335x-boneblue.dts | 2 +- arch/arm/boot/dts/am335x-evm.dts | 2 +- arch/arm/boot/dts/am335x-evmsk.dts | 2 +- arch/arm/boot/dts/am335x-osd3358-sm-red.dts | 2 +- arch/arm/boot/dts/am33xx-clocks.dtsi | 110 +++++++++++++++++++++------- arch/arm/boot/dts/am33xx.dtsi | 2 +- 7 files changed, 88 insertions(+), 34 deletions(-) diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 9e5e75ea87f5..456eef57ef89 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -419,6 +419,6 @@ }; &rtc { - clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index 7bcd72691f06..ccb147e70d17 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -515,7 +515,7 @@ &rtc { system-power-controller; - clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 98ec9c3e49ba..b7343fab899b 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -797,6 +797,6 @@ }; &rtc { - clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 245868f58fe3..88b41f8d08ae 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -738,6 +738,6 @@ }; &rtc { - clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts index 85cd1d0a73ca..95d54cf3849e 100644 --- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts +++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts @@ -456,6 +456,6 @@ }; &rtc { - clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "ext-clk", "int-clk"; }; diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index 95d5c9d136c5..922182439048 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -334,49 +334,49 @@ timer1_fck: timer1_fck@528 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; + clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; reg = <0x0528>; }; timer2_fck: timer2_fck@508 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0508>; }; timer3_fck: timer3_fck@50c { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x050c>; }; timer4_fck: timer4_fck@510 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0510>; }; timer5_fck: timer5_fck@518 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0518>; }; timer6_fck: timer6_fck@51c { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x051c>; }; timer7_fck: timer7_fck@504 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0504>; }; @@ -407,7 +407,7 @@ wdt1_fck: wdt1_fck@538 { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x0538>; }; @@ -477,7 +477,7 @@ gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c { #clock-cells = <0>; compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; reg = <0x053c>; }; @@ -539,86 +539,140 @@ }; &prcm { - l4_per_cm: l4_per_cm@0 { + per_cm: per-cm@0 { compatible = "ti,omap4-cm"; - reg = <0x0 0x200>; + reg = <0x0 0x400>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x0 0x200>; + ranges = <0 0x0 0x400>; - l4_per_clkctrl: clk@14 { + l4ls_clkctrl: l4ls-clkctrl@38 { compatible = "ti,clkctrl"; - reg = <0x14 0x13c>; + reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; + #clock-cells = <2>; + }; + + l3s_clkctrl: l3s-clkctrl@1c { + compatible = "ti,clkctrl"; + reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>; + #clock-cells = <2>; + }; + + l3_clkctrl: l3-clkctrl@24 { + compatible = "ti,clkctrl"; + reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; + #clock-cells = <2>; + }; + + l4hs_clkctrl: l4hs-clkctrl@120 { + compatible = "ti,clkctrl"; + reg = <0x120 0x4>; + #clock-cells = <2>; + }; + + pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 { + compatible = "ti,clkctrl"; + reg = <0xe8 0x4>; + #clock-cells = <2>; + }; + + cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x18>; + #clock-cells = <2>; + }; + + lcdc_clkctrl: lcdc-clkctrl@18 { + compatible = "ti,clkctrl"; + reg = <0x18 0x4>; + #clock-cells = <2>; + }; + + clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c { + compatible = "ti,clkctrl"; + reg = <0x14c 0x4>; #clock-cells = <2>; }; }; - l4_wkup_cm: l4_wkup_cm@400 { + wkup_cm: wkup-cm@400 { compatible = "ti,omap4-cm"; reg = <0x400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x400 0x100>; - l4_wkup_clkctrl: clk@4 { + l4_wkup_clkctrl: l4-wkup-clkctrl@0 { + compatible = "ti,clkctrl"; + reg = <0x0 0x10>, <0xb4 0x24>; + #clock-cells = <2>; + }; + + l3_aon_clkctrl: l3-aon-clkctrl@14 { + compatible = "ti,clkctrl"; + reg = <0x14 0x4>; + #clock-cells = <2>; + }; + + l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 { compatible = "ti,clkctrl"; - reg = <0x4 0xd4>; + reg = <0xb0 0x4>; #clock-cells = <2>; }; }; - mpu_cm: mpu_cm@600 { + mpu_cm: mpu-cm@600 { compatible = "ti,omap4-cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; - mpu_clkctrl: clk@4 { + mpu_clkctrl: mpu-clkctrl@0 { compatible = "ti,clkctrl"; - reg = <0x4 0x4>; + reg = <0x0 0x8>; #clock-cells = <2>; }; }; - l4_rtc_cm: l4_rtc_cm@800 { + l4_rtc_cm: l4-rtc-cm@800 { compatible = "ti,omap4-cm"; reg = <0x800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x800 0x100>; - l4_rtc_clkctrl: clk@0 { + l4_rtc_clkctrl: l4-rtc-clkctrl@0 { compatible = "ti,clkctrl"; reg = <0x0 0x4>; #clock-cells = <2>; }; }; - gfx_l3_cm: gfx_l3_cm@900 { + gfx_l3_cm: gfx-l3-cm@900 { compatible = "ti,omap4-cm"; reg = <0x900 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x900 0x100>; - gfx_l3_clkctrl: clk@4 { + gfx_l3_clkctrl: gfx-l3-clkctrl@0 { compatible = "ti,clkctrl"; - reg = <0x4 0x4>; + reg = <0x0 0x8>; #clock-cells = <2>; }; }; - l4_cefuse_cm: l4_cefuse_cm@a00 { + l4_cefuse_cm: l4-cefuse-cm@a00 { compatible = "ti,omap4-cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xa00 0x100>; - l4_cefuse_clkctrl: clk@20 { + l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 { compatible = "ti,clkctrl"; - reg = <0x20 0x4>; + reg = <0x0 0x24>; #clock-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index d3dd6a16e70a..44240c797e2c 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -581,7 +581,7 @@ interrupts = <75 76>; ti,hwmods = "rtc"; - clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>; + clocks = <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; clock-names = "int-clk"; }; -- cgit From 23298c33f9b3c6a8d7b6bed303b7ee4d87a42b94 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 31 Aug 2018 18:14:50 +0300 Subject: ARM: dts: am43xx: convert to use new clkctrl layout Convert AM43xx to use the new clockdomain based layout. Previously the clkctrl split was based on CM isntance boundaries. The new layout helps with introducing the interconnect driver instances. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 4 +- arch/arm/boot/dts/am43xx-clocks.dtsi | 74 ++++++++++++++++++++++++++++++------ 2 files changed, 64 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index a68e89dae7a1..af624f8a387f 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -1017,7 +1017,7 @@ reg = <0x483a8000 0x8000>; syscon-phy-power = <&scm_conf 0x620>; clocks = <&usb_phy0_always_on_clk32k>, - <&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>; + <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; status = "disabled"; @@ -1036,7 +1036,7 @@ reg = <0x483e8000 0x8000>; syscon-phy-power = <&scm_conf 0x628>; clocks = <&usb_phy1_always_on_clk32k>, - <&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>; + <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; status = "disabled"; diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index a7037a4b4fd4..e3f420793c12 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -710,73 +710,123 @@ }; &prcm { - l4_wkup_cm: l4_wkup_cm@2800 { + wkup_cm: wkup-cm@2800 { compatible = "ti,omap4-cm"; reg = <0x2800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2800 0x400>; - l4_wkup_clkctrl: clk@20 { + l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 { compatible = "ti,clkctrl"; - reg = <0x20 0x34c>; + reg = <0x120 0x4>; #clock-cells = <2>; }; + + l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 { + compatible = "ti,clkctrl"; + reg = <0x228 0xc>; + #clock-cells = <2>; + }; + + l4_wkup_clkctrl: l4-wkup-clkctrl@220 { + compatible = "ti,clkctrl"; + reg = <0x220 0x4>, <0x328 0x44>; + #clock-cells = <2>; + }; + }; - mpu_cm: mpu_cm@8300 { + mpu_cm: mpu-cm@8300 { compatible = "ti,omap4-cm"; reg = <0x8300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8300 0x100>; - mpu_clkctrl: clk@20 { + mpu_clkctrl: mpu-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - gfx_l3_cm: gfx_l3_cm@8400 { + gfx_l3_cm: gfx-l3-cm@8400 { compatible = "ti,omap4-cm"; reg = <0x8400 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8400 0x100>; - gfx_l3_clkctrl: clk@20 { + gfx_l3_clkctrl: gfx-l3-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - l4_rtc_cm: l4_rtc_cm@8500 { + l4_rtc_cm: l4-rtc-cm@8500 { compatible = "ti,omap4-cm"; reg = <0x8500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8500 0x100>; - l4_rtc_clkctrl: clk@20 { + l4_rtc_clkctrl: l4-rtc-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - l4_per_cm: l4_per_cm@8800 { + per_cm: per-cm@8800 { compatible = "ti,omap4-cm"; reg = <0x8800 0xc00>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8800 0xc00>; - l4_per_clkctrl: clk@20 { + l3_clkctrl: l3-clkctrl@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x3c>, <0x78 0x2c>; + #clock-cells = <2>; + }; + + l3s_clkctrl: l3s-clkctrl@68 { + compatible = "ti,clkctrl"; + reg = <0x68 0xc>, <0x220 0x4c>; + #clock-cells = <2>; + }; + + pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 { compatible = "ti,clkctrl"; - reg = <0x20 0xb04>; + reg = <0x320 0x4>; #clock-cells = <2>; }; + + l4ls_clkctrl: l4ls-clkctrl@420 { + compatible = "ti,clkctrl"; + reg = <0x420 0x1a4>; + #clock-cells = <2>; + }; + + emif_clkctrl: emif-clkctrl@720 { + compatible = "ti,clkctrl"; + reg = <0x720 0x4>; + #clock-cells = <2>; + }; + + dss_clkctrl: dss-clkctrl@a20 { + compatible = "ti,clkctrl"; + reg = <0xa20 0x4>; + #clock-cells = <2>; + }; + + cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 { + compatible = "ti,clkctrl"; + reg = <0xb20 0x4>; + #clock-cells = <2>; + }; + }; }; -- cgit From b5f8ffbb6fad9151634805c2001af4afbb884eca Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 31 Aug 2018 18:14:51 +0300 Subject: ARM: dts: dra7: convert to use new clkctrl layout Convert DRA7xx to use the new clockdomain based layout. Previously the clkctrl split was based on CM isntance boundaries. The new layout helps with introducing the interconnect driver instances. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 2 +- arch/arm/boot/dts/dra7-evm-common.dtsi | 4 +- arch/arm/boot/dts/dra7.dtsi | 76 +++++------ arch/arm/boot/dts/dra72-evm-common.dtsi | 4 +- arch/arm/boot/dts/dra72x.dtsi | 4 +- arch/arm/boot/dts/dra74x.dtsi | 6 +- arch/arm/boot/dts/dra76x.dtsi | 2 +- arch/arm/boot/dts/dra7xx-clocks.dtsi | 159 ++++++++++++++++++------ 8 files changed, 171 insertions(+), 86 deletions(-) diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index ad953113cefb..1e6620f139dd 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -555,7 +555,7 @@ &mcasp3 { #sound-dai-cells = <0>; - assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; + assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; assigned-clock-parents = <&sys_clkin2>; status = "okay"; diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi index 7e18147dc563..0d6f8647cc91 100644 --- a/arch/arm/boot/dts/dra7-evm-common.dtsi +++ b/arch/arm/boot/dts/dra7-evm-common.dtsi @@ -214,7 +214,7 @@ &atl { assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_clkctrl DRA7_ATL_CLKCTRL 26>, + <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, <&dpll_abe_ck>, <&dpll_abe_m2x2_ck>, <&atl_clkin2_ck>; @@ -232,7 +232,7 @@ &mcasp3 { #sound-dai-cells = <0>; - assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; + assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; assigned-clock-parents = <&atl_clkin2_ck>; status = "okay"; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 7ce24b282d42..d140d970672e 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -899,7 +899,7 @@ ti,hwmods = "timer1"; ti,timer-alwon; clock-names = "fck"; - clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; }; timer2: timer@48032000 { @@ -1380,7 +1380,7 @@ #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; - clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>; + clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; clock-names = "fck"; num-cs = <4>; interrupts = ; @@ -1403,7 +1403,7 @@ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; syscon-phy-power = <&scm_conf 0x374>; clocks = <&sys_clkin1>, - <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>; + <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; clock-names = "sysclk", "refclk"; syscon-pllreset = <&scm_conf 0x3fc>; #phy-cells = <0>; @@ -1418,9 +1418,9 @@ syscon-pcs = <&scm_conf_pcie 0x10>; clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_m2ldo_ck>, - <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>, - <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>, - <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, <&optfclk_pciephy_div>, <&sys_clkin1>; clock-names = "dpll_ref", "dpll_ref_m2", @@ -1438,9 +1438,9 @@ syscon-pcs = <&scm_conf_pcie 0x10>; clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_m2ldo_ck>, - <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>, - <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>, - <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, <&optfclk_pciephy_div>, <&sys_clkin1>; clock-names = "dpll_ref", "dpll_ref_m2", @@ -1457,7 +1457,7 @@ interrupts = ; phys = <&sata_phy>; phy-names = "sata-phy"; - clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>; + clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; ti,hwmods = "sata"; ports-implemented = <0x1>; }; @@ -1485,7 +1485,7 @@ reg = <0x4a084000 0x400>; syscon-phy-power = <&scm_conf 0x300>; clocks = <&usb_phy1_always_on_clk32k>, - <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>; + <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; @@ -1497,7 +1497,7 @@ reg = <0x4a085000 0x400>; syscon-phy-power = <&scm_conf 0xe74>; clocks = <&usb_phy2_always_on_clk32k>, - <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>; + <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; @@ -1512,7 +1512,7 @@ syscon-phy-power = <&scm_conf 0x370>; clocks = <&usb_phy3_always_on_clk32k>, <&sys_clkin1>, - <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>; + <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; clock-names = "wkupclk", "sysclk", "refclk"; @@ -1530,7 +1530,7 @@ , , ; - clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>; + clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; @@ -1549,7 +1549,7 @@ , , ; - clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>; + clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; @@ -1672,7 +1672,7 @@ ti,hwmods = "atl"; ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, <&atl_clkin2_ck>, <&atl_clkin3_ck>; - clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; clock-names = "fck"; status = "disabled"; }; @@ -1688,8 +1688,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; dma-names = "tx", "rx"; - clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>, - <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>; + clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; status = "disabled"; }; @@ -1705,9 +1705,9 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; dma-names = "tx", "rx"; - clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>, - <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>, - <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; clock-names = "fck", "ahclkx", "ahclkr"; status = "disabled"; }; @@ -1723,8 +1723,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; dma-names = "tx", "rx"; - clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>, - <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; @@ -1740,8 +1740,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; dma-names = "tx", "rx"; - clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>, - <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; @@ -1757,8 +1757,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; dma-names = "tx", "rx"; - clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>, - <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; @@ -1774,8 +1774,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; dma-names = "tx", "rx"; - clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>, - <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; @@ -1791,8 +1791,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; dma-names = "tx", "rx"; - clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>, - <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; @@ -1808,8 +1808,8 @@ interrupt-names = "tx", "rx"; dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; dma-names = "tx", "rx"; - clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>, - <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; clock-names = "fck", "ahclkx"; status = "disabled"; }; @@ -1831,7 +1831,7 @@ mac: ethernet@48484000 { compatible = "ti,dra7-cpsw","ti,cpsw"; ti,hwmods = "gmac"; - clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>; + clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; clock-names = "fck", "cpts"; cpdma_channels = <8>; ale_entries = <1024>; @@ -1901,7 +1901,7 @@ reg = <0x4ae3c000 0x2000>; syscon-raminit = <&scm_conf 0x558 0>; interrupts = ; - clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; status = "disabled"; }; @@ -1932,7 +1932,7 @@ reg = <0x58001000 0x1000>; interrupts = ; ti,hwmods = "dss_dispc"; - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; /* CTRL_CORE_SMA_SW_1 */ syscon-pol = <&scm_conf 0x534>; @@ -1948,8 +1948,8 @@ interrupts = ; status = "disabled"; ti,hwmods = "dss_hdmi"; - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; dmas = <&sdma_xbar 76>; dma-names = "audio_tx"; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index e297b923b71a..be65f3bc59d1 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -530,7 +530,7 @@ &atl { assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_clkctrl DRA7_ATL_CLKCTRL 26>, + <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, <&dpll_abe_ck>, <&dpll_abe_m2x2_ck>, <&atl_clkin2_ck>; @@ -548,7 +548,7 @@ &mcasp3 { #sound-dai-cells = <0>; - assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; + assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; assigned-clock-parents = <&atl_clkin2_ck>; status = "okay"; diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index c011d2e64fef..89831552cd86 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -25,8 +25,8 @@ <0x58004300 0x20>; reg-names = "dss", "pll1_clkctrl", "pll1"; - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>, - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>; clock-names = "fck", "video1_clk"; }; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 8f9df09155d8..8294a607fec8 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -103,9 +103,9 @@ reg-names = "dss", "pll1_clkctrl", "pll1", "pll2_clkctrl", "pll2"; - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>, - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>, - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 13>; + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>, + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>; clock-names = "fck", "video1_clk", "video2_clk"; }; diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi index 613e4dc0ed3e..9ee45aa365d8 100644 --- a/arch/arm/boot/dts/dra76x.dtsi +++ b/arch/arm/boot/dts/dra76x.dtsi @@ -24,7 +24,7 @@ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET | SYSC_DRA7_MCAN_ENAWAKEUP)>; ti,syss-mask = <1>; - clocks = <&wkupaon_clkctrl DRA7_ADC_CLKCTRL 0>; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>; clock-names = "fck"; m_can0: mcan@1a00 { diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 69562cdbeada..bb52c6f0e90e 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -11,25 +11,25 @@ atl_clkin0_ck: atl_clkin0_ck { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; - clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; atl_clkin1_ck: atl_clkin1_ck { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; - clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; atl_clkin2_ck: atl_clkin2_ck { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; - clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; atl_clkin3_ck: atl_clkin3_ck { #clock-cells = <0>; compatible = "ti,dra7-atl-clock"; - clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; }; hdmi_clkin_ck: hdmi_clkin_ck { @@ -1526,44 +1526,82 @@ }; &cm_core_aon { - mpu_cm: mpu_cm@300 { + mpu_cm: mpu-cm@300 { compatible = "ti,omap4-cm"; reg = <0x300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x300 0x100>; - mpu_clkctrl: clk@20 { + mpu_clkctrl: mpu-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; + + }; + + dsp1_cm: dsp1-cm@400 { + compatible = "ti,omap4-cm"; + reg = <0x400 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x400 0x100>; + + dsp1_clkctrl: dsp1-clkctrl@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; - ipu_cm: ipu_cm@500 { + ipu_cm: ipu-cm@500 { compatible = "ti,omap4-cm"; reg = <0x500 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x500 0x100>; - ipu_clkctrl: clk@40 { + ipu1_clkctrl: ipu1-clkctrl@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + + ipu_clkctrl: ipu-clkctrl@50 { + compatible = "ti,clkctrl"; + reg = <0x50 0x34>; + #clock-cells = <2>; + }; + + }; + + dsp2_cm: dsp2-cm@600 { + compatible = "ti,omap4-cm"; + reg = <0x600 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x600 0x100>; + + dsp2_clkctrl: dsp2-clkctrl@20 { compatible = "ti,clkctrl"; - reg = <0x40 0x44>; + reg = <0x20 0x4>; #clock-cells = <2>; }; + }; - rtc_cm: rtc_cm@700 { + rtc_cm: rtc-cm@700 { compatible = "ti,omap4-cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x700 0x100>; - rtc_clkctrl: clk@40 { + rtc_clkctrl: rtc-clkctrl@20 { compatible = "ti,clkctrl"; - reg = <0x40 0x8>; + reg = <0x20 0x28>; #clock-cells = <2>; }; }; @@ -1571,160 +1609,207 @@ }; &cm_core { - coreaon_cm: coreaon_cm@600 { + coreaon_cm: coreaon-cm@600 { compatible = "ti,omap4-cm"; reg = <0x600 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x600 0x100>; - coreaon_clkctrl: clk@20 { + coreaon_clkctrl: coreaon-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x1c>; #clock-cells = <2>; }; }; - l3main1_cm: l3main1_cm@700 { + l3main1_cm: l3main1-cm@700 { compatible = "ti,omap4-cm"; reg = <0x700 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x700 0x100>; - l3main1_clkctrl: clk@20 { + l3main1_clkctrl: l3main1-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x74>; #clock-cells = <2>; }; + + }; + + ipu2_cm: ipu2-cm@900 { + compatible = "ti,omap4-cm"; + reg = <0x900 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x900 0x100>; + + ipu2_clkctrl: ipu2-clkctrl@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x4>; + #clock-cells = <2>; + }; + }; - dma_cm: dma_cm@a00 { + dma_cm: dma-cm@a00 { compatible = "ti,omap4-cm"; reg = <0xa00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xa00 0x100>; - dma_clkctrl: clk@20 { + dma_clkctrl: dma-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - emif_cm: emif_cm@b00 { + emif_cm: emif-cm@b00 { compatible = "ti,omap4-cm"; reg = <0xb00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xb00 0x100>; - emif_clkctrl: clk@20 { + emif_clkctrl: emif-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x4>; #clock-cells = <2>; }; }; - atl_cm: atl_cm@c00 { + atl_cm: atl-cm@c00 { compatible = "ti,omap4-cm"; reg = <0xc00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xc00 0x100>; - atl_clkctrl: clk@0 { + atl_clkctrl: atl-clkctrl@0 { compatible = "ti,clkctrl"; reg = <0x0 0x4>; #clock-cells = <2>; }; }; - l4cfg_cm: l4cfg_cm@d00 { + l4cfg_cm: l4cfg-cm@d00 { compatible = "ti,omap4-cm"; reg = <0xd00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xd00 0x100>; - l4cfg_clkctrl: clk@20 { + l4cfg_clkctrl: l4cfg-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x84>; #clock-cells = <2>; }; }; - l3instr_cm: l3instr_cm@e00 { + l3instr_cm: l3instr-cm@e00 { compatible = "ti,omap4-cm"; reg = <0xe00 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xe00 0x100>; - l3instr_clkctrl: clk@20 { + l3instr_clkctrl: l3instr-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0xc>; #clock-cells = <2>; }; }; - dss_cm: dss_cm@1100 { + dss_cm: dss-cm@1100 { compatible = "ti,omap4-cm"; reg = <0x1100 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1100 0x100>; - dss_clkctrl: clk@20 { + dss_clkctrl: dss-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x14>; #clock-cells = <2>; }; }; - l3init_cm: l3init_cm@1300 { + l3init_cm: l3init-cm@1300 { compatible = "ti,omap4-cm"; reg = <0x1300 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1300 0x100>; - l3init_clkctrl: clk@20 { + l3init_clkctrl: l3init-clkctrl@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0x6c>, <0xe0 0x14>; + #clock-cells = <2>; + }; + + pcie_clkctrl: pcie-clkctrl@b0 { + compatible = "ti,clkctrl"; + reg = <0xb0 0xc>; + #clock-cells = <2>; + }; + + gmac_clkctrl: gmac-clkctrl@d0 { compatible = "ti,clkctrl"; - reg = <0x20 0xd4>; + reg = <0xd0 0x4>; #clock-cells = <2>; }; + }; - l4per_cm: l4per_cm@1700 { + l4per_cm: l4per-cm@1700 { compatible = "ti,omap4-cm"; reg = <0x1700 0x300>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1700 0x300>; - l4per_clkctrl: clk@0 { + l4per_clkctrl: l4per-clkctrl@28 { compatible = "ti,clkctrl"; - reg = <0x0 0x20c>; + reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>; #clock-cells = <2>; - assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; + assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; assigned-clock-parents = <&abe_24m_fclk>; }; + + l4sec_clkctrl: l4sec-clkctrl@1a0 { + compatible = "ti,clkctrl"; + reg = <0x1a0 0x2c>; + #clock-cells = <2>; + }; + + l4per2_clkctrl: l4per2-clkctrl@c { + compatible = "ti,clkctrl"; + reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>; + #clock-cells = <2>; + }; + + l4per3_clkctrl: l4per3-clkctrl@14 { + compatible = "ti,clkctrl"; + reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>; + #clock-cells = <2>; + }; }; }; &prm { - wkupaon_cm: wkupaon_cm@1800 { + wkupaon_cm: wkupaon-cm@1800 { compatible = "ti,omap4-cm"; reg = <0x1800 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1800 0x100>; - wkupaon_clkctrl: clk@20 { + wkupaon_clkctrl: wkupaon-clkctrl@20 { compatible = "ti,clkctrl"; reg = <0x20 0x6c>; #clock-cells = <2>; -- cgit From 21c0607cc40d2ae169e2d3ddd10ed0e43206032f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 18 Oct 2018 09:32:02 -0700 Subject: ARM: dts: am437x: Add l4 interconnect hierarchy and ti-sysc data Similar to commit 8f42cb7f64c7 ("ARM: dts: omap4: Add l4 interconnect hierarchy and ti-sysc data"), let's add proper interconnect hierarchy for l4 interconnect instances with the related ti-sysc interconnect module data as in Documentation/devicetree/bindings/bus/ti-sysc.txt. Using ti-sysc driver binding allows us to start dropping legacy platform data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of ti-sysc dts data. This data is generated based on platform data from a booted system and the interconnect acces protection registers for ranges. To avoid regressions, we initially validate the device tree provided data against the existing platform data on boot. Note that we cannot yet include this file from the SoC dtsi file until the child devices are moved to their proper locations in the interconnect hierarchy in the following patch. Otherwise we would have the each module probed twice. Cc: Dave Gerlach Cc: Keerthy Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 1662 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 1662 insertions(+) create mode 100644 arch/arm/boot/dts/am437x-l4.dtsi diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi new file mode 100644 index 000000000000..4829129aabd5 --- /dev/null +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -0,0 +1,1662 @@ +&l4_wkup { /* 0x44c00000 */ + compatible = "ti,am4-l4-wkup", "simple-bus"; + reg = <0x44c00000 0x800>, + <0x44c00800 0x800>, + <0x44c01000 0x400>, + <0x44c01400 0x400>; + reg-names = "ap", "la", "ia0", "ia1"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ + <0x00100000 0x44d00000 0x100000>, /* segment 1 */ + <0x00200000 0x44e00000 0x100000>; /* segment 2 */ + + segment@0 { /* 0x44c00000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00001400 0x00001400 0x000400>; /* ap 3 */ + }; + + segment@100000 { /* 0x44d00000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ + <0x00004000 0x00104000 0x001000>, /* ap 5 */ + <0x00080000 0x00180000 0x002000>, /* ap 6 */ + <0x00082000 0x00182000 0x001000>, /* ap 7 */ + <0x000f0000 0x001f0000 0x010000>; /* ap 8 */ + + target-module@0 { /* 0x44d00000, ap 4 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x4000>; + }; + + target-module@80000 { /* 0x44d80000, ap 6 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x2000>; + }; + + target-module@f0000 { /* 0x44df0000, ap 8 58.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0000 0x10000>; + }; + }; + + segment@200000 { /* 0x44e00000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */ + <0x00003000 0x00203000 0x001000>, /* ap 10 */ + <0x00004000 0x00204000 0x001000>, /* ap 11 */ + <0x00005000 0x00205000 0x001000>, /* ap 12 */ + <0x00006000 0x00206000 0x001000>, /* ap 13 */ + <0x00007000 0x00207000 0x001000>, /* ap 14 */ + <0x00008000 0x00208000 0x001000>, /* ap 15 */ + <0x00009000 0x00209000 0x001000>, /* ap 16 */ + <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ + <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ + <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ + <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ + <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ + <0x00010000 0x00210000 0x010000>, /* ap 22 */ + <0x00030000 0x00230000 0x001000>, /* ap 23 */ + <0x00031000 0x00231000 0x001000>, /* ap 24 */ + <0x00032000 0x00232000 0x001000>, /* ap 25 */ + <0x00033000 0x00233000 0x001000>, /* ap 26 */ + <0x00034000 0x00234000 0x001000>, /* ap 27 */ + <0x00035000 0x00235000 0x001000>, /* ap 28 */ + <0x00036000 0x00236000 0x001000>, /* ap 29 */ + <0x00037000 0x00237000 0x001000>, /* ap 30 */ + <0x00038000 0x00238000 0x001000>, /* ap 31 */ + <0x00039000 0x00239000 0x001000>, /* ap 32 */ + <0x0003a000 0x0023a000 0x001000>, /* ap 33 */ + <0x0003e000 0x0023e000 0x001000>, /* ap 34 */ + <0x0003f000 0x0023f000 0x001000>, /* ap 35 */ + <0x00040000 0x00240000 0x040000>, /* ap 36 */ + <0x00080000 0x00280000 0x001000>, /* ap 37 */ + <0x00088000 0x00288000 0x008000>, /* ap 38 */ + <0x00092000 0x00292000 0x001000>, /* ap 39 */ + <0x00086000 0x00286000 0x001000>, /* ap 40 */ + <0x00087000 0x00287000 0x001000>, /* ap 41 */ + <0x00090000 0x00290000 0x001000>, /* ap 42 */ + <0x00091000 0x00291000 0x001000>; /* ap 43 */ + + target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3000 0x1000>; + }; + + target-module@5000 { /* 0x44e05000, ap 12 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5000 0x1000>; + }; + + target-module@7000 { /* 0x44e07000, ap 14 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio1"; + reg = <0x7000 0x4>, + <0x7010 0x4>, + <0x7114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>, + <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; + }; + + target-module@9000 { /* 0x44e09000, ap 16 04.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart1"; + reg = <0x9050 0x4>, + <0x9054 0x4>, + <0x9058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9000 0x1000>; + }; + + target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c1"; + reg = <0xb000 0x8>, + <0xb010 0x8>, + <0xb090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb000 0x1000>; + }; + + target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "adc_tsc"; + reg = <0xd000 0x4>, + <0xd010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkup_pwrdm, l3s_tsc_clkdm */ + clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd000 0x1000>; + }; + + target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x10000>; + }; + + target-module@31000 { /* 0x44e31000, ap 24 40.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + ti,hwmods = "timer1"; + reg = <0x31000 0x4>, + <0x31010 0x4>, + <0x31014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x31000 0x1000>; + }; + + target-module@33000 { /* 0x44e33000, ap 26 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x33000 0x1000>; + }; + + target-module@35000 { /* 0x44e35000, ap 28 50.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "wd_timer2"; + reg = <0x35000 0x4>, + <0x35010 0x4>, + <0x35014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x35000 0x1000>; + }; + + target-module@37000 { /* 0x44e37000, ap 30 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x37000 0x1000>; + }; + + target-module@39000 { /* 0x44e39000, ap 32 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x39000 0x1000>; + }; + + target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "rtc"; + reg = <0x3e074 0x4>, + <0x3e078 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ + clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + }; + + target-module@40000 { /* 0x44e40000, ap 36 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x40000>; + }; + + target-module@86000 { /* 0x44e86000, ap 40 70.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "counter_32k"; + reg = <0x86000 0x4>, + <0x86004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + /* Domains (P, C): wkup_pwrdm, l4_wkup_aon_clkdm */ + clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x86000 0x1000>; + }; + + target-module@88000 { /* 0x44e88000, ap 38 12.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00088000 0x00008000>, + <0x00008000 0x00090000 0x00001000>, + <0x00009000 0x00091000 0x00001000>; + }; + }; +}; + +&l4_fast { /* 0x4a000000 */ + compatible = "ti,am4-l4-fast", "simple-bus"; + reg = <0x4a000000 0x800>, + <0x4a000800 0x800>, + <0x4a001000 0x400>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ + + segment@0 { /* 0x4a000000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00100000 0x00100000 0x008000>, /* ap 3 */ + <0x00108000 0x00108000 0x001000>, /* ap 4 */ + <0x00400000 0x00400000 0x002000>, /* ap 5 */ + <0x00402000 0x00402000 0x001000>, /* ap 6 */ + <0x00200000 0x00200000 0x080000>, /* ap 7 */ + <0x00280000 0x00280000 0x001000>; /* ap 8 */ + + target-module@100000 { /* 0x4a100000, ap 3 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x100000 0x8000>; + }; + + target-module@200000 { /* 0x4a200000, ap 7 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x200000 0x80000>; + }; + + target-module@400000 { /* 0x4a400000, ap 5 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x400000 0x2000>; + }; + }; +}; + +&l4_per { /* 0x48000000 */ + compatible = "ti,am4-l4-per", "simple-bus"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ + <0x00100000 0x48100000 0x100000>, /* segment 1 */ + <0x00200000 0x48200000 0x100000>, /* segment 2 */ + <0x00300000 0x48300000 0x100000>; /* segment 3 */ + + segment@0 { /* 0x48000000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00001400 0x00001400 0x000400>, /* ap 3 */ + <0x00001800 0x00001800 0x000400>, /* ap 4 */ + <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ + <0x00008000 0x00008000 0x001000>, /* ap 6 */ + <0x00009000 0x00009000 0x001000>, /* ap 7 */ + <0x00022000 0x00022000 0x001000>, /* ap 8 */ + <0x00023000 0x00023000 0x001000>, /* ap 9 */ + <0x00024000 0x00024000 0x001000>, /* ap 10 */ + <0x00025000 0x00025000 0x001000>, /* ap 11 */ + <0x0002a000 0x0002a000 0x001000>, /* ap 12 */ + <0x0002b000 0x0002b000 0x001000>, /* ap 13 */ + <0x00038000 0x00038000 0x002000>, /* ap 14 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 15 */ + <0x0003c000 0x0003c000 0x002000>, /* ap 16 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 17 */ + <0x00040000 0x00040000 0x001000>, /* ap 18 */ + <0x00041000 0x00041000 0x001000>, /* ap 19 */ + <0x00042000 0x00042000 0x001000>, /* ap 20 */ + <0x00043000 0x00043000 0x001000>, /* ap 21 */ + <0x00044000 0x00044000 0x001000>, /* ap 22 */ + <0x00045000 0x00045000 0x001000>, /* ap 23 */ + <0x00046000 0x00046000 0x001000>, /* ap 24 */ + <0x00047000 0x00047000 0x001000>, /* ap 25 */ + <0x00048000 0x00048000 0x001000>, /* ap 26 */ + <0x00049000 0x00049000 0x001000>, /* ap 27 */ + <0x0004c000 0x0004c000 0x001000>, /* ap 28 */ + <0x0004d000 0x0004d000 0x001000>, /* ap 29 */ + <0x00060000 0x00060000 0x001000>, /* ap 30 */ + <0x00061000 0x00061000 0x001000>, /* ap 31 */ + <0x00080000 0x00080000 0x010000>, /* ap 32 */ + <0x00090000 0x00090000 0x001000>, /* ap 33 */ + <0x00030000 0x00030000 0x001000>, /* ap 65 */ + <0x00031000 0x00031000 0x001000>, /* ap 66 */ + <0x0004a000 0x0004a000 0x001000>, /* ap 71 */ + <0x0004b000 0x0004b000 0x001000>, /* ap 72 */ + <0x000c8000 0x000c8000 0x001000>, /* ap 73 */ + <0x000c9000 0x000c9000 0x001000>, /* ap 74 */ + <0x000ca000 0x000ca000 0x001000>, /* ap 77 */ + <0x000cb000 0x000cb000 0x001000>, /* ap 78 */ + <0x00034000 0x00034000 0x001000>, /* ap 80 */ + <0x00035000 0x00035000 0x001000>, /* ap 81 */ + <0x00036000 0x00036000 0x001000>, /* ap 84 */ + <0x00037000 0x00037000 0x001000>; /* ap 85 */ + + target-module@8000 { /* 0x48008000, ap 6 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@22000 { /* 0x48022000, ap 8 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart2"; + reg = <0x22050 0x4>, + <0x22054 0x4>, + <0x22058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + }; + + target-module@24000 { /* 0x48024000, ap 10 1c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart3"; + reg = <0x24050 0x4>, + <0x24054 0x4>, + <0x24058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + }; + + target-module@2a000 { /* 0x4802a000, ap 12 22.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c2"; + reg = <0x2a000 0x8>, + <0x2a010 0x8>, + <0x2a090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + }; + + target-module@30000 { /* 0x48030000, ap 65 08.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi0"; + reg = <0x30000 0x4>, + <0x30110 0x4>, + <0x30114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000 0x1000>; + }; + + target-module@34000 { /* 0x48034000, ap 80 56.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x34000 0x1000>; + }; + + target-module@36000 { /* 0x48036000, ap 84 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + + target-module@38000 { /* 0x48038000, ap 14 04.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp0"; + reg = <0x38000 0x4>, + <0x38004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x38000 0x2000>; + }; + + target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp1"; + reg = <0x3c000 0x4>, + <0x3c004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x2000>; + }; + + target-module@40000 { /* 0x48040000, ap 18 1e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer2"; + reg = <0x40000 0x4>, + <0x40010 0x4>, + <0x40014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + }; + + target-module@42000 { /* 0x48042000, ap 20 24.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer3"; + reg = <0x42000 0x4>, + <0x42010 0x4>, + <0x42014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42000 0x1000>; + }; + + target-module@44000 { /* 0x48044000, ap 22 26.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer4"; + reg = <0x44000 0x4>, + <0x44010 0x4>, + <0x44014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x44000 0x1000>; + }; + + target-module@46000 { /* 0x48046000, ap 24 28.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer5"; + reg = <0x46000 0x4>, + <0x46010 0x4>, + <0x46014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x46000 0x1000>; + }; + + target-module@48000 { /* 0x48048000, ap 26 1a.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer6"; + reg = <0x48000 0x4>, + <0x48010 0x4>, + <0x48014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48000 0x1000>; + }; + + target-module@4a000 { /* 0x4804a000, ap 71 48.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer7"; + reg = <0x4a000 0x4>, + <0x4a010 0x4>, + <0x4a014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4a000 0x1000>; + }; + + target-module@4c000 { /* 0x4804c000, ap 28 36.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio2"; + reg = <0x4c000 0x4>, + <0x4c010 0x4>, + <0x4c114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>, + <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000 0x1000>; + }; + + target-module@60000 { /* 0x48060000, ap 30 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmc1"; + reg = <0x602fc 0x4>, + <0x60110 0x4>, + <0x60114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + }; + + target-module@80000 { /* 0x48080000, ap 32 18.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "elm"; + reg = <0x80000 0x4>, + <0x80010 0x4>, + <0x80014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x10000>; + }; + + target-module@c8000 { /* 0x480c8000, ap 73 06.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox"; + reg = <0xc8000 0x4>, + <0xc8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8000 0x1000>; + }; + + target-module@ca000 { /* 0x480ca000, ap 77 38.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spinlock"; + reg = <0xca000 0x4>, + <0xca010 0x4>, + <0xca014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xca000 0x1000>; + }; + }; + + segment@100000 { /* 0x48100000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */ + <0x0008d000 0x0018d000 0x001000>, /* ap 35 */ + <0x0008e000 0x0018e000 0x001000>, /* ap 36 */ + <0x0008f000 0x0018f000 0x001000>, /* ap 37 */ + <0x0009c000 0x0019c000 0x001000>, /* ap 38 */ + <0x0009d000 0x0019d000 0x001000>, /* ap 39 */ + <0x000a6000 0x001a6000 0x001000>, /* ap 40 */ + <0x000a7000 0x001a7000 0x001000>, /* ap 41 */ + <0x000a8000 0x001a8000 0x001000>, /* ap 42 */ + <0x000a9000 0x001a9000 0x001000>, /* ap 43 */ + <0x000aa000 0x001aa000 0x001000>, /* ap 44 */ + <0x000ab000 0x001ab000 0x001000>, /* ap 45 */ + <0x000ac000 0x001ac000 0x001000>, /* ap 46 */ + <0x000ad000 0x001ad000 0x001000>, /* ap 47 */ + <0x000ae000 0x001ae000 0x001000>, /* ap 48 */ + <0x000af000 0x001af000 0x001000>, /* ap 49 */ + <0x000cc000 0x001cc000 0x002000>, /* ap 50 */ + <0x000ce000 0x001ce000 0x002000>, /* ap 51 */ + <0x000d0000 0x001d0000 0x002000>, /* ap 52 */ + <0x000d2000 0x001d2000 0x002000>, /* ap 53 */ + <0x000d8000 0x001d8000 0x001000>, /* ap 54 */ + <0x000d9000 0x001d9000 0x001000>, /* ap 55 */ + <0x000a0000 0x001a0000 0x001000>, /* ap 67 */ + <0x000a1000 0x001a1000 0x001000>, /* ap 68 */ + <0x000a2000 0x001a2000 0x001000>, /* ap 69 */ + <0x000a3000 0x001a3000 0x001000>, /* ap 70 */ + <0x000a4000 0x001a4000 0x001000>, /* ap 92 */ + <0x000a5000 0x001a5000 0x001000>, /* ap 93 */ + <0x000c1000 0x001c1000 0x001000>, /* ap 94 */ + <0x000c2000 0x001c2000 0x001000>; /* ap 95 */ + + target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8c000 0x1000>; + }; + + target-module@8e000 { /* 0x4818e000, ap 36 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8e000 0x1000>; + }; + + target-module@9c000 { /* 0x4819c000, ap 38 52.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c3"; + reg = <0x9c000 0x8>, + <0x9c010 0x8>, + <0x9c090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9c000 0x1000>; + }; + + target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi1"; + reg = <0xa0000 0x4>, + <0xa0110 0x4>, + <0xa0114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa0000 0x1000>; + }; + + target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi2"; + reg = <0xa2000 0x4>, + <0xa2110 0x4>, + <0xa2114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa2000 0x1000>; + }; + + target-module@a4000 { /* 0x481a4000, ap 92 62.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi3"; + reg = <0xa4000 0x4>, + <0xa4110 0x4>, + <0xa4114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa4000 0x1000>; + }; + + target-module@a6000 { /* 0x481a6000, ap 40 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart4"; + reg = <0xa6050 0x4>, + <0xa6054 0x4>, + <0xa6058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa6000 0x1000>; + }; + + target-module@a8000 { /* 0x481a8000, ap 42 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart5"; + reg = <0xa8050 0x4>, + <0xa8054 0x4>, + <0xa8058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x1000>; + }; + + target-module@aa000 { /* 0x481aa000, ap 44 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart6"; + reg = <0xaa050 0x4>, + <0xaa054 0x4>, + <0xaa058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xaa000 0x1000>; + }; + + target-module@ac000 { /* 0x481ac000, ap 46 30.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio3"; + reg = <0xac000 0x4>, + <0xac010 0x4>, + <0xac114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>, + <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xac000 0x1000>; + }; + + target-module@ae000 { /* 0x481ae000, ap 48 32.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio4"; + reg = <0xae000 0x4>, + <0xae010 0x4>, + <0xae114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>, + <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xae000 0x1000>; + }; + + target-module@c1000 { /* 0x481c1000, ap 94 68.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer8"; + reg = <0xc1000 0x4>, + <0xc1010 0x4>, + <0xc1014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc1000 0x1000>; + }; + + target-module@cc000 { /* 0x481cc000, ap 50 46.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xcc000 0x2000>; + }; + + target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000 0x2000>; + }; + + target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmc2"; + reg = <0xd82fc 0x4>, + <0xd8110 0x4>, + <0xd8114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd8000 0x1000>; + }; + }; + + segment@200000 { /* 0x48200000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; + + segment@300000 { /* 0x48300000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */ + <0x00001000 0x00301000 0x001000>, /* ap 57 */ + <0x00002000 0x00302000 0x001000>, /* ap 58 */ + <0x00003000 0x00303000 0x001000>, /* ap 59 */ + <0x00004000 0x00304000 0x001000>, /* ap 60 */ + <0x00005000 0x00305000 0x001000>, /* ap 61 */ + <0x00018000 0x00318000 0x004000>, /* ap 62 */ + <0x0001c000 0x0031c000 0x001000>, /* ap 63 */ + <0x00010000 0x00310000 0x002000>, /* ap 64 */ + <0x00028000 0x00328000 0x001000>, /* ap 75 */ + <0x00029000 0x00329000 0x001000>, /* ap 76 */ + <0x00012000 0x00312000 0x001000>, /* ap 79 */ + <0x00020000 0x00320000 0x001000>, /* ap 82 */ + <0x00021000 0x00321000 0x001000>, /* ap 83 */ + <0x00026000 0x00326000 0x001000>, /* ap 86 */ + <0x00027000 0x00327000 0x001000>, /* ap 87 */ + <0x0002a000 0x0032a000 0x000400>, /* ap 88 */ + <0x0002c000 0x0032c000 0x001000>, /* ap 89 */ + <0x00013000 0x00313000 0x001000>, /* ap 90 */ + <0x00014000 0x00314000 0x001000>, /* ap 91 */ + <0x00006000 0x00306000 0x001000>, /* ap 96 */ + <0x00007000 0x00307000 0x001000>, /* ap 97 */ + <0x00008000 0x00308000 0x001000>, /* ap 98 */ + <0x00009000 0x00309000 0x001000>, /* ap 99 */ + <0x0000a000 0x0030a000 0x001000>, /* ap 100 */ + <0x0000b000 0x0030b000 0x001000>, /* ap 101 */ + <0x0003d000 0x0033d000 0x001000>, /* ap 102 */ + <0x0003e000 0x0033e000 0x001000>, /* ap 103 */ + <0x0003f000 0x0033f000 0x001000>, /* ap 104 */ + <0x00040000 0x00340000 0x001000>, /* ap 105 */ + <0x00041000 0x00341000 0x001000>, /* ap 106 */ + <0x00042000 0x00342000 0x001000>, /* ap 107 */ + <0x00045000 0x00345000 0x001000>, /* ap 108 */ + <0x00046000 0x00346000 0x001000>, /* ap 109 */ + <0x00047000 0x00347000 0x001000>, /* ap 110 */ + <0x00048000 0x00348000 0x001000>, /* ap 111 */ + <0x000f2000 0x003f2000 0x002000>, /* ap 112 */ + <0x000f4000 0x003f4000 0x001000>, /* ap 113 */ + <0x0004c000 0x0034c000 0x002000>, /* ap 114 */ + <0x0004e000 0x0034e000 0x001000>, /* ap 115 */ + <0x00022000 0x00322000 0x001000>, /* ap 116 */ + <0x00023000 0x00323000 0x001000>, /* ap 117 */ + <0x000f0000 0x003f0000 0x001000>, /* ap 118 */ + <0x0002a400 0x0032a400 0x000400>, /* ap 119 */ + <0x0002a800 0x0032a800 0x000400>, /* ap 120 */ + <0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */ + <0x0002b000 0x0032b000 0x001000>, /* ap 122 */ + <0x00080000 0x00380000 0x020000>, /* ap 123 */ + <0x000a0000 0x003a0000 0x001000>, /* ap 124 */ + <0x000a8000 0x003a8000 0x008000>, /* ap 125 */ + <0x000b0000 0x003b0000 0x001000>, /* ap 126 */ + <0x000c0000 0x003c0000 0x020000>, /* ap 127 */ + <0x000e0000 0x003e0000 0x001000>, /* ap 128 */ + <0x000e8000 0x003e8000 0x008000>; /* ap 129 */ + + target-module@0 { /* 0x48300000, ap 56 40.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss0"; + reg = <0x0 0x4>, + <0x4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@2000 { /* 0x48302000, ap 58 4a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss1"; + reg = <0x2000 0x4>, + <0x2004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@4000 { /* 0x48304000, ap 60 44.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss2"; + reg = <0x4000 0x4>, + <0x4004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@6000 { /* 0x48306000, ap 96 58.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss3"; + reg = <0x6000 0x4>, + <0x6004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x1000>; + }; + + target-module@8000 { /* 0x48308000, ap 98 54.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss4"; + reg = <0x8000 0x4>, + <0x8004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@a000 { /* 0x4830a000, ap 100 60.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss5"; + reg = <0xa000 0x4>, + <0xa004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@10000 { /* 0x48310000, ap 64 4e.1 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "rng"; + reg = <0x11fe0 0x4>, + <0x11fe4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x2000>; + }; + + target-module@13000 { /* 0x48313000, ap 90 50.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x13000 0x1000>; + }; + + target-module@18000 { /* 0x48318000, ap 62 4c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000 0x4000>; + }; + + target-module@20000 { /* 0x48320000, ap 82 34.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio5"; + reg = <0x20000 0x4>, + <0x20010 0x4>, + <0x20114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>, + <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@22000 { /* 0x48322000, ap 116 64.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio6"; + reg = <0x22000 0x4>, + <0x22010 0x4>, + <0x22114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>, + <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + }; + + target-module@26000 { /* 0x48326000, ap 86 66.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "vpfe0"; + reg = <0x26000 0x4>, + <0x26104 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + }; + + target-module@28000 { /* 0x48328000, ap 75 0e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "vpfe1"; + reg = <0x28000 0x4>, + <0x28104 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>; + }; + + target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "dss_core"; + reg = <0x2a000 0x4>, + <0x2a010 0x4>, + <0x2a014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, dss_clkdm */ + clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x0002a000 0x00000400>, + <0x00000400 0x0002a400 0x00000400>, + <0x00000800 0x0002a800 0x00000400>, + <0x00000c00 0x0002ac00 0x00000400>, + <0x00001000 0x0002b000 0x00001000>; + }; + + target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer9"; + reg = <0x3d000 0x4>, + <0x3d010 0x4>, + <0x3d014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3d000 0x1000>; + }; + + target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer10"; + reg = <0x3f000 0x4>, + <0x3f010 0x4>, + <0x3f014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3f000 0x1000>; + }; + + target-module@41000 { /* 0x48341000, ap 106 76.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer11"; + reg = <0x41000 0x4>, + <0x41010 0x4>, + <0x41014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x41000 0x1000>; + }; + + target-module@45000 { /* 0x48345000, ap 108 6a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi4"; + reg = <0x45000 0x4>, + <0x45110 0x4>, + <0x45114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x45000 0x1000>; + }; + + target-module@47000 { /* 0x48347000, ap 110 70.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "hdq1w"; + reg = <0x47000 0x4>, + <0x47014 0x4>, + <0x47018 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x47000 0x1000>; + }; + + target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000 0x2000>; + }; + + target-module@80000 { /* 0x48380000, ap 123 42.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "usb_otg_ss0"; + reg = <0x80000 0x4>, + <0x80010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x20000>; + }; + + target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x8000>; + }; + + target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "usb_otg_ss1"; + reg = <0xc0000 0x4>, + <0xc0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc0000 0x20000>; + }; + + target-module@e8000 { /* 0x483e8000, ap 129 78.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe8000 0x8000>; + }; + + target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf2000 0x2000>; + }; + }; +}; + -- cgit From d95adfd4585305ba52f56b8351cdd21842f9354a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 24 Sep 2018 16:22:37 -0700 Subject: ARM: dts: am437x: Move l4 child devices to probe them with ti-sysc With l4 interconnect hierarchy and ti-sysc interconnect target module data in place, we can simply move all the related child devices to their proper location and enable probing using ti-sysc. In general the first child device address range starts at range 0 from the ti-sysc interconnect target so the move involves adjusting the child device reg properties for that. In case of any regressions, problem devices can be reverted to probe with legacy platform data as needed by moving them back and removing the related interconnect target module node. Note that we are not yet moving dss or wkup_m3, those will be moved later after some related driver changes. Cc: Dave Gerlach Cc: Keerthy Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 876 +-------------------------------------- arch/arm/boot/dts/am437x-l4.dtsi | 865 +++++++++++++++++++++++++++++++++++++- 2 files changed, 858 insertions(+), 883 deletions(-) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index af624f8a387f..55aff4db9c7c 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -8,6 +8,7 @@ * kind, whether express or implied. */ +#include #include #include #include @@ -159,12 +160,7 @@ interrupts = , ; - l4_wkup: l4_wkup@44c00000 { - compatible = "ti,am4-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x44c00000 0x287000>; - + l4_wkup: interconnect@44c00000 { wkup_m3: wkup_m3@100000 { compatible = "ti,am4372-wkup-m3"; reg = <0x100000 0x4000>, @@ -173,75 +169,10 @@ ti,hwmods = "wkup_m3"; ti,pm-firmware = "am335x-pm-firmware.elf"; }; - - prcm: prcm@1f0000 { - compatible = "ti,am4-prcm", "simple-bus"; - reg = <0x1f0000 0x11000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1f0000 0x11000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scm: scm@210000 { - compatible = "ti,am4-scm", "simple-bus"; - reg = <0x210000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x210000 0x4000>; - - am43xx_pinmux: pinmux@800 { - compatible = "ti,am437-padconf", - "pinctrl-single"; - reg = <0x800 0x31c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - wkup_m3_ipc: wkup_m3_ipc@1324 { - compatible = "ti,am4372-wkup-m3-ipc"; - reg = <0x1324 0x44>; - interrupts = ; - ti,rproc = <&wkup_m3>; - mboxes = <&mailbox &mbox_wkupm3>; - }; - - edma_xbar: dma-router@f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0xf90 0x40>; - #dma-cells = <3>; - dma-requests = <64>; - dma-masters = <&edma>; - }; - - scm_clockdomains: clockdomains { - }; - }; + }; + l4_per: interconnect@48000000 { + }; + l4_fast: interconnect@4a000000 { }; emif: emif@4c000000 { @@ -297,333 +228,6 @@ interrupt-names = "edma3_tcerrint"; }; - uart0: serial@44e09000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x44e09000 0x2000>; - interrupts = ; - ti,hwmods = "uart1"; - }; - - uart1: serial@48022000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x48022000 0x2000>; - interrupts = ; - ti,hwmods = "uart2"; - status = "disabled"; - }; - - uart2: serial@48024000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x48024000 0x2000>; - interrupts = ; - ti,hwmods = "uart3"; - status = "disabled"; - }; - - uart3: serial@481a6000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x481a6000 0x2000>; - interrupts = ; - ti,hwmods = "uart4"; - status = "disabled"; - }; - - uart4: serial@481a8000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x481a8000 0x2000>; - interrupts = ; - ti,hwmods = "uart5"; - status = "disabled"; - }; - - uart5: serial@481aa000 { - compatible = "ti,am4372-uart","ti,omap2-uart"; - reg = <0x481aa000 0x2000>; - interrupts = ; - ti,hwmods = "uart6"; - status = "disabled"; - }; - - mailbox: mailbox@480c8000 { - compatible = "ti,omap4-mailbox"; - reg = <0x480C8000 0x200>; - interrupts = ; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { - ti,mbox-send-noirq; - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <0 0 3>; - }; - }; - - timer1: timer@44e31000 { - compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; - reg = <0x44e31000 0x400>; - interrupts = ; - ti,timer-alwon; - ti,hwmods = "timer1"; - clocks = <&timer1_fck>; - clock-names = "fck"; - }; - - timer2: timer@48040000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48040000 0x400>; - interrupts = ; - ti,hwmods = "timer2"; - clocks = <&timer2_fck>; - clock-names = "fck"; - }; - - timer3: timer@48042000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48042000 0x400>; - interrupts = ; - ti,hwmods = "timer3"; - status = "disabled"; - }; - - timer4: timer@48044000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48044000 0x400>; - interrupts = ; - ti,timer-pwm; - ti,hwmods = "timer4"; - status = "disabled"; - }; - - timer5: timer@48046000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48046000 0x400>; - interrupts = ; - ti,timer-pwm; - ti,hwmods = "timer5"; - status = "disabled"; - }; - - timer6: timer@48048000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48048000 0x400>; - interrupts = ; - ti,timer-pwm; - ti,hwmods = "timer6"; - status = "disabled"; - }; - - timer7: timer@4804a000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x4804a000 0x400>; - interrupts = ; - ti,timer-pwm; - ti,hwmods = "timer7"; - status = "disabled"; - }; - - timer8: timer@481c1000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x481c1000 0x400>; - interrupts = ; - ti,hwmods = "timer8"; - status = "disabled"; - }; - - timer9: timer@4833d000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x4833d000 0x400>; - interrupts = ; - ti,hwmods = "timer9"; - status = "disabled"; - }; - - timer10: timer@4833f000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x4833f000 0x400>; - interrupts = ; - ti,hwmods = "timer10"; - status = "disabled"; - }; - - timer11: timer@48341000 { - compatible = "ti,am4372-timer","ti,am335x-timer"; - reg = <0x48341000 0x400>; - interrupts = ; - ti,hwmods = "timer11"; - status = "disabled"; - }; - - counter32k: counter@44e86000 { - compatible = "ti,am4372-counter32k","ti,omap-counter32k"; - reg = <0x44e86000 0x40>; - ti,hwmods = "counter_32k"; - }; - - rtc: rtc@44e3e000 { - compatible = "ti,am4372-rtc", "ti,am3352-rtc", - "ti,da830-rtc"; - reg = <0x44e3e000 0x1000>; - interrupts = ; - ti,hwmods = "rtc"; - clocks = <&clk_32768_ck>; - clock-names = "int-clk"; - system-power-controller; - status = "disabled"; - }; - - wdt: wdt@44e35000 { - compatible = "ti,am4372-wdt","ti,omap3-wdt"; - reg = <0x44e35000 0x1000>; - interrupts = ; - ti,hwmods = "wd_timer2"; - }; - - gpio0: gpio@44e07000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x44e07000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio1"; - status = "disabled"; - }; - - gpio1: gpio@4804c000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x4804c000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio2"; - status = "disabled"; - }; - - gpio2: gpio@481ac000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x481ac000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio3"; - status = "disabled"; - }; - - gpio3: gpio@481ae000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x481ae000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio4"; - status = "disabled"; - }; - - gpio4: gpio@48320000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x48320000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio5"; - status = "disabled"; - }; - - gpio5: gpio@48322000 { - compatible = "ti,am4372-gpio","ti,omap4-gpio"; - reg = <0x48322000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - ti,hwmods = "gpio6"; - status = "disabled"; - }; - - hwspinlock: spinlock@480ca000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x480ca000 0x1000>; - ti,hwmods = "spinlock"; - #hwlock-cells = <1>; - }; - - i2c0: i2c@44e0b000 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x44e0b000 0x1000>; - interrupts = ; - ti,hwmods = "i2c1"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@4802a000 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x4802a000 0x1000>; - interrupts = ; - ti,hwmods = "i2c2"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@4819c000 { - compatible = "ti,am4372-i2c","ti,omap4-i2c"; - reg = <0x4819c000 0x1000>; - interrupts = ; - ti,hwmods = "i2c3"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@48030000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x48030000 0x400>; - interrupts = ; - ti,hwmods = "spi0"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc1: mmc@48060000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x48060000 0x1000>; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&edma 24 0>, - <&edma 25 0>; - dma-names = "tx", "rx"; - interrupts = ; - status = "disabled"; - }; - - mmc2: mmc@481d8000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x481d8000 0x1000>; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&edma 2 0>, - <&edma 3 0>; - dma-names = "tx", "rx"; - interrupts = ; - status = "disabled"; - }; - mmc3: mmc@47810000 { compatible = "ti,omap4-hsmmc"; reg = <0x47810000 0x1000>; @@ -633,282 +237,6 @@ status = "disabled"; }; - spi1: spi@481a0000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x481a0000 0x400>; - interrupts = ; - ti,hwmods = "spi1"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@481a2000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x481a2000 0x400>; - interrupts = ; - ti,hwmods = "spi2"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@481a4000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x481a4000 0x400>; - interrupts = ; - ti,hwmods = "spi3"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@48345000 { - compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; - reg = <0x48345000 0x400>; - interrupts = ; - ti,hwmods = "spi4"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mac: ethernet@4a100000 { - compatible = "ti,am4372-cpsw","ti,cpsw"; - reg = <0x4a100000 0x800 - 0x4a101200 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "cpgmac0"; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, - <&dpll_clksel_mac_clk>; - clock-names = "fck", "cpts", "50mclk"; - assigned-clocks = <&dpll_clksel_mac_clk>; - assigned-clock-rates = <50000000>; - status = "disabled"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - ranges; - syscon = <&scm_conf>; - - davinci_mdio: mdio@4a101000 { - compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x4a101000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - status = "disabled"; - }; - - cpsw_emac0: slave@4a100200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - cpsw_emac1: slave@4a100300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@44e10650 { - compatible = "ti,am43xx-cpsw-phy-sel"; - reg= <0x44e10650 0x4>; - reg-names = "gmii-sel"; - }; - }; - - epwmss0: epwmss@48300000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48300000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss0"; - status = "disabled"; - - ecap0: ecap@48300100 { - compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48300100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm0: pwm@48300200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48300200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss1: epwmss@48302000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48302000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss1"; - status = "disabled"; - - ecap1: ecap@48302100 { - compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48302100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm1: pwm@48302200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48302200 0x80>; - clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss2: epwmss@48304000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48304000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss2"; - status = "disabled"; - - ecap2: ecap@48304100 { - compatible = "ti,am4372-ecap", - "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48304100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - - ehrpwm2: pwm@48304200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48304200 0x80>; - clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss3: epwmss@48306000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48306000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss3"; - status = "disabled"; - - ehrpwm3: pwm@48306200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48306200 0x80>; - clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss4: epwmss@48308000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x48308000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss4"; - status = "disabled"; - - ehrpwm4: pwm@48308200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48308200 0x80>; - clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss5: epwmss@4830a000 { - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; - reg = <0x4830a000 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "epwmss5"; - status = "disabled"; - - ehrpwm5: pwm@4830a200 { - compatible = "ti,am4372-ehrpwm", - "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x4830a200 0x80>; - clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - tscadc: tscadc@44e0d000 { - compatible = "ti,am3359-tscadc"; - reg = <0x44e0d000 0x1000>; - ti,hwmods = "adc_tsc"; - interrupts = ; - clocks = <&adc_tsc_fck>; - clock-names = "fck"; - status = "disabled"; - dmas = <&edma 53 0>, <&edma 57 0>; - dma-names = "fifo0", "fifo1"; - - tsc { - compatible = "ti,am3359-tsc"; - }; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - - }; - sham: sham@53100000 { compatible = "ti,omap5-sham"; ti,hwmods = "sham"; @@ -938,53 +266,6 @@ dma-names = "tx", "rx"; }; - rng: rng@48310000 { - compatible = "ti,omap4-rng"; - ti,hwmods = "rng"; - reg = <0x48310000 0x2000>; - interrupts = ; - }; - - mcasp0: mcasp@48038000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp0"; - reg = <0x48038000 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 8 2>, - <&edma 9 2>; - dma-names = "tx", "rx"; - }; - - mcasp1: mcasp@4803c000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp1"; - reg = <0x4803C000 0x2000>, - <0x46400000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 10 2>, - <&edma 11 2>; - dma-names = "tx", "rx"; - }; - - elm: elm@48080000 { - compatible = "ti,am3352-elm"; - reg = <0x48080000 0x2000>; - interrupts = ; - ti,hwmods = "elm"; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - status = "disabled"; - }; - gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; @@ -1005,102 +286,6 @@ status = "disabled"; }; - ocp2scp0: ocp2scp@483a8000 { - compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "ocp2scp0"; - - usb2_phy1: phy@483a8000 { - compatible = "ti,am437x-usb2"; - reg = <0x483a8000 0x8000>; - syscon-phy-power = <&scm_conf 0x620>; - clocks = <&usb_phy0_always_on_clk32k>, - <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - ocp2scp1: ocp2scp@483e8000 { - compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,hwmods = "ocp2scp1"; - - usb2_phy2: phy@483e8000 { - compatible = "ti,am437x-usb2"; - reg = <0x483e8000 0x8000>; - syscon-phy-power = <&scm_conf 0x628>; - clocks = <&usb_phy1_always_on_clk32k>, - <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - dwc3_1: omap_dwc3@48380000 { - compatible = "ti,am437x-dwc3"; - ti,hwmods = "usb_otg_ss0"; - reg = <0x48380000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <1>; - ranges; - - usb1: usb@48390000 { - compatible = "synopsys,dwc3"; - reg = <0x48390000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy1>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - status = "disabled"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - - dwc3_2: omap_dwc3@483c0000 { - compatible = "ti,am437x-dwc3"; - ti,hwmods = "usb_otg_ss1"; - reg = <0x483c0000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <1>; - ranges; - - usb2: usb@483d0000 { - compatible = "synopsys,dwc3"; - reg = <0x483d0000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy2>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - status = "disabled"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - qspi: spi@47900000 { compatible = "ti,am4372-qspi"; reg = <0x47900000 0x100>, @@ -1114,16 +299,6 @@ status = "disabled"; }; - hdq: hdq@48347000 { - compatible = "ti,am4372-hdq"; - reg = <0x48347000 0x1000>; - interrupts = ; - clocks = <&func_12m_clk>; - clock-names = "fck"; - ti,hwmods = "hdq1w"; - status = "disabled"; - }; - dss: dss@4832a000 { compatible = "ti,omap3-dss"; reg = <0x4832a000 0x200>; @@ -1173,45 +348,8 @@ pool; }; }; - - dcan0: can@481cc000 { - compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - ti,hwmods = "d_can0"; - clocks = <&dcan0_fck>; - clock-names = "fck"; - reg = <0x481cc000 0x2000>; - syscon-raminit = <&scm_conf 0x644 0>; - interrupts = ; - status = "disabled"; - }; - - dcan1: can@481d0000 { - compatible = "ti,am4372-d_can", "ti,am3352-d_can"; - ti,hwmods = "d_can1"; - clocks = <&dcan1_fck>; - clock-names = "fck"; - reg = <0x481d0000 0x2000>; - syscon-raminit = <&scm_conf 0x644 1>; - interrupts = ; - status = "disabled"; - }; - - vpfe0: vpfe@48326000 { - compatible = "ti,am437x-vpfe"; - reg = <0x48326000 0x2000>; - interrupts = ; - ti,hwmods = "vpfe0"; - status = "disabled"; - }; - - vpfe1: vpfe@48328000 { - compatible = "ti,am437x-vpfe"; - reg = <0x48328000 0x2000>; - interrupts = ; - ti,hwmods = "vpfe1"; - status = "disabled"; - }; }; }; +#include "am437x-l4.dtsi" #include "am43xx-clocks.dtsi" diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index 4829129aabd5..ff2c11ed0877 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -48,11 +48,29 @@ }; target-module@f0000 { /* 0x44df0000, ap 8 58.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xf0000 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf0000 0x10000>; + + prcm: prcm@0 { + compatible = "ti,am4-prcm", "simple-bus"; + reg = <0x0 0x11000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; }; }; @@ -134,6 +152,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7000 0x1000>; + + gpio0: gpio@0 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; }; target-module@9000 { /* 0x44e09000, ap 16 04.0 */ @@ -156,6 +185,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9000 0x1000>; + + uart0: serial@0 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x0 0x2000>; + interrupts = ; + }; }; target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ @@ -180,6 +215,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb000 0x1000>; + + i2c0: i2c@0 { + compatible = "ti,am4372-i2c","ti,omap4-i2c"; + reg = <0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ @@ -198,14 +242,94 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd000 0x1000>; + + tscadc: tscadc@0 { + compatible = "ti,am3359-tscadc"; + reg = <0x0 0x1000>; + interrupts = ; + clocks = <&adc_tsc_fck>; + clock-names = "fck"; + status = "disabled"; + dmas = <&edma 53 0>, <&edma 57 0>; + dma-names = "fifo0", "fifo1"; + + tsc { + compatible = "ti,am3359-tsc"; + }; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + + }; }; target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x10000 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x10000 0x10000>; + + scm: scm@0 { + compatible = "ti,am4-scm", "simple-bus"; + reg = <0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x4000>; + + phy_sel: cpsw-phy-sel@650 { + compatible = "ti,am43xx-cpsw-phy-sel"; + reg= <0x650 0x4>; + reg-names = "gmii-sel"; + }; + + am43xx_pinmux: pinmux@800 { + compatible = "ti,am437-padconf", + "pinctrl-single"; + reg = <0x800 0x31c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + wkup_m3_ipc: wkup_m3_ipc@1324 { + compatible = "ti,am4372-wkup-m3-ipc"; + reg = <0x1324 0x44>; + interrupts = ; + ti,rproc = <&wkup_m3>; + mboxes = <&mailbox &mbox_wkupm3>; + }; + + edma_xbar: dma-router@f90 { + compatible = "ti,am335x-edma-crossbar"; + reg = <0xf90 0x40>; + #dma-cells = <3>; + dma-requests = <64>; + dma-masters = <&edma>; + }; + + scm_clockdomains: clockdomains { + }; + }; }; target-module@31000 { /* 0x44e31000, ap 24 40.0 */ @@ -228,6 +352,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x31000 0x1000>; + + timer1: timer@0 { + compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; + reg = <0x0 0x400>; + interrupts = ; + ti,timer-alwon; + clocks = <&timer1_fck>; + clock-names = "fck"; + }; }; target-module@33000 { /* 0x44e33000, ap 26 18.0 */ @@ -258,6 +391,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x35000 0x1000>; + + wdt: wdt@0 { + compatible = "ti,am4372-wdt","ti,omap3-wdt"; + reg = <0x0 0x1000>; + interrupts = ; + }; }; target-module@37000 { /* 0x44e37000, ap 30 08.0 */ @@ -292,6 +431,18 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; + + rtc: rtc@0 { + compatible = "ti,am4372-rtc", "ti,am3352-rtc", + "ti,da830-rtc"; + reg = <0x0 0x1000>; + interrupts = ; + clocks = <&clk_32768_ck>; + clock-names = "int-clk"; + system-power-controller; + status = "disabled"; + }; }; target-module@40000 { /* 0x44e40000, ap 36 68.0 */ @@ -316,6 +467,11 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x86000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,am4372-counter32k","ti,omap-counter32k"; + reg = <0x0 0x40>; + }; }; target-module@88000 { /* 0x44e88000, ap 38 12.0 */ @@ -355,11 +511,74 @@ <0x00280000 0x00280000 0x001000>; /* ap 8 */ target-module@100000 { /* 0x4a100000, ap 3 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "cpgmac0"; + reg = <0x101200 0x4>, + <0x101208 0x4>, + <0x101204 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <0>; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + ti,syss-mask = <1>; + clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x100000 0x8000>; + + mac: ethernet@0 { + compatible = "ti,am4372-cpsw","ti,cpsw"; + reg = <0x0 0x800 + 0x1200 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, + <&dpll_clksel_mac_clk>; + clock-names = "fck", "cpts", "50mclk"; + assigned-clocks = <&dpll_clksel_mac_clk>; + assigned-clock-rates = <50000000>; + status = "disabled"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + ranges = <0 0 0x8000>; + syscon = <&scm_conf>; + cpsw-phy-sel = <&phy_sel>; + + davinci_mdio: mdio@1000 { + compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x1000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpsw_125mhz_gclk>; + clock-names = "fck"; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpsw_emac0: slave@200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + cpsw_emac1: slave@300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + }; }; target-module@200000 { /* 0x4a200000, ap 7 02.0 */ @@ -475,6 +694,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; + + uart1: serial@0 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; }; target-module@24000 { /* 0x48024000, ap 10 1c.0 */ @@ -497,6 +723,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>; + + uart2: serial@0 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; }; target-module@2a000 { /* 0x4802a000, ap 12 22.0 */ @@ -521,6 +754,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2a000 0x1000>; + + i2c1: i2c@0 { + compatible = "ti,am4372-i2c","ti,omap4-i2c"; + reg = <0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@30000 { /* 0x48030000, ap 65 08.0 */ @@ -543,6 +785,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x30000 0x1000>; + + spi0: spi@0 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@34000 { /* 0x48034000, ap 80 56.0 */ @@ -576,6 +827,20 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x38000 0x2000>; + + mcasp0: mcasp@0 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x2000>, + <0x46000000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 8 2>, + <&edma 9 2>; + dma-names = "tx", "rx"; + }; }; target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */ @@ -593,6 +858,20 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3c000 0x2000>; + + mcasp1: mcasp@0 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x2000>, + <0x46400000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 10 2>, + <&edma 11 2>; + dma-names = "tx", "rx"; + }; }; target-module@40000 { /* 0x48040000, ap 18 1e.0 */ @@ -613,6 +892,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x1000>; + + timer2: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + clocks = <&timer2_fck>; + clock-names = "fck"; + }; }; target-module@42000 { /* 0x48042000, ap 20 24.0 */ @@ -633,6 +920,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x42000 0x1000>; + + timer3: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + }; }; target-module@44000 { /* 0x48044000, ap 22 26.0 */ @@ -653,6 +947,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x44000 0x1000>; + + timer4: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + ti,timer-pwm; + status = "disabled"; + }; }; target-module@46000 { /* 0x48046000, ap 24 28.0 */ @@ -673,6 +975,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x46000 0x1000>; + + timer5: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + ti,timer-pwm; + status = "disabled"; + }; }; target-module@48000 { /* 0x48048000, ap 26 1a.0 */ @@ -693,6 +1003,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x48000 0x1000>; + + timer6: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + ti,timer-pwm; + status = "disabled"; + }; }; target-module@4a000 { /* 0x4804a000, ap 71 48.0 */ @@ -713,6 +1031,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4a000 0x1000>; + + timer7: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + ti,timer-pwm; + status = "disabled"; + }; }; target-module@4c000 { /* 0x4804c000, ap 28 36.0 */ @@ -737,6 +1063,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4c000 0x1000>; + + gpio1: gpio@0 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; }; target-module@60000 { /* 0x48060000, ap 30 14.0 */ @@ -760,6 +1097,18 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; + + mmc1: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x1000>; + ti,dual-volt; + ti,needs-special-reset; + dmas = <&edma 24 0>, + <&edma 25 0>; + dma-names = "tx", "rx"; + interrupts = ; + status = "disabled"; + }; }; target-module@80000 { /* 0x48080000, ap 32 18.0 */ @@ -782,6 +1131,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x10000>; + + elm: elm@0 { + compatible = "ti,am3352-elm"; + reg = <0x0 0x2000>; + interrupts = ; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; }; target-module@c8000 { /* 0x480c8000, ap 73 06.0 */ @@ -800,6 +1158,20 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc8000 0x1000>; + + mailbox: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <8>; + mbox_wkupm3: wkup_m3 { + ti,mbox-send-noirq; + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <0 0 3>; + }; + }; }; target-module@ca000 { /* 0x480ca000, ap 77 38.0 */ @@ -823,6 +1195,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xca000 0x1000>; + + hwspinlock: spinlock@0 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x0 0x1000>; + #hwlock-cells = <1>; + }; }; }; @@ -899,6 +1277,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9c000 0x1000>; + + i2c2: i2c@0 { + compatible = "ti,am4372-i2c","ti,omap4-i2c"; + reg = <0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */ @@ -921,6 +1308,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa0000 0x1000>; + + spi1: spi@0 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */ @@ -943,6 +1339,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa2000 0x1000>; + + spi2: spi@0 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@a4000 { /* 0x481a4000, ap 92 62.0 */ @@ -965,6 +1370,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa4000 0x1000>; + + spi3: spi@0 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@a6000 { /* 0x481a6000, ap 40 16.0 */ @@ -987,6 +1401,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa6000 0x1000>; + + uart3: serial@0 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; }; target-module@a8000 { /* 0x481a8000, ap 42 20.0 */ @@ -1009,6 +1430,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa8000 0x1000>; + + uart4: serial@0 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; }; target-module@aa000 { /* 0x481aa000, ap 44 12.0 */ @@ -1031,6 +1459,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xaa000 0x1000>; + + uart5: serial@0 { + compatible = "ti,am4372-uart","ti,omap2-uart"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; }; target-module@ac000 { /* 0x481ac000, ap 46 30.0 */ @@ -1055,6 +1490,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xac000 0x1000>; + + gpio2: gpio@0 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; }; target-module@ae000 { /* 0x481ae000, ap 48 32.0 */ @@ -1079,6 +1525,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xae000 0x1000>; + + gpio3: gpio@0 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; }; target-module@c1000 { /* 0x481c1000, ap 94 68.0 */ @@ -1099,22 +1556,55 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc1000 0x1000>; + + timer8: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + }; }; target-module@cc000 { /* 0x481cc000, ap 50 46.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "d_can0"; + reg = <0xcc000 0x4>; + reg-names = "rev"; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xcc000 0x2000>; + + dcan0: can@0 { + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; + reg = <0x0 0x2000>; + syscon-raminit = <&scm_conf 0x644 0>; + interrupts = ; + status = "disabled"; + }; }; target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "d_can1"; + reg = <0xd0000 0x4>; + reg-names = "rev"; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000 0x2000>; + + dcan1: can@0 { + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; + reg = <0x0 0x2000>; + syscon-raminit = <&scm_conf 0x644 1>; + interrupts = ; + status = "disabled"; + }; }; target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */ @@ -1138,6 +1628,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd8000 0x1000>; + + mmc2: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x1000>; + ti,needs-special-reset; + dmas = <&edma 2 0>, + <&edma 3 0>; + dma-names = "tx", "rx"; + interrupts = ; + status = "disabled"; + }; }; }; @@ -1226,6 +1727,37 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; + + epwmss0: epwmss@0 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + status = "disabled"; + + ecap0: ecap@100 { + compatible = "ti,am4372-ecap", + "ti,am3352-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; + + ehrpwm0: pwm@200 { + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; }; target-module@2000 { /* 0x48302000, ap 58 4a.0 */ @@ -1248,6 +1780,37 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; + + epwmss1: epwmss@0 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + status = "disabled"; + + ecap1: ecap@100 { + compatible = "ti,am4372-ecap", + "ti,am3352-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; + + ehrpwm1: pwm@200 { + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; }; target-module@4000 { /* 0x48304000, ap 60 44.0 */ @@ -1270,6 +1833,37 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; + + epwmss2: epwmss@0 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + status = "disabled"; + + ecap2: ecap@100 { + compatible = "ti,am4372-ecap", + "ti,am3352-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + status = "disabled"; + }; + + ehrpwm2: pwm@200 { + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; }; target-module@6000 { /* 0x48306000, ap 96 58.0 */ @@ -1292,6 +1886,26 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6000 0x1000>; + + epwmss3: epwmss@0 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + status = "disabled"; + + ehrpwm3: pwm@200 { + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; }; target-module@8000 { /* 0x48308000, ap 98 54.0 */ @@ -1314,6 +1928,26 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; + + epwmss4: epwmss@0 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + status = "disabled"; + + ehrpwm4: pwm@48308200 { + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; }; target-module@a000 { /* 0x4830a000, ap 100 60.0 */ @@ -1336,6 +1970,26 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa000 0x1000>; + + epwmss5: epwmss@0 { + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + status = "disabled"; + + ehrpwm5: pwm@200 { + compatible = "ti,am4372-ehrpwm", + "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; }; target-module@10000 { /* 0x48310000, ap 64 4e.1 */ @@ -1353,6 +2007,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x10000 0x2000>; + + rng: rng@0 { + compatible = "ti,omap4-rng"; + reg = <0x0 0x2000>; + interrupts = ; + }; }; target-module@13000 { /* 0x48313000, ap 90 50.0 */ @@ -1393,6 +2053,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; + + gpio4: gpio@0 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; }; target-module@22000 { /* 0x48322000, ap 116 64.0 */ @@ -1417,6 +2088,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; + + gpio5: gpio@0 { + compatible = "ti,am4372-gpio","ti,omap4-gpio"; + reg = <0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; }; target-module@26000 { /* 0x48326000, ap 86 66.0 */ @@ -1437,6 +2119,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x26000 0x1000>; + + vpfe0: vpfe@0 { + compatible = "ti,am437x-vpfe"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; }; target-module@28000 { /* 0x48328000, ap 75 0e.0 */ @@ -1457,6 +2146,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x28000 0x1000>; + + vpfe1: vpfe@0 { + compatible = "ti,am437x-vpfe"; + reg = <0x0 0x2000>; + interrupts = ; + status = "disabled"; + }; }; target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */ @@ -1499,6 +2195,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3d000 0x1000>; + + timer9: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + }; }; target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */ @@ -1519,6 +2222,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3f000 0x1000>; + + timer10: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + }; }; target-module@41000 { /* 0x48341000, ap 106 76.0 */ @@ -1539,6 +2249,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x41000 0x1000>; + + timer11: timer@0 { + compatible = "ti,am4372-timer","ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + }; }; target-module@45000 { /* 0x48345000, ap 108 6a.0 */ @@ -1561,6 +2278,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x45000 0x1000>; + + spi4: spi@0 { + compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@47000 { /* 0x48347000, ap 110 70.0 */ @@ -1578,6 +2304,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x47000 0x1000>; + + hdq: hdq@0 { + compatible = "ti,am4372-hdq"; + reg = <0x0 0x1000>; + interrupts = ; + clocks = <&func_12m_clk>; + clock-names = "fck"; + status = "disabled"; + }; }; target-module@4c000 { /* 0x4834c000, ap 114 72.0 */ @@ -1609,14 +2344,65 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x20000>; + + dwc3_1: omap_dwc3@0 { + compatible = "ti,am437x-dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <1>; + ranges = <0 0 0x20000>; + + usb1: usb@10000 { + compatible = "synopsys,dwc3"; + reg = <0x10000 0x10000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + phys = <&usb2_phy1>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + status = "disabled"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + }; + }; }; target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "ocp2scp0"; + reg = <0xa8000 0x4>; + reg-names = "rev"; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa8000 0x8000>; + + ocp2scp0: ocp2scp@0 { + compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x8000>; + + usb2_phy1: phy@8000 { + compatible = "ti,am437x-usb2"; + reg = <0x0 0x8000>; + syscon-phy-power = <&scm_conf 0x620>; + clocks = <&usb_phy0_always_on_clk32k>, + <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 8>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */ @@ -1640,14 +2426,65 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc0000 0x20000>; + + dwc3_2: omap_dwc3@0 { + compatible = "ti,am437x-dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <1>; + ranges = <0 0 0x20000>; + + usb2: usb@10000 { + compatible = "synopsys,dwc3"; + reg = <0x10000 0x10000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + phys = <&usb2_phy2>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + status = "disabled"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + }; + }; }; target-module@e8000 { /* 0x483e8000, ap 129 78.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "ocp2scp1"; + reg = <0xe8000 0x4>; + reg-names = "rev"; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe8000 0x8000>; + + ocp2scp1: ocp2scp@0 { + compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x8000>; + + usb2_phy2: phy@8000 { + compatible = "ti,am437x-usb2"; + reg = <0x0 0x8000>; + syscon-phy-power = <&scm_conf 0x628>; + clocks = <&usb_phy1_always_on_clk32k>, + <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 8>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */ -- cgit From f711c575cfeca820b97bbec8d05c958e82f5fec4 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 24 Sep 2018 16:20:37 -0700 Subject: ARM: dts: am335x: Add l4 interconnect hierarchy and ti-sysc data Similar to commit 8f42cb7f64c7 ("ARM: dts: omap4: Add l4 interconnect hierarchy and ti-sysc data"), let's add proper interconnect hierarchy for l4 interconnect instances with the related ti-sysc interconnect module data as in Documentation/devicetree/bindings/bus/ti-sysc.txt. Using ti-sysc driver binding allows us to start dropping legacy platform data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of ti-sysc dts data. This data is generated based on platform data from a booted system and the interconnect acces protection registers for ranges. To avoid regressions, we initially validate the device tree provided data against the existing platform data on boot. Note that we cannot yet include this file from the SoC dtsi file until the child devices are moved to their proper locations in the interconnect hierarchy in the following patch. Otherwise we would have the each module probed twice. Cc: Dave Gerlach Cc: Keerthy Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 1543 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 1543 insertions(+) create mode 100644 arch/arm/boot/dts/am33xx-l4.dtsi diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi new file mode 100644 index 000000000000..f6751cea2688 --- /dev/null +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -0,0 +1,1543 @@ +&l4_wkup { /* 0x44c00000 */ + compatible = "ti,am33xx-l4-wkup", "simple-bus"; + reg = <0x44c00000 0x800>, + <0x44c00800 0x800>, + <0x44c01000 0x400>, + <0x44c01400 0x400>; + reg-names = "ap", "la", "ia0", "ia1"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ + <0x00100000 0x44d00000 0x100000>, /* segment 1 */ + <0x00200000 0x44e00000 0x100000>; /* segment 2 */ + + segment@0 { /* 0x44c00000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00001400 0x00001400 0x000400>; /* ap 3 */ + }; + + segment@100000 { /* 0x44d00000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ + <0x00004000 0x00104000 0x001000>, /* ap 5 */ + <0x00080000 0x00180000 0x002000>, /* ap 6 */ + <0x00082000 0x00182000 0x001000>; /* ap 7 */ + + target-module@0 { /* 0x44d00000, ap 4 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x4000>; + }; + + target-module@80000 { /* 0x44d80000, ap 6 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x2000>; + }; + }; + + segment@200000 { /* 0x44e00000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ + <0x00002000 0x00202000 0x001000>, /* ap 9 */ + <0x00003000 0x00203000 0x001000>, /* ap 10 */ + <0x00004000 0x00204000 0x001000>, /* ap 11 */ + <0x00005000 0x00205000 0x001000>, /* ap 12 */ + <0x00006000 0x00206000 0x001000>, /* ap 13 */ + <0x00007000 0x00207000 0x001000>, /* ap 14 */ + <0x00008000 0x00208000 0x001000>, /* ap 15 */ + <0x00009000 0x00209000 0x001000>, /* ap 16 */ + <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ + <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ + <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ + <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ + <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ + <0x00010000 0x00210000 0x010000>, /* ap 22 */ + <0x00020000 0x00220000 0x010000>, /* ap 23 */ + <0x00030000 0x00230000 0x001000>, /* ap 24 */ + <0x00031000 0x00231000 0x001000>, /* ap 25 */ + <0x00032000 0x00232000 0x001000>, /* ap 26 */ + <0x00033000 0x00233000 0x001000>, /* ap 27 */ + <0x00034000 0x00234000 0x001000>, /* ap 28 */ + <0x00035000 0x00235000 0x001000>, /* ap 29 */ + <0x00036000 0x00236000 0x001000>, /* ap 30 */ + <0x00037000 0x00237000 0x001000>, /* ap 31 */ + <0x00038000 0x00238000 0x001000>, /* ap 32 */ + <0x00039000 0x00239000 0x001000>, /* ap 33 */ + <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ + <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ + <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ + <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ + <0x00040000 0x00240000 0x040000>, /* ap 38 */ + <0x00080000 0x00280000 0x001000>; /* ap 39 */ + + target-module@0 { /* 0x44e00000, ap 8 58.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x2000>; + }; + + target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3000 0x1000>; + }; + + target-module@5000 { /* 0x44e05000, ap 12 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5000 0x1000>; + }; + + target-module@7000 { /* 0x44e07000, ap 14 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio1"; + reg = <0x7000 0x4>, + <0x7010 0x4>, + <0x7114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, + <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; + }; + + target-module@9000 { /* 0x44e09000, ap 16 04.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart1"; + reg = <0x9050 0x4>, + <0x9054 0x4>, + <0x9058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9000 0x1000>; + }; + + target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c1"; + reg = <0xb000 0x8>, + <0xb010 0x8>, + <0xb090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb000 0x1000>; + }; + + target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "adc_tsc"; + reg = <0xd000 0x4>, + <0xd010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x0000d000 0x00001000>, + <0x00001000 0x0000e000 0x00001000>; + }; + + target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00010000 0x00010000>, + <0x00010000 0x00020000 0x00010000>; + }; + + target-module@31000 { /* 0x44e31000, ap 25 40.0 */ + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + ti,hwmods = "timer1"; + reg = <0x31000 0x4>, + <0x31010 0x4>, + <0x31014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x31000 0x1000>; + }; + + target-module@33000 { /* 0x44e33000, ap 27 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x33000 0x1000>; + }; + + target-module@35000 { /* 0x44e35000, ap 29 50.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "wd_timer2"; + reg = <0x35000 0x4>, + <0x35010 0x4>, + <0x35014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x35000 0x1000>; + }; + + target-module@37000 { /* 0x44e37000, ap 31 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x37000 0x1000>; + }; + + target-module@39000 { /* 0x44e39000, ap 33 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x39000 0x1000>; + }; + + target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "rtc"; + reg = <0x3e074 0x4>, + <0x3e078 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ + clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + }; + + target-module@40000 { /* 0x44e40000, ap 38 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x40000>; + }; + }; +}; + +&l4_fw { /* 0x47c00000 */ + compatible = "ti,am33xx-l4-fw", "simple-bus"; + reg = <0x47c00000 0x800>, + <0x47c00800 0x800>, + <0x47c01000 0x400>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ + + segment@0 { /* 0x47c00000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ + <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ + <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ + <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ + <0x00010000 0x00010000 0x001000>, /* ap 7 */ + <0x00011000 0x00011000 0x001000>, /* ap 8 */ + <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ + <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ + <0x00024000 0x00024000 0x001000>, /* ap 11 */ + <0x00025000 0x00025000 0x001000>, /* ap 12 */ + <0x00026000 0x00026000 0x001000>, /* ap 13 */ + <0x00027000 0x00027000 0x001000>, /* ap 14 */ + <0x00030000 0x00030000 0x001000>, /* ap 15 */ + <0x00031000 0x00031000 0x001000>, /* ap 16 */ + <0x00038000 0x00038000 0x001000>, /* ap 17 */ + <0x00039000 0x00039000 0x001000>, /* ap 18 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ + <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ + <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ + <0x00040000 0x00040000 0x001000>, /* ap 24 */ + <0x00046000 0x00046000 0x001000>, /* ap 25 */ + <0x00047000 0x00047000 0x001000>, /* ap 26 */ + <0x00044000 0x00044000 0x001000>, /* ap 27 */ + <0x00045000 0x00045000 0x001000>, /* ap 28 */ + <0x00028000 0x00028000 0x001000>, /* ap 29 */ + <0x00029000 0x00029000 0x001000>, /* ap 30 */ + <0x00032000 0x00032000 0x001000>, /* ap 31 */ + <0x00033000 0x00033000 0x001000>, /* ap 32 */ + <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ + <0x00041000 0x00041000 0x001000>, /* ap 34 */ + <0x00042000 0x00042000 0x001000>, /* ap 35 */ + <0x00043000 0x00043000 0x001000>, /* ap 36 */ + <0x00014000 0x00014000 0x001000>, /* ap 37 */ + <0x00015000 0x00015000 0x001000>; /* ap 38 */ + + target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + + target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe000 0x1000>; + }; + + target-module@10000 { /* 0x47c10000, ap 7 20.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x1000>; + }; + + target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x14000 0x1000>; + }; + + target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + + target-module@24000 { /* 0x47c24000, ap 11 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + }; + + target-module@26000 { /* 0x47c26000, ap 13 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + }; + + target-module@28000 { /* 0x47c28000, ap 29 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>; + }; + + target-module@30000 { /* 0x47c30000, ap 15 14.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000 0x1000>; + }; + + target-module@32000 { /* 0x47c32000, ap 31 06.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>; + }; + + target-module@38000 { /* 0x47c38000, ap 17 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x38000 0x1000>; + }; + + target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3a000 0x1000>; + }; + + target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x1000>; + }; + + target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + }; + + target-module@40000 { /* 0x47c40000, ap 24 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + }; + + target-module@42000 { /* 0x47c42000, ap 35 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42000 0x1000>; + }; + + target-module@44000 { /* 0x47c44000, ap 27 24.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x44000 0x1000>; + }; + + target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x46000 0x1000>; + }; + }; +}; + +&l4_fast { /* 0x4a000000 */ + compatible = "ti,am33xx-l4-fast", "simple-bus"; + reg = <0x4a000000 0x800>, + <0x4a000800 0x800>, + <0x4a001000 0x400>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ + + segment@0 { /* 0x4a000000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00100000 0x00100000 0x008000>, /* ap 3 */ + <0x00108000 0x00108000 0x001000>, /* ap 4 */ + <0x00180000 0x00180000 0x020000>, /* ap 5 */ + <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ + <0x00200000 0x00200000 0x080000>, /* ap 7 */ + <0x00280000 0x00280000 0x001000>, /* ap 8 */ + <0x00300000 0x00300000 0x080000>, /* ap 9 */ + <0x00380000 0x00380000 0x001000>; /* ap 10 */ + + target-module@100000 { /* 0x4a100000, ap 3 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x100000 0x8000>; + }; + + target-module@180000 { /* 0x4a180000, ap 5 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x180000 0x20000>; + }; + + target-module@200000 { /* 0x4a200000, ap 7 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x200000 0x80000>; + }; + + target-module@300000 { /* 0x4a300000, ap 9 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x300000 0x80000>; + }; + }; +}; + +&l4_mpuss { /* 0x4b140000 */ + compatible = "ti,am33xx-l4-mpuss", "simple-bus"; + reg = <0x4b144400 0x100>, + <0x4b144800 0x400>; + reg-names = "la", "ap"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ + + segment@0 { /* 0x4b140000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00002000 0x00002000 0x001000>, /* ap 2 */ + <0x00004000 0x00004000 0x000400>, /* ap 3 */ + <0x00005000 0x00005000 0x000400>, /* ap 4 */ + <0x00000000 0x00000000 0x001000>, /* ap 5 */ + <0x00003000 0x00003000 0x001000>, /* ap 6 */ + <0x00000800 0x00000800 0x000800>; /* ap 7 */ + + target-module@0 { /* 0x4b140000, ap 5 02.2 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x00001000>, + <0x00001000 0x00001000 0x00001000>, + <0x00002000 0x00002000 0x00001000>; + }; + + target-module@3000 { /* 0x4b143000, ap 6 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3000 0x1000>; + }; + }; +}; + +&l4_per { /* 0x48000000 */ + compatible = "ti,am33xx-l4-per", "simple-bus"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ + <0x00100000 0x48100000 0x100000>, /* segment 1 */ + <0x00200000 0x48200000 0x100000>, /* segment 2 */ + <0x00300000 0x48300000 0x100000>; /* segment 3 */ + + segment@0 { /* 0x48000000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00001400 0x00001400 0x000400>, /* ap 3 */ + <0x00001800 0x00001800 0x000400>, /* ap 4 */ + <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ + <0x00008000 0x00008000 0x001000>, /* ap 6 */ + <0x00009000 0x00009000 0x001000>, /* ap 7 */ + <0x00016000 0x00016000 0x001000>, /* ap 8 */ + <0x00017000 0x00017000 0x001000>, /* ap 9 */ + <0x00022000 0x00022000 0x001000>, /* ap 10 */ + <0x00023000 0x00023000 0x001000>, /* ap 11 */ + <0x00024000 0x00024000 0x001000>, /* ap 12 */ + <0x00025000 0x00025000 0x001000>, /* ap 13 */ + <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ + <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ + <0x00038000 0x00038000 0x002000>, /* ap 16 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ + <0x00014000 0x00014000 0x001000>, /* ap 18 */ + <0x00015000 0x00015000 0x001000>, /* ap 19 */ + <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ + <0x00040000 0x00040000 0x001000>, /* ap 22 */ + <0x00041000 0x00041000 0x001000>, /* ap 23 */ + <0x00042000 0x00042000 0x001000>, /* ap 24 */ + <0x00043000 0x00043000 0x001000>, /* ap 25 */ + <0x00044000 0x00044000 0x001000>, /* ap 26 */ + <0x00045000 0x00045000 0x001000>, /* ap 27 */ + <0x00046000 0x00046000 0x001000>, /* ap 28 */ + <0x00047000 0x00047000 0x001000>, /* ap 29 */ + <0x00048000 0x00048000 0x001000>, /* ap 30 */ + <0x00049000 0x00049000 0x001000>, /* ap 31 */ + <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ + <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ + <0x00050000 0x00050000 0x002000>, /* ap 34 */ + <0x00052000 0x00052000 0x001000>, /* ap 35 */ + <0x00060000 0x00060000 0x001000>, /* ap 36 */ + <0x00061000 0x00061000 0x001000>, /* ap 37 */ + <0x00080000 0x00080000 0x010000>, /* ap 38 */ + <0x00090000 0x00090000 0x001000>, /* ap 39 */ + <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ + <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ + <0x00030000 0x00030000 0x001000>, /* ap 77 */ + <0x00031000 0x00031000 0x001000>, /* ap 78 */ + <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ + <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ + <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ + <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ + <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ + <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ + <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ + <0x000cb000 0x000cb000 0x001000>; /* ap 92 */ + + target-module@8000 { /* 0x48008000, ap 6 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@14000 { /* 0x48014000, ap 18 58.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x14000 0x1000>; + }; + + target-module@16000 { /* 0x48016000, ap 8 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x16000 0x1000>; + }; + + target-module@22000 { /* 0x48022000, ap 10 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart2"; + reg = <0x22050 0x4>, + <0x22054 0x4>, + <0x22058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + }; + + target-module@24000 { /* 0x48024000, ap 12 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart3"; + reg = <0x24050 0x4>, + <0x24054 0x4>, + <0x24058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + }; + + target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c2"; + reg = <0x2a000 0x8>, + <0x2a010 0x8>, + <0x2a090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + }; + + target-module@30000 { /* 0x48030000, ap 77 08.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi0"; + reg = <0x30000 0x4>, + <0x30110 0x4>, + <0x30114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000 0x1000>; + }; + + target-module@38000 { /* 0x48038000, ap 16 02.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp0"; + reg = <0x38000 0x4>, + <0x38004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x38000 0x2000>; + }; + + target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp1"; + reg = <0x3c000 0x4>, + <0x3c004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l3s_clkdm */ + clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x2000>; + }; + + target-module@40000 { /* 0x48040000, ap 22 1e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer2"; + reg = <0x40000 0x4>, + <0x40010 0x4>, + <0x40014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + }; + + target-module@42000 { /* 0x48042000, ap 24 1c.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer3"; + reg = <0x42000 0x4>, + <0x42010 0x4>, + <0x42014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42000 0x1000>; + }; + + target-module@44000 { /* 0x48044000, ap 26 26.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer4"; + reg = <0x44000 0x4>, + <0x44010 0x4>, + <0x44014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x44000 0x1000>; + }; + + target-module@46000 { /* 0x48046000, ap 28 28.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer5"; + reg = <0x46000 0x4>, + <0x46010 0x4>, + <0x46014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x46000 0x1000>; + }; + + target-module@48000 { /* 0x48048000, ap 30 22.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer6"; + reg = <0x48000 0x4>, + <0x48010 0x4>, + <0x48014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48000 0x1000>; + }; + + target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer7"; + reg = <0x4a000 0x4>, + <0x4a010 0x4>, + <0x4a014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4a000 0x1000>; + }; + + target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio2"; + reg = <0x4c000 0x4>, + <0x4c010 0x4>, + <0x4c114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, + <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000 0x1000>; + }; + + target-module@50000 { /* 0x48050000, ap 34 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000 0x2000>; + }; + + target-module@60000 { /* 0x48060000, ap 36 0c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmc1"; + reg = <0x602fc 0x4>, + <0x60110 0x4>, + <0x60114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + }; + + target-module@80000 { /* 0x48080000, ap 38 18.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "elm"; + reg = <0x80000 0x4>, + <0x80010 0x4>, + <0x80014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x10000>; + }; + + target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa0000 0x10000>; + }; + + target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox"; + reg = <0xc8000 0x4>, + <0xc8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8000 0x1000>; + }; + + target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spinlock"; + reg = <0xca000 0x4>, + <0xca010 0x4>, + <0xca014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xca000 0x1000>; + }; + + target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xcc000 0x1000>; + }; + }; + + segment@100000 { /* 0x48100000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ + <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ + <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ + <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ + <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ + <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ + <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ + <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ + <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ + <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ + <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ + <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ + <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ + <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ + <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ + <0x000af000 0x001af000 0x001000>, /* ap 57 */ + <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ + <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ + <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ + <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ + <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ + <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ + <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ + <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ + <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ + <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ + <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ + <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ + <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ + <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ + + target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8c000 0x1000>; + }; + + target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8e000 0x1000>; + }; + + target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c3"; + reg = <0x9c000 0x8>, + <0x9c010 0x8>, + <0x9c090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9c000 0x1000>; + }; + + target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spi1"; + reg = <0xa0000 0x4>, + <0xa0110 0x4>, + <0xa0114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa0000 0x1000>; + }; + + target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa2000 0x1000>; + }; + + target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa4000 0x1000>; + }; + + target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart4"; + reg = <0xa6050 0x4>, + <0xa6054 0x4>, + <0xa6058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa6000 0x1000>; + }; + + target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart5"; + reg = <0xa8050 0x4>, + <0xa8054 0x4>, + <0xa8058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x1000>; + }; + + target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart6"; + reg = <0xaa050 0x4>, + <0xaa054 0x4>, + <0xaa058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xaa000 0x1000>; + }; + + target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio3"; + reg = <0xac000 0x4>, + <0xac010 0x4>, + <0xac114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, + <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xac000 0x1000>; + }; + + target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio4"; + reg = <0xae000 0x4>, + <0xae010 0x4>, + <0xae114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, + <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xae000 0x1000>; + }; + + target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb0000 0x10000>; + }; + + target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xcc000 0x2000>; + }; + + target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000 0x2000>; + }; + + target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmc2"; + reg = <0xd82fc 0x4>, + <0xd8110 0x4>, + <0xd8114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd8000 0x1000>; + }; + }; + + segment@200000 { /* 0x48200000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; + + segment@300000 { /* 0x48300000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ + <0x00001000 0x00301000 0x001000>, /* ap 67 */ + <0x00002000 0x00302000 0x001000>, /* ap 68 */ + <0x00003000 0x00303000 0x001000>, /* ap 69 */ + <0x00004000 0x00304000 0x001000>, /* ap 70 */ + <0x00005000 0x00305000 0x001000>, /* ap 71 */ + <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ + <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ + <0x00018000 0x00318000 0x004000>, /* ap 74 */ + <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ + <0x00010000 0x00310000 0x002000>, /* ap 76 */ + <0x00012000 0x00312000 0x001000>, /* ap 93 */ + <0x00015000 0x00315000 0x001000>, /* ap 94 */ + <0x00016000 0x00316000 0x001000>, /* ap 95 */ + <0x00017000 0x00317000 0x001000>, /* ap 96 */ + <0x00013000 0x00313000 0x001000>, /* ap 97 */ + <0x00014000 0x00314000 0x001000>, /* ap 98 */ + <0x00020000 0x00320000 0x001000>, /* ap 99 */ + <0x00021000 0x00321000 0x001000>, /* ap 100 */ + <0x00022000 0x00322000 0x001000>, /* ap 101 */ + <0x00023000 0x00323000 0x001000>, /* ap 102 */ + <0x00024000 0x00324000 0x001000>, /* ap 103 */ + <0x00025000 0x00325000 0x001000>; /* ap 104 */ + + target-module@0 { /* 0x48300000, ap 66 48.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss0"; + reg = <0x0 0x4>, + <0x4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@2000 { /* 0x48302000, ap 68 52.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss1"; + reg = <0x2000 0x4>, + <0x2004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@4000 { /* 0x48304000, ap 70 44.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss2"; + reg = <0x4000 0x4>, + <0x4004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "lcdc"; + reg = <0xe000 0x4>, + <0xe054 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): per_pwrdm, lcdc_clkdm */ + clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe000 0x1000>; + }; + + target-module@10000 { /* 0x48310000, ap 76 4e.1 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "rng"; + reg = <0x11fe0 0x4>, + <0x11fe4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + ; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x2000>; + }; + + target-module@13000 { /* 0x48313000, ap 97 62.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x13000 0x1000>; + }; + + target-module@15000 { /* 0x48315000, ap 94 56.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00015000 0x00001000>, + <0x00001000 0x00016000 0x00001000>; + }; + + target-module@18000 { /* 0x48318000, ap 74 4c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000 0x4000>; + }; + + target-module@20000 { /* 0x48320000, ap 99 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@22000 { /* 0x48322000, ap 101 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + }; + + target-module@24000 { /* 0x48324000, ap 103 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + }; + }; +}; + -- cgit From 87fc89ced3a78f7f0845afab1934d509ef4ad0f2 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 24 Sep 2018 16:20:54 -0700 Subject: ARM: dts: am335x: Move l4 child devices to probe them with ti-sysc With l4 interconnect hierarchy and ti-sysc interconnect target module data in place, we can simply move all the related child devices to their proper location and enable probing using ti-sysc. In general the first child device address range starts at range 0 from the ti-sysc interconnect target so the move involves adjusting the child device reg properties for that. In case of any regressions, problem devices can be reverted to probe with legacy platform data as needed by moving them back and removing the related interconnect target module node. Note that we are not yet moving dss or wkup_m3, those will be moved later after some related driver changes. Cc: Dave Gerlach Cc: Keerthy Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-shc.dts | 2 +- arch/arm/boot/dts/am33xx-l4.dtsi | 613 +++++++++++++++++++++++++++++++++++++- arch/arm/boot/dts/am33xx.dtsi | 623 +-------------------------------------- 3 files changed, 614 insertions(+), 624 deletions(-) diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index 1d925ed2b102..c9e07584549d 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -205,7 +205,7 @@ pinctrl-1 = <&cpsw_sleep>; status = "okay"; slaves = <1>; - cpsw_emac0: slave@4a100200 { + cpsw_emac0: slave@200 { phy-mode = "mii"; phy-handle = <ðernetphy0>; }; diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index f6751cea2688..918bf57a520d 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -31,11 +31,13 @@ <0x00082000 0x00182000 0x001000>; /* ap 7 */ target-module@0 { /* 0x44d00000, ap 4 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x0 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x4000>; + status = "disabled"; }; target-module@80000 { /* 0x44d80000, ap 6 10.0 */ @@ -85,11 +87,28 @@ <0x00080000 0x00280000 0x001000>; /* ap 39 */ target-module@0 { /* 0x44e00000, ap 8 58.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x2000>; + + prcm: prcm@0 { + compatible = "ti,am3-prcm", "simple-bus"; + reg = <0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; }; target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ @@ -130,6 +149,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7000 0x1000>; + + gpio0: gpio@0 { + compatible = "ti,omap4-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x1000>; + interrupts = <96>; + }; }; target-module@9000 { /* 0x44e09000, ap 16 04.0 */ @@ -152,6 +181,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9000 0x1000>; + + uart0: serial@0 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + clock-frequency = <48000000>; + reg = <0x0 0x2000>; + interrupts = <72>; + status = "disabled"; + dmas = <&edma 26 0>, <&edma 27 0>; + dma-names = "tx", "rx"; + }; }; target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ @@ -176,6 +215,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb000 0x1000>; + + i2c0: i2c@0 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1000>; + interrupts = <70>; + status = "disabled"; + }; }; target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ @@ -195,15 +243,90 @@ #size-cells = <1>; ranges = <0x00000000 0x0000d000 0x00001000>, <0x00001000 0x0000e000 0x00001000>; + + tscadc: tscadc@0 { + compatible = "ti,am3359-tscadc"; + reg = <0x0 0x1000>; + interrupts = <16>; + status = "disabled"; + dmas = <&edma 53 0>, <&edma 57 0>; + dma-names = "fifo0", "fifo1"; + + tsc { + compatible = "ti,am3359-tsc"; + }; + am335x_adc: adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; }; target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x10000 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00010000 0x00010000>, <0x00010000 0x00020000 0x00010000>; + + scm: scm@0 { + compatible = "ti,am3-scm", "simple-bus"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + #pinctrl-cells = <1>; + ranges = <0 0 0x2000>; + + phy_sel: cpsw-phy-sel@650 { + compatible = "ti,am3352-cpsw-phy-sel"; + reg= <0x650 0x4>; + reg-names = "gmii-sel"; + }; + + am33xx_pinmux: pinmux@800 { + compatible = "pinctrl-single"; + reg = <0x800 0x238>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7f>; + }; + + scm_conf: scm_conf@0 { + compatible = "syscon", "simple-bus"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x800>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + wkup_m3_ipc: wkup_m3_ipc@1324 { + compatible = "ti,am3352-wkup-m3-ipc"; + reg = <0x1324 0x24>; + interrupts = <78>; + ti,rproc = <&wkup_m3>; + mboxes = <&mailbox &mbox_wkupm3>; + }; + + edma_xbar: dma-router@f90 { + compatible = "ti,am335x-edma-crossbar"; + reg = <0xf90 0x40>; + #dma-cells = <3>; + dma-requests = <32>; + dma-masters = <&edma>; + }; + + scm_clockdomains: clockdomains { + }; + }; }; target-module@31000 { /* 0x44e31000, ap 25 40.0 */ @@ -226,6 +349,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x31000 0x1000>; + + timer1: timer@0 { + compatible = "ti,am335x-timer-1ms"; + reg = <0x0 0x400>; + interrupts = <67>; + ti,timer-alwon; + clocks = <&timer1_fck>; + clock-names = "fck"; + }; }; target-module@33000 { /* 0x44e33000, ap 27 18.0 */ @@ -256,6 +388,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x35000 0x1000>; + + wdt2: wdt@0 { + compatible = "ti,omap3-wdt"; + reg = <0x0 0x1000>; + interrupts = <91>; + }; }; target-module@37000 { /* 0x44e37000, ap 31 08.0 */ @@ -290,6 +428,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; + + rtc: rtc@0 { + compatible = "ti,am3352-rtc", "ti,da830-rtc"; + reg = <0x0 0x1000>; + interrupts = <75 + 76>; + }; }; target-module@40000 { /* 0x44e40000, ap 38 68.0 */ @@ -529,11 +674,72 @@ <0x00380000 0x00380000 0x001000>; /* ap 10 */ target-module@100000 { /* 0x4a100000, ap 3 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "cpgmac0"; + reg = <0x101200 0x4>, + <0x101208 0x4>, + <0x101204 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <0>; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + ti,syss-mask = <1>; + clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x100000 0x8000>; + + mac: ethernet@0 { + compatible = "ti,am335x-cpsw","ti,cpsw"; + clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; + clock-names = "fck", "cpts"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + reg = <0x0 0x800 + 0x1200 0x100>; + #address-cells = <1>; + #size-cells = <1>; + /* + * c0_rx_thresh_pend + * c0_rx_pend + * c0_tx_pend + * c0_misc_pend + */ + interrupts = <40 41 42 43>; + ranges = <0 0 0x8000>; + syscon = <&scm_conf>; + cpsw-phy-sel = <&phy_sel>; + status = "disabled"; + + davinci_mdio: mdio@1000 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + reg = <0x1000 0x100>; + status = "disabled"; + }; + + cpsw_emac0: slave@200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + cpsw_emac1: slave@300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + }; }; target-module@180000 { /* 0x4a180000, ap 5 10.0 */ @@ -721,6 +927,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; + + uart1: serial@0 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + clock-frequency = <48000000>; + reg = <0x0 0x2000>; + interrupts = <73>; + status = "disabled"; + dmas = <&edma 28 0>, <&edma 29 0>; + dma-names = "tx", "rx"; + }; }; target-module@24000 { /* 0x48024000, ap 12 14.0 */ @@ -743,6 +959,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>; + + uart2: serial@0 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + clock-frequency = <48000000>; + reg = <0x0 0x2000>; + interrupts = <74>; + status = "disabled"; + dmas = <&edma 30 0>, <&edma 31 0>; + dma-names = "tx", "rx"; + }; }; target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ @@ -767,6 +993,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2a000 0x1000>; + + i2c1: i2c@0 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1000>; + interrupts = <71>; + status = "disabled"; + }; }; target-module@30000 { /* 0x48030000, ap 77 08.0 */ @@ -789,6 +1024,21 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x30000 0x1000>; + + spi0: spi@0 { + compatible = "ti,omap4-mcspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x400>; + interrupts = <65>; + ti,spi-num-cs = <2>; + dmas = <&edma 16 0 + &edma 17 0 + &edma 18 0 + &edma 19 0>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + status = "disabled"; + }; }; target-module@38000 { /* 0x48038000, ap 16 02.0 */ @@ -806,6 +1056,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x38000 0x2000>; + + mcasp0: mcasp@0 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x2000>, + <0x46000000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <80>, <81>; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 8 2>, + <&edma 9 2>; + dma-names = "tx", "rx"; + }; }; target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ @@ -823,6 +1086,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3c000 0x2000>; + + mcasp1: mcasp@0 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x2000>, + <0x46400000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <82>, <83>; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 10 2>, + <&edma 11 2>; + dma-names = "tx", "rx"; + }; }; target-module@40000 { /* 0x48040000, ap 22 1e.0 */ @@ -843,6 +1119,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x1000>; + + timer2: timer@0 { + compatible = "ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = <68>; + clocks = <&timer2_fck>; + clock-names = "fck"; + }; }; target-module@42000 { /* 0x48042000, ap 24 1c.0 */ @@ -863,6 +1147,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x42000 0x1000>; + + timer3: timer@0 { + compatible = "ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = <69>; + }; }; target-module@44000 { /* 0x48044000, ap 26 26.0 */ @@ -883,6 +1173,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x44000 0x1000>; + + timer4: timer@0 { + compatible = "ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = <92>; + ti,timer-pwm; + }; }; target-module@46000 { /* 0x48046000, ap 28 28.0 */ @@ -903,6 +1200,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x46000 0x1000>; + + timer5: timer@0 { + compatible = "ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = <93>; + ti,timer-pwm; + }; }; target-module@48000 { /* 0x48048000, ap 30 22.0 */ @@ -923,6 +1227,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x48000 0x1000>; + + timer6: timer@0 { + compatible = "ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = <94>; + ti,timer-pwm; + }; }; target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ @@ -943,6 +1254,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4a000 0x1000>; + + timer7: timer@0 { + compatible = "ti,am335x-timer"; + reg = <0x0 0x400>; + interrupts = <95>; + ti,timer-pwm; + }; }; target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ @@ -967,6 +1285,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4c000 0x1000>; + + gpio1: gpio@0 { + compatible = "ti,omap4-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x1000>; + interrupts = <98>; + }; }; target-module@50000 { /* 0x48050000, ap 34 2c.0 */ @@ -998,6 +1326,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; + + mmc1: mmc@0 { + compatible = "ti,omap4-hsmmc"; + ti,dual-volt; + ti,needs-special-reset; + ti,needs-special-hs-handling; + dmas = <&edma_xbar 24 0 0 + &edma_xbar 25 0 0>; + dma-names = "tx", "rx"; + interrupts = <64>; + reg = <0x0 0x1000>; + status = "disabled"; + }; }; target-module@80000 { /* 0x48080000, ap 38 18.0 */ @@ -1020,6 +1361,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x10000>; + + elm: elm@0 { + compatible = "ti,am3352-elm"; + reg = <0x0 0x2000>; + interrupts = <4>; + status = "disabled"; + }; }; target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ @@ -1046,6 +1394,20 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc8000 0x1000>; + + mailbox: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = <77>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <8>; + mbox_wkupm3: wkup_m3 { + ti,mbox-send-noirq; + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <0 0 3>; + }; + }; }; target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ @@ -1069,6 +1431,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xca000 0x1000>; + + hwspinlock: spinlock@0 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x0 0x1000>; + #hwlock-cells = <1>; + }; }; target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ @@ -1153,6 +1521,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9c000 0x1000>; + + i2c2: i2c@0 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1000>; + interrupts = <30>; + status = "disabled"; + }; }; target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ @@ -1175,6 +1552,21 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa0000 0x1000>; + + spi1: spi@0 { + compatible = "ti,omap4-mcspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x400>; + interrupts = <125>; + ti,spi-num-cs = <2>; + dmas = <&edma 42 0 + &edma 43 0 + &edma 44 0 + &edma 45 0>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + status = "disabled"; + }; }; target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ @@ -1213,6 +1605,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa6000 0x1000>; + + uart3: serial@0 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + clock-frequency = <48000000>; + reg = <0x0 0x2000>; + interrupts = <44>; + status = "disabled"; + }; }; target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ @@ -1235,6 +1635,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xa8000 0x1000>; + + uart4: serial@0 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + clock-frequency = <48000000>; + reg = <0x0 0x2000>; + interrupts = <45>; + status = "disabled"; + }; }; target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ @@ -1257,6 +1665,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xaa000 0x1000>; + + uart5: serial@0 { + compatible = "ti,am3352-uart", "ti,omap3-uart"; + clock-frequency = <48000000>; + reg = <0x0 0x2000>; + interrupts = <46>; + status = "disabled"; + }; }; target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ @@ -1281,6 +1697,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xac000 0x1000>; + + gpio2: gpio@0 { + compatible = "ti,omap4-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x1000>; + interrupts = <32>; + }; }; target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ @@ -1305,6 +1731,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xae000 0x1000>; + + gpio3: gpio@0 { + compatible = "ti,omap4-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x1000>; + interrupts = <62>; + }; }; target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ @@ -1316,19 +1752,49 @@ }; target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "d_can0"; + reg = <0xcc000 0x4>; + reg-names = "rev"; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_D_CAN0_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xcc000 0x2000>; + + dcan0: can@0 { + compatible = "ti,am3352-d_can"; + reg = <0x0 0x2000>; + clocks = <&dcan0_fck>; + clock-names = "fck"; + syscon-raminit = <&scm_conf 0x644 0>; + interrupts = <52>; + status = "disabled"; + }; }; target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "d_can1"; + reg = <0xd0000 0x4>; + reg-names = "rev"; + /* Domains (P, C): per_pwrdm, l4ls_clkdm */ + clocks = <&l4ls_clkctrl AM3_D_CAN1_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000 0x2000>; + + dcan1: can@0 { + compatible = "ti,am3352-d_can"; + reg = <0x0 0x2000>; + clocks = <&dcan1_fck>; + clock-names = "fck"; + syscon-raminit = <&scm_conf 0x644 1>; + interrupts = <55>; + status = "disabled"; + }; }; target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ @@ -1352,6 +1818,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd8000 0x1000>; + + mmc2: mmc@0 { + compatible = "ti,omap4-hsmmc"; + ti,needs-special-reset; + dmas = <&edma 2 0 + &edma 3 0>; + dma-names = "tx", "rx"; + interrupts = <28>; + reg = <0x0 0x1000>; + status = "disabled"; + }; }; }; @@ -1409,6 +1886,39 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; + + epwmss0: epwmss@0 { + compatible = "ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48300100 0x48300100 0x80 /* ECAP */ + 0x48300180 0x48300180 0x80 /* EQEP */ + 0x48300200 0x48300200 0x80>; /* EHRPWM */ + + ecap0: ecap@48300100 { + compatible = "ti,am3352-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48300100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + interrupts = <31>; + interrupt-names = "ecap0"; + status = "disabled"; + }; + + ehrpwm0: pwm@48300200 { + compatible = "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48300200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; }; target-module@2000 { /* 0x48302000, ap 68 52.0 */ @@ -1431,6 +1941,39 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; + + epwmss1: epwmss@0 { + compatible = "ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48302100 0x48302100 0x80 /* ECAP */ + 0x48302180 0x48302180 0x80 /* EQEP */ + 0x48302200 0x48302200 0x80>; /* EHRPWM */ + + ecap1: ecap@48302100 { + compatible = "ti,am3352-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48302100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + interrupts = <47>; + interrupt-names = "ecap1"; + status = "disabled"; + }; + + ehrpwm1: pwm@48302200 { + compatible = "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48302200 0x80>; + clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; }; target-module@4000 { /* 0x48304000, ap 70 44.0 */ @@ -1453,6 +1996,39 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; + + epwmss2: epwmss@0 { + compatible = "ti,am33xx-pwmss"; + reg = <0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0x48304100 0x48304100 0x80 /* ECAP */ + 0x48304180 0x48304180 0x80 /* EQEP */ + 0x48304200 0x48304200 0x80>; /* EHRPWM */ + + ecap2: ecap@48304100 { + compatible = "ti,am3352-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48304100 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "fck"; + interrupts = <61>; + interrupt-names = "ecap2"; + status = "disabled"; + }; + + ehrpwm2: pwm@48304200 { + compatible = "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48304200 0x80>; + clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; }; target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ @@ -1471,6 +2047,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe000 0x1000>; + + lcdc: lcdc@0 { + compatible = "ti,am33xx-tilcdc"; + reg = <0x0 0x1000>; + interrupts = <36>; + status = "disabled"; + }; }; target-module@10000 { /* 0x48310000, ap 76 4e.1 */ @@ -1488,6 +2071,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x10000 0x2000>; + + rng: rng@0 { + compatible = "ti,omap4-rng"; + reg = <0x0 0x2000>; + interrupts = <111>; + }; }; target-module@13000 { /* 0x48313000, ap 97 62.0 */ diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 44240c797e2c..e5c2f71a7c77 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -8,6 +8,7 @@ * kind, whether express or implied. */ +#include #include #include #include @@ -166,87 +167,23 @@ ranges; ti,hwmods = "l3_main"; - l4_wkup: l4_wkup@44c00000 { - compatible = "ti,am3-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x44c00000 0x280000>; - + l4_wkup: interconnect@44c00000 { wkup_m3: wkup_m3@100000 { compatible = "ti,am3352-wkup-m3"; reg = <0x100000 0x4000>, - <0x180000 0x2000>; + <0x180000 0x2000>; reg-names = "umem", "dmem"; ti,hwmods = "wkup_m3"; ti,pm-firmware = "am335x-pm-firmware.elf"; }; - - prcm: prcm@200000 { - compatible = "ti,am3-prcm", "simple-bus"; - reg = <0x200000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x200000 0x4000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scm: scm@210000 { - compatible = "ti,am3-scm", "simple-bus"; - reg = <0x210000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - ranges = <0 0x210000 0x2000>; - - am33xx_pinmux: pinmux@800 { - compatible = "pinctrl-single"; - reg = <0x800 0x238>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x7f>; - }; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x800>; - - scm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - wkup_m3_ipc: wkup_m3_ipc@1324 { - compatible = "ti,am3352-wkup-m3-ipc"; - reg = <0x1324 0x24>; - interrupts = <78>; - ti,rproc = <&wkup_m3>; - mboxes = <&mailbox &mbox_wkupm3>; - }; - - edma_xbar: dma-router@f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0xf90 0x40>; - #dma-cells = <3>; - dma-requests = <32>; - dma-masters = <&edma>; - }; - - scm_clockdomains: clockdomains { - }; - }; + }; + l4_per: interconnect@48000000 { + }; + l4_fw: interconnect@47c00000 { + }; + l4_fast: interconnect@4a000000 { + }; + l4_mpuss: interconnect@4b140000 { }; intc: interrupt-controller@48200000 { @@ -297,166 +234,6 @@ interrupt-names = "edma3_tcerrint"; }; - gpio0: gpio@44e07000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio1"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x44e07000 0x1000>; - interrupts = <96>; - }; - - gpio1: gpio@4804c000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x4804c000 0x1000>; - interrupts = <98>; - }; - - gpio2: gpio@481ac000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x481ac000 0x1000>; - interrupts = <32>; - }; - - gpio3: gpio@481ae000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x481ae000 0x1000>; - interrupts = <62>; - }; - - uart0: serial@44e09000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - reg = <0x44e09000 0x2000>; - interrupts = <72>; - status = "disabled"; - dmas = <&edma 26 0>, <&edma 27 0>; - dma-names = "tx", "rx"; - }; - - uart1: serial@48022000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - reg = <0x48022000 0x2000>; - interrupts = <73>; - status = "disabled"; - dmas = <&edma 28 0>, <&edma 29 0>; - dma-names = "tx", "rx"; - }; - - uart2: serial@48024000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - reg = <0x48024000 0x2000>; - interrupts = <74>; - status = "disabled"; - dmas = <&edma 30 0>, <&edma 31 0>; - dma-names = "tx", "rx"; - }; - - uart3: serial@481a6000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - reg = <0x481a6000 0x2000>; - interrupts = <44>; - status = "disabled"; - }; - - uart4: serial@481a8000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart5"; - clock-frequency = <48000000>; - reg = <0x481a8000 0x2000>; - interrupts = <45>; - status = "disabled"; - }; - - uart5: serial@481aa000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart6"; - clock-frequency = <48000000>; - reg = <0x481aa000 0x2000>; - interrupts = <46>; - status = "disabled"; - }; - - i2c0: i2c@44e0b000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - reg = <0x44e0b000 0x1000>; - interrupts = <70>; - status = "disabled"; - }; - - i2c1: i2c@4802a000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - reg = <0x4802a000 0x1000>; - interrupts = <71>; - status = "disabled"; - }; - - i2c2: i2c@4819c000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - reg = <0x4819c000 0x1000>; - interrupts = <30>; - status = "disabled"; - }; - - mmc1: mmc@48060000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - ti,needs-special-hs-handling; - dmas = <&edma_xbar 24 0 0 - &edma_xbar 25 0 0>; - dma-names = "tx", "rx"; - interrupts = <64>; - reg = <0x48060000 0x1000>; - status = "disabled"; - }; - - mmc2: mmc@481d8000 { - compatible = "ti,omap4-hsmmc"; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&edma 2 0 - &edma 3 0>; - dma-names = "tx", "rx"; - interrupts = <28>; - reg = <0x481d8000 0x1000>; - status = "disabled"; - }; - mmc3: mmc@47810000 { compatible = "ti,omap4-hsmmc"; ti,hwmods = "mmc3"; @@ -466,157 +243,6 @@ status = "disabled"; }; - hwspinlock: spinlock@480ca000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x480ca000 0x1000>; - ti,hwmods = "spinlock"; - #hwlock-cells = <1>; - }; - - wdt2: wdt@44e35000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer2"; - reg = <0x44e35000 0x1000>; - interrupts = <91>; - }; - - dcan0: can@481cc000 { - compatible = "ti,am3352-d_can"; - ti,hwmods = "d_can0"; - reg = <0x481cc000 0x2000>; - clocks = <&dcan0_fck>; - clock-names = "fck"; - syscon-raminit = <&scm_conf 0x644 0>; - interrupts = <52>; - status = "disabled"; - }; - - dcan1: can@481d0000 { - compatible = "ti,am3352-d_can"; - ti,hwmods = "d_can1"; - reg = <0x481d0000 0x2000>; - clocks = <&dcan1_fck>; - clock-names = "fck"; - syscon-raminit = <&scm_conf 0x644 1>; - interrupts = <55>; - status = "disabled"; - }; - - mailbox: mailbox@480c8000 { - compatible = "ti,omap4-mailbox"; - reg = <0x480C8000 0x200>; - interrupts = <77>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <8>; - mbox_wkupm3: wkup_m3 { - ti,mbox-send-noirq; - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <0 0 3>; - }; - }; - - timer1: timer@44e31000 { - compatible = "ti,am335x-timer-1ms"; - reg = <0x44e31000 0x400>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; - clocks = <&timer1_fck>; - clock-names = "fck"; - }; - - timer2: timer@48040000 { - compatible = "ti,am335x-timer"; - reg = <0x48040000 0x400>; - interrupts = <68>; - ti,hwmods = "timer2"; - clocks = <&timer2_fck>; - clock-names = "fck"; - }; - - timer3: timer@48042000 { - compatible = "ti,am335x-timer"; - reg = <0x48042000 0x400>; - interrupts = <69>; - ti,hwmods = "timer3"; - }; - - timer4: timer@48044000 { - compatible = "ti,am335x-timer"; - reg = <0x48044000 0x400>; - interrupts = <92>; - ti,hwmods = "timer4"; - ti,timer-pwm; - }; - - timer5: timer@48046000 { - compatible = "ti,am335x-timer"; - reg = <0x48046000 0x400>; - interrupts = <93>; - ti,hwmods = "timer5"; - ti,timer-pwm; - }; - - timer6: timer@48048000 { - compatible = "ti,am335x-timer"; - reg = <0x48048000 0x400>; - interrupts = <94>; - ti,hwmods = "timer6"; - ti,timer-pwm; - }; - - timer7: timer@4804a000 { - compatible = "ti,am335x-timer"; - reg = <0x4804a000 0x400>; - interrupts = <95>; - ti,hwmods = "timer7"; - ti,timer-pwm; - }; - - rtc: rtc@44e3e000 { - compatible = "ti,am3352-rtc", "ti,da830-rtc"; - reg = <0x44e3e000 0x1000>; - interrupts = <75 - 76>; - ti,hwmods = "rtc"; - clocks = <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "int-clk"; - }; - - spi0: spi@48030000 { - compatible = "ti,omap4-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x48030000 0x400>; - interrupts = <65>; - ti,spi-num-cs = <2>; - ti,hwmods = "spi0"; - dmas = <&edma 16 0 - &edma 17 0 - &edma 18 0 - &edma 19 0>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - - spi1: spi@481a0000 { - compatible = "ti,omap4-mcspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x481a0000 0x400>; - interrupts = <125>; - ti,spi-num-cs = <2>; - ti,hwmods = "spi1"; - dmas = <&edma 42 0 - &edma 43 0 - &edma 44 0 - &edma 45 0>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - usb: usb@47400000 { compatible = "ti,am33xx-usb"; reg = <0x47400000 0x1000>; @@ -747,163 +373,6 @@ }; }; - epwmss0: epwmss@48300000 { - compatible = "ti,am33xx-pwmss"; - reg = <0x48300000 0x10>; - ti,hwmods = "epwmss0"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0x48300100 0x48300100 0x80 /* ECAP */ - 0x48300180 0x48300180 0x80 /* EQEP */ - 0x48300200 0x48300200 0x80>; /* EHRPWM */ - - ecap0: ecap@48300100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48300100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - interrupts = <31>; - interrupt-names = "ecap0"; - status = "disabled"; - }; - - ehrpwm0: pwm@48300200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48300200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss1: epwmss@48302000 { - compatible = "ti,am33xx-pwmss"; - reg = <0x48302000 0x10>; - ti,hwmods = "epwmss1"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0x48302100 0x48302100 0x80 /* ECAP */ - 0x48302180 0x48302180 0x80 /* EQEP */ - 0x48302200 0x48302200 0x80>; /* EHRPWM */ - - ecap1: ecap@48302100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48302100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - interrupts = <47>; - interrupt-names = "ecap1"; - status = "disabled"; - }; - - ehrpwm1: pwm@48302200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48302200 0x80>; - clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - epwmss2: epwmss@48304000 { - compatible = "ti,am33xx-pwmss"; - reg = <0x48304000 0x10>; - ti,hwmods = "epwmss2"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges = <0x48304100 0x48304100 0x80 /* ECAP */ - 0x48304180 0x48304180 0x80 /* EQEP */ - 0x48304200 0x48304200 0x80>; /* EHRPWM */ - - ecap2: ecap@48304100 { - compatible = "ti,am3352-ecap", - "ti,am33xx-ecap"; - #pwm-cells = <3>; - reg = <0x48304100 0x80>; - clocks = <&l4ls_gclk>; - clock-names = "fck"; - interrupts = <61>; - interrupt-names = "ecap2"; - status = "disabled"; - }; - - ehrpwm2: pwm@48304200 { - compatible = "ti,am3352-ehrpwm", - "ti,am33xx-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48304200 0x80>; - clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - }; - - mac: ethernet@4a100000 { - compatible = "ti,am335x-cpsw","ti,cpsw"; - ti,hwmods = "cpgmac0"; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - reg = <0x4a100000 0x800 - 0x4a101200 0x100>; - #address-cells = <1>; - #size-cells = <1>; - /* - * c0_rx_thresh_pend - * c0_rx_pend - * c0_tx_pend - * c0_misc_pend - */ - interrupts = <40 41 42 43>; - ranges; - syscon = <&scm_conf>; - status = "disabled"; - - davinci_mdio: mdio@4a101000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - reg = <0x4a101000 0x100>; - status = "disabled"; - }; - - cpsw_emac0: slave@4a100200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - cpsw_emac1: slave@4a100300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@44e10650 { - compatible = "ti,am3352-cpsw-phy-sel"; - reg= <0x44e10650 0x4>; - reg-names = "gmii-sel"; - }; - }; - ocmcram: ocmcram@40300000 { compatible = "mmio-sram"; reg = <0x40300000 0x10000>; /* 64k */ @@ -924,40 +393,6 @@ }; }; - elm: elm@48080000 { - compatible = "ti,am3352-elm"; - reg = <0x48080000 0x2000>; - interrupts = <4>; - ti,hwmods = "elm"; - status = "disabled"; - }; - - lcdc: lcdc@4830e000 { - compatible = "ti,am33xx-tilcdc"; - reg = <0x4830e000 0x1000>; - interrupts = <36>; - ti,hwmods = "lcdc"; - status = "disabled"; - }; - - tscadc: tscadc@44e0d000 { - compatible = "ti,am3359-tscadc"; - reg = <0x44e0d000 0x1000>; - interrupts = <16>; - ti,hwmods = "adc_tsc"; - status = "disabled"; - dmas = <&edma 53 0>, <&edma 57 0>; - dma-names = "fifo0", "fifo1"; - - tsc { - compatible = "ti,am3359-tsc"; - }; - am335x_adc: adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - emif: emif@4c000000 { compatible = "ti,emif-am3352"; reg = <0x4c000000 0x1000000>; @@ -1005,42 +440,8 @@ <&edma 5 0>; dma-names = "tx", "rx"; }; - - mcasp0: mcasp@48038000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp0"; - reg = <0x48038000 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <80>, <81>; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 8 2>, - <&edma 9 2>; - dma-names = "tx", "rx"; - }; - - mcasp1: mcasp@4803c000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp1"; - reg = <0x4803C000 0x2000>, - <0x46400000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <82>, <83>; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 10 2>, - <&edma 11 2>; - dma-names = "tx", "rx"; - }; - - rng: rng@48310000 { - compatible = "ti,omap4-rng"; - ti,hwmods = "rng"; - reg = <0x48310000 0x2000>; - interrupts = <111>; - }; }; }; +#include "am33xx-l4.dtsi" #include "am33xx-clocks.dtsi" -- cgit From 549fce068a3112815e57ba65a067f6b9c3b7ec10 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 27 Sep 2018 13:36:28 -0700 Subject: ARM: dts: dra7: Add l4 interconnect hierarchy and ti-sysc data Similar to commit 8f42cb7f64c7 ("ARM: dts: omap4: Add l4 interconnect hierarchy and ti-sysc data"), let's add proper interconnect hierarchy for l4 interconnect instances with the related ti-sysc interconnect module data as in Documentation/devicetree/bindings/bus/ti-sysc.txt. Using ti-sysc driver binding allows us to start dropping legacy platform data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of ti-sysc dts data. This data is generated based on platform data from a booted system and the interconnect acces protection registers for ranges. To avoid regressions, we initially validate the device tree provided data against the existing platform data on boot. Note that we cannot yet include this file from the SoC dtsi file until the child devices are moved to their proper locations in the interconnect hierarchy in the following patch. Otherwise we would have the each module probed twice. Cc: Dave Gerlach Cc: Keerthy Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 3225 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 3225 insertions(+) create mode 100644 arch/arm/boot/dts/dra7-l4.dtsi diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi new file mode 100644 index 000000000000..73cd83a04450 --- /dev/null +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -0,0 +1,3225 @@ +&l4_cfg { /* 0x4a000000 */ + compatible = "ti,dra7-l4-cfg", "simple-bus"; + reg = <0x4a000000 0x800>, + <0x4a000800 0x800>, + <0x4a001000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ + <0x00100000 0x4a100000 0x100000>, /* segment 1 */ + <0x00200000 0x4a200000 0x100000>; /* segment 2 */ + + segment@0 { /* 0x4a000000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x001000>, /* ap 2 */ + <0x00002000 0x00002000 0x002000>, /* ap 3 */ + <0x00004000 0x00004000 0x001000>, /* ap 4 */ + <0x00005000 0x00005000 0x001000>, /* ap 5 */ + <0x00006000 0x00006000 0x001000>, /* ap 6 */ + <0x00008000 0x00008000 0x002000>, /* ap 7 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 8 */ + <0x00056000 0x00056000 0x001000>, /* ap 9 */ + <0x00057000 0x00057000 0x001000>, /* ap 10 */ + <0x0005e000 0x0005e000 0x002000>, /* ap 11 */ + <0x00060000 0x00060000 0x001000>, /* ap 12 */ + <0x00080000 0x00080000 0x008000>, /* ap 13 */ + <0x00088000 0x00088000 0x001000>, /* ap 14 */ + <0x000a0000 0x000a0000 0x008000>, /* ap 15 */ + <0x000a8000 0x000a8000 0x001000>, /* ap 16 */ + <0x000d9000 0x000d9000 0x001000>, /* ap 17 */ + <0x000da000 0x000da000 0x001000>, /* ap 18 */ + <0x000dd000 0x000dd000 0x001000>, /* ap 19 */ + <0x000de000 0x000de000 0x001000>, /* ap 20 */ + <0x000e0000 0x000e0000 0x001000>, /* ap 21 */ + <0x000e1000 0x000e1000 0x001000>, /* ap 22 */ + <0x000f4000 0x000f4000 0x001000>, /* ap 23 */ + <0x000f5000 0x000f5000 0x001000>, /* ap 24 */ + <0x000f6000 0x000f6000 0x001000>, /* ap 25 */ + <0x000f7000 0x000f7000 0x001000>, /* ap 26 */ + <0x00090000 0x00090000 0x008000>, /* ap 59 */ + <0x00098000 0x00098000 0x001000>; /* ap 60 */ + + target-module@2000 { /* 0x4a002000, ap 3 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x2000>; + }; + + target-module@5000 { /* 0x4a005000, ap 5 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5000 0x1000>; + }; + + target-module@8000 { /* 0x4a008000, ap 7 0e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x2000>; + }; + + target-module@56000 { /* 0x4a056000, ap 9 02.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "dma_system"; + reg = <0x56000 0x4>, + <0x5602c 0x4>, + <0x56028 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): core_pwrdm, dma_clkdm */ + clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x56000 0x1000>; + }; + + target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5e000 0x2000>; + }; + + target-module@80000 { /* 0x4a080000, ap 13 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "ocp2scp1"; + reg = <0x80000 0x4>, + <0x80010 0x4>, + <0x80014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x8000>; + }; + + target-module@90000 { /* 0x4a090000, ap 59 42.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "ocp2scp3"; + reg = <0x90000 0x4>, + <0x90010 0x4>, + <0x90014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x90000 0x8000>; + }; + + target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa0000 0x8000>; + }; + + target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */ + compatible = "ti,sysc-omap3630-sr", "ti,sysc"; + ti,hwmods = "smartreflex_mpu"; + reg = <0xd9038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ + clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd9000 0x1000>; + }; + + target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */ + compatible = "ti,sysc-omap3630-sr", "ti,sysc"; + ti,hwmods = "smartreflex_core"; + reg = <0xdd038 0x4>; + reg-names = "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ + clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xdd000 0x1000>; + }; + + target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0000 0x1000>; + }; + + target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox1"; + reg = <0xf4000 0x4>, + <0xf4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf4000 0x1000>; + }; + + target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spinlock"; + reg = <0xf6000 0x4>, + <0xf6010 0x4>, + <0xf6014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf6000 0x1000>; + }; + }; + + segment@100000 { /* 0x4a100000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */ + <0x00003000 0x00103000 0x001000>, /* ap 28 */ + <0x00008000 0x00108000 0x001000>, /* ap 29 */ + <0x00009000 0x00109000 0x001000>, /* ap 30 */ + <0x00040000 0x00140000 0x010000>, /* ap 31 */ + <0x00050000 0x00150000 0x001000>, /* ap 32 */ + <0x00051000 0x00151000 0x001000>, /* ap 33 */ + <0x00052000 0x00152000 0x001000>, /* ap 34 */ + <0x00053000 0x00153000 0x001000>, /* ap 35 */ + <0x00054000 0x00154000 0x001000>, /* ap 36 */ + <0x00055000 0x00155000 0x001000>, /* ap 37 */ + <0x00056000 0x00156000 0x001000>, /* ap 38 */ + <0x00057000 0x00157000 0x001000>, /* ap 39 */ + <0x00058000 0x00158000 0x001000>, /* ap 40 */ + <0x0005b000 0x0015b000 0x001000>, /* ap 41 */ + <0x0005c000 0x0015c000 0x001000>, /* ap 42 */ + <0x0005d000 0x0015d000 0x001000>, /* ap 45 */ + <0x0005e000 0x0015e000 0x001000>, /* ap 46 */ + <0x0005f000 0x0015f000 0x001000>, /* ap 47 */ + <0x00060000 0x00160000 0x001000>, /* ap 48 */ + <0x00061000 0x00161000 0x001000>, /* ap 49 */ + <0x00062000 0x00162000 0x001000>, /* ap 50 */ + <0x00063000 0x00163000 0x001000>, /* ap 51 */ + <0x00064000 0x00164000 0x001000>, /* ap 52 */ + <0x00065000 0x00165000 0x001000>, /* ap 53 */ + <0x00066000 0x00166000 0x001000>, /* ap 54 */ + <0x00067000 0x00167000 0x001000>, /* ap 55 */ + <0x00068000 0x00168000 0x001000>, /* ap 56 */ + <0x0006d000 0x0016d000 0x001000>, /* ap 57 */ + <0x0006e000 0x0016e000 0x001000>, /* ap 58 */ + <0x00071000 0x00171000 0x001000>, /* ap 61 */ + <0x00072000 0x00172000 0x001000>, /* ap 62 */ + <0x00073000 0x00173000 0x001000>, /* ap 63 */ + <0x00074000 0x00174000 0x001000>, /* ap 64 */ + <0x00075000 0x00175000 0x001000>, /* ap 65 */ + <0x00076000 0x00176000 0x001000>, /* ap 66 */ + <0x00077000 0x00177000 0x001000>, /* ap 67 */ + <0x00078000 0x00178000 0x001000>, /* ap 68 */ + <0x00081000 0x00181000 0x001000>, /* ap 69 */ + <0x00082000 0x00182000 0x001000>, /* ap 70 */ + <0x00083000 0x00183000 0x001000>, /* ap 71 */ + <0x00084000 0x00184000 0x001000>, /* ap 72 */ + <0x00085000 0x00185000 0x001000>, /* ap 73 */ + <0x00086000 0x00186000 0x001000>, /* ap 74 */ + <0x00087000 0x00187000 0x001000>, /* ap 75 */ + <0x00088000 0x00188000 0x001000>, /* ap 76 */ + <0x00069000 0x00169000 0x001000>, /* ap 103 */ + <0x0006a000 0x0016a000 0x001000>, /* ap 104 */ + <0x00079000 0x00179000 0x001000>, /* ap 105 */ + <0x0007a000 0x0017a000 0x001000>, /* ap 106 */ + <0x0006b000 0x0016b000 0x001000>, /* ap 107 */ + <0x0006c000 0x0016c000 0x001000>, /* ap 108 */ + <0x0007b000 0x0017b000 0x001000>, /* ap 121 */ + <0x0007c000 0x0017c000 0x001000>, /* ap 122 */ + <0x0007d000 0x0017d000 0x001000>, /* ap 123 */ + <0x0007e000 0x0017e000 0x001000>, /* ap 124 */ + <0x00059000 0x00159000 0x001000>, /* ap 125 */ + <0x0005a000 0x0015a000 0x001000>; /* ap 126 */ + + target-module@2000 { /* 0x4a102000, ap 27 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@8000 { /* 0x4a108000, ap 29 1e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@40000 { /* 0x4a140000, ap 31 06.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x10000>; + }; + + target-module@51000 { /* 0x4a151000, ap 33 50.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x51000 0x1000>; + }; + + target-module@53000 { /* 0x4a153000, ap 35 54.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53000 0x1000>; + }; + + target-module@55000 { /* 0x4a155000, ap 37 46.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x55000 0x1000>; + }; + + target-module@57000 { /* 0x4a157000, ap 39 58.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x57000 0x1000>; + }; + + target-module@59000 { /* 0x4a159000, ap 125 6a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + }; + + target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + }; + + target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + }; + + target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5f000 0x1000>; + }; + + target-module@61000 { /* 0x4a161000, ap 49 32.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x61000 0x1000>; + }; + + target-module@63000 { /* 0x4a163000, ap 51 5c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x63000 0x1000>; + }; + + target-module@65000 { /* 0x4a165000, ap 53 4e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x65000 0x1000>; + }; + + target-module@67000 { /* 0x4a167000, ap 55 5e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x67000 0x1000>; + }; + + target-module@69000 { /* 0x4a169000, ap 103 4a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x69000 0x1000>; + }; + + target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6b000 0x1000>; + }; + + target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6d000 0x1000>; + }; + + target-module@71000 { /* 0x4a171000, ap 61 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x71000 0x1000>; + }; + + target-module@73000 { /* 0x4a173000, ap 63 2a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x73000 0x1000>; + }; + + target-module@75000 { /* 0x4a175000, ap 65 64.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x75000 0x1000>; + }; + + target-module@77000 { /* 0x4a177000, ap 67 66.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x77000 0x1000>; + }; + + target-module@79000 { /* 0x4a179000, ap 105 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x79000 0x1000>; + }; + + target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7b000 0x1000>; + }; + + target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7d000 0x1000>; + }; + + target-module@81000 { /* 0x4a181000, ap 69 26.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x81000 0x1000>; + }; + + target-module@83000 { /* 0x4a183000, ap 71 2e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x83000 0x1000>; + }; + + target-module@85000 { /* 0x4a185000, ap 73 36.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x85000 0x1000>; + }; + + target-module@87000 { /* 0x4a187000, ap 75 74.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x87000 0x1000>; + }; + }; + + segment@200000 { /* 0x4a200000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */ + <0x00019000 0x00219000 0x001000>, /* ap 44 */ + <0x00000000 0x00200000 0x001000>, /* ap 77 */ + <0x00001000 0x00201000 0x001000>, /* ap 78 */ + <0x0000a000 0x0020a000 0x001000>, /* ap 79 */ + <0x0000b000 0x0020b000 0x001000>, /* ap 80 */ + <0x0000c000 0x0020c000 0x001000>, /* ap 81 */ + <0x0000d000 0x0020d000 0x001000>, /* ap 82 */ + <0x0000e000 0x0020e000 0x001000>, /* ap 83 */ + <0x0000f000 0x0020f000 0x001000>, /* ap 84 */ + <0x00010000 0x00210000 0x001000>, /* ap 85 */ + <0x00011000 0x00211000 0x001000>, /* ap 86 */ + <0x00012000 0x00212000 0x001000>, /* ap 87 */ + <0x00013000 0x00213000 0x001000>, /* ap 88 */ + <0x00014000 0x00214000 0x001000>, /* ap 89 */ + <0x00015000 0x00215000 0x001000>, /* ap 90 */ + <0x0002a000 0x0022a000 0x001000>, /* ap 91 */ + <0x0002b000 0x0022b000 0x001000>, /* ap 92 */ + <0x0001c000 0x0021c000 0x001000>, /* ap 93 */ + <0x0001d000 0x0021d000 0x001000>, /* ap 94 */ + <0x0001e000 0x0021e000 0x001000>, /* ap 95 */ + <0x0001f000 0x0021f000 0x001000>, /* ap 96 */ + <0x00020000 0x00220000 0x001000>, /* ap 97 */ + <0x00021000 0x00221000 0x001000>, /* ap 98 */ + <0x00024000 0x00224000 0x001000>, /* ap 99 */ + <0x00025000 0x00225000 0x001000>, /* ap 100 */ + <0x00026000 0x00226000 0x001000>, /* ap 101 */ + <0x00027000 0x00227000 0x001000>, /* ap 102 */ + <0x0002c000 0x0022c000 0x001000>, /* ap 109 */ + <0x0002d000 0x0022d000 0x001000>, /* ap 110 */ + <0x0002e000 0x0022e000 0x001000>, /* ap 111 */ + <0x0002f000 0x0022f000 0x001000>, /* ap 112 */ + <0x00030000 0x00230000 0x001000>, /* ap 113 */ + <0x00031000 0x00231000 0x001000>, /* ap 114 */ + <0x00032000 0x00232000 0x001000>, /* ap 115 */ + <0x00033000 0x00233000 0x001000>, /* ap 116 */ + <0x00034000 0x00234000 0x001000>, /* ap 117 */ + <0x00035000 0x00235000 0x001000>, /* ap 118 */ + <0x00036000 0x00236000 0x001000>, /* ap 119 */ + <0x00037000 0x00237000 0x001000>, /* ap 120 */ + <0x0001a000 0x0021a000 0x001000>, /* ap 127 */ + <0x0001b000 0x0021b000 0x001000>; /* ap 128 */ + + target-module@0 { /* 0x4a200000, ap 77 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@a000 { /* 0x4a20a000, ap 79 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + + target-module@e000 { /* 0x4a20e000, ap 83 22.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe000 0x1000>; + }; + + target-module@10000 { /* 0x4a210000, ap 85 14.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x1000>; + }; + + target-module@12000 { /* 0x4a212000, ap 87 16.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x12000 0x1000>; + }; + + target-module@14000 { /* 0x4a214000, ap 89 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x14000 0x1000>; + }; + + target-module@18000 { /* 0x4a218000, ap 43 12.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000 0x1000>; + }; + + target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + + target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1c000 0x1000>; + }; + + target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000 0x1000>; + }; + + target-module@20000 { /* 0x4a220000, ap 97 24.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@24000 { /* 0x4a224000, ap 99 44.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + }; + + target-module@26000 { /* 0x4a226000, ap 101 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + }; + + target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + }; + + target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2c000 0x1000>; + }; + + target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2e000 0x1000>; + }; + + target-module@30000 { /* 0x4a230000, ap 113 70.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000 0x1000>; + }; + + target-module@32000 { /* 0x4a232000, ap 115 5a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>; + }; + + target-module@34000 { /* 0x4a234000, ap 117 76.1 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x34000 0x1000>; + }; + + target-module@36000 { /* 0x4a236000, ap 119 62.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + }; +}; + +&l4_per1 { /* 0x48000000 */ + compatible = "ti,dra7-l4-per1", "simple-bus"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ + <0x00200000 0x48200000 0x200000>; /* segment 1 */ + + segment@0 { /* 0x48000000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x000400>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00020000 0x00020000 0x001000>, /* ap 3 */ + <0x00021000 0x00021000 0x001000>, /* ap 4 */ + <0x00032000 0x00032000 0x001000>, /* ap 5 */ + <0x00033000 0x00033000 0x001000>, /* ap 6 */ + <0x00034000 0x00034000 0x001000>, /* ap 7 */ + <0x00035000 0x00035000 0x001000>, /* ap 8 */ + <0x00036000 0x00036000 0x001000>, /* ap 9 */ + <0x00037000 0x00037000 0x001000>, /* ap 10 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ + <0x00055000 0x00055000 0x001000>, /* ap 13 */ + <0x00056000 0x00056000 0x001000>, /* ap 14 */ + <0x00057000 0x00057000 0x001000>, /* ap 15 */ + <0x00058000 0x00058000 0x001000>, /* ap 16 */ + <0x00059000 0x00059000 0x001000>, /* ap 17 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ + <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ + <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ + <0x00060000 0x00060000 0x001000>, /* ap 23 */ + <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ + <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ + <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ + <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ + <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ + <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ + <0x00070000 0x00070000 0x001000>, /* ap 30 */ + <0x00071000 0x00071000 0x001000>, /* ap 31 */ + <0x00072000 0x00072000 0x001000>, /* ap 32 */ + <0x00073000 0x00073000 0x001000>, /* ap 33 */ + <0x00061000 0x00061000 0x001000>, /* ap 34 */ + <0x00053000 0x00053000 0x001000>, /* ap 35 */ + <0x00054000 0x00054000 0x001000>, /* ap 36 */ + <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ + <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ + <0x00078000 0x00078000 0x001000>, /* ap 39 */ + <0x00079000 0x00079000 0x001000>, /* ap 40 */ + <0x00086000 0x00086000 0x001000>, /* ap 41 */ + <0x00087000 0x00087000 0x001000>, /* ap 42 */ + <0x00088000 0x00088000 0x001000>, /* ap 43 */ + <0x00089000 0x00089000 0x001000>, /* ap 44 */ + <0x00051000 0x00051000 0x001000>, /* ap 45 */ + <0x00052000 0x00052000 0x001000>, /* ap 46 */ + <0x00098000 0x00098000 0x001000>, /* ap 47 */ + <0x00099000 0x00099000 0x001000>, /* ap 48 */ + <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ + <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ + <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ + <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ + <0x00068000 0x00068000 0x001000>, /* ap 53 */ + <0x00069000 0x00069000 0x001000>, /* ap 54 */ + <0x00090000 0x00090000 0x002000>, /* ap 55 */ + <0x00092000 0x00092000 0x001000>, /* ap 56 */ + <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ + <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ + <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ + <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ + <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ + <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ + <0x00066000 0x00066000 0x001000>, /* ap 63 */ + <0x00067000 0x00067000 0x001000>, /* ap 64 */ + <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ + <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ + <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ + <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ + <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ + <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ + <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ + <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ + <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ + <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ + <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ + <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ + <0x00001400 0x00001400 0x000400>, /* ap 77 */ + <0x00001800 0x00001800 0x000400>, /* ap 78 */ + <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ + <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ + <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ + <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ + <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ + <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ + + target-module@20000 { /* 0x48020000, ap 3 04.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart3"; + reg = <0x20050 0x4>, + <0x20054 0x4>, + <0x20058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; + ti,no-idle-on-init; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@32000 { /* 0x48032000, ap 5 3e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer2"; + reg = <0x32000 0x4>, + <0x32010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>; + }; + + target-module@34000 { /* 0x48034000, ap 7 46.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer3"; + reg = <0x34000 0x4>, + <0x34010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x34000 0x1000>; + }; + + target-module@36000 { /* 0x48036000, ap 9 4e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer4"; + reg = <0x36000 0x4>, + <0x36010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + + target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer9"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + }; + + target-module@51000 { /* 0x48051000, ap 45 2e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio7"; + reg = <0x51000 0x4>, + <0x51010 0x4>, + <0x51114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; + ti,no-idle-on-init; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x51000 0x1000>; + }; + + target-module@53000 { /* 0x48053000, ap 35 36.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio8"; + reg = <0x53000 0x4>, + <0x53010 0x4>, + <0x53114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53000 0x1000>; + }; + + target-module@55000 { /* 0x48055000, ap 13 0e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio2"; + reg = <0x55000 0x4>, + <0x55010 0x4>, + <0x55114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x55000 0x1000>; + }; + + target-module@57000 { /* 0x48057000, ap 15 06.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio3"; + reg = <0x57000 0x4>, + <0x57010 0x4>, + <0x57114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x57000 0x1000>; + }; + + target-module@59000 { /* 0x48059000, ap 17 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio4"; + reg = <0x59000 0x4>, + <0x59010 0x4>, + <0x59114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + }; + + target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio5"; + reg = <0x5b000 0x4>, + <0x5b010 0x4>, + <0x5b114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + }; + + target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio6"; + reg = <0x5d000 0x4>, + <0x5d010 0x4>, + <0x5d114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>, + <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + }; + + target-module@60000 { /* 0x48060000, ap 23 32.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c3"; + reg = <0x60000 0x8>, + <0x60010 0x8>, + <0x60090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + }; + + target-module@66000 { /* 0x48066000, ap 63 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart5"; + reg = <0x66050 0x4>, + <0x66054 0x4>, + <0x66058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x66000 0x1000>; + }; + + target-module@68000 { /* 0x48068000, ap 53 1c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart6"; + reg = <0x68050 0x4>, + <0x68054 0x4>, + <0x68058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x68000 0x1000>; + }; + + target-module@6a000 { /* 0x4806a000, ap 24 24.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart1"; + reg = <0x6a050 0x4>, + <0x6a054 0x4>, + <0x6a058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6a000 0x1000>; + }; + + target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart2"; + reg = <0x6c050 0x4>, + <0x6c054 0x4>, + <0x6c058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6c000 0x1000>; + }; + + target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart4"; + reg = <0x6e050 0x4>, + <0x6e054 0x4>, + <0x6e058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6e000 0x1000>; + }; + + target-module@70000 { /* 0x48070000, ap 30 22.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c1"; + reg = <0x70000 0x8>, + <0x70010 0x8>, + <0x70090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x70000 0x1000>; + }; + + target-module@72000 { /* 0x48072000, ap 32 2a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c2"; + reg = <0x72000 0x8>, + <0x72010 0x8>, + <0x72090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x72000 0x1000>; + }; + + target-module@78000 { /* 0x48078000, ap 39 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "elm"; + reg = <0x78000 0x4>, + <0x78010 0x4>, + <0x78014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x78000 0x1000>; + }; + + target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c4"; + reg = <0x7a000 0x8>, + <0x7a010 0x8>, + <0x7a090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7a000 0x1000>; + }; + + target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c5"; + reg = <0x7c000 0x8>, + <0x7c010 0x8>, + <0x7c090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7c000 0x1000>; + }; + + target-module@86000 { /* 0x48086000, ap 41 5e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer10"; + reg = <0x86000 0x4>, + <0x86010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x86000 0x1000>; + }; + + target-module@88000 { /* 0x48088000, ap 43 66.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer11"; + reg = <0x88000 0x4>, + <0x88010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x88000 0x1000>; + }; + + target-module@90000 { /* 0x48090000, ap 55 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "rng"; + reg = <0x91fe0 0x4>, + <0x91fe4 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + ; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x90000 0x2000>; + }; + + target-module@98000 { /* 0x48098000, ap 47 08.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi1"; + reg = <0x98000 0x4>, + <0x98010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000 0x1000>; + }; + + target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi2"; + reg = <0x9a000 0x4>, + <0x9a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9a000 0x1000>; + }; + + target-module@9c000 { /* 0x4809c000, ap 51 38.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc1"; + reg = <0x9c000 0x4>, + <0x9c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9c000 0x1000>; + }; + + target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa2000 0x1000>; + }; + + target-module@a4000 { /* 0x480a4000, ap 57 42.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x000a4000 0x00001000>, + <0x00001000 0x000a5000 0x00001000>; + }; + + target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x4000>; + }; + + target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc3"; + reg = <0xad000 0x4>, + <0xad010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xad000 0x1000>; + }; + + target-module@b2000 { /* 0x480b2000, ap 37 52.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "hdq1w"; + reg = <0xb2000 0x4>, + <0xb2014 0x4>, + <0xb2018 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,syss-mask = <1>; + ti,no-reset-on-init; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb2000 0x1000>; + }; + + target-module@b4000 { /* 0x480b4000, ap 65 40.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc2"; + reg = <0xb4000 0x4>, + <0xb4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb4000 0x1000>; + }; + + target-module@b8000 { /* 0x480b8000, ap 67 48.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi3"; + reg = <0xb8000 0x4>, + <0xb8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb8000 0x1000>; + }; + + target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi4"; + reg = <0xba000 0x4>, + <0xba010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xba000 0x1000>; + }; + + target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc4"; + reg = <0xd1000 0x4>, + <0xd1010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd1000 0x1000>; + }; + + target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd5000 0x1000>; + }; + }; + + segment@200000 { /* 0x48200000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&l4_per2 { /* 0x48400000 */ + compatible = "ti,dra7-l4-per2", "simple-bus"; + reg = <0x48400000 0x800>, + <0x48400800 0x800>, + <0x48401000 0x400>, + <0x48401400 0x400>, + <0x48401800 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48400000 0x400000>; /* segment 0 */ + + segment@0 { /* 0x48400000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x000400>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00084000 0x00084000 0x004000>, /* ap 3 */ + <0x00001400 0x00001400 0x000400>, /* ap 4 */ + <0x00001800 0x00001800 0x000400>, /* ap 5 */ + <0x00088000 0x00088000 0x001000>, /* ap 6 */ + <0x0002c000 0x0002c000 0x001000>, /* ap 7 */ + <0x0002d000 0x0002d000 0x001000>, /* ap 8 */ + <0x00060000 0x00060000 0x002000>, /* ap 9 */ + <0x00062000 0x00062000 0x001000>, /* ap 10 */ + <0x00064000 0x00064000 0x002000>, /* ap 11 */ + <0x00066000 0x00066000 0x001000>, /* ap 12 */ + <0x00068000 0x00068000 0x002000>, /* ap 13 */ + <0x0006a000 0x0006a000 0x001000>, /* ap 14 */ + <0x0006c000 0x0006c000 0x002000>, /* ap 15 */ + <0x0006e000 0x0006e000 0x001000>, /* ap 16 */ + <0x00036000 0x00036000 0x001000>, /* ap 17 */ + <0x00037000 0x00037000 0x001000>, /* ap 18 */ + <0x00070000 0x00070000 0x002000>, /* ap 19 */ + <0x00072000 0x00072000 0x001000>, /* ap 20 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 21 */ + <0x0003b000 0x0003b000 0x001000>, /* ap 22 */ + <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ + <0x0003d000 0x0003d000 0x001000>, /* ap 24 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 25 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 26 */ + <0x00040000 0x00040000 0x001000>, /* ap 27 */ + <0x00041000 0x00041000 0x001000>, /* ap 28 */ + <0x00042000 0x00042000 0x001000>, /* ap 29 */ + <0x00043000 0x00043000 0x001000>, /* ap 30 */ + <0x00080000 0x00080000 0x002000>, /* ap 31 */ + <0x00082000 0x00082000 0x001000>, /* ap 32 */ + <0x0004a000 0x0004a000 0x001000>, /* ap 33 */ + <0x0004b000 0x0004b000 0x001000>, /* ap 34 */ + <0x00074000 0x00074000 0x002000>, /* ap 35 */ + <0x00076000 0x00076000 0x001000>, /* ap 36 */ + <0x00050000 0x00050000 0x001000>, /* ap 37 */ + <0x00051000 0x00051000 0x001000>, /* ap 38 */ + <0x00078000 0x00078000 0x002000>, /* ap 39 */ + <0x0007a000 0x0007a000 0x001000>, /* ap 40 */ + <0x00054000 0x00054000 0x001000>, /* ap 41 */ + <0x00055000 0x00055000 0x001000>, /* ap 42 */ + <0x0007c000 0x0007c000 0x002000>, /* ap 43 */ + <0x0007e000 0x0007e000 0x001000>, /* ap 44 */ + <0x0004c000 0x0004c000 0x001000>, /* ap 45 */ + <0x0004d000 0x0004d000 0x001000>, /* ap 46 */ + <0x00020000 0x00020000 0x001000>, /* ap 47 */ + <0x00021000 0x00021000 0x001000>, /* ap 48 */ + <0x00022000 0x00022000 0x001000>, /* ap 49 */ + <0x00023000 0x00023000 0x001000>, /* ap 50 */ + <0x00024000 0x00024000 0x001000>, /* ap 51 */ + <0x00025000 0x00025000 0x001000>, /* ap 52 */ + <0x00046000 0x00046000 0x001000>, /* ap 53 */ + <0x00047000 0x00047000 0x001000>, /* ap 54 */ + <0x00048000 0x00048000 0x001000>, /* ap 55 */ + <0x00049000 0x00049000 0x001000>, /* ap 56 */ + <0x00058000 0x00058000 0x002000>, /* ap 57 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 58 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 59 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 60 */ + <0x0005d000 0x0005d000 0x001000>, /* ap 61 */ + <0x0005e000 0x0005e000 0x001000>; /* ap 62 */ + + target-module@20000 { /* 0x48420000, ap 47 02.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart7"; + reg = <0x20050 0x4>, + <0x20054 0x4>, + <0x20058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@22000 { /* 0x48422000, ap 49 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart8"; + reg = <0x22050 0x4>, + <0x22054 0x4>, + <0x22058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + }; + + target-module@24000 { /* 0x48424000, ap 51 12.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart9"; + reg = <0x24050 0x4>, + <0x24054 0x4>, + <0x24058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + }; + + target-module@2c000 { /* 0x4842c000, ap 7 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2c000 0x1000>; + }; + + target-module@36000 { /* 0x48436000, ap 17 06.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + + target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3a000 0x1000>; + }; + + target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x1000>; + }; + + target-module@3e000 { /* 0x4843e000, ap 25 30.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss0"; + reg = <0x3e000 0x4>, + <0x3e004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + }; + + target-module@40000 { /* 0x48440000, ap 27 38.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss1"; + reg = <0x40000 0x4>, + <0x40004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + }; + + target-module@42000 { /* 0x48442000, ap 29 20.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "epwmss2"; + reg = <0x42000 0x4>, + <0x42004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42000 0x1000>; + }; + + target-module@46000 { /* 0x48446000, ap 53 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x46000 0x1000>; + }; + + target-module@48000 { /* 0x48448000, ap 55 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48000 0x1000>; + }; + + target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4a000 0x1000>; + }; + + target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000 0x1000>; + }; + + target-module@50000 { /* 0x48450000, ap 37 24.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000 0x1000>; + }; + + target-module@54000 { /* 0x48454000, ap 41 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x54000 0x1000>; + }; + + target-module@58000 { /* 0x48458000, ap 57 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x58000 0x2000>; + }; + + target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + }; + + target-module@5d000 { /* 0x4845d000, ap 61 22.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + }; + + target-module@60000 { /* 0x48460000, ap 9 0e.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp1"; + reg = <0x60000 0x4>, + <0x60004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x2000>; + }; + + target-module@64000 { /* 0x48464000, ap 11 1e.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp2"; + reg = <0x64000 0x4>, + <0x64004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x64000 0x2000>; + }; + + target-module@68000 { /* 0x48468000, ap 13 26.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp3"; + reg = <0x68000 0x4>, + <0x68004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x68000 0x2000>; + }; + + target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp4"; + reg = <0x6c000 0x4>, + <0x6c004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6c000 0x2000>; + }; + + target-module@70000 { /* 0x48470000, ap 19 36.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp5"; + reg = <0x70000 0x4>, + <0x70004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x70000 0x2000>; + }; + + target-module@74000 { /* 0x48474000, ap 35 14.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp6"; + reg = <0x74000 0x4>, + <0x74004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x74000 0x2000>; + }; + + target-module@78000 { /* 0x48478000, ap 39 0c.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp7"; + reg = <0x78000 0x4>, + <0x78004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x78000 0x2000>; + }; + + target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "mcasp8"; + reg = <0x7c000 0x4>, + <0x7c004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7c000 0x2000>; + }; + + target-module@80000 { /* 0x48480000, ap 31 16.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x2000>; + }; + + target-module@84000 { /* 0x48484000, ap 3 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x84000 0x4000>; + }; + }; +}; + +&l4_per3 { /* 0x48800000 */ + compatible = "ti,dra7-l4-per3", "simple-bus"; + reg = <0x48800000 0x800>, + <0x48800800 0x800>, + <0x48801000 0x400>, + <0x48801400 0x400>, + <0x48801800 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */ + + segment@0 { /* 0x48800000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00000800 0x00000800 0x000800>, /* ap 1 */ + <0x00001000 0x00001000 0x000400>, /* ap 2 */ + <0x00001400 0x00001400 0x000400>, /* ap 3 */ + <0x00001800 0x00001800 0x000400>, /* ap 4 */ + <0x00020000 0x00020000 0x001000>, /* ap 5 */ + <0x00021000 0x00021000 0x001000>, /* ap 6 */ + <0x00022000 0x00022000 0x001000>, /* ap 7 */ + <0x00023000 0x00023000 0x001000>, /* ap 8 */ + <0x00024000 0x00024000 0x001000>, /* ap 9 */ + <0x00025000 0x00025000 0x001000>, /* ap 10 */ + <0x00026000 0x00026000 0x001000>, /* ap 11 */ + <0x00027000 0x00027000 0x001000>, /* ap 12 */ + <0x00028000 0x00028000 0x001000>, /* ap 13 */ + <0x00029000 0x00029000 0x001000>, /* ap 14 */ + <0x0002a000 0x0002a000 0x001000>, /* ap 15 */ + <0x0002b000 0x0002b000 0x001000>, /* ap 16 */ + <0x0002c000 0x0002c000 0x001000>, /* ap 17 */ + <0x0002d000 0x0002d000 0x001000>, /* ap 18 */ + <0x0002e000 0x0002e000 0x001000>, /* ap 19 */ + <0x0002f000 0x0002f000 0x001000>, /* ap 20 */ + <0x00170000 0x00170000 0x010000>, /* ap 21 */ + <0x00180000 0x00180000 0x001000>, /* ap 22 */ + <0x00190000 0x00190000 0x010000>, /* ap 23 */ + <0x001a0000 0x001a0000 0x001000>, /* ap 24 */ + <0x001b0000 0x001b0000 0x010000>, /* ap 25 */ + <0x001c0000 0x001c0000 0x001000>, /* ap 26 */ + <0x001d0000 0x001d0000 0x010000>, /* ap 27 */ + <0x001e0000 0x001e0000 0x001000>, /* ap 28 */ + <0x00038000 0x00038000 0x001000>, /* ap 29 */ + <0x00039000 0x00039000 0x001000>, /* ap 30 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 31 */ + <0x0005d000 0x0005d000 0x001000>, /* ap 32 */ + <0x0003a000 0x0003a000 0x001000>, /* ap 33 */ + <0x0003b000 0x0003b000 0x001000>, /* ap 34 */ + <0x0003c000 0x0003c000 0x001000>, /* ap 35 */ + <0x0003d000 0x0003d000 0x001000>, /* ap 36 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 37 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 38 */ + <0x00040000 0x00040000 0x001000>, /* ap 39 */ + <0x00041000 0x00041000 0x001000>, /* ap 40 */ + <0x00042000 0x00042000 0x001000>, /* ap 41 */ + <0x00043000 0x00043000 0x001000>, /* ap 42 */ + <0x00044000 0x00044000 0x001000>, /* ap 43 */ + <0x00045000 0x00045000 0x001000>, /* ap 44 */ + <0x00046000 0x00046000 0x001000>, /* ap 45 */ + <0x00047000 0x00047000 0x001000>, /* ap 46 */ + <0x00048000 0x00048000 0x001000>, /* ap 47 */ + <0x00049000 0x00049000 0x001000>, /* ap 48 */ + <0x0004a000 0x0004a000 0x001000>, /* ap 49 */ + <0x0004b000 0x0004b000 0x001000>, /* ap 50 */ + <0x0004c000 0x0004c000 0x001000>, /* ap 51 */ + <0x0004d000 0x0004d000 0x001000>, /* ap 52 */ + <0x0004e000 0x0004e000 0x001000>, /* ap 53 */ + <0x0004f000 0x0004f000 0x001000>, /* ap 54 */ + <0x00050000 0x00050000 0x001000>, /* ap 55 */ + <0x00051000 0x00051000 0x001000>, /* ap 56 */ + <0x00052000 0x00052000 0x001000>, /* ap 57 */ + <0x00053000 0x00053000 0x001000>, /* ap 58 */ + <0x00054000 0x00054000 0x001000>, /* ap 59 */ + <0x00055000 0x00055000 0x001000>, /* ap 60 */ + <0x00056000 0x00056000 0x001000>, /* ap 61 */ + <0x00057000 0x00057000 0x001000>, /* ap 62 */ + <0x00058000 0x00058000 0x001000>, /* ap 63 */ + <0x00059000 0x00059000 0x001000>, /* ap 64 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 65 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 66 */ + <0x00064000 0x00064000 0x001000>, /* ap 67 */ + <0x00065000 0x00065000 0x001000>, /* ap 68 */ + <0x0005e000 0x0005e000 0x001000>, /* ap 69 */ + <0x0005f000 0x0005f000 0x001000>, /* ap 70 */ + <0x00060000 0x00060000 0x001000>, /* ap 71 */ + <0x00061000 0x00061000 0x001000>, /* ap 72 */ + <0x00062000 0x00062000 0x001000>, /* ap 73 */ + <0x00063000 0x00063000 0x001000>, /* ap 74 */ + <0x00140000 0x00140000 0x020000>, /* ap 75 */ + <0x00160000 0x00160000 0x001000>, /* ap 76 */ + <0x00016000 0x00016000 0x001000>, /* ap 77 */ + <0x00017000 0x00017000 0x001000>, /* ap 78 */ + <0x000c0000 0x000c0000 0x020000>, /* ap 79 */ + <0x000e0000 0x000e0000 0x001000>, /* ap 80 */ + <0x00004000 0x00004000 0x001000>, /* ap 81 */ + <0x00005000 0x00005000 0x001000>, /* ap 82 */ + <0x00080000 0x00080000 0x020000>, /* ap 83 */ + <0x000a0000 0x000a0000 0x001000>, /* ap 84 */ + <0x00100000 0x00100000 0x020000>, /* ap 85 */ + <0x00120000 0x00120000 0x001000>, /* ap 86 */ + <0x00010000 0x00010000 0x001000>, /* ap 87 */ + <0x00011000 0x00011000 0x001000>, /* ap 88 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 89 */ + <0x0000b000 0x0000b000 0x001000>, /* ap 90 */ + <0x0001c000 0x0001c000 0x001000>, /* ap 91 */ + <0x0001d000 0x0001d000 0x001000>, /* ap 92 */ + <0x0001e000 0x0001e000 0x001000>, /* ap 93 */ + <0x0001f000 0x0001f000 0x001000>, /* ap 94 */ + <0x00002000 0x00002000 0x001000>, /* ap 95 */ + <0x00003000 0x00003000 0x001000>; /* ap 96 */ + + target-module@2000 { /* 0x48802000, ap 95 7c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox13"; + reg = <0x2000 0x4>, + <0x2010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@4000 { /* 0x48804000, ap 81 20.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@a000 { /* 0x4880a000, ap 89 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@10000 { /* 0x48810000, ap 87 28.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x1000>; + }; + + target-module@16000 { /* 0x48816000, ap 77 1e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x16000 0x1000>; + }; + + target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1c000 0x1000>; + }; + + target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000 0x1000>; + }; + + target-module@20000 { /* 0x48820000, ap 5 08.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer5"; + reg = <0x20000 0x4>, + <0x20010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@22000 { /* 0x48822000, ap 7 24.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer6"; + reg = <0x22000 0x4>, + <0x22010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + }; + + target-module@24000 { /* 0x48824000, ap 9 26.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer7"; + reg = <0x24000 0x4>, + <0x24010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + }; + + target-module@26000 { /* 0x48826000, ap 11 0c.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer8"; + reg = <0x26000 0x4>, + <0x26010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ + clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + }; + + target-module@28000 { /* 0x48828000, ap 13 16.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer13"; + reg = <0x28000 0x4>, + <0x28010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>; + }; + + target-module@2a000 { /* 0x4882a000, ap 15 10.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer14"; + reg = <0x2a000 0x4>, + <0x2a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + }; + + target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer15"; + reg = <0x2c000 0x4>, + <0x2c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2c000 0x1000>; + }; + + target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer16"; + reg = <0x2e000 0x4>, + <0x2e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2e000 0x1000>; + }; + + target-module@38000 { /* 0x48838000, ap 29 12.0 */ + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "rtcss"; + reg = <0x38074 0x4>, + <0x38078 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): rtc_pwrdm, rtc_clkdm */ + clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x38000 0x1000>; + }; + + target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox2"; + reg = <0x3a000 0x4>, + <0x3a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3a000 0x1000>; + }; + + target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox3"; + reg = <0x3c000 0x4>, + <0x3c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3c000 0x1000>; + }; + + target-module@3e000 { /* 0x4883e000, ap 37 46.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox4"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + }; + + target-module@40000 { /* 0x48840000, ap 39 64.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox5"; + reg = <0x40000 0x4>, + <0x40010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + }; + + target-module@42000 { /* 0x48842000, ap 41 4e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox6"; + reg = <0x42000 0x4>, + <0x42010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42000 0x1000>; + }; + + target-module@44000 { /* 0x48844000, ap 43 42.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox7"; + reg = <0x44000 0x4>, + <0x44010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x44000 0x1000>; + }; + + target-module@46000 { /* 0x48846000, ap 45 48.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox8"; + reg = <0x46000 0x4>, + <0x46010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x46000 0x1000>; + }; + + target-module@48000 { /* 0x48848000, ap 47 36.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48000 0x1000>; + }; + + target-module@4a000 { /* 0x4884a000, ap 49 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4a000 0x1000>; + }; + + target-module@4c000 { /* 0x4884c000, ap 51 44.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000 0x1000>; + }; + + target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4e000 0x1000>; + }; + + target-module@50000 { /* 0x48850000, ap 55 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000 0x1000>; + }; + + target-module@52000 { /* 0x48852000, ap 57 54.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x52000 0x1000>; + }; + + target-module@54000 { /* 0x48854000, ap 59 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x54000 0x1000>; + }; + + target-module@56000 { /* 0x48856000, ap 61 22.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x56000 0x1000>; + }; + + target-module@58000 { /* 0x48858000, ap 63 2a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x58000 0x1000>; + }; + + target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5a000 0x1000>; + }; + + target-module@5c000 { /* 0x4885c000, ap 31 32.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5c000 0x1000>; + }; + + target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox9"; + reg = <0x5e000 0x4>, + <0x5e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5e000 0x1000>; + }; + + target-module@60000 { /* 0x48860000, ap 71 4a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox10"; + reg = <0x60000 0x4>, + <0x60010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + }; + + target-module@62000 { /* 0x48862000, ap 73 74.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox11"; + reg = <0x62000 0x4>, + <0x62010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x62000 0x1000>; + }; + + target-module@64000 { /* 0x48864000, ap 67 52.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox12"; + reg = <0x64000 0x4>, + <0x64010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x64000 0x1000>; + }; + + target-module@80000 { /* 0x48880000, ap 83 0e.1 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "usb_otg_ss1"; + reg = <0x80000 0x4>, + <0x80010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80000 0x20000>; + }; + + target-module@c0000 { /* 0x488c0000, ap 79 06.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "usb_otg_ss2"; + reg = <0xc0000 0x4>, + <0xc0010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc0000 0x20000>; + }; + + target-module@100000 { /* 0x48900000, ap 85 04.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "usb_otg_ss3"; + reg = <0x100000 0x4>, + <0x100010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x100000 0x20000>; + }; + + target-module@140000 { /* 0x48940000, ap 75 3c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "usb_otg_ss4"; + reg = <0x140000 0x4>, + <0x140010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x140000 0x20000>; + }; + + target-module@170000 { /* 0x48970000, ap 21 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x170000 0x10000>; + }; + + target-module@190000 { /* 0x48990000, ap 23 2e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x190000 0x10000>; + }; + + target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b0000 0x10000>; + }; + + target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1d0000 0x10000>; + }; + }; +}; + +&l4_wkup { /* 0x4ae00000 */ + compatible = "ti,dra7-l4-wkup", "simple-bus"; + reg = <0x4ae00000 0x800>, + <0x4ae00800 0x800>, + <0x4ae01000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ + <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ + <0x00020000 0x4ae20000 0x010000>, /* segment 2 */ + <0x00030000 0x4ae30000 0x010000>; /* segment 3 */ + + segment@0 { /* 0x4ae00000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00006000 0x00006000 0x002000>, /* ap 3 */ + <0x00008000 0x00008000 0x001000>, /* ap 4 */ + <0x00004000 0x00004000 0x001000>, /* ap 15 */ + <0x00005000 0x00005000 0x001000>, /* ap 16 */ + <0x0000c000 0x0000c000 0x001000>, /* ap 17 */ + <0x0000d000 0x0000d000 0x001000>; /* ap 18 */ + + target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "counter_32k"; + reg = <0x4000 0x4>, + <0x4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@6000 { /* 0x4ae06000, ap 3 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x2000>; + }; + + target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + }; + + segment@10000 { /* 0x4ae10000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ + <0x00001000 0x00011000 0x001000>, /* ap 6 */ + <0x00004000 0x00014000 0x001000>, /* ap 7 */ + <0x00005000 0x00015000 0x001000>, /* ap 8 */ + <0x00008000 0x00018000 0x001000>, /* ap 9 */ + <0x00009000 0x00019000 0x001000>, /* ap 10 */ + <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ + <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ + + target-module@0 { /* 0x4ae10000, ap 5 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio1"; + reg = <0x0 0x4>, + <0x10 0x4>, + <0x114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>, + <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@4000 { /* 0x4ae14000, ap 7 28.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "wd_timer2"; + reg = <0x4000 0x4>, + <0x4010 0x4>, + <0x4014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer1"; + reg = <0x8000 0x4>, + <0x8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + }; + + segment@20000 { /* 0x4ae20000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ + <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ + <0x00000000 0x00020000 0x001000>, /* ap 19 */ + <0x00001000 0x00021000 0x001000>, /* ap 20 */ + <0x00002000 0x00022000 0x001000>, /* ap 21 */ + <0x00003000 0x00023000 0x001000>, /* ap 22 */ + <0x00007000 0x00027000 0x000400>, /* ap 23 */ + <0x00008000 0x00028000 0x000800>, /* ap 24 */ + <0x00009000 0x00029000 0x000100>, /* ap 25 */ + <0x00008800 0x00028800 0x000200>, /* ap 26 */ + <0x00008a00 0x00028a00 0x000100>, /* ap 27 */ + <0x0000b000 0x0002b000 0x001000>, /* ap 28 */ + <0x0000c000 0x0002c000 0x001000>, /* ap 29 */ + <0x0000f000 0x0002f000 0x001000>; /* ap 32 */ + + target-module@0 { /* 0x4ae20000, ap 19 08.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer12"; + reg = <0x0 0x4>, + <0x10 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@2000 { /* 0x4ae22000, ap 21 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@6000 { /* 0x4ae26000, ap 13 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00006000 0x00001000>, + <0x00001000 0x00007000 0x00000400>, + <0x00002000 0x00008000 0x00000800>, + <0x00002800 0x00008800 0x00000200>, + <0x00002a00 0x00008a00 0x00000100>, + <0x00003000 0x00009000 0x00000100>; + }; + + target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart10"; + reg = <0xb050 0x4>, + <0xb054 0x4>, + <0xb058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb000 0x1000>; + }; + + target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf000 0x1000>; + }; + }; + + segment@30000 { /* 0x4ae30000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */ + <0x0000e000 0x0003e000 0x001000>, /* ap 31 */ + <0x00000000 0x00030000 0x001000>, /* ap 33 */ + <0x00001000 0x00031000 0x001000>, /* ap 34 */ + <0x00002000 0x00032000 0x001000>, /* ap 35 */ + <0x00003000 0x00033000 0x001000>, /* ap 36 */ + <0x00004000 0x00034000 0x001000>, /* ap 37 */ + <0x00005000 0x00035000 0x001000>, /* ap 38 */ + <0x00006000 0x00036000 0x001000>, /* ap 39 */ + <0x00007000 0x00037000 0x001000>, /* ap 40 */ + <0x00008000 0x00038000 0x001000>, /* ap 41 */ + <0x00009000 0x00039000 0x001000>, /* ap 42 */ + <0x0000a000 0x0003a000 0x001000>; /* ap 43 */ + + target-module@1000 { /* 0x4ae31000, ap 34 60.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1000 0x1000>; + }; + + target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3000 0x1000>; + }; + + target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5000 0x1000>; + }; + + target-module@7000 { /* 0x4ae37000, ap 40 68.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; + }; + + target-module@9000 { /* 0x4ae39000, ap 42 70.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9000 0x1000>; + }; + + target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x2000>; + }; + }; +}; + -- cgit From 4ed0dfe3cf39a97cd0ed532212b5e55e9752fe3f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 27 Sep 2018 13:39:07 -0700 Subject: ARM: dts: dra7: Move l4 child devices to probe them with ti-sysc With l4 interconnect hierarchy and ti-sysc interconnect target module data in place, we can simply move all the related child devices to their proper location and enable probing using ti-sysc. In general the first child device address range starts at range 0 from the ti-sysc interconnect target so the move involves adjusting the child device reg properties for that. In case of any regressions, problem devices can be reverted to probe with legacy platform data as needed by moving them back and removing the related interconnect target module node. Cc: Dave Gerlach Cc: Keerthy Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 1384 +++++++++++++++++++++++++++++++++++++- arch/arm/boot/dts/dra7.dtsi | 1424 +--------------------------------------- 2 files changed, 1371 insertions(+), 1437 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 73cd83a04450..efca29aff633 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -45,27 +45,143 @@ <0x00098000 0x00098000 0x001000>; /* ap 60 */ target-module@2000 { /* 0x4a002000, ap 3 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x2000 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x2000>; + + scm: scm@0 { + compatible = "ti,dra7-scm-core", "simple-bus"; + reg = <0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + scm_conf: scm_conf@0 { + compatible = "syscon", "simple-bus"; + reg = <0x0 0x1400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x1400>; + + pbias_regulator: pbias_regulator@e00 { + compatible = "ti,pbias-dra7", "ti,pbias-omap"; + reg = <0xe00 0x4>; + syscon = <&scm_conf>; + pbias_mmc_reg: pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + + scm_conf_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + phy_sel: cpsw-phy-sel@554 { + compatible = "ti,dra7xx-cpsw-phy-sel"; + reg= <0x554 0x4>; + reg-names = "gmii-sel"; + }; + + dra7_pmx_core: pinmux@1400 { + compatible = "ti,dra7-padconf", + "pinctrl-single"; + reg = <0x1400 0x0468>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x3fffffff>; + }; + + scm_conf1: scm_conf@1c04 { + compatible = "syscon"; + reg = <0x1c04 0x0020>; + #syscon-cells = <2>; + }; + + scm_conf_pcie: scm_conf@1c24 { + compatible = "syscon"; + reg = <0x1c24 0x0024>; + }; + + sdma_xbar: dma-router@b78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0xb78 0xfc>; + #dma-cells = <1>; + dma-requests = <205>; + ti,dma-safe-map = <0>; + dma-masters = <&sdma>; + }; + + edma_xbar: dma-router@c78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0xc78 0x7c>; + #dma-cells = <2>; + dma-requests = <204>; + ti,dma-safe-map = <0>; + dma-masters = <&edma>; + }; + }; }; target-module@5000 { /* 0x4a005000, ap 5 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5000 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5000 0x1000>; + + cm_core_aon: cm_core_aon@0 { + compatible = "ti,dra7-cm-core-aon", + "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x2000>; + ranges = <0 0 0x2000>; + + cm_core_aon_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_aon_clockdomains: clockdomains { + }; + }; }; target-module@8000 { /* 0x4a008000, ap 7 0e.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x8000 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x2000>; + + cm_core: cm_core@0 { + compatible = "ti,dra7-cm-core", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x3000>; + ranges = <0 0 0x3000>; + + cm_core_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_clockdomains: clockdomains { + }; + }; }; target-module@56000 { /* 0x4a056000, ap 9 02.0 */ @@ -94,6 +210,18 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x56000 0x1000>; + + sdma: dma-controller@0 { + compatible = "ti,omap4430-sdma"; + reg = <0x0 0x1000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <127>; + }; }; target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */ @@ -123,6 +251,53 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x8000>; + + ocp2scp@0 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x8000>; + reg = <0x0 0x20>; + + usb2_phy1: phy@4000 { + compatible = "ti,dra7x-usb2", "ti,omap-usb2"; + reg = <0x4000 0x400>; + syscon-phy-power = <&scm_conf 0x300>; + clocks = <&usb_phy1_always_on_clk32k>, + <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; + clock-names = "wkupclk", + "refclk"; + #phy-cells = <0>; + }; + + usb2_phy2: phy@5000 { + compatible = "ti,dra7x-usb2-phy2", + "ti,omap-usb2"; + reg = <0x5000 0x400>; + syscon-phy-power = <&scm_conf 0xe74>; + clocks = <&usb_phy2_always_on_clk32k>, + <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; + clock-names = "wkupclk", + "refclk"; + #phy-cells = <0>; + }; + + usb3_phy1: phy@4400 { + compatible = "ti,omap-usb3"; + reg = <0x4400 0x80>, + <0x4800 0x64>, + <0x4c00 0x40>; + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + syscon-phy-power = <&scm_conf 0x370>; + clocks = <&usb_phy3_always_on_clk32k>, + <&sys_clkin1>, + <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; + clock-names = "wkupclk", + "sysclk", + "refclk"; + #phy-cells = <0>; + }; + }; }; target-module@90000 { /* 0x4a090000, ap 59 42.0 */ @@ -144,6 +319,69 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x90000 0x8000>; + + ocp2scp@0 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x8000>; + reg = <0x0 0x20>; + + pcie1_phy: pciephy@4000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x4000 0x80>, /* phy_rx */ + <0x4400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + syscon-phy-power = <&scm_conf_pcie 0x1c>; + syscon-pcs = <&scm_conf_pcie 0x10>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, + <&optfclk_pciephy_div>, + <&sys_clkin1>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div", "sysclk"; + #phy-cells = <0>; + }; + + pcie2_phy: pciephy@5000 { + compatible = "ti,phy-pipe3-pcie"; + reg = <0x5000 0x80>, /* phy_rx */ + <0x5400 0x64>; /* phy_tx */ + reg-names = "phy_rx", "phy_tx"; + syscon-phy-power = <&scm_conf_pcie 0x20>; + syscon-pcs = <&scm_conf_pcie 0x10>; + clocks = <&dpll_pcie_ref_ck>, + <&dpll_pcie_ref_m2ldo_ck>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, + <&optfclk_pciephy_div>, + <&sys_clkin1>; + clock-names = "dpll_ref", "dpll_ref_m2", + "wkupclk", "refclk", + "div-clk", "phy-div", "sysclk"; + #phy-cells = <0>; + status = "disabled"; + }; + + sata_phy: phy@6000 { + compatible = "ti,phy-pipe3-sata"; + reg = <0x6000 0x80>, /* phy_rx */ + <0x6400 0x64>, /* phy_tx */ + <0x6800 0x40>; /* pll_ctrl */ + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + syscon-phy-power = <&scm_conf 0x374>; + clocks = <&sys_clkin1>, + <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; + clock-names = "sysclk", "refclk"; + syscon-pllreset = <&scm_conf 0x3fc>; + #phy-cells = <0>; + }; + }; }; target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */ @@ -155,7 +393,7 @@ }; target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */ - compatible = "ti,sysc-omap3630-sr", "ti,sysc"; + compatible = "ti,sysc-omap4-sr", "ti,sysc"; ti,hwmods = "smartreflex_mpu"; reg = <0xd9038 0x4>; reg-names = "sysc"; @@ -170,10 +408,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd9000 0x1000>; + + /* SmartReflex child device marked reserved in TRM */ }; target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */ - compatible = "ti,sysc-omap3630-sr", "ti,sysc"; + compatible = "ti,sysc-omap4-sr", "ti,sysc"; ti,hwmods = "smartreflex_core"; reg = <0xdd038 0x4>; reg-names = "sysc"; @@ -188,6 +428,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xdd000 0x1000>; + + /* SmartReflex child device marked reserved in TRM */ }; target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */ @@ -214,6 +456,18 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf4000 0x1000>; + + mailbox1: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; + status = "disabled"; + }; }; target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */ @@ -236,6 +490,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf6000 0x1000>; + + hwspinlock: spinlock@0 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x0 0x1000>; + #hwlock-cells = <1>; + }; }; }; @@ -871,14 +1131,22 @@ , ; ti,syss-mask = <1>; - ti,no-reset-on-init; - ti,no-idle-on-init; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; + + uart3: serial@0 { + compatible = "ti,dra742-uart", "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; + dma-names = "tx", "rx"; + }; }; target-module@32000 { /* 0x48032000, ap 5 3e.0 */ @@ -899,6 +1167,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x32000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@34000 { /* 0x48034000, ap 7 46.0 */ @@ -919,6 +1195,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x34000 0x1000>; + + timer3: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@36000 { /* 0x48036000, ap 9 4e.0 */ @@ -939,6 +1223,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x36000 0x1000>; + + timer4: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ @@ -959,6 +1251,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; + + timer9: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@51000 { /* 0x48051000, ap 45 2e.0 */ @@ -976,8 +1276,6 @@ , ; ti,syss-mask = <1>; - ti,no-reset-on-init; - ti,no-idle-on-init; /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>, <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>; @@ -985,6 +1283,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x51000 0x1000>; + + gpio7: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@53000 { /* 0x48053000, ap 35 36.0 */ @@ -1009,6 +1317,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x53000 0x1000>; + + gpio8: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@55000 { /* 0x48055000, ap 13 0e.0 */ @@ -1033,6 +1351,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x55000 0x1000>; + + gpio2: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@57000 { /* 0x48057000, ap 15 06.0 */ @@ -1057,6 +1385,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x57000 0x1000>; + + gpio3: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@59000 { /* 0x48059000, ap 17 16.0 */ @@ -1081,6 +1419,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x59000 0x1000>; + + gpio4: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ @@ -1105,6 +1453,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5b000 0x1000>; + + gpio5: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ @@ -1129,6 +1487,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5d000 0x1000>; + + gpio6: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@60000 { /* 0x48060000, ap 23 32.0 */ @@ -1153,6 +1521,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; + + i2c3: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@66000 { /* 0x48066000, ap 63 14.0 */ @@ -1176,6 +1553,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x66000 0x1000>; + + uart5: serial@0 { + compatible = "ti,dra742-uart", "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; + dma-names = "tx", "rx"; + }; }; target-module@68000 { /* 0x48068000, ap 53 1c.0 */ @@ -1199,6 +1586,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x68000 0x1000>; + + uart6: serial@0 { + compatible = "ti,dra742-uart", "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; + dma-names = "tx", "rx"; + }; }; target-module@6a000 { /* 0x4806a000, ap 24 24.0 */ @@ -1222,6 +1619,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6a000 0x1000>; + + uart1: serial@0 { + compatible = "ti,dra742-uart", "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; + dma-names = "tx", "rx"; + }; }; target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */ @@ -1245,6 +1652,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6c000 0x1000>; + + uart2: serial@0 { + compatible = "ti,dra742-uart", "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; + dma-names = "tx", "rx"; + }; }; target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */ @@ -1268,6 +1685,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6e000 0x1000>; + + uart4: serial@0 { + compatible = "ti,dra742-uart", "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; + dma-names = "tx", "rx"; + }; }; target-module@70000 { /* 0x48070000, ap 30 22.0 */ @@ -1292,6 +1719,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x70000 0x1000>; + + i2c1: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@72000 { /* 0x48072000, ap 32 2a.0 */ @@ -1316,6 +1752,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x72000 0x1000>; + + i2c2: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@78000 { /* 0x48078000, ap 39 0a.0 */ @@ -1339,6 +1784,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x78000 0x1000>; + + elm: elm@0 { + compatible = "ti,am3352-elm"; + reg = <0x0 0xfc0>; /* device IO registers */ + interrupts = ; + status = "disabled"; + }; }; target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */ @@ -1363,6 +1815,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7a000 0x1000>; + + i2c4: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */ @@ -1387,6 +1848,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7c000 0x1000>; + + i2c5: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; target-module@86000 { /* 0x48086000, ap 41 5e.0 */ @@ -1407,6 +1877,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x86000 0x1000>; + + timer10: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@88000 { /* 0x48088000, ap 43 66.0 */ @@ -1427,6 +1905,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x88000 0x1000>; + + timer11: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@90000 { /* 0x48090000, ap 55 12.0 */ @@ -1444,6 +1930,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x90000 0x2000>; + + rng: rng@0 { + compatible = "ti,omap4-rng"; + reg = <0x0 0x2000>; + interrupts = ; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; }; target-module@98000 { /* 0x48098000, ap 47 08.0 */ @@ -1464,6 +1958,26 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x98000 0x1000>; + + mcspi1: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <4>; + dmas = <&sdma_xbar 35>, + <&sdma_xbar 36>, + <&sdma_xbar 37>, + <&sdma_xbar 38>, + <&sdma_xbar 39>, + <&sdma_xbar 40>, + <&sdma_xbar 41>, + <&sdma_xbar 42>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + status = "disabled"; + }; }; target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ @@ -1484,6 +1998,21 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9a000 0x1000>; + + mcspi2: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma_xbar 43>, + <&sdma_xbar 44>, + <&sdma_xbar 45>, + <&sdma_xbar 46>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + status = "disabled"; + }; }; target-module@9c000 { /* 0x4809c000, ap 51 38.0 */ @@ -1508,6 +2037,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x9c000 0x1000>; + + mmc1: mmc@0 { + compatible = "ti,dra7-sdhci"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + pbias-supply = <&pbias_mmc_reg>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; + }; }; target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ @@ -1557,6 +2097,17 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xad000 0x1000>; + + mmc3: mmc@0 { + compatible = "ti,dra7-sdhci"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ + max-frequency = <64000000>; + /* SDMA is not supported */ + sdhci-caps-mask = <0x0 0x400000>; + }; }; target-module@b2000 { /* 0x480b2000, ap 37 52.0 */ @@ -1576,6 +2127,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb2000 0x1000>; + + hdqw1w: 1w@0 { + compatible = "ti,omap3-1w"; + reg = <0x0 0x1000>; + interrupts = ; + }; }; target-module@b4000 { /* 0x480b4000, ap 65 40.0 */ @@ -1600,6 +2157,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb4000 0x1000>; + + mmc2: mmc@0 { + compatible = "ti,dra7-sdhci"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + max-frequency = <192000000>; + /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ + sdhci-caps-mask = <0x7 0x0>; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + mmc-ddr-3_3v; + }; }; target-module@b8000 { /* 0x480b8000, ap 67 48.0 */ @@ -1620,6 +2190,18 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb8000 0x1000>; + + mcspi3: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; + dma-names = "tx0", "rx0"; + status = "disabled"; + }; }; target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ @@ -1640,6 +2222,18 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xba000 0x1000>; + + mcspi4: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <1>; + dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; + dma-names = "tx0", "rx0"; + status = "disabled"; + }; }; target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ @@ -1664,6 +2258,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd1000 0x1000>; + + mmc4: mmc@0 { + compatible = "ti,dra7-sdhci"; + reg = <0x0 0x400>; + interrupts = ; + status = "disabled"; + max-frequency = <192000000>; + /* SDMA is not supported */ + sdhci-caps-mask = <0x0 0x400000>; + }; }; target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ @@ -1783,6 +2387,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; + + uart7: serial@0 { + compatible = "ti,dra742-uart", "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + }; }; target-module@22000 { /* 0x48422000, ap 49 0a.0 */ @@ -1806,6 +2418,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; + + uart8: serial@0 { + compatible = "ti,dra742-uart", "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + }; }; target-module@24000 { /* 0x48424000, ap 51 12.0 */ @@ -1829,6 +2449,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>; + + uart9: serial@0 { + compatible = "ti,dra742-uart", "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + }; }; target-module@2c000 { /* 0x4842c000, ap 7 18.0 */ @@ -1856,11 +2484,24 @@ }; target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x3c000 0x4>; + reg-names = "rev"; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3c000 0x1000>; + + atl: atl@0 { + compatible = "ti,dra7-atl"; + reg = <0x0 0x3ff>; + ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, + <&atl_clkin2_ck>, <&atl_clkin3_ck>; + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; + clock-names = "fck"; + status = "disabled"; + }; }; target-module@3e000 { /* 0x4843e000, ap 25 30.0 */ @@ -1879,6 +2520,35 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; + + epwmss0: epwmss@0 { + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x0 0x30>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0 0 0x1000>; + + ecap0: ecap@100 { + compatible = "ti,dra746-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; + status = "disabled"; + }; + + ehrpwm0: pwm@200 { + compatible = "ti,dra746-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; }; target-module@40000 { /* 0x48440000, ap 27 38.0 */ @@ -1897,6 +2567,35 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x1000>; + + epwmss1: epwmss@0 { + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x0 0x30>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0 0 0x1000>; + + ecap1: ecap@100 { + compatible = "ti,dra746-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; + status = "disabled"; + }; + + ehrpwm1: pwm@200 { + compatible = "ti,dra746-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; }; target-module@42000 { /* 0x48442000, ap 29 20.0 */ @@ -1915,6 +2614,35 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x42000 0x1000>; + + epwmss2: epwmss@0 { + compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; + reg = <0x0 0x30>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges = <0 0 0x1000>; + + ecap2: ecap@100 { + compatible = "ti,dra746-ecap", + "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x100 0x80>; + clocks = <&l4_root_clk_div>; + clock-names = "fck"; + status = "disabled"; + }; + + ehrpwm2: pwm@200 { + compatible = "ti,dra746-ehrpwm", + "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x200 0x80>; + clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + }; }; target-module@46000 { /* 0x48446000, ap 53 40.0 */ @@ -2004,6 +2732,23 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x2000>; + + mcasp1: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x45800000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; + dma-names = "tx", "rx"; + clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>, + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; + status = "disabled"; + }; }; target-module@64000 { /* 0x48464000, ap 11 1e.0 */ @@ -2021,6 +2766,23 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x64000 0x2000>; + + mcasp2: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x45c00000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; + status = "disabled"; + }; }; target-module@68000 { /* 0x48468000, ap 13 26.0 */ @@ -2038,6 +2800,22 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x68000 0x2000>; + + mcasp3: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x46000000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; }; target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ @@ -2055,6 +2833,22 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6c000 0x2000>; + + mcasp4: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x48436000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; }; target-module@70000 { /* 0x48470000, ap 19 36.0 */ @@ -2072,6 +2866,22 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x70000 0x2000>; + + mcasp5: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x4843a000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; }; target-module@74000 { /* 0x48474000, ap 35 14.0 */ @@ -2089,6 +2899,22 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x74000 0x2000>; + + mcasp6: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x4844c000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; }; target-module@78000 { /* 0x48478000, ap 39 0c.0 */ @@ -2106,6 +2932,22 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x78000 0x2000>; + + mcasp7: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x48450000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; }; target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ @@ -2123,22 +2965,123 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x7c000 0x2000>; + + mcasp8: mcasp@0 { + compatible = "ti,dra7-mcasp-audio"; + reg = <0x0 0x2000>, + <0x48454000 0x1000>; /* L3 data port */ + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; + dma-names = "tx", "rx"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; }; target-module@80000 { /* 0x48480000, ap 31 16.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x80000 0x4>; + reg-names = "rev"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x2000>; + + dcan2: can@0 { + compatible = "ti,dra7-d_can"; + reg = <0x0 0x2000>; + syscon-raminit = <&scm_conf 0x558 1>; + interrupts = ; + clocks = <&sys_clkin1>; + status = "disabled"; + }; }; target-module@84000 { /* 0x48484000, ap 3 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + ti,hwmods = "gmac"; + reg = <0x85200 0x4>, + <0x85208 0x4>, + <0x85204 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <0>; + ti,sysc-midle = , + ; + ti,sysc-sidle = , + ; + ti,syss-mask = <1>; + clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x84000 0x4000>; + + mac: ethernet@0 { + compatible = "ti,dra7-cpsw","ti,cpsw"; + clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; + clock-names = "fck", "cpts"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x784CFE14>; + cpts_clock_shift = <29>; + reg = <0x0 0x1000 + 0x1200 0x2e00>; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Do not allow gating of cpsw clock as workaround + * for errata i877. Keeping internal clock disabled + * causes the device switching characteristics + * to degrade over time and eventually fail to meet + * the data manual delay time/skew specs. + */ + ti,no-idle; + + /* + * rx_thresh_pend + * rx_pend + * tx_pend + * misc_pend + */ + interrupts = , + , + , + ; + ranges = <0 0 0x4000>; + syscon = <&scm_conf>; + cpsw-phy-sel = <&phy_sel>; + status = "disabled"; + + davinci_mdio: mdio@1000 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + reg = <0x1000 0x100>; + }; + + cpsw_emac0: slave@200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + cpsw_emac1: slave@300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + }; }; }; }; @@ -2273,6 +3216,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2000 0x1000>; + + mailbox13: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; }; target-module@4000 { /* 0x48804000, ap 81 20.0 */ @@ -2341,6 +3297,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x20000 0x1000>; + + timer5: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@22000 { /* 0x48822000, ap 7 24.0 */ @@ -2361,6 +3325,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x22000 0x1000>; + + timer6: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@24000 { /* 0x48824000, ap 9 26.0 */ @@ -2381,6 +3353,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x24000 0x1000>; + + timer7: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@26000 { /* 0x48826000, ap 11 0c.0 */ @@ -2401,6 +3381,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x26000 0x1000>; + + timer8: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@28000 { /* 0x48828000, ap 13 16.0 */ @@ -2421,6 +3409,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x28000 0x1000>; + + timer13: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@2a000 { /* 0x4882a000, ap 15 10.0 */ @@ -2441,6 +3437,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2a000 0x1000>; + + timer14: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ @@ -2461,6 +3465,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2c000 0x1000>; + + timer15: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ @@ -2481,6 +3493,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2e000 0x1000>; + + timer16: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; }; target-module@38000 { /* 0x48838000, ap 29 12.0 */ @@ -2499,6 +3519,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x38000 0x1000>; + + rtc: rtc@0 { + compatible = "ti,am3352-rtc"; + reg = <0x0 0x100>; + interrupts = , + ; + clocks = <&sys_32k_ck>; + }; }; target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */ @@ -2517,6 +3545,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3a000 0x1000>; + + mailbox2: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; }; target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */ @@ -2535,6 +3576,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3c000 0x1000>; + + mailbox3: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; }; target-module@3e000 { /* 0x4883e000, ap 37 46.0 */ @@ -2553,6 +3607,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3e000 0x1000>; + + mailbox4: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; }; target-module@40000 { /* 0x48840000, ap 39 64.0 */ @@ -2571,6 +3638,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x40000 0x1000>; + + mailbox5: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; }; target-module@42000 { /* 0x48842000, ap 41 4e.0 */ @@ -2589,6 +3669,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x42000 0x1000>; + + mailbox6: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; }; target-module@44000 { /* 0x48844000, ap 43 42.0 */ @@ -2607,6 +3700,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x44000 0x1000>; + + mailbox7: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; }; target-module@46000 { /* 0x48846000, ap 45 48.0 */ @@ -2625,6 +3731,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x46000 0x1000>; + + mailbox8: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; }; target-module@48000 { /* 0x48848000, ap 47 36.0 */ @@ -2731,6 +3850,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x5e000 0x1000>; + + mailbox9: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; }; target-module@60000 { /* 0x48860000, ap 71 4a.0 */ @@ -2749,6 +3881,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x60000 0x1000>; + + mailbox10: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; }; target-module@62000 { /* 0x48862000, ap 73 74.0 */ @@ -2767,6 +3912,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x62000 0x1000>; + + mailbox11: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; }; target-module@64000 { /* 0x48864000, ap 67 52.0 */ @@ -2785,6 +3943,19 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x64000 0x1000>; + + mailbox12: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <12>; + status = "disabled"; + }; }; target-module@80000 { /* 0x48880000, ap 83 0e.1 */ @@ -2808,6 +3979,33 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x20000>; + + omap_dwc3_1: omap_dwc3_1@0 { + compatible = "ti,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges = <0 0 0x20000>; + + usb1: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x17000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + phys = <&usb2_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + }; + }; }; target-module@c0000 { /* 0x488c0000, ap 79 06.0 */ @@ -2831,6 +4029,34 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc0000 0x20000>; + + omap_dwc3_2: omap_dwc3_2@0 { + compatible = "ti,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges = <0 0 0x20000>; + + usb2: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x17000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + phys = <&usb2_phy2>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_metastability_quirk; + }; + }; }; target-module@100000 { /* 0x48900000, ap 85 04.0 */ @@ -2854,6 +4080,32 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x100000 0x20000>; + + omap_dwc3_3: omap_dwc3_3@0 { + compatible = "ti,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges = <0 0 0x20000>; + status = "disabled"; + + usb3: usb@10000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x17000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + }; + }; }; target-module@140000 { /* 0x48940000, ap 75 3c.0 */ @@ -2956,22 +4208,51 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0x0 0x40>; + }; }; target-module@6000 { /* 0x4ae06000, ap 3 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x6000 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6000 0x2000>; + + prm: prm@0 { + compatible = "ti,dra7-prm", "simple-bus"; + reg = <0 0x3000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x3000>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; }; target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xc000 0x4>; + reg-names = "rev"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x1000>; + + scm_wkup: scm_conf@0 { + compatible = "syscon"; + reg = <0 0x1000>; + }; }; }; @@ -3010,6 +4291,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; + + gpio1: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; target-module@4000 { /* 0x4ae14000, ap 7 28.0 */ @@ -3032,6 +4323,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; + + wdt2: wdt@0 { + compatible = "ti,omap3-wdt"; + reg = <0x0 0x80>; + interrupts = ; + }; }; target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ @@ -3052,6 +4349,15 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x8000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-alwon; + }; }; target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ @@ -3100,6 +4406,16 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x1000>; + + timer12: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-alwon; + ti,timer-secure; + }; }; target-module@2000 { /* 0x4ae22000, ap 21 18.0 */ @@ -3144,6 +4460,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xb000 0x1000>; + + uart10: serial@0 { + compatible = "ti,dra742-uart", "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + status = "disabled"; + }; }; target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ @@ -3214,11 +4538,23 @@ }; target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xc000 0x4>; + reg-names = "rev"; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc000 0x2000>; + + dcan1: can@0 { + compatible = "ti,dra7-d_can"; + reg = <0x0 0x2000>; + syscon-raminit = <&scm_conf 0x558 0>; + interrupts = ; + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d140d970672e..2bc9add8b7a5 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -156,153 +156,15 @@ interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - l4_cfg: l4@4a000000 { - compatible = "ti,dra7-l4-cfg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a000000 0x22c000>; - - scm: scm@2000 { - compatible = "ti,dra7-scm-core", "simple-bus"; - reg = <0x2000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x2000>; - - scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x1400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x1400>; - - pbias_regulator: pbias_regulator@e00 { - compatible = "ti,pbias-dra7", "ti,pbias-omap"; - reg = <0xe00 0x4>; - syscon = <&scm_conf>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - - scm_conf_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dra7_pmx_core: pinmux@1400 { - compatible = "ti,dra7-padconf", - "pinctrl-single"; - reg = <0x1400 0x0468>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x3fffffff>; - }; - - scm_conf1: scm_conf@1c04 { - compatible = "syscon"; - reg = <0x1c04 0x0020>; - #syscon-cells = <2>; - }; - - scm_conf_pcie: scm_conf@1c24 { - compatible = "syscon"; - reg = <0x1c24 0x0024>; - }; - - sdma_xbar: dma-router@b78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0xb78 0xfc>; - #dma-cells = <1>; - dma-requests = <205>; - ti,dma-safe-map = <0>; - dma-masters = <&sdma>; - }; - - edma_xbar: dma-router@c78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0xc78 0x7c>; - #dma-cells = <2>; - dma-requests = <204>; - ti,dma-safe-map = <0>; - dma-masters = <&edma>; - }; - }; - - cm_core_aon: cm_core_aon@5000 { - compatible = "ti,dra7-cm-core-aon", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x5000 0x2000>; - ranges = <0 0x5000 0x2000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - - cm_core: cm_core@8000 { - compatible = "ti,dra7-cm-core", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8000 0x3000>; - ranges = <0 0x8000 0x3000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; + l4_cfg: interconnect@4a000000 { }; - - l4_wkup: l4@4ae00000 { - compatible = "ti,dra7-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4ae00000 0x3f000>; - - counter32k: counter@4000 { - compatible = "ti,omap-counter32k"; - reg = <0x4000 0x40>; - ti,hwmods = "counter_32k"; - }; - - prm: prm@6000 { - compatible = "ti,dra7-prm", "simple-bus"; - reg = <0x6000 0x3000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x6000 0x3000>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - - scm_wkup: scm_conf@c000 { - compatible = "syscon"; - reg = <0xc000 0x1000>; - }; + l4_wkup: interconnect@4ae00000 { + }; + l4_per1: interconnect@48000000 { + }; + l4_per2: interconnect@48400000 { + }; + l4_per3: interconnect@48800000 { }; axi@0 { @@ -469,19 +331,6 @@ #pinctrl-cells = <2>; }; - sdma: dma-controller@4a056000 { - compatible = "ti,omap4430-sdma"; - reg = <0x4a056000 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - ti,hwmods = "dma_system"; - }; - edma: edma@43300000 { compatible = "ti,edma3-tpcc"; ti,hwmods = "tpcc"; @@ -521,508 +370,6 @@ interrupt-names = "edma3_tcerrint"; }; - gpio1: gpio@4ae10000 { - compatible = "ti,omap4-gpio"; - reg = <0x4ae10000 0x200>; - interrupts = ; - ti,hwmods = "gpio1"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@48055000 { - compatible = "ti,omap4-gpio"; - reg = <0x48055000 0x200>; - interrupts = ; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@48057000 { - compatible = "ti,omap4-gpio"; - reg = <0x48057000 0x200>; - interrupts = ; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@48059000 { - compatible = "ti,omap4-gpio"; - reg = <0x48059000 0x200>; - interrupts = ; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@4805b000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805b000 0x200>; - interrupts = ; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@4805d000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805d000 0x200>; - interrupts = ; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@48051000 { - compatible = "ti,omap4-gpio"; - reg = <0x48051000 0x200>; - interrupts = ; - ti,hwmods = "gpio7"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio8: gpio@48053000 { - compatible = "ti,omap4-gpio"; - reg = <0x48053000 0x200>; - interrupts = ; - ti,hwmods = "gpio8"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart1: serial@4806a000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x4806a000 0x100>; - interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; - dma-names = "tx", "rx"; - }; - - uart2: serial@4806c000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x4806c000 0x100>; - interrupts = ; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; - dma-names = "tx", "rx"; - }; - - uart3: serial@48020000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x48020000 0x100>; - interrupts = ; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; - dma-names = "tx", "rx"; - }; - - uart4: serial@4806e000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x4806e000 0x100>; - interrupts = ; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; - dma-names = "tx", "rx"; - }; - - uart5: serial@48066000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x48066000 0x100>; - interrupts = ; - ti,hwmods = "uart5"; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; - dma-names = "tx", "rx"; - }; - - uart6: serial@48068000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x48068000 0x100>; - interrupts = ; - ti,hwmods = "uart6"; - clock-frequency = <48000000>; - status = "disabled"; - dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; - dma-names = "tx", "rx"; - }; - - uart7: serial@48420000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x48420000 0x100>; - interrupts = ; - ti,hwmods = "uart7"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart8: serial@48422000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x48422000 0x100>; - interrupts = ; - ti,hwmods = "uart8"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart9: serial@48424000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x48424000 0x100>; - interrupts = ; - ti,hwmods = "uart9"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - uart10: serial@4ae2b000 { - compatible = "ti,dra742-uart", "ti,omap4-uart"; - reg = <0x4ae2b000 0x100>; - interrupts = ; - ti,hwmods = "uart10"; - clock-frequency = <48000000>; - status = "disabled"; - }; - - mailbox1: mailbox@4a0f4000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4a0f4000 0x200>; - interrupts = , - , - ; - ti,hwmods = "mailbox1"; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - status = "disabled"; - }; - - mailbox2: mailbox@4883a000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4883a000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox2"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox3: mailbox@4883c000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4883c000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox3"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox4: mailbox@4883e000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4883e000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox4"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox5: mailbox@48840000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48840000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox5"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox6: mailbox@48842000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48842000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox6"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox7: mailbox@48844000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48844000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox7"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox8: mailbox@48846000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48846000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox8"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox9: mailbox@4885e000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4885e000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox9"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox10: mailbox@48860000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48860000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox10"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox11: mailbox@48862000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48862000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox11"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox12: mailbox@48864000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48864000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox12"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - mailbox13: mailbox@48802000 { - compatible = "ti,omap4-mailbox"; - reg = <0x48802000 0x200>; - interrupts = , - , - , - ; - ti,hwmods = "mailbox13"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - status = "disabled"; - }; - - timer1: timer@4ae18000 { - compatible = "ti,omap5430-timer"; - reg = <0x4ae18000 0x80>; - interrupts = ; - ti,hwmods = "timer1"; - ti,timer-alwon; - clock-names = "fck"; - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; - }; - - timer2: timer@48032000 { - compatible = "ti,omap5430-timer"; - reg = <0x48032000 0x80>; - interrupts = ; - ti,hwmods = "timer2"; - }; - - timer3: timer@48034000 { - compatible = "ti,omap5430-timer"; - reg = <0x48034000 0x80>; - interrupts = ; - ti,hwmods = "timer3"; - }; - - timer4: timer@48036000 { - compatible = "ti,omap5430-timer"; - reg = <0x48036000 0x80>; - interrupts = ; - ti,hwmods = "timer4"; - }; - - timer5: timer@48820000 { - compatible = "ti,omap5430-timer"; - reg = <0x48820000 0x80>; - interrupts = ; - ti,hwmods = "timer5"; - }; - - timer6: timer@48822000 { - compatible = "ti,omap5430-timer"; - reg = <0x48822000 0x80>; - interrupts = ; - ti,hwmods = "timer6"; - }; - - timer7: timer@48824000 { - compatible = "ti,omap5430-timer"; - reg = <0x48824000 0x80>; - interrupts = ; - ti,hwmods = "timer7"; - }; - - timer8: timer@48826000 { - compatible = "ti,omap5430-timer"; - reg = <0x48826000 0x80>; - interrupts = ; - ti,hwmods = "timer8"; - }; - - timer9: timer@4803e000 { - compatible = "ti,omap5430-timer"; - reg = <0x4803e000 0x80>; - interrupts = ; - ti,hwmods = "timer9"; - }; - - timer10: timer@48086000 { - compatible = "ti,omap5430-timer"; - reg = <0x48086000 0x80>; - interrupts = ; - ti,hwmods = "timer10"; - }; - - timer11: timer@48088000 { - compatible = "ti,omap5430-timer"; - reg = <0x48088000 0x80>; - interrupts = ; - ti,hwmods = "timer11"; - }; - - timer12: timer@4ae20000 { - compatible = "ti,omap5430-timer"; - reg = <0x4ae20000 0x80>; - interrupts = ; - ti,hwmods = "timer12"; - ti,timer-alwon; - ti,timer-secure; - }; - - timer13: timer@48828000 { - compatible = "ti,omap5430-timer"; - reg = <0x48828000 0x80>; - interrupts = ; - ti,hwmods = "timer13"; - }; - - timer14: timer@4882a000 { - compatible = "ti,omap5430-timer"; - reg = <0x4882a000 0x80>; - interrupts = ; - ti,hwmods = "timer14"; - }; - - timer15: timer@4882c000 { - compatible = "ti,omap5430-timer"; - reg = <0x4882c000 0x80>; - interrupts = ; - ti,hwmods = "timer15"; - }; - - timer16: timer@4882e000 { - compatible = "ti,omap5430-timer"; - reg = <0x4882e000 0x80>; - interrupts = ; - ti,hwmods = "timer16"; - }; - - wdt2: wdt@4ae14000 { - compatible = "ti,omap3-wdt"; - reg = <0x4ae14000 0x80>; - interrupts = ; - ti,hwmods = "wd_timer2"; - }; - - hwspinlock: spinlock@4a0f6000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x4a0f6000 0x1000>; - ti,hwmods = "spinlock"; - #hwlock-cells = <1>; - }; - dmm@4e000000 { compatible = "ti,omap5-dmm"; reg = <0x4e000000 0x800>; @@ -1030,112 +377,6 @@ ti,hwmods = "dmm"; }; - i2c1: i2c@48070000 { - compatible = "ti,omap4-i2c"; - reg = <0x48070000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - status = "disabled"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap4-i2c"; - reg = <0x48072000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - status = "disabled"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap4-i2c"; - reg = <0x48060000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - status = "disabled"; - }; - - i2c4: i2c@4807a000 { - compatible = "ti,omap4-i2c"; - reg = <0x4807a000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c4"; - status = "disabled"; - }; - - i2c5: i2c@4807c000 { - compatible = "ti,omap4-i2c"; - reg = <0x4807c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c5"; - status = "disabled"; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,dra7-sdhci"; - reg = <0x4809c000 0x400>; - interrupts = ; - ti,hwmods = "mmc1"; - status = "disabled"; - pbias-supply = <&pbias_mmc_reg>; - max-frequency = <192000000>; - mmc-ddr-1_8v; - mmc-ddr-3_3v; - }; - - hdqw1w: 1w@480b2000 { - compatible = "ti,omap3-1w"; - reg = <0x480b2000 0x1000>; - interrupts = ; - ti,hwmods = "hdq1w"; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,dra7-sdhci"; - reg = <0x480b4000 0x400>; - interrupts = ; - ti,hwmods = "mmc2"; - status = "disabled"; - max-frequency = <192000000>; - /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ - sdhci-caps-mask = <0x7 0x0>; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - mmc-ddr-3_3v; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,dra7-sdhci"; - reg = <0x480ad000 0x400>; - interrupts = ; - ti,hwmods = "mmc3"; - status = "disabled"; - /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ - max-frequency = <64000000>; - /* SDMA is not supported */ - sdhci-caps-mask = <0x0 0x400000>; - }; - - mmc4: mmc@480d1000 { - compatible = "ti,dra7-sdhci"; - reg = <0x480d1000 0x400>; - interrupts = ; - ti,hwmods = "mmc4"; - status = "disabled"; - max-frequency = <192000000>; - /* SDMA is not supported */ - sdhci-caps-mask = <0x0 0x400000>; - }; - mmu0_dsp1: mmu@40d01000 { compatible = "ti,dra7-dsp-iommu"; reg = <0x40d01000 0x100>; @@ -1308,69 +549,6 @@ >; }; - mcspi1: spi@48098000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48098000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - dmas = <&sdma_xbar 35>, - <&sdma_xbar 36>, - <&sdma_xbar 37>, - <&sdma_xbar 38>, - <&sdma_xbar 39>, - <&sdma_xbar 40>, - <&sdma_xbar 41>, - <&sdma_xbar 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - status = "disabled"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap4-mcspi"; - reg = <0x4809a000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - dmas = <&sdma_xbar 43>, - <&sdma_xbar 44>, - <&sdma_xbar 45>, - <&sdma_xbar 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - status = "disabled"; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480b8000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; - dma-names = "tx0", "rx0"; - status = "disabled"; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480ba000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; - dma-names = "tx0", "rx0"; - status = "disabled"; - }; - qspi: spi@4b300000 { compatible = "ti,dra7xxx-qspi"; reg = <0x4b300000 0x100>, @@ -1388,69 +566,6 @@ }; /* OCP2SCP3 */ - ocp2scp@4a090000 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0x4a090000 0x20>; - ti,hwmods = "ocp2scp3"; - sata_phy: phy@4a096000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x4A096000 0x80>, /* phy_rx */ - <0x4A096400 0x64>, /* phy_tx */ - <0x4A096800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin1>, - <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; - clock-names = "sysclk", "refclk"; - syscon-pllreset = <&scm_conf 0x3fc>; - #phy-cells = <0>; - }; - - pcie1_phy: pciephy@4a094000 { - compatible = "ti,phy-pipe3-pcie"; - reg = <0x4a094000 0x80>, /* phy_rx */ - <0x4a094400 0x64>; /* phy_tx */ - reg-names = "phy_rx", "phy_tx"; - syscon-phy-power = <&scm_conf_pcie 0x1c>; - syscon-pcs = <&scm_conf_pcie 0x10>; - clocks = <&dpll_pcie_ref_ck>, - <&dpll_pcie_ref_m2ldo_ck>, - <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, - <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, - <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, - <&optfclk_pciephy_div>, - <&sys_clkin1>; - clock-names = "dpll_ref", "dpll_ref_m2", - "wkupclk", "refclk", - "div-clk", "phy-div", "sysclk"; - #phy-cells = <0>; - }; - - pcie2_phy: pciephy@4a095000 { - compatible = "ti,phy-pipe3-pcie"; - reg = <0x4a095000 0x80>, /* phy_rx */ - <0x4a095400 0x64>; /* phy_tx */ - reg-names = "phy_rx", "phy_tx"; - syscon-phy-power = <&scm_conf_pcie 0x20>; - syscon-pcs = <&scm_conf_pcie 0x10>; - clocks = <&dpll_pcie_ref_ck>, - <&dpll_pcie_ref_m2ldo_ck>, - <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, - <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, - <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, - <&optfclk_pciephy_div>, - <&sys_clkin1>; - clock-names = "dpll_ref", "dpll_ref_m2", - "wkupclk", "refclk", - "div-clk", "phy-div", "sysclk"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - sata: sata@4a141100 { compatible = "snps,dwc-ahci"; reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; @@ -1462,192 +577,8 @@ ports-implemented = <0x1>; }; - rtc: rtc@48838000 { - compatible = "ti,am3352-rtc"; - reg = <0x48838000 0x100>; - interrupts = , - ; - ti,hwmods = "rtcss"; - clocks = <&sys_32k_ck>; - }; - /* OCP2SCP1 */ - ocp2scp@4a080000 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0x4a080000 0x20>; - ti,hwmods = "ocp2scp1"; - - usb2_phy1: phy@4a084000 { - compatible = "ti,dra7x-usb2", "ti,omap-usb2"; - reg = <0x4a084000 0x400>; - syscon-phy-power = <&scm_conf 0x300>; - clocks = <&usb_phy1_always_on_clk32k>, - <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; - clock-names = "wkupclk", - "refclk"; - #phy-cells = <0>; - }; - - usb2_phy2: phy@4a085000 { - compatible = "ti,dra7x-usb2-phy2", - "ti,omap-usb2"; - reg = <0x4a085000 0x400>; - syscon-phy-power = <&scm_conf 0xe74>; - clocks = <&usb_phy2_always_on_clk32k>, - <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; - clock-names = "wkupclk", - "refclk"; - #phy-cells = <0>; - }; - - usb3_phy1: phy@4a084400 { - compatible = "ti,omap-usb3"; - reg = <0x4a084400 0x80>, - <0x4a084800 0x64>, - <0x4a084c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x370>; - clocks = <&usb_phy3_always_on_clk32k>, - <&sys_clkin1>, - <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; - clock-names = "wkupclk", - "sysclk", - "refclk"; - #phy-cells = <0>; - }; - }; - - target-module@4a0dd000 { - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_core"; - reg = <0x4a0dd038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a0dd000 0x001000>; - - /* SmartReflex child device marked reserved in TRM */ - }; - - target-module@4a0d9000 { - compatible = "ti,sysc-omap4-sr", "ti,sysc"; - ti,hwmods = "smartreflex_mpu"; - reg = <0x4a0d9038 0x4>; - reg-names = "sysc"; - ti,sysc-mask = ; - ti,sysc-sidle = , - , - , - ; - clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a0d9000 0x001000>; - - /* SmartReflex child device marked reserved in TRM */ - }; - - omap_dwc3_1: omap_dwc3_1@48880000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss1"; - reg = <0x48880000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - usb1: usb@48890000 { - compatible = "snps,dwc3"; - reg = <0x48890000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy1>, <&usb3_phy1>; - phy-names = "usb2-phy", "usb3-phy"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - - omap_dwc3_2: omap_dwc3_2@488c0000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss2"; - reg = <0x488c0000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - usb2: usb@488d0000 { - compatible = "snps,dwc3"; - reg = <0x488d0000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy2>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - snps,dis_metastability_quirk; - }; - }; - /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ - omap_dwc3_3: omap_dwc3_3@48900000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss3"; - reg = <0x48900000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - status = "disabled"; - usb3: usb@48910000 { - compatible = "snps,dwc3"; - reg = <0x48910000 0x17000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - snps,dis_u2_susphy_quirk; - }; - }; - - elm: elm@48078000 { - compatible = "ti,am3352-elm"; - reg = <0x48078000 0xfc0>; /* device IO registers */ - interrupts = ; - ti,hwmods = "elm"; - status = "disabled"; - }; - gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; @@ -1666,154 +597,6 @@ status = "disabled"; }; - atl: atl@4843c000 { - compatible = "ti,dra7-atl"; - reg = <0x4843c000 0x3ff>; - ti,hwmods = "atl"; - ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, - <&atl_clkin2_ck>, <&atl_clkin3_ck>; - clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; - clock-names = "fck"; - status = "disabled"; - }; - - mcasp1: mcasp@48460000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp1"; - reg = <0x48460000 0x2000>, - <0x45800000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; - dma-names = "tx", "rx"; - clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, - <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; - clock-names = "fck", "ahclkx", "ahclkr"; - status = "disabled"; - }; - - mcasp2: mcasp@48464000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp2"; - reg = <0x48464000 0x2000>, - <0x45c00000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; - clock-names = "fck", "ahclkx", "ahclkr"; - status = "disabled"; - }; - - mcasp3: mcasp@48468000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp3"; - reg = <0x48468000 0x2000>, - <0x46000000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - - mcasp4: mcasp@4846c000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp4"; - reg = <0x4846c000 0x2000>, - <0x48436000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - - mcasp5: mcasp@48470000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp5"; - reg = <0x48470000 0x2000>, - <0x4843a000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - - mcasp6: mcasp@48474000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp6"; - reg = <0x48474000 0x2000>, - <0x4844c000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - - mcasp7: mcasp@48478000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp7"; - reg = <0x48478000 0x2000>, - <0x48450000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - - mcasp8: mcasp@4847c000 { - compatible = "ti,dra7-mcasp-audio"; - ti,hwmods = "mcasp8"; - reg = <0x4847c000 0x2000>, - <0x48454000 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; - dma-names = "tx", "rx"; - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>, - <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; - clock-names = "fck", "ahclkx"; - status = "disabled"; - }; - crossbar_mpu: crossbar@4a002a48 { compatible = "ti,irq-crossbar"; reg = <0x4a002a48 0x130>; @@ -1828,93 +611,6 @@ ti,irqs-safe-map = <0>; }; - mac: ethernet@48484000 { - compatible = "ti,dra7-cpsw","ti,cpsw"; - ti,hwmods = "gmac"; - clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x784CFE14>; - cpts_clock_shift = <29>; - reg = <0x48484000 0x1000 - 0x48485200 0x2E00>; - #address-cells = <1>; - #size-cells = <1>; - - /* - * Do not allow gating of cpsw clock as workaround - * for errata i877. Keeping internal clock disabled - * causes the device switching characteristics - * to degrade over time and eventually fail to meet - * the data manual delay time/skew specs. - */ - ti,no-idle; - - /* - * rx_thresh_pend - * rx_pend - * tx_pend - * misc_pend - */ - interrupts = , - , - , - ; - ranges; - syscon = <&scm_conf>; - status = "disabled"; - - davinci_mdio: mdio@48485000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - reg = <0x48485000 0x100>; - }; - - cpsw_emac0: slave@48480200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - cpsw_emac1: slave@48480300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@4a002554 { - compatible = "ti,dra7xx-cpsw-phy-sel"; - reg= <0x4a002554 0x4>; - reg-names = "gmii-sel"; - }; - }; - - dcan1: can@4ae3c000 { - compatible = "ti,dra7-d_can"; - ti,hwmods = "dcan1"; - reg = <0x4ae3c000 0x2000>; - syscon-raminit = <&scm_conf 0x558 0>; - interrupts = ; - clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; - status = "disabled"; - }; - - dcan2: can@48480000 { - compatible = "ti,dra7-d_can"; - ti,hwmods = "dcan2"; - reg = <0x48480000 0x2000>; - syscon-raminit = <&scm_conf 0x558 1>; - interrupts = ; - clocks = <&sys_clkin1>; - status = "disabled"; - }; - dss: dss@58000000 { compatible = "ti,dra7-dss"; /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ @@ -1956,96 +652,6 @@ }; }; - epwmss0: epwmss@4843e000 { - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x4843e000 0x30>; - ti,hwmods = "epwmss0"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges; - - ehrpwm0: pwm@4843e200 { - compatible = "ti,dra746-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x4843e200 0x80>; - clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - ecap0: ecap@4843e100 { - compatible = "ti,dra746-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x4843e100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - epwmss1: epwmss@48440000 { - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x48440000 0x30>; - ti,hwmods = "epwmss1"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges; - - ehrpwm1: pwm@48440200 { - compatible = "ti,dra746-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48440200 0x80>; - clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - ecap1: ecap@48440100 { - compatible = "ti,dra746-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x48440100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; - status = "disabled"; - }; - }; - - epwmss2: epwmss@48442000 { - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; - reg = <0x48442000 0x30>; - ti,hwmods = "epwmss2"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - ranges; - - ehrpwm2: pwm@48442200 { - compatible = "ti,dra746-ehrpwm", - "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x48442200 0x80>; - clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; - clock-names = "tbclk", "fck"; - status = "disabled"; - }; - - ecap2: ecap@48442100 { - compatible = "ti,dra746-ecap", - "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x48442100 0x80>; - clocks = <&l4_root_clk_div>; - clock-names = "fck"; - status = "disabled"; - }; - }; - aes1: aes@4b500000 { compatible = "ti,omap4-aes"; ti,hwmods = "aes1"; @@ -2090,15 +696,6 @@ clock-names = "fck"; }; - rng: rng@48090000 { - compatible = "ti,omap4-rng"; - ti,hwmods = "rng"; - reg = <0x48090000 0x2000>; - interrupts = ; - clocks = <&l3_iclk_div>; - clock-names = "fck"; - }; - opp_supply_mpu: opp-supply@4a003b20 { compatible = "ti,omap5-opp-supply"; reg = <0x4a003b20 0xc>; @@ -2148,8 +745,6 @@ temperature = <120000>; /* milli Celsius */ }; -#include "dra7xx-clocks.dtsi" - &core_crit { temperature = <120000>; /* milli Celsius */ }; @@ -2165,3 +760,6 @@ &iva_crit { temperature = <120000>; /* milli Celsius */ }; + +#include "dra7-l4.dtsi" +#include "dra7xx-clocks.dtsi" -- cgit From ca4b4d373fcc9dc617bb68f4a4f40e1a70ab08a5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 27 Sep 2018 12:47:46 -0300 Subject: ARM: dts: vf610: Add ZII SCU4 AIB board Add support for the ZII SCU 4 board, which has lots of switches and SFF ports. Based on the work from Andrew Lunn. Signed-off-by: Fabio Estevam Reviewed-by: Chris Healy Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/vf610-zii-scu4-aib.dts | 837 +++++++++++++++++++++++++++++++ 2 files changed, 838 insertions(+) create mode 100644 arch/arm/boot/dts/vf610-zii-scu4-aib.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..912c9f52bfe7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -589,6 +589,7 @@ dtb-$(CONFIG_SOC_VF610) += \ vf610-zii-cfu1.dtb \ vf610-zii-dev-rev-b.dtb \ vf610-zii-dev-rev-c.dtb \ + vf610-zii-scu4-aib.dtb \ vf610-zii-ssmb-spu3.dtb dtb-$(CONFIG_ARCH_MXS) += \ imx23-evk.dtb \ diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts new file mode 100644 index 000000000000..52bac1403f70 --- /dev/null +++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts @@ -0,0 +1,837 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright (C) 2016-2018 Zodiac Inflight Innovations + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 SCU4 AIB"; + compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + debug { + label = "zii:green:debug1"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + mdio-mux { + compatible = "mdio-mux-gpio"; + pinctrl-0 = <&pinctrl_mdio_mux>; + pinctrl-names = "default"; + gpios = <&gpio4 4 GPIO_ACTIVE_HIGH + &gpio4 5 GPIO_ACTIVE_HIGH + &gpio3 30 GPIO_ACTIVE_HIGH + &gpio3 31 GPIO_ACTIVE_HIGH>; + mdio-parent-bus = <&mdio1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio_mux_1: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + reg = <0>; + dsa,member = <0 0>; + eeprom-length = <65536>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "aib2main_1"; + }; + + port@2 { + reg = <2>; + label = "aib2main_2"; + }; + + port@3 { + reg = <3>; + label = "eth_cu_1000_5"; + }; + + port@4 { + reg = <4>; + label = "eth_cu_1000_6"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_4"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_7"; + }; + + port@7 { + reg = <7>; + label = "modem_pic"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + switch0port10: port@10 { + reg = <10>; + label = "dsa"; + phy-mode = "xgmii"; + link = <&switch1port10 + &switch3port10 + &switch2port10>; + }; + }; + }; + }; + + mdio_mux_2: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + switch1: switch1@0 { + compatible = "marvell,mv88e6190"; + reg = <0>; + dsa,member = <0 1>; + eeprom-length = <65536>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "eth_cu_1000_3"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_100_2"; + }; + + port@3 { + reg = <3>; + label = "eth_cu_100_3"; + }; + + switch1port9: port@9 { + reg = <9>; + label = "dsa"; + phy-mode = "xgmii"; + link = <&switch3port10 + &switch2port10>; + }; + + switch1port10: port@10 { + reg = <10>; + label = "dsa"; + phy-mode = "xgmii"; + link = <&switch0port10>; + }; + }; + }; + }; + + mdio_mux_4: mdio@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + switch2: switch2@0 { + compatible = "marvell,mv88e6190"; + reg = <0>; + dsa,member = <0 2>; + eeprom-length = <65536>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "internal_j9"; + }; + + port@2 { + reg = <2>; + label = "eth_fc_1000_2"; + phy-mode = "sgmii"; + managed = "in-band-status"; + sfp = <&sff1>; + }; + + port@3 { + reg = <3>; + label = "eth_fc_1000_3"; + phy-mode = "sgmii"; + managed = "in-band-status"; + sfp = <&sff2>; + }; + + port@4 { + reg = <4>; + label = "eth_fc_1000_4"; + phy-mode = "sgmii"; + managed = "in-band-status"; + sfp = <&sff3>; + }; + + port@5 { + reg = <5>; + label = "eth_fc_1000_5"; + phy-mode = "sgmii"; + managed = "in-band-status"; + sfp = <&sff4>; + }; + + port@6 { + reg = <6>; + label = "eth_fc_1000_6"; + phy-mode = "sgmii"; + managed = "in-band-status"; + sfp = <&sff5>; + }; + + port@7 { + reg = <7>; + label = "eth_fc_1000_7"; + phy-mode = "sgmii"; + managed = "in-band-status"; + sfp = <&sff6>; + }; + + port@9 { + reg = <9>; + label = "eth_fc_1000_1"; + phy-mode = "sgmii"; + managed = "in-band-status"; + sfp = <&sff0>; + }; + + switch2port10: port@10 { + reg = <10>; + label = "dsa"; + phy-mode = "2500base-x"; + link = <&switch3port9 + &switch1port9 + &switch0port10>; + }; + }; + }; + }; + + mdio_mux_8: mdio@8 { + reg = <8>; + #address-cells = <1>; + #size-cells = <0>; + + switch3: switch3@0 { + compatible = "marvell,mv88e6190"; + reg = <0>; + dsa,member = <0 3>; + eeprom-length = <65536>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "internal_j8"; + }; + + port@2 { + reg = <2>; + label = "eth_fc_1000_8"; + phy-mode = "sgmii"; + managed = "in-band-status"; + sfp = <&sff7>; + }; + + port@3 { + reg = <3>; + label = "eth_fc_1000_9"; + phy-mode = "sgmii"; + managed = "in-band-status"; + sfp = <&sff8>; + }; + + port@4 { + reg = <4>; + label = "eth_fc_1000_10"; + phy-mode = "sgmii"; + managed = "in-band-status"; + sfp = <&sff9>; + }; + + switch3port9: port@9 { + reg = <9>; + label = "dsa"; + phy-mode = "2500base-x"; + link = <&switch2port10>; + }; + + switch3port10: port@10 { + reg = <10>; + label = "dsa"; + phy-mode = "xgmii"; + link = <&switch1port9 + &switch0port10>; + }; + }; + }; + }; + }; + + sff0: sff0 { + compatible = "sff,sff"; + i2c-bus = <&sff0_i2c>; + los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + }; + + sff1: sff1 { + compatible = "sff,sff"; + i2c-bus = <&sff1_i2c>; + los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + }; + + sff2: sff2 { + compatible = "sff,sff"; + i2c-bus = <&sff2_i2c>; + los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + }; + + sff3: sff3 { + compatible = "sff,sff"; + i2c-bus = <&sff3_i2c>; + los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; + }; + + sff4: sff4 { + compatible = "sff,sff"; + i2c-bus = <&sff4_i2c>; + los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; + }; + + sff5: sff5 { + compatible = "sff,sff"; + i2c-bus = <&sff5_i2c>; + los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>; + }; + + sff6: sff6 { + compatible = "sff,sff"; + i2c-bus = <&sff6_i2c>; + los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; + }; + + sff7: sff7 { + compatible = "sff,sff"; + i2c-bus = <&sff7_i2c>; + los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; + }; + + sff8: sff8 { + compatible = "sff,sff"; + i2c-bus = <&sff8_i2c>; + los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + }; + + sff9: sff9 { + compatible = "sff,sff"; + i2c-bus = <&sff9_i2c>; + los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + }; + + reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partition@0 { + label = "m25p128-0"; + reg = <0x0 0x01000000>; + }; + }; + + spi-flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <50000000>; + + partition@0 { + label = "m25p128-1"; + reg = <0x0 0x01000000>; + }; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + no-sd; + no-sdio; + keep-power-in-suspend; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + no-sdio; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + gpio5: pca9554@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio6: pca9554@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + at24c04@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + }; + + at24c04@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; + + ds1682@6b { + compatible = "dallas,ds1682"; + reg = <0x6b>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + adt7411@4a { + compatible = "adi,adt7411"; + reg = <0x4a>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + gpio9: sx1503q@20 { + compatible = "semtech,sx1503q"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sx1503_20>; + #gpio-cells = <2>; + reg = <0x20>; + gpio-controller; + }; + + lm75@4e { + compatible = "national,lm75"; + reg = <0x4e>; + }; + + lm75@4f { + compatible = "national,lm75"; + reg = <0x4f>; + }; + + gpio7: pca9555@23 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x23>; + }; + + adt7411@4a { + compatible = "adi,adt7411"; + reg = <0x4a>; + }; + + at24c08@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + }; + + tca9548@70 { + compatible = "nxp,pca9548"; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + sff0_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + sff1_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + sff2_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + sff3_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + sff4_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + }; + + tca9548@71 { + compatible = "nxp,pca9548"; + pinctrl-names = "default"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + + sff5_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + sff6_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + sff7_i2c: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + sff8_i2c: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + sff9_i2c: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + linux,rs485-enabled-at-boot-time; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rs485-rts-delay = <0 200>; + status = "okay"; +}; + +&uart2 { + linux,rs485-enabled-at-boot-time; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rs485-rts-delay = <0 200>; + status = "okay"; +}; + +&iomuxc { + pinctrl_dspi0: dspi0grp { + fsl,pins = < + VF610_PAD_PTB19__DSPI0_CS0 0x1182 + VF610_PAD_PTB18__DSPI0_CS1 0x1182 + VF610_PAD_PTB13__DSPI0_CS4 0x1182 + VF610_PAD_PTB12__DSPI0_CS5 0x1182 + VF610_PAD_PTB20__DSPI0_SIN 0x1181 + VF610_PAD_PTB21__DSPI0_SOUT 0x1182 + VF610_PAD_PTB22__DSPI0_SCK 0x1182 + >; + }; + + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_dspi2: dspi2gpio { + fsl,pins = < + VF610_PAD_PTD30__GPIO_64 0x33e2 + VF610_PAD_PTD29__GPIO_65 0x33e1 + VF610_PAD_PTD28__GPIO_66 0x33e2 + VF610_PAD_PTD27__GPIO_67 0x33e2 + VF610_PAD_PTD26__GPIO_68 0x31c2 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + VF610_PAD_PTA22__I2C2_SCL 0x37ff + VF610_PAD_PTA23__I2C2_SDA 0x37ff + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + VF610_PAD_PTA30__I2C3_SCL 0x37ff + VF610_PAD_PTA31__I2C3_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTB26__GPIO_96 0x31c2 + >; + }; + + pinctrl_mdio_mux: pinctrl-mdio-mux { + fsl,pins = < + VF610_PAD_PTE27__GPIO_132 0x31c2 + VF610_PAD_PTE28__GPIO_133 0x31c2 + VF610_PAD_PTE21__GPIO_126 0x31c2 + VF610_PAD_PTE22__GPIO_127 0x31c2 + >; + }; + + pinctrl_qspi0: qspi0grp { + fsl,pins = < + VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 + VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff + VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 + VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 + VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 + VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 + >; + }; + + pinctrl_sx1503_20: pinctrl-sx1503-20 { + fsl,pins = < + VF610_PAD_PTD31__GPIO_63 0x219d + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB23__UART1_TX 0x21a2 + VF610_PAD_PTB24__UART1_RX 0x21a1 + VF610_PAD_PTB25__UART1_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + VF610_PAD_PTD2__UART2_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ + >; + }; +}; -- cgit From 918c9752fb274fde21445de48c22df7515941f7a Mon Sep 17 00:00:00 2001 From: Markus Kueffner Date: Wed, 10 Oct 2018 08:32:09 +0200 Subject: ARM: dts: imx6qdl-udoo: Add Pincfgs for UART4 Add Pincfgs for UART4 to enable Communication with the onboard SAM3X Signed-off-by: Markus Kueffner Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-udoo.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi index 4f27861bbb32..40d1b0d9faff 100644 --- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi @@ -195,6 +195,13 @@ >; }; + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + pinctrl_usbh: usbhgrp { fsl,pins = < MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 @@ -265,6 +272,12 @@ status = "okay"; }; +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh>; -- cgit From a67d2c52a82ff9d6037bf4e6cc5d42e2ccd4cf1d Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 9 Oct 2018 12:50:28 +0200 Subject: ARM: dts: Add support for Liebherr's BK4 device (vf610 based) This commit adds DTS support for BK4 device from Liebherr. It uses vf610 SoC from NXP. Signed-off-by: Lukasz Majewski Reviewed-by: Stefan Agner Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/vf610-bk4.dts | 501 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 502 insertions(+) create mode 100644 arch/arm/boot/dts/vf610-bk4.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 912c9f52bfe7..ef9ffa44d705 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -581,6 +581,7 @@ dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-twr.dtb dtb-$(CONFIG_SOC_VF610) += \ vf500-colibri-eval-v3.dtb \ + vf610-bk4.dtb \ vf610-colibri-eval-v3.dtb \ vf610m4-colibri.dtb \ vf610-cosmic.dtb \ diff --git a/arch/arm/boot/dts/vf610-bk4.dts b/arch/arm/boot/dts/vf610-bk4.dts new file mode 100644 index 000000000000..cab95714c058 --- /dev/null +++ b/arch/arm/boot/dts/vf610-bk4.dts @@ -0,0 +1,501 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "Liebherr BK4 controller"; + compatible = "lwn,bk4", "fsl,vf610"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + reg = <0x80000000 0x8000000>; + }; + + audio_ext: oscillator-audio { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + enet_ext: oscillator-ethernet { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + /* LED D5 */ + led0: heartbeat { + label = "heartbeat"; + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vcc_3v3_mcu: regulator-vcc3v3mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&clks { + clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; + clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; +}; + +&dspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi0>; + bus-num = <0>; + status = "okay"; + + spidev0@0 { + compatible = "lwn,bk4"; + spi-max-frequency = <30000000>; + reg = <0>; + fsl,spi-cs-sck-delay = <200>; + fsl,spi-sck-cs-delay = <400>; + }; +}; + +&dspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi3>; + bus-num = <3>; + status = "okay"; + spi-slave; + + slave@0 { + compatible = "lwn,bk4"; + spi-max-frequency = <30000000>; + reg = <0>; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec0 { + phy-mode = "rmii"; + phy-handle = <ðphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + reg = <1>; + clocks = <&clks VF610_CLK_ENET_50M>; + clock-names = "rmii-ref"; + }; + }; +}; + +&fec1 { + phy-mode = "rmii"; + phy-handle = <ðphy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + clocks = <&clks VF610_CLK_ENET_50M>; + clock-names = "rmii-ref"; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + at24c256: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + + m41t62: rtc@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; + +&nfc { + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <33000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + status = "okay"; + + nand@0 { + compatible = "fsl,vf610-nfc-nandcs"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <16>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <24>; + nand-ecc-step-size = <2048>; + nand-on-flash-bbt; + }; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + status = "okay"; + + n25q128a13_4: flash@0 { + compatible = "n25q128a13", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + reg = <0>; + }; + + n25q128a13_2: flash@1 { + compatible = "n25q128a13", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <2>; + reg = <1>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbdev0 { + disable-over-current; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbmisc0 { + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* One_Wire_PSU_EN */ + VF610_PAD_PTC29__GPIO_102 0x1183 + /* SPI ENABLE */ + VF610_PAD_PTB26__GPIO_96 0x1183 + /* EB control */ + VF610_PAD_PTE14__GPIO_119 0x1183 + VF610_PAD_PTE4__GPIO_109 0x1181 + /* Feedback_Lines */ + VF610_PAD_PTC31__GPIO_104 0x1181 + VF610_PAD_PTA7__GPIO_134 0x1181 + VF610_PAD_PTD9__GPIO_88 0x1181 + VF610_PAD_PTE1__GPIO_106 0x1183 + VF610_PAD_PTB2__GPIO_24 0x1181 + VF610_PAD_PTB3__GPIO_25 0x1181 + VF610_PAD_PTB1__GPIO_23 0x1181 + /* SDHC Enable */ + VF610_PAD_PTE19__GPIO_124 0x1183 + /* SDHC Overcurrent */ + VF610_PAD_PTB23__GPIO_93 0x1181 + /* GPI */ + VF610_PAD_PTE2__GPIO_107 0x1181 + VF610_PAD_PTE3__GPIO_108 0x1181 + VF610_PAD_PTE5__GPIO_110 0x1181 + VF610_PAD_PTE6__GPIO_111 0x1181 + /* GPO */ + VF610_PAD_PTE0__GPIO_105 0x1183 + VF610_PAD_PTE7__GPIO_112 0x1183 + /* RS485 Control */ + VF610_PAD_PTB8__GPIO_30 0x1183 + VF610_PAD_PTB9__GPIO_31 0x1183 + VF610_PAD_PTE8__GPIO_113 0x1183 + /* MPBUS MPB_EN */ + VF610_PAD_PTE28__GPIO_133 0x1183 + /* MISC */ + VF610_PAD_PTE10__GPIO_115 0x1183 + VF610_PAD_PTE11__GPIO_116 0x1183 + VF610_PAD_PTE17__GPIO_122 0x1183 + VF610_PAD_PTC30__GPIO_103 0x1183 + VF610_PAD_PTB0__GPIO_22 0x1181 + /* RESETINFO */ + VF610_PAD_PTE26__GPIO_131 0x1183 + VF610_PAD_PTD6__GPIO_85 0x1181 + VF610_PAD_PTE27__GPIO_132 0x1181 + VF610_PAD_PTE13__GPIO_118 0x1181 + VF610_PAD_PTE21__GPIO_126 0x1181 + VF610_PAD_PTE22__GPIO_127 0x1181 + /* EE_5V_EN */ + VF610_PAD_PTE18__GPIO_123 0x1183 + /* EE_5V_OC_N */ + VF610_PAD_PTE25__GPIO_130 0x1181 + >; + }; + + pinctrl_can0: can0grp { + fsl,pins = < + VF610_PAD_PTB14__CAN0_RX 0x1181 + VF610_PAD_PTB15__CAN0_TX 0x1182 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + VF610_PAD_PTB16__CAN1_RX 0x1181 + VF610_PAD_PTB17__CAN1_TX 0x1182 + >; + }; + + pinctrl_dspi0: dspi0grp { + fsl,pins = < + VF610_PAD_PTB18__DSPI0_CS1 0x1182 + VF610_PAD_PTB19__DSPI0_CS0 0x1182 + VF610_PAD_PTB20__DSPI0_SIN 0x1181 + VF610_PAD_PTB21__DSPI0_SOUT 0x1182 + VF610_PAD_PTB22__DSPI0_SCK 0x1182 + >; + }; + + pinctrl_dspi3: dspi3grp { + fsl,pins = < + VF610_PAD_PTD10__DSPI3_CS0 0x1181 + VF610_PAD_PTD11__DSPI3_SIN 0x1181 + VF610_PAD_PTD12__DSPI3_SOUT 0x1182 + VF610_PAD_PTD13__DSPI3_SCK 0x1181 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_fec0: fec0grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30dd + VF610_PAD_PTC0__ENET_RMII0_MDC 0x30de + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df + VF610_PAD_PTC2__ENET_RMII0_CRS 0x30dd + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30dd + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30dd + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30dd + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30de + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30de + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30de + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + /* Heart bit LED */ + VF610_PAD_PTE12__GPIO_117 0x1183 + /* LEDS */ + VF610_PAD_PTE15__GPIO_120 0x1183 + VF610_PAD_PTA12__GPIO_5 0x1183 + VF610_PAD_PTA16__GPIO_6 0x1183 + VF610_PAD_PTE9__GPIO_114 0x1183 + VF610_PAD_PTE20__GPIO_125 0x1183 + VF610_PAD_PTE23__GPIO_128 0x1183 + VF610_PAD_PTE16__GPIO_121 0x1183 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + VF610_PAD_PTA22__I2C2_SCL 0x34df + VF610_PAD_PTA23__I2C2_SDA 0x34df + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + VF610_PAD_PTD23__NF_IO7 0x28df + VF610_PAD_PTD22__NF_IO6 0x28df + VF610_PAD_PTD21__NF_IO5 0x28df + VF610_PAD_PTD20__NF_IO4 0x28df + VF610_PAD_PTD19__NF_IO3 0x28df + VF610_PAD_PTD18__NF_IO2 0x28df + VF610_PAD_PTD17__NF_IO1 0x28df + VF610_PAD_PTD16__NF_IO0 0x28df + VF610_PAD_PTB24__NF_WE_B 0x28c2 + VF610_PAD_PTB25__NF_CE0_B 0x28c2 + VF610_PAD_PTB27__NF_RE_B 0x28c2 + VF610_PAD_PTC26__NF_RB_B 0x283d + VF610_PAD_PTC27__NF_ALE 0x28c2 + VF610_PAD_PTC28__NF_CLE 0x28c2 + >; + }; + + pinctrl_qspi0: qspi0grp { + fsl,pins = < + VF610_PAD_PTD0__QSPI0_A_QSCK 0x397f + VF610_PAD_PTD1__QSPI0_A_CS0 0x397f + VF610_PAD_PTD2__QSPI0_A_DATA3 0x397f + VF610_PAD_PTD3__QSPI0_A_DATA2 0x397f + VF610_PAD_PTD4__QSPI0_A_DATA1 0x397f + VF610_PAD_PTD5__QSPI0_A_DATA0 0x397f + VF610_PAD_PTD7__QSPI0_B_QSCK 0x397f + VF610_PAD_PTD8__QSPI0_B_CS0 0x397f + VF610_PAD_PTD11__QSPI0_B_DATA1 0x397f + VF610_PAD_PTD12__QSPI0_B_DATA0 0x397f + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB4__UART1_TX 0x21a2 + VF610_PAD_PTB5__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTB6__UART2_TX 0x21a2 + VF610_PAD_PTB7__UART2_RX 0x21a1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + VF610_PAD_PTA20__UART3_TX 0x21a2 + VF610_PAD_PTA21__UART3_RX 0x21a1 + >; + }; +}; -- cgit From c8c23423cc98f56519d7aa6c063603a646850c5c Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Wed, 17 Oct 2018 12:37:54 +0000 Subject: ARM: dts: imx6ull: Add dcp node The DCP block on 6ull has no major differences other than requiring explicit clock enabling. Signed-off-by: Leonard Crestez Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index 796ed35d4ac9..f3668fe69eac 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -39,6 +39,16 @@ reg = <0x02200000 0x100000>; ranges; + dcp: crypto@2280000 { + compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp"; + reg = <0x02280000 0x4000>; + interrupts = , + , + ; + clocks = <&clks IMX6ULL_CLK_DCP_CLK>; + clock-names = "dcp"; + }; + iomuxc_snvs: iomuxc-snvs@2290000 { compatible = "fsl,imx6ull-iomuxc-snvs"; reg = <0x02290000 0x4000>; -- cgit From 3aca6e4e6e512b4d7c0fddd1b99955f9aa55c89a Mon Sep 17 00:00:00 2001 From: Shyam Saini Date: Thu, 18 Oct 2018 20:33:05 +0530 Subject: ARM: dts: imx6qdl-icore: Add missing stdout-path property This would help us to get early boot logs by passing "earlycon" to kernel bootargs. Further, by adding this we don't have to depend on complex earlyprintk configs for early boot logs. Reviewed-by: Fabio Estevam Signed-off-by: Shyam Saini Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-icore.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi index 84d03c65f4c8..aaed37c73c29 100644 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -13,6 +13,10 @@ reg = <0x10000000 0x80000000>; }; + chosen { + stdout-path = &uart4; + }; + backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; pwms = <&pwm3 0 100000>; -- cgit From 46f3b54de80958f0246ffcb37a19fd3bf6c8cd04 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Wed, 24 Oct 2018 10:25:12 +0000 Subject: ARM: dts: imx6qdl-sabreauto: Remove reg property from fixed regulator Drop reg property from fixed regulator and remove the unncessary bus node. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 53 +++++++++++++------------------- 1 file changed, 22 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index a6dc5c42c632..a10f0ad0bfb1 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -75,39 +75,30 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_audio: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "cs42888_supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb_h1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound-cs42888 { -- cgit From d548c217c6a3cdc6aeb6c8e3457cca2aad5e5738 Mon Sep 17 00:00:00 2001 From: Vabhav Sharma Date: Mon, 29 Oct 2018 08:57:54 +0000 Subject: arm64: dts: add QorIQ LX2160A SoC support LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture. LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA UARTs etc. Signed-off-by: Ramneek Mehresh Signed-off-by: Zhang Ying-22455 Signed-off-by: Nipun Gupta Signed-off-by: Priyanka Jain Signed-off-by: Yogesh Gaur Signed-off-by: Sriram Dash Signed-off-by: Vabhav Sharma Signed-off-by: Horia Geanta Signed-off-by: Ran Wang Signed-off-by: Yinbo Zhu Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 766 +++++++++++++++++++++++++ 1 file changed, 766 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi new file mode 100644 index 000000000000..a79f5c1ea56d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -0,0 +1,766 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree Include file for Layerscape-LX2160A family SoC. +// +// Copyright 2018 NXP + +#include +#include + +/memreserve/ 0x80000000 0x00010000; + +/ { + compatible = "fsl,lx2160a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + // 8 clusters having 2 Cortex-A72 cores each + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x0>; + clocks = <&clockgen 1 0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster0_l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x1>; + clocks = <&clockgen 1 0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster0_l2>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x100>; + clocks = <&clockgen 1 1>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster1_l2>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x101>; + clocks = <&clockgen 1 1>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster1_l2>; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x200>; + clocks = <&clockgen 1 2>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster2_l2>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x201>; + clocks = <&clockgen 1 2>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster2_l2>; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x300>; + clocks = <&clockgen 1 3>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster3_l2>; + }; + + cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x301>; + clocks = <&clockgen 1 3>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster3_l2>; + }; + + cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x400>; + clocks = <&clockgen 1 4>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster4_l2>; + }; + + cpu@401 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x401>; + clocks = <&clockgen 1 4>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster4_l2>; + }; + + cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x500>; + clocks = <&clockgen 1 5>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster5_l2>; + }; + + cpu@501 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x501>; + clocks = <&clockgen 1 5>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster5_l2>; + }; + + cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x600>; + clocks = <&clockgen 1 6>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster6_l2>; + }; + + cpu@601 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x601>; + clocks = <&clockgen 1 6>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster6_l2>; + }; + + cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x700>; + clocks = <&clockgen 1 7>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster7_l2>; + }; + + cpu@701 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x701>; + clocks = <&clockgen 1 7>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <192>; + next-level-cache = <&cluster7_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster2_l2: l2-cache2 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster3_l2: l2-cache3 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster4_l2: l2-cache4 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster5_l2: l2-cache5 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster6_l2: l2-cache6 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + + cluster7_l2: l2-cache7 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + }; + + gic: interrupt-controller@6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, // GIC Dist + <0x0 0x06200000 0 0x200000>, // GICR (RD_base + + // SGI_base) + <0x0 0x0c0c0000 0 0x2000>, // GICC + <0x0 0x0c0d0000 0 0x1000>, // GICH + <0x0 0x0c0e0000 0 0x20000>; // GICV + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + interrupts = ; + + its: gic-its@6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x6020000 0 0x20000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + memory@80000000 { + // DRAM space - 1, size : 2 GB DRAM + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + }; + + ddr1: memory-controller@1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = ; + little-endian; + }; + + ddr2: memory-controller@1090000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1090000 0x0 0x1000>; + interrupts = ; + little-endian; + }; + + // One clock unit-sysclk node which bootloader require during DT fix-up + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; // fixed up by bootloader + clock-output-names = "sysclk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = ; + dma-coherent; + status = "disabled"; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = ; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = ; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + }; + }; + + clockgen: clock-controller@1300000 { + compatible = "fsl,lx2160a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + dcfg: syscon@1e00000 { + compatible = "fsl,lx2160a-dcfg", "syscon"; + reg = <0x0 0x1e00000 0x0 0x10000>; + little-endian; + }; + + i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + status = "disabled"; + }; + + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + status = "disabled"; + }; + + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + status = "disabled"; + }; + + i2c4: i2c@2040000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2040000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + i2c5: i2c@2050000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2050000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + status = "disabled"; + }; + + i2c6: i2c@2060000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2060000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + status = "disabled"; + }; + + i2c7: i2c@2070000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2070000 0x0 0x10000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&clockgen 4 7>; + status = "disabled"; + }; + + esdhc0: esdhc@2140000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clocks = <&clockgen 4 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width = <4>; + status = "disabled"; + }; + + esdhc1: esdhc@2150000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2150000 0x0 0x10000>; + interrupts = <0 63 0x4>; /* Level high type */ + clocks = <&clockgen 4 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + broken-cd; + little-endian; + bus-width = <4>; + status = "disabled"; + }; + + uart0: serial@21c0000 { + compatible = "arm,sbsa-uart","arm,pl011"; + reg = <0x0 0x21c0000 0x0 0x1000>; + interrupts = ; + current-speed = <115200>; + status = "disabled"; + }; + + uart1: serial@21d0000 { + compatible = "arm,sbsa-uart","arm,pl011"; + reg = <0x0 0x21d0000 0x0 0x1000>; + interrupts = ; + current-speed = <115200>; + status = "disabled"; + }; + + uart2: serial@21e0000 { + compatible = "arm,sbsa-uart","arm,pl011"; + reg = <0x0 0x21e0000 0x0 0x1000>; + interrupts = ; + current-speed = <115200>; + status = "disabled"; + }; + + uart3: serial@21f0000 { + compatible = "arm,sbsa-uart","arm,pl011"; + reg = <0x0 0x21f0000 0x0 0x1000>; + interrupts = ; + current-speed = <115200>; + status = "disabled"; + }; + + gpio0: gpio@2300000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = ; + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = ; + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = ; + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = ; + gpio-controller; + little-endian; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + watchdog@23a0000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x23a0000 0 0x1000>, + <0x0 0x2390000 0 0x1000>; + interrupts = ; + timeout-sec = <30>; + }; + + usb0: usb@3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = ; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + + usb1: usb@3110000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = ; + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + + smmu: iommu@5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #iommu-cells = <1>; + #global-interrupts = <14>; + // global secure fault + interrupts = , + // combined secure + , + // global non-secure fault + , + // combined non-secure + , + // performance counter interrupts 0-9 + , + , + , + , + , + , + , + , + , + , + // per context interrupt, 64 interrupts + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-coherent; + }; + }; +}; -- cgit From b068890c34dda4c2a7dd87fa0d291020da0e67f3 Mon Sep 17 00:00:00 2001 From: Vabhav Sharma Date: Mon, 29 Oct 2018 08:58:01 +0000 Subject: arm64: dts: add LX2160ARDB board support LX2160A reference design board (RDB) is a high-performance computing, evaluation, and development platform with LX2160A SoC. Signed-off-by: Priyanka Jain Signed-off-by: Sriram Dash Signed-off-by: Vabhav Sharma Signed-off-by: Horia Geanta Signed-off-by: Ran Wang Signed-off-by: Zhang Ying-22455 Signed-off-by: Yinbo Zhu Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 119 ++++++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 86e18adb695a..445b72bd5a36 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts new file mode 100644 index 000000000000..6481e5f20e69 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2160ARDB +// +// Copyright 2018 NXP + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" + +/ { + model = "NXP Layerscape LX2160ARDB"; + compatible = "fsl,lx2160a-rdb", "fsl,lx2160a"; + + aliases { + crypto = &crypto; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sb_3v3: regulator-sb3v3 { + compatible = "regulator-fixed"; + regulator-name = "MC34717-3.3VSB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&crypto { + status = "okay"; +}; + +&esdhc0 { + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; + status = "okay"; +}; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + power-monitor@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + vcc-supply = <&sb_3v3>; + }; + + temperature-sensor@4d { + compatible = "nxp,sa56004"; + reg = <0x4d>; + vcc-supply = <&sb_3v3>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + // IRQ10_B + interrupts = <0 150 0x4>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; -- cgit From fa86cfe89748abb8558d24c2d16203d1cb02a5a1 Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Wed, 17 Oct 2018 10:32:45 +0000 Subject: arm64: dts: add LX2160AQDS board support The LX2160A QorIQ Development System (QDS) is a test, evaluation, and development platform, supporting QorIQ LX2160A processor. Signed-off-by: Sriram Dash Signed-off-by: Pankaj Bansal Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 112 ++++++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 445b72bd5a36..46b1479b7a6b 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -13,4 +13,5 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts new file mode 100644 index 000000000000..99a22abbe725 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2160AQDS +// +// Copyright 2018 NXP + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS"; + compatible = "fsl,lx2160a-qds", "fsl,lx2160a"; + + aliases { + crypto = &crypto; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sb_3v3: regulator-sb3v3 { + compatible = "regulator-fixed"; + regulator-name = "MC34717-3.3VSB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&crypto { + status = "okay"; +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + power-monitor@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <500>; + }; + + power-monitor@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + vcc-supply = <&sb_3v3>; + }; + + temperature-sensor@4d { + compatible = "nxp,sa56004"; + reg = <0x4d>; + vcc-supply = <&sb_3v3>; + }; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; -- cgit From 39db0e136b23b3c2318714013e97f6093e38229d Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 31 Aug 2018 15:53:18 +0800 Subject: ARM: dts: imx6: add mmdc ipg clock i.MX6 SoCs has MMDC clock gates in CCM CCGR, add clock property for MMDC driver's clock operation. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 1 + arch/arm/boot/dts/imx6sl.dtsi | 1 + arch/arm/boot/dts/imx6sll.dtsi | 1 + arch/arm/boot/dts/imx6sx.dtsi | 1 + arch/arm/boot/dts/imx6ul.dtsi | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index e4daf150881a..f782dc020f5b 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1115,6 +1115,7 @@ mmdc0: mmdc@21b0000 { /* MMDC0 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; }; mmdc1: mmdc@21b4000 { /* MMDC1 */ diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 7a3ae7160c12..9bbc5b0adf85 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -921,6 +921,7 @@ mmdc: mmdc@21b0000 { compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>; }; rngb: rngb@21b4000 { diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index ed9a980bce85..e462f76a1c01 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -770,6 +770,7 @@ mmdc: memory-controller@21b0000 { compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>; }; ocotp: ocotp-ctrl@21bc000 { diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 95a3c1cb877d..84b7687b2d31 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -1002,6 +1002,7 @@ mmdc: mmdc@21b0000 { compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; }; fec2: ethernet@21b4000 { diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 083d3446c41d..c71d2d648c2e 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -917,6 +917,7 @@ mmdc: mmdc@21b0000 { compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; }; weim: weim@21b8000 { -- cgit From 1a9e779679a0e175462d8c3ce4aeea8da120af5b Mon Sep 17 00:00:00 2001 From: Suzuki K Poulose Date: Wed, 12 Sep 2018 14:53:45 +0100 Subject: arm64: dts: sc9836/sc9860: Update coresight bindings for hardware ports Switch to the new coresight bindings for hw ports Cc: orsonzhai@gmail.com Cc: zhang.lyra@gmail.com Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Chunyan Zhang --- arch/arm64/boot/dts/sprd/sc9836.dtsi | 78 +++++++------ arch/arm64/boot/dts/sprd/sc9860.dtsi | 215 ++++++++++++++++++----------------- 2 files changed, 151 insertions(+), 142 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi index 63894c456969..4bcdbb709c01 100644 --- a/arch/arm64/boot/dts/sprd/sc9836.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9836.dtsi @@ -50,10 +50,11 @@ reg = <0 0x10003000 0 0x1000>; clocks = <&clk26mhz>; clock-names = "apb_pclk"; - port { - etf_in: endpoint { - slave-mode; - remote-endpoint = <&funnel_out_port0>; + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&funnel_out_port0>; + }; }; }; }; @@ -63,55 +64,50 @@ reg = <0 0x10001000 0 0x1000>; clocks = <&clk26mhz>; clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - /* funnel output port */ - port@0 { - reg = <0>; + out-ports { + port { funnel_out_port0: endpoint { remote-endpoint = <&etf_in>; }; }; + }; - /* funnel input port 0-4 */ - port@1 { + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { reg = <0>; funnel_in_port0: endpoint { - slave-mode; remote-endpoint = <&etm0_out>; }; }; - port@2 { + port@1 { reg = <1>; funnel_in_port1: endpoint { - slave-mode; remote-endpoint = <&etm1_out>; }; }; - port@3 { + port@2 { reg = <2>; funnel_in_port2: endpoint { - slave-mode; remote-endpoint = <&etm2_out>; }; }; - port@4 { + port@3 { reg = <3>; funnel_in_port3: endpoint { - slave-mode; remote-endpoint = <&etm3_out>; }; }; - port@5 { + port@4 { reg = <4>; funnel_in_port4: endpoint { - slave-mode; remote-endpoint = <&stm_out>; }; }; @@ -126,9 +122,11 @@ cpu = <&cpu0>; clocks = <&clk26mhz>; clock-names = "apb_pclk"; - port { - etm0_out: endpoint { - remote-endpoint = <&funnel_in_port0>; + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; }; }; }; @@ -140,9 +138,11 @@ cpu = <&cpu1>; clocks = <&clk26mhz>; clock-names = "apb_pclk"; - port { - etm1_out: endpoint { - remote-endpoint = <&funnel_in_port1>; + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; }; }; }; @@ -154,9 +154,11 @@ cpu = <&cpu2>; clocks = <&clk26mhz>; clock-names = "apb_pclk"; - port { - etm2_out: endpoint { - remote-endpoint = <&funnel_in_port2>; + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&funnel_in_port2>; + }; }; }; }; @@ -168,9 +170,11 @@ cpu = <&cpu3>; clocks = <&clk26mhz>; clock-names = "apb_pclk"; - port { - etm3_out: endpoint { - remote-endpoint = <&funnel_in_port3>; + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&funnel_in_port3>; + }; }; }; }; @@ -182,9 +186,11 @@ reg-names = "stm-base", "stm-stimulus-base"; clocks = <&clk26mhz>; clock-names = "apb_pclk"; - port { - stm_out: endpoint { - remote-endpoint = <&funnel_in_port4>; + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel_in_port4>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index 48f5928ed45c..5f57bf055cde 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -304,30 +304,29 @@ reg = <0 0x10001000 0 0x1000>; clocks = <&ext_26m>; clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; + out-ports { + port { soc_funnel_out_port: endpoint { remote-endpoint = <&etb_in>; }; }; + }; - port@1 { + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { reg = <0>; soc_funnel_in_port0: endpoint { - slave-mode; remote-endpoint = <&main_funnel_out_port>; }; }; - port@2 { + port@4 { reg = <4>; soc_funnel_in_port1: endpoint { - slave-mode; remote-endpoint = <&stm_out_port>; }; @@ -340,11 +339,12 @@ reg = <0 0x10003000 0 0x1000>; clocks = <&ext_26m>; clock-names = "apb_pclk"; - port { - etb_in: endpoint { - slave-mode; - remote-endpoint = - <&soc_funnel_out_port>; + out-ports { + port { + etb_in: endpoint { + remote-endpoint = + <&soc_funnel_out_port>; + }; }; }; }; @@ -356,10 +356,12 @@ reg-names = "stm-base", "stm-stimulus-base"; clocks = <&ext_26m>; clock-names = "apb_pclk"; - port { - stm_out_port: endpoint { - remote-endpoint = - <&soc_funnel_in_port1>; + out-ports { + port { + stm_out_port: endpoint { + remote-endpoint = + <&soc_funnel_in_port1>; + }; }; }; }; @@ -369,38 +371,36 @@ reg = <0 0x11001000 0 0x1000>; clocks = <&ext_26m>; clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; + out-ports { + port { cluster0_funnel_out_port: endpoint { remote-endpoint = <&cluster0_etf_in>; }; }; + }; - port@1 { + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { reg = <0>; cluster0_funnel_in_port0: endpoint { - slave-mode; remote-endpoint = <&etm0_out>; }; }; - port@2 { + port@1 { reg = <1>; cluster0_funnel_in_port1: endpoint { - slave-mode; remote-endpoint = <&etm1_out>; }; }; - port@3 { + port@2 { reg = <2>; cluster0_funnel_in_port2: endpoint { - slave-mode; remote-endpoint = <&etm2_out>; }; }; @@ -408,7 +408,6 @@ port@4 { reg = <4>; cluster0_funnel_in_port3: endpoint { - slave-mode; remote-endpoint = <&etm3_out>; }; }; @@ -420,46 +419,43 @@ reg = <0 0x11002000 0 0x1000>; clocks = <&ext_26m>; clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; + out-ports { + port { cluster1_funnel_out_port: endpoint { remote-endpoint = <&cluster1_etf_in>; }; }; + }; - port@1 { + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { reg = <0>; cluster1_funnel_in_port0: endpoint { - slave-mode; remote-endpoint = <&etm4_out>; }; }; - port@2 { + port@1 { reg = <1>; cluster1_funnel_in_port1: endpoint { - slave-mode; remote-endpoint = <&etm5_out>; }; }; - port@3 { + port@2 { reg = <2>; cluster1_funnel_in_port2: endpoint { - slave-mode; remote-endpoint = <&etm6_out>; }; }; - port@4 { + port@3 { reg = <3>; cluster1_funnel_in_port3: endpoint { - slave-mode; remote-endpoint = <&etm7_out>; }; }; @@ -472,22 +468,18 @@ clocks = <&ext_26m>; clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; + out-ports { + port { cluster0_etf_out: endpoint { remote-endpoint = <&main_funnel_in_port0>; }; }; + }; - port@1 { - reg = <0>; + in-ports { + port { cluster0_etf_in: endpoint { - slave-mode; remote-endpoint = <&cluster0_funnel_out_port>; }; @@ -501,22 +493,18 @@ clocks = <&ext_26m>; clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; + out-ports { + port { cluster1_etf_out: endpoint { remote-endpoint = <&main_funnel_in_port1>; }; }; + }; - port@1 { - reg = <0>; + in-ports { + port { cluster1_etf_in: endpoint { - slave-mode; remote-endpoint = <&cluster1_funnel_out_port>; }; @@ -530,31 +518,30 @@ clocks = <&ext_26m>; clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; + out-ports { + port { main_funnel_out_port: endpoint { remote-endpoint = <&soc_funnel_in_port0>; }; }; + }; - port@1 { + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { reg = <0>; main_funnel_in_port0: endpoint { - slave-mode; remote-endpoint = <&cluster0_etf_out>; }; }; - port@2 { + port@1 { reg = <1>; main_funnel_in_port1: endpoint { - slave-mode; remote-endpoint = <&cluster1_etf_out>; }; @@ -569,10 +556,12 @@ clocks = <&ext_26m>; clock-names = "apb_pclk"; - port { - etm0_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in_port0>; + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&cluster0_funnel_in_port0>; + }; }; }; }; @@ -584,10 +573,12 @@ clocks = <&ext_26m>; clock-names = "apb_pclk"; - port { - etm1_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in_port1>; + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&cluster0_funnel_in_port1>; + }; }; }; }; @@ -599,10 +590,12 @@ clocks = <&ext_26m>; clock-names = "apb_pclk"; - port { - etm2_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in_port2>; + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&cluster0_funnel_in_port2>; + }; }; }; }; @@ -614,10 +607,12 @@ clocks = <&ext_26m>; clock-names = "apb_pclk"; - port { - etm3_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in_port3>; + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&cluster0_funnel_in_port3>; + }; }; }; }; @@ -629,10 +624,12 @@ clocks = <&ext_26m>; clock-names = "apb_pclk"; - port { - etm4_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in_port0>; + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&cluster1_funnel_in_port0>; + }; }; }; }; @@ -644,10 +641,12 @@ clocks = <&ext_26m>; clock-names = "apb_pclk"; - port { - etm5_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in_port1>; + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&cluster1_funnel_in_port1>; + }; }; }; }; @@ -659,10 +658,12 @@ clocks = <&ext_26m>; clock-names = "apb_pclk"; - port { - etm6_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in_port2>; + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&cluster1_funnel_in_port2>; + }; }; }; }; @@ -674,10 +675,12 @@ clocks = <&ext_26m>; clock-names = "apb_pclk"; - port { - etm7_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in_port3>; + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&cluster1_funnel_in_port3>; + }; }; }; }; -- cgit From b0fe0f47be46096cb0edf38d015c6b0a4472c7ae Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Wed, 10 Oct 2018 11:00:34 +0200 Subject: arm64: dts: rockchip: add rk3399 SPI DMAs Add spi dma channels as specified by the rk3399 TRM. Signed-off-by: Emil Renner Berthing Tested-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 99e7f65c1779..c0f1cc403670 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -681,6 +681,8 @@ clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_peri 10>, <&dmac_peri 11>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; #address-cells = <1>; @@ -694,6 +696,8 @@ clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_peri 12>, <&dmac_peri 13>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; #address-cells = <1>; @@ -707,6 +711,8 @@ clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_peri 14>, <&dmac_peri 15>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; #address-cells = <1>; @@ -720,6 +726,8 @@ clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_peri 18>, <&dmac_peri 19>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; #address-cells = <1>; @@ -733,6 +741,8 @@ clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; clock-names = "spiclk", "apb_pclk"; interrupts = ; + dmas = <&dmac_bus 8>, <&dmac_bus 9>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; power-domains = <&power RK3399_PD_SDIOAUDIO>; -- cgit From 6d2520783035c6ec16c8580f319276e2bb427bee Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Sun, 30 Sep 2018 17:50:33 +0200 Subject: arm64: dts: rockchip: add fan on rk3399-sapphire board The Sapphire board has a 12V fan. So, adding it to the DTS. There is no power supply directly connected, it needs the baseboard to work. If the board is used standalone then a hardware modification is needed. On the Sapphire board there is an unpopulated resistor to connect it to VBUS_TYPEC, which is usually 5V (too low) and can range up to 20V (too high). I tested it for a week connected to VCC_SYS which is 8.4V and proved to be more than enough for the required cooling needs. This is the connection described in the comment. Signed-off-by: Vicente Bergas Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 5421e23760c3..90d813bdabde 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -66,6 +66,19 @@ regulator-max-microvolt = <12000000>; }; + /* + * The fan power supply comes from the baseboard. + * For the standalone Sapphire one option is to connect a wire + * from R90030 DNP R0805 pin2 to C90002 10uF C0805 pin1 (vcc_sys). + */ + fan0: gpio-fan { + #cooling-cells = <2>; + compatible = "gpio-fan"; + gpio-fan,speed-map = <0 0 3000 1>; + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + keys: gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -183,6 +196,24 @@ cpu-supply = <&vdd_cpu_b>; }; +&cpu_thermal { + trips { + cpu_hot: cpu_hot { + hysteresis = <10000>; + temperature = <55000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + cooling-device = + <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&cpu_hot>; + }; + }; +}; + &emmc_phy { status = "okay"; }; @@ -472,6 +503,13 @@ }; }; + fan { + motor_pwr: motor-pwr { + rockchip,pins = + ; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = -- cgit From cff6d1d6f88bc8763f40f87869e8361fb0dbeb80 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Sat, 20 Oct 2018 10:57:56 -0700 Subject: arm64: dts: rockchip: enable HS200 for eMMC on rock64 eMMC that's sold by Pine64 can do HS200, rk3328 can do it as well, so update DTS to enable it. Signed-off-by: Vasily Khoruzhick Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index dc20145dd393..bd937d68ca3b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -100,6 +100,7 @@ &emmc { bus-width = <8>; cap-mmc-highspeed; + mmc-hs200-1_8v; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; -- cgit From d840db386a57d60da8c2b41b393cd97f47a575e2 Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Tue, 30 Oct 2018 15:59:41 +0100 Subject: arm64: dts: rockchip: add chosen node on rk3399-sapphire In order to use earlycon, the stdout-path property needs to be set in the chosen node. Signed-off-by: Vicente Bergas Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 90d813bdabde..561fe6657368 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -11,6 +11,10 @@ / { compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; + chosen { + stdout-path = "serial2:1500000n8"; + }; + backlight: backlight { compatible = "pwm-backlight"; brightness-levels = < -- cgit From 365af3f160f61b7afaa15d5ff6717e7d15ceedee Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Tue, 16 Oct 2018 16:13:04 +0200 Subject: arm64: dts: rockchip: Use default brightness table for rk3399-gru After commit 88ba95bedb79 ("backlight: pwm_bl: Compute brightness of LED linearly to human eye") the pwm_bl driver is able to calculate a default brightness table. The calculated table for this PWM will have more granularity and will be adjusted to change the brightness linearly to the human eye. Use that table instead of have a DT-defined table with less granularity. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index ff81dfda3b95..c400be64170e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -194,14 +194,6 @@ backlight: backlight { compatible = "pwm-backlight"; - brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - 45 46 47 48 49 50 51 52 53 54 55 56 57 58 - 59 60 61 62 63 64 65 66 67 68 69 70 71 72 - 73 74 75 76 77 78 79 80 81 82 83 84 85 86 - 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; - default-brightness-level = <51>; enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; power-supply = <&pp3300_disp>; pinctrl-names = "default"; -- cgit From 5a2a93f1ee186ee7fe61bb09fc3680985b44ba3f Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Tue, 30 Oct 2018 16:00:49 +0100 Subject: arm64: dts: rockchip: move backlight from rk3399 sapphire to excavator The backlight is for the eDP panel and it has the connector on the excavator baseboard. Signed-off-by: Vicente Bergas Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-sapphire-excavator.dts | 46 +++++++++++++++++++--- arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 39 ------------------ 2 files changed, 41 insertions(+), 44 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index fef2c0608999..0b8f1edbd746 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts @@ -42,6 +42,47 @@ }; }; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pwms = <&pwm0 0 25000 0>; + status = "okay"; + }; + edp_panel: edp-panel { compatible ="lg,lp079qx1-sp0v", "simple-panel"; backlight = <&backlight>; @@ -95,11 +136,6 @@ }; }; -&backlight { - enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - &edp { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 561fe6657368..946d3589575a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -15,45 +15,6 @@ stdout-path = "serial2:1500000n8"; }; - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - pwms = <&pwm0 0 25000 0>; - }; - clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; -- cgit From a63ea49a653c5164312aeebf43c50bce5f57ca5a Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 22 Oct 2018 18:43:51 +0200 Subject: ARM: dts: sun8i-a83t-tbs-a711: Change MMC0 bus-width to 4 The actual hardware has 4 data lines. Use them. Signed-off-by: Ondrej Jirman Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts index 1537ce148cc1..98e8cea26dbe 100644 --- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts @@ -160,6 +160,7 @@ vmmc-supply = <®_dcdc1>; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; + bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; status = "okay"; }; -- cgit From 2dae149d9219edaa97f87a0282a5695639c27435 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Mon, 8 Oct 2018 20:46:09 -0700 Subject: arm64: dts: allwinner: add backlight regulator for Pinebook Backlight power is controlled by PH6 GPIO, so add corresponding regulator-fixed node for it. Otherwise backlight won't light up if bootloader doesn't enable it. Signed-off-by: Vasily Khoruzhick Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 77fac84797e9..ec537c529726 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -22,12 +22,22 @@ ethernet0 = &rtl8723cs; }; + vdd_bl: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "bl-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + enable-active-high; + }; + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 50000 0>; brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; default-brightness-level = <2>; enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ + power-supply = <&vdd_bl>; }; chosen { -- cgit From e98d72d98a25890308941080d3a17b4c77e3f460 Mon Sep 17 00:00:00 2001 From: Jorik Jonker Date: Sat, 29 Sep 2018 15:18:30 +0200 Subject: ARM: dts: sun8i-h3: add sy8106a to orange pi plus The Orange Pi Plus board lacks voltage scaling capabilities in its current form. This results in random freezes during boot when cpufreq is enabled, probably due to wrong voltages. This patch (more or less copy/paste from 06139c) does the following things on this board: - enable r_i2c - add sy8106a to the r_i2c bus - have the sy8106a regulate VDD of cpu Since the Orange Pi Plus has the same PMU setup as the Orange Pi PC, I simply took min/max/fixed/ramp from the latter DTS. In that file the origin of the values are described by the following comment: "The datasheet uses 1.1V as the minimum value of VDD-CPUX, however both the Armbian DVFS table and the official one have operating points with voltage under 1.1V, and both DVFS table are known to work properly at the lowest operating point. Use 1.0V as the minimum voltage instead." I have tested this on patch two Orange Pi Plus boards, by running a kernel with this patch and do intermettent runs of cpuburn while monitoring voltage, frequency and temperature. The board runs stable across its operatiing points while showing a reasonable (< 40C) temperature. My Orange Pi PC, when put to the same test, yields similar stable results. Signed-off-by: Jorik Jonker Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index b403e5d787cb..ac8438c2cff1 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -74,6 +74,10 @@ }; }; +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + &ehci3 { status = "okay"; }; @@ -119,6 +123,22 @@ }; }; +&r_i2c { + status = "okay"; + + reg_vdd_cpux: regulator@65 { + compatible = "silergy,sy8106a"; + reg = <0x65>; + regulator-name = "vdd-cpux"; + silergy,fixed-microvolt = <1200000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <200>; + regulator-boot-on; + regulator-always-on; + }; +}; + &usbphy { usb3_vbus-supply = <®_usb3_vbus>; }; -- cgit From f517232c5a95408e43b40aa9337e6b742beaa9da Mon Sep 17 00:00:00 2001 From: Aleksandr Aleksandrov Date: Mon, 15 Oct 2018 14:49:49 +0300 Subject: dt-bindings: vendor-prefix: new vendor - Emlid Add vendor Emlid Ltd to vendor-prefixes.txt Acked-by: Rob Herring Signed-off-by: Aleksandr Aleksandrov Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 4b1a2a8fcc16..1b531c730c87 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -113,6 +113,7 @@ edt Emerging Display Technologies eeti eGalax_eMPIA Technology Inc elan Elan Microelectronic Corp. embest Shenzhen Embest Technology Co., Ltd. +emlid Emlid, Ltd. emmicro EM Microelectronic emtrion emtrion GmbH endless Endless Mobile, Inc. -- cgit From 8fb3d7deaeaf316c784b1f08f16d8050e8ced024 Mon Sep 17 00:00:00 2001 From: Aleksandr Aleksandrov Date: Mon, 15 Oct 2018 14:49:50 +0300 Subject: arm64: dts: allwinner: new board - Emlid Neutis N5 Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT module, DDR3 RAM and eMMC. - add neutis n5 dtsi file for SoM needs - add neutis devboard dts file - add neutis devboard target to dtb makefile Signed-off-by: Aleksandr Aleksandrov Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../sun50i-h5-emlid-neutis-n5-devboard.dts | 149 +++++++++++++++++++++ .../dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi | 61 +++++++++ 3 files changed, 211 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 8d4f97f279e0..9ff8b9d3a9db 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts new file mode 100644 index 000000000000..85e7993a74e7 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * DTS for Emlid Neutis N5 Dev board. + * + * Copyright (C) 2018 Aleksandr Aleksandrov + */ + +/dts-v1/; + +#include "sun50i-h5-emlid-neutis-n5.dtsi" + +/ { + model = "Emlid Neutis N5 Developer board"; + compatible = "emlid,neutis-n5-devboard", + "emlid,neutis-n5", + "allwinner,sun50i-h5"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ + status = "okay"; + }; + + vdd_cpux: gpio-regulator { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + gpios-states = <0x1>; + states = <1100000 0x0 + 1300000 0x1>; + }; +}; + +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "LINEIN", "Line In", + "MIC1", "Mic", + "MIC2", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi new file mode 100644 index 000000000000..e4d50373c8ef --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * DTSI for Emlid Neutis N5 SoM. + * + * Copyright (C) 2018 Aleksandr Aleksandrov + */ + +/dts-v1/; + +#include "sun50i-h5.dtsi" + +#include + +/ { + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ + post-power-on-delay-ms = <200>; + }; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + status = "okay"; +}; -- cgit From 3e712a03d0481f7b0c24d961a43e385dcfa78c74 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 28 Aug 2017 00:38:36 +0200 Subject: ARM: dts: rockchip: add qos nodes found on rk3066 and rk3188 QoS nodes keep information about priorites etc on the interconnect and loose state when the power-domain gets disabled. Therefore the power-domain driver stores the settings of available qos nodes and restores them when the power-domain gets enabled again. So add the qos nodes found on the Cortex-A9 socs from Rockchip, so that they can then be connected to the power-domains. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3xxx.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index d752dc611fd7..97307a405e60 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -147,6 +147,46 @@ status = "disabled"; }; + qos_gpu: qos@1012d000 { + compatible = "syscon"; + reg = <0x1012d000 0x20>; + }; + + qos_vpu: qos@1012e000 { + compatible = "syscon"; + reg = <0x1012e000 0x20>; + }; + + qos_lcdc0: qos@1012f000 { + compatible = "syscon"; + reg = <0x1012f000 0x20>; + }; + + qos_cif0: qos@1012f080 { + compatible = "syscon"; + reg = <0x1012f080 0x20>; + }; + + qos_ipp: qos@1012f100 { + compatible = "syscon"; + reg = <0x1012f100 0x20>; + }; + + qos_lcdc1: qos@1012f180 { + compatible = "syscon"; + reg = <0x1012f180 0x20>; + }; + + qos_cif1: qos@1012f200 { + compatible = "syscon"; + reg = <0x1012f200 0x20>; + }; + + qos_rga: qos@1012f280 { + compatible = "syscon"; + reg = <0x1012f280 0x20>; + }; + usb_otg: usb@10180000 { compatible = "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x10180000 0x40000>; -- cgit From e6e1869f0b71638e5317c3942463bfbb198b244d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 15 Sep 2017 09:54:28 +0200 Subject: ARM: dts: rockchip: add rk3066/rk3188 power-domains Add the power-domain nodes to both rk3066 and rk3188 including their clocks and qos connections. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3188.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 103 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 2ab3c4b32003..112d2bf8e998 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include "rk3xxx.dtsi" / { @@ -595,6 +596,7 @@ "ppmmu2", "pp3", "ppmmu3"; + power-domains = <&power RK3066_PD_GPU>; }; &i2c0 { @@ -643,6 +645,56 @@ dma-names = "rx-tx"; }; +&pmu { + power: power-controller { + compatible = "rockchip,rk3066-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vio@RK3066_PD_VIO { + reg = ; + clocks = <&cru ACLK_LCDC0>, + <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC0>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC0>, + <&cru HCLK_LCDC1>, + <&cru SCLK_CIF1>, + <&cru ACLK_CIF1>, + <&cru HCLK_CIF1>, + <&cru SCLK_CIF0>, + <&cru ACLK_CIF0>, + <&cru HCLK_CIF0>, + <&cru ACLK_IPP>, + <&cru HCLK_IPP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_lcdc0>, + <&qos_lcdc1>, + <&qos_cif0>, + <&qos_cif1>, + <&qos_ipp>, + <&qos_rga>; + }; + + pd_video@RK3066_PD_VIDEO { + reg = ; + clocks = <&cru ACLK_VDPU>, + <&cru ACLK_VEPU>, + <&cru HCLK_VDPU>, + <&cru HCLK_VEPU>; + pm_qos = <&qos_vpu>; + }; + + pd_gpu@RK3066_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + }; + }; +}; + &pwm0 { pinctrl-names = "default"; pinctrl-0 = <&pwm0_out>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index b6f790973736..7e0dc52630d9 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include "rk3xxx.dtsi" / { @@ -80,6 +81,7 @@ interrupts = ; clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3188_PD_VIO>; resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; reset-names = "axi", "ahb", "dclk"; status = "disabled"; @@ -96,6 +98,7 @@ interrupts = ; clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3188_PD_VIO>; resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; reset-names = "axi", "ahb", "dclk"; status = "disabled"; @@ -620,6 +623,7 @@ "ppmmu2", "pp3", "ppmmu3"; + power-domains = <&power RK3188_PD_GPU>; }; &i2c0 { @@ -652,6 +656,53 @@ pinctrl-0 = <&i2c4_xfer>; }; +&pmu { + power: power-controller { + compatible = "rockchip,rk3188-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vio@RK3188_PD_VIO { + reg = ; + clocks = <&cru ACLK_LCDC0>, + <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC0>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC0>, + <&cru HCLK_LCDC1>, + <&cru SCLK_CIF0>, + <&cru ACLK_CIF0>, + <&cru HCLK_CIF0>, + <&cru ACLK_IPP>, + <&cru HCLK_IPP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_lcdc0>, + <&qos_lcdc1>, + <&qos_cif0>, + <&qos_cif1>, + <&qos_ipp>, + <&qos_rga>; + }; + + pd_video@RK3188_PD_VIDEO { + reg = ; + clocks = <&cru ACLK_VDPU>, + <&cru ACLK_VEPU>, + <&cru HCLK_VDPU>, + <&cru HCLK_VEPU>; + pm_qos = <&qos_vpu>; + }; + + pd_gpu@RK3188_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + }; + }; +}; + &pwm0 { pinctrl-names = "default"; pinctrl-0 = <&pwm0_out>; -- cgit From 186172f465c29ee6b617af961723a3ce5029a9c8 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 3 Nov 2018 20:32:36 +0800 Subject: dt-binding: dwmac-sun8i: add H6 compatible string (w/ A64 fallback) The Allwinner H6 SoC features a Ethernet MAC that is similar to the one in A64. Add a compatible string for it with A64 fallback compatible string, in this case the A64 driver can be used. The "internal" PHY is not internal from the perspective of the H6 main die, instead it's on the co-packaged AC200 chip, and connected to the main die with RMII at the in-package Port A PIO bank. So from the SoC driver side it needs no special treatment. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 5bb3a18cc38d..54c66d0611cb 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -10,6 +10,7 @@ Required properties: "allwinner,sun8i-r40-gmac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" + "allwinner,sun50i-h6-emac", "allwinner-sun50i-a64-emac" - reg: address and length of the register for the device. - interrupts: interrupt for the device - interrupt-names: must be "macirq" -- cgit From c8ced5516d2340641a676d6f139577d45bcb4e56 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 3 Nov 2018 20:32:37 +0800 Subject: arm64: allwinner: h6: add EMAC device nodes Allwinner H6 SoC has an EMAC like the one in A64. Add device tree nodes for the H6 DTSI file. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 040828d2e2c0..11f7ce7d1876 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -149,6 +149,14 @@ interrupt-controller; #interrupt-cells = <3>; + ext_rgmii_pins: rgmii_pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", + "PD5", "PD7", "PD8", "PD9", "PD10", + "PD11", "PD12", "PD13", "PD19", "PD20"; + function = "emac"; + drive-strength = <40>; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -258,6 +266,26 @@ status = "disabled"; }; + emac: ethernet@5020000 { + compatible = "allwinner,sun50i-a64-emac", + "allwinner,sun50i-h6-emac"; + syscon = <&syscon>; + reg = <0x05020000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + r_ccu: clock@7010000 { compatible = "allwinner,sun50i-h6-r-ccu"; reg = <0x07010000 0x400>; -- cgit From 729e1ffcf47e5e035a9a504e81e8d25403919993 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 3 Nov 2018 20:32:38 +0800 Subject: arm64: allwinner: h6: add support for the Ethernet on Pine H64 The Pine H64 board has an Ethernet port, which is connected to a RTL8211E PHY, then the PHY is connected to the MAC on H6 SoC. Add support for the Ethernet port. The PHY needs some time to start up, and the time is modelled as enable ramp delay of the regulator. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index 48daec7f78ba..fcf3c1de4aa2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -14,6 +14,7 @@ compatible = "pine64,pine-h64", "allwinner,sun50i-h6"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -41,6 +42,24 @@ }; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_aldo2>; + allwinner,rx-delay-ps = <200>; + allwinner,tx-delay-ps = <200>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -85,6 +104,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc-ac200"; + regulator-enable-ramp-delay = <100000>; }; reg_aldo3: aldo3 { -- cgit From 4f16ca40de15cd1073d5e9540d8e810deeab7d87 Mon Sep 17 00:00:00 2001 From: Jonathan McDowell Date: Tue, 30 Oct 2018 22:14:30 +0000 Subject: ARM: dts: sun8i-h3: Add dts for the Mapleboard MP130 The Mapleboard MP130 is a single board computer based on the Allwinner H3 SoC, with all schematics freely available. The Lite version includes 1GB main memory and 8GB eMMC. https://www.mapleboard.org/en (still mostly in Chinese even when English is selected) This DTS is based upon the DTS shipped with the board which uses mapleboard,mp130- prefixes instead of the allwinner,sun8i variants. v2: Fold in review comments from Maxime Ripard Signed-off-by: Jonathan McDowell Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts | 153 ++++++++++++++++++++++++ 2 files changed, 154 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..8b76c7b38d40 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1043,6 +1043,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-bananapi-m2-plus-v1.2.dtb \ sun8i-h3-beelink-x2.dtb \ sun8i-h3-libretech-all-h3-cc.dtb \ + sun8i-h3-mapleboard-mp130.dtb \ sun8i-h3-nanopi-m1.dtb \ sun8i-h3-nanopi-m1-plus.dtb \ sun8i-h3-nanopi-neo.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts new file mode 100644 index 000000000000..2c952eacfef5 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-mapleboard-mp130.dts @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Centrum Embedded Systems, Jia-Bin Huang + * Copyright (C) 2018 Jonathan McDowell + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "MapleBoard MP130"; + compatible = "mapleboard,mp130", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr_led { + label = "mp130:orange:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "mp130:orange:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; + }; + }; + + r_gpio_keys { + compatible = "gpio-keys"; + + power { + label = "power"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ + }; + + user { + label = "user"; + linux,code = ; + gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "LINEIN", "Line In"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; -- cgit From ac1e507fe61db9aacb3d6f2c57f095c1cb3cbacb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 26 Sep 2018 13:36:16 +0200 Subject: ARM: dts: Use mmc@ instead sdhci@ mmc name is recommended based on devicetree specification. Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index e22507e23303..ca6425ad794c 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -219,7 +219,7 @@ #size-cells = <0>; }; - sdhci0: sdhci@e0100000 { + sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; @@ -229,7 +229,7 @@ reg = <0xe0100000 0x1000>; }; - sdhci1: sdhci@e0101000 { + sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; -- cgit From b823d65f3380e9d7dd19c8e015dd7f22a0a09957 Mon Sep 17 00:00:00 2001 From: Chris Paterson Date: Mon, 10 Sep 2018 11:43:15 +0100 Subject: arm64: dts: renesas: r8a774a1: Add CAN nodes Add the device nodes for both RZ/G2M CAN channels. Signed-off-by: Chris Paterson Reviewed-by: Biju Das Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 012cbb64246e..a4817a012e11 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -873,6 +873,30 @@ status = "disabled"; }; + can0: can@e6c30000 { + compatible = "renesas,can-r8a774a1", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, <&can_clk>; + clock-names = "clkp1", "can_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a774a1", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, <&can_clk>; + clock-names = "clkp1", "can_clk"; + power-domains = <&sysc 32>; + resets = <&cpg 915>; + status = "disabled"; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; -- cgit From e20a1b9e10e3d01155bfd3faa2a49174ee16df08 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 28 Sep 2018 02:39:47 +0000 Subject: arm64: dts: renesas: r8a7795: remove unneeded sound #address/size-cells commit 2d87dc0e5be2 ("arm64: dts: renesas: r8a7795: Add address properties to rcar_sound port nodes") added missing #address-cells and #size-cells for sound ports. But, these are based on platform, not on SoC. This patch cleanups it. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts | 2 ++ arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 2 ++ arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 2 ++ arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 -------------- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 3 +++ 5 files changed, 9 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts index 0895503b69d0..c1a56eab7b24 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts @@ -112,6 +112,7 @@ ports { /* rsnd_port0 is on salvator-common */ rsnd_port1: port@1 { + reg = <1>; rsnd_endpoint1: endpoint { remote-endpoint = <&dw_hdmi0_snd_in>; @@ -123,6 +124,7 @@ }; }; rsnd_port2: port@2 { + reg = <2>; rsnd_endpoint2: endpoint { remote-endpoint = <&dw_hdmi1_snd_in>; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 1620e8d8dacc..d2d48b33b37f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -112,6 +112,7 @@ ports { /* rsnd_port0 is on salvator-common */ rsnd_port1: port@1 { + reg = <1>; rsnd_endpoint1: endpoint { remote-endpoint = <&dw_hdmi0_snd_in>; @@ -123,6 +124,7 @@ }; }; rsnd_port2: port@2 { + reg = <2>; rsnd_endpoint2: endpoint { remote-endpoint = <&dw_hdmi1_snd_in>; diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts index cf08a119eec0..42101fc76837 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts @@ -127,6 +127,7 @@ ports { /* rsnd_port0 is on salvator-common */ rsnd_port1: port@1 { + reg = <1>; rsnd_endpoint1: endpoint { remote-endpoint = <&dw_hdmi0_snd_in>; @@ -138,6 +139,7 @@ }; }; rsnd_port2: port@2 { + reg = <2>; rsnd_endpoint2: endpoint { remote-endpoint = <&dw_hdmi1_snd_in>; diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index b5f2273caca4..95a8ed40e7d3 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1972,20 +1972,6 @@ dma-names = "rx", "tx", "rxu", "txu"; }; }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - }; - port@2 { - reg = <2>; - }; - }; }; audma0: dma-controller@ec700000 { diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 7f91ff524109..054a7eeeef92 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -707,7 +707,10 @@ <&cpg CPG_CORE CPG_AUDIO_CLK_I>; ports { + #address-cells = <1>; + #size-cells = <0>; rsnd_port0: port@0 { + reg = <0>; rsnd_endpoint0: endpoint { remote-endpoint = <&ak4613_endpoint>; -- cgit From 0c793a02cc7cc8ba66855a08d3015b8385885b1e Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Fri, 28 Sep 2018 13:37:56 +0200 Subject: arm64: dts: renesas: r8a77990: Add INTC-EX device node This patch adds a device node for the Interrupt Controller for External Devices (INTC-EX) on R-Car E3, which serves external IRQ pins IRQ[0-5]. Signed-off-by: Takeshi Kihara Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 9509dc05665f..7278cd52891d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -341,6 +341,22 @@ #power-domain-cells = <1>; }; + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a77990", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a77990", "renesas,rcar-dmac"; -- cgit From de625477c632abecf23feba94ff4c5904764f57d Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 1 Oct 2018 23:25:43 +0300 Subject: arm64: dts: renesas: r8a779{7|8}0: add PWM support Describe PWMs in the R8A779{7|8}0 device trees. Based on the original (and large) patches by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 50 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 50 +++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index cba7885cf7c3..e58040e76303 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -543,6 +543,56 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77970", "renesas,rcar-gen3-scif", diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index d4952b527d14..a1fda9901423 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -594,6 +594,56 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 523>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77980", "renesas,rcar-gen3-scif", -- cgit From 8517042060b55a37c1b7d3cbb04e131bfe61c13a Mon Sep 17 00:00:00 2001 From: Yoshihiro Kaneko Date: Tue, 9 Oct 2018 16:38:50 +0900 Subject: arm64: dts: renesas: r8a77990: Add DMA properties to MSIOF nodes This patch adds DMA properties to the MSIOF device nodes of R8A77990 SoC. Signed-off-by: Yoshihiro Kaneko Reviewed-by: Geert Uytterhoeven Tested-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 7278cd52891d..6d5efeb9f363 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -700,6 +700,9 @@ reg = <0 0xe6e90000 0 0x0064>; interrupts = ; clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 211>; #address-cells = <1>; @@ -713,6 +716,9 @@ reg = <0 0xe6ea0000 0 0x0064>; interrupts = ; clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 210>; #address-cells = <1>; @@ -726,6 +732,8 @@ reg = <0 0xe6c00000 0 0x0064>; interrupts = ; clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 209>; #address-cells = <1>; @@ -739,6 +747,8 @@ reg = <0 0xe6c10000 0 0x0064>; interrupts = ; clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 208>; #address-cells = <1>; -- cgit From f1487c19781a07144d8be88cca3c1c85a62f00da Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 9 Oct 2018 22:47:47 +0300 Subject: arm64: dts: renesas: r8a77970: add thermal support Describe THS/CIVM in the R8A77970 device tree. Based on the original (and large) patches by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index e58040e76303..ba903fc32166 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -300,6 +300,19 @@ #power-domain-cells = <1>; }; + thermal: thermal@e6190000 { + compatible = "renesas,thermal-r8a77970"; + reg = <0 0xe6190000 0 0x10 + 0 0xe6190100 0 0x120>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; #interrupt-cells = <2>; @@ -1033,6 +1046,25 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, -- cgit From 69c5e602d0bd717da04c18c08017d195ec10da8d Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 10 Oct 2018 22:18:11 +0300 Subject: arm64: dts: renesas: r8a77980: add thermal support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe THS/CIVM in the R8A77980 device trees. Signed-off-by: Sergei Shtylyov Reviewed-by: Niklas Söderlund Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 53 +++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index a1fda9901423..42c7088223c8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -330,6 +330,19 @@ #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a77980-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; #interrupt-cells = <2>; @@ -1404,6 +1417,46 @@ }; }; + thermal-zones { + thermal-sensor-1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1-passive { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + sensor1-critical { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal-sensor-2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2-passive { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + sensor2-critical { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | -- cgit From bae66bbcf2011f4048d2a99fd02d3a6608327c60 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 18 Oct 2018 03:41:49 +0300 Subject: arm64: dts: renesas: r8a77965: Add LVDS support The M3-N (r8a77965) platform has one LVDS encoder connected to the DU. Add the corresponding DT node and wire it up. Signed-off-by: Laurent Pinchart Reviewed-by: Kieran Bingham Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 83946ca2eba5..b984b85dc066 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2153,6 +2153,33 @@ port@2 { reg = <2>; du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a77965-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { }; }; }; -- cgit From e67898dc2d2b4bf484dd8807d62c88480f6290fb Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 16 Oct 2018 15:04:50 +0900 Subject: arm64: dts: renesas: revise hsusb's reg size This patch revises the reg size of each hsusb device node for r8a7795, r8a7796 and r8a77965. Reported-by: Biju Das Fixes: d2422e108812 ("arm64: dts: r8a7795: Add HSUSB device node") Fixes: 4725f2b88057 ("arm64: dts: renesas: r8a7795: add hsusb ch3 device node") Fixes: b9535853777f ("arm64: dts: r8a7796: Add HSUSB device node") Fixes: 9e1b00a2ef43 ("arm64: dts: renesas: r8a77965: Add "reg" properties") Signed-off-by: Yoshihiro Shimoda Reviewed-by: Biju Das Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 95a8ed40e7d3..27faaccd0cae 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -695,7 +695,7 @@ hsusb: usb@e6590000 { compatible = "renesas,usbhs-r8a7795", "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x100>; + reg = <0 0xe6590000 0 0x200>; interrupts = ; clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, @@ -712,7 +712,7 @@ hsusb3: usb@e659c000 { compatible = "renesas,usbhs-r8a7795", "renesas,rcar-gen3-usbhs"; - reg = <0 0xe659c000 0 0x100>; + reg = <0 0xe659c000 0 0x200>; interrupts = ; clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>; dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 1ec6aaa520c1..3baee26ae372 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -674,7 +674,7 @@ hsusb: usb@e6590000 { compatible = "renesas,usbhs-r8a7796", "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x100>; + reg = <0 0xe6590000 0 0x200>; interrupts = ; clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index b984b85dc066..4ac2abeda48c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -590,7 +590,7 @@ hsusb: usb@e6590000 { compatible = "renesas,usbhs-r8a77965", "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x100>; + reg = <0 0xe6590000 0 0x200>; interrupts = ; clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, -- cgit From 0c85e78fb1d3742c36ff085999624cc912128776 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 10 Sep 2018 15:31:18 +0100 Subject: arm64: dts: renesas: r8a774a1: Add VIN and CSI-2 nodes Add VIN and CSI-2 nodes to RZ/G2M SoC dtsi. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 367 ++++++++++++++++++++++++++++++ 1 file changed, 367 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index a4817a012e11..78ac8e3cda6e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1126,6 +1126,262 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc 32>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc 32>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc 32>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc 32>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc 32>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin4>; + }; + vin4csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc 32>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin5>; + }; + vin5csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc 32>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin6>; + }; + vin6csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a774a1"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc 32>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin7>; + }; + vin7csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin7>; + }; + }; + }; + }; + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required @@ -1613,6 +1869,117 @@ iommus = <&ipmmu_vc0 19>; }; + csi20: csi2@fea80000 { + compatible = "renesas,r8a774a1-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc 32>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a774a1-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc 32>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + csi40vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi40>; + }; + csi40vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi40>; + }; + csi40vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi40>; + }; + csi40vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi40>; + }; + }; + + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; -- cgit From 122ddb7104f7c305ed83d49b2e2b65df497519e0 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 19 Oct 2018 22:10:44 +0300 Subject: arm64: dts: renesas: r8a779{7|8}0: add MSIOF support Describe MSIOF in the R8A779{7|8}0 device trees. The DMA props are omitted for R8A77980 as the RT-DMAC isn't supported (yet?)... Based on the original (and large) patches by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 64 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 52 +++++++++++++++++++++++++ 2 files changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index ba903fc32166..4abd154bca1f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -688,6 +688,70 @@ status = "disabled"; }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a77970", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a77970", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a77970", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 209>; + dmas = <&dmac1 0x45>, <&dmac1 0x44>, + <&dmac2 0x45>, <&dmac2 0x44>; + dma-names = "tx", "rx", "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a77970", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 208>; + dmas = <&dmac1 0x47>, <&dmac1 0x46>, + <&dmac2 0x47>, <&dmac2 0x46>; + dma-names = "tx", "rx", "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + vin0: video@e6ef0000 { compatible = "renesas,vin-r8a77970"; reg = <0 0xe6ef0000 0 0x1000>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 42c7088223c8..54acc494a43f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -740,6 +740,58 @@ status = "disabled"; }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a77980", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a77980", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a77980", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a77980", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + vin0: video@e6ef0000 { compatible = "renesas,vin-r8a77980"; reg = <0 0xe6ef0000 0 0x1000>; -- cgit From a5ebe5e49a862e21c620656d2dc244a0d92833d9 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Sun, 21 Oct 2018 06:30:00 +0900 Subject: arm64: dts: renesas: r8a77990: Add SCIF-{0,1,3,4,5} device nodes This patch adds the device nodes for SCIF-{0,1,3,4,5} serial ports to the R8A77990 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 83 +++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 6d5efeb9f363..f969e680b9ba 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -679,6 +679,40 @@ status = "disabled"; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77990", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A77990_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77990", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A77990_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a77990", "renesas,rcar-gen3-scif", "renesas,scif"; @@ -694,6 +728,55 @@ status = "disabled"; }; + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a77990", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A77990_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a77990", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A77990_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a77990", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A77990_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + msiof0: spi@e6e90000 { compatible = "renesas,msiof-r8a77990", "renesas,rcar-gen3-msiof"; -- cgit From 8dae1d2bbc128201bde30eee41940fab4c4f18c0 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 22 Oct 2018 15:47:08 +0900 Subject: arm64: dts: renesas: r8a77990: add/enable USB3.0 peripheral device node This patch adds/enables USB3.0 peripheral device node for r8a77990 ebisu board. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 5 +++++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index f342dd85b152..ff428a64341c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -362,6 +362,11 @@ status = "okay"; }; +&usb3_peri0 { + companion = <&xhci0>; + status = "okay"; +}; + &vin4 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index f969e680b9ba..cb83d866db7f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -898,6 +898,17 @@ status = "disabled"; }; + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a77990-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + ohci0: usb@ee080000 { compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; -- cgit From ea57402f3671d877f12616581bca4c4923bbfd10 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 22 Oct 2018 02:14:44 +0900 Subject: arm64: dts: renesas: r8a77965: Connect R-Car M3-N AVB to IPMMU Hook up the R-Car M3-N AVB device to IPMMU-DS0 16 as described in the data sheet. Signed-off-by: Magnus Damm Tested-by: Simon Horman Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 4ac2abeda48c..3a958fb25245 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -900,6 +900,7 @@ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit From 7ffbcb232c7b8f90dbb40338ce084b65c65fb9fc Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 22 Oct 2018 02:14:54 +0900 Subject: arm64: dts: renesas: r8a77980: Connect R-Car V3H AVB to IPMMU Hook up the R-Car V3H AVB device to IPMMU-DS1 33 as described in the data sheet. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 54acc494a43f..ce2c9955df75 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -602,6 +602,7 @@ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + iommus = <&ipmmu_ds1 33>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit From 430212752cd71fe8ed10a6c1cd9e6f8fe7fda222 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 22 Oct 2018 02:15:03 +0900 Subject: arm64: dts: renesas: r8a77990: Connect R-Car E3 AVB to IPMMU Hook up the R-Car E3 AVB device to IPMMU-DS0 16 as described in the data sheet. Signed-off-by: Magnus Damm Tested-by: Simon Horman Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index cb83d866db7f..a945db3c4644 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -604,6 +604,7 @@ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit From 396aadeb951dfb11c075ac6ed18178fa8513e746 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 22 Oct 2018 15:47:29 +0900 Subject: arm64: dts: renesas: salvator-common: add companion property in usb3_peri0 This patch adds a property "companion" with xhci0 phandle to the usb3_peri0 node in salvator-common.dtsi. About the detail of this property for renesas_usb3 udc driver, please refer to the commit 39facfa01c9f ("usb: gadget: udc: renesas_usb3: Add register of usb role switch"). Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 054a7eeeef92..a3e89504e044 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -817,6 +817,8 @@ phys = <&usb3_phy0>; phy-names = "usb"; + companion = <&xhci0>; + status = "okay"; }; -- cgit From 5c6479d9b25b40001e814003f62a93485f9ff82f Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 24 Oct 2018 17:32:33 +0900 Subject: arm64: dts: renesas: r8a7799{0|5}: add/enable USB2.0 peripheral This patch adds/enables USB2.0 peripheral for R-Car [DE]3 boards. R-Car E3 Ebisu board connects the ID pin to the SoC, so this adds a group "usb0_id" into usb0_pins node. Also, to use SW15 pin 3 side, this patch adds vbus0_usb2 node on r8a77990-ebisu.dts. R-Car D3 Draak board doesn't connect the ID pin, so this adds "renesas,no-otg-pins" property into usb2_phy0 node. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 21 +++++++++++- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 45 ++++++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 8 +++++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 45 ++++++++++++++++++++++++++ 4 files changed, 118 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index ff428a64341c..038664e0cdcb 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -128,6 +128,17 @@ regulator-always-on; }; + vbus0_usb2: regulator-vbus0-usb2 { + compatible = "regulator-fixed"; + + regulator-name = "USB20_VBUS_CN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + x13_clk: x13 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -188,6 +199,7 @@ }; &ehci0 { + dr_mode = "otg"; status = "okay"; }; @@ -195,6 +207,11 @@ clock-frequency = <48000000>; }; +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -295,6 +312,7 @@ }; &ohci0 { + dr_mode = "otg"; status = "okay"; }; @@ -322,7 +340,7 @@ }; usb0_pins: usb { - groups = "usb0_b"; + groups = "usb0_b", "usb0_id"; function = "usb0"; }; @@ -359,6 +377,7 @@ pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; + vbus-supply = <&vbus0_usb2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index a945db3c4644..8c9d7faa9e65 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -357,6 +357,51 @@ resets = <&cpg 407>; }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a77990", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x200>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 704>, <&cpg 703>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a77990-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a77990-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a77990", "renesas,rcar-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 2405eaad0296..48bb1d77744f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -179,6 +179,7 @@ }; &ehci0 { + dr_mode = "host"; status = "okay"; }; @@ -186,6 +187,11 @@ clock-frequency = <48000000>; }; +&hsusb { + dr_mode = "host"; + status = "okay"; +}; + &i2c0 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; @@ -337,6 +343,7 @@ }; &ohci0 { + dr_mode = "host"; status = "okay"; }; @@ -445,6 +452,7 @@ pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; + renesas,no-otg-pins; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 214f4954b321..8530d9fc1371 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -344,6 +344,51 @@ status = "disabled"; }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a77995", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x200>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 704>, <&cpg 703>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a77995-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a77995-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + canfd: can@e66c0000 { compatible = "renesas,r8a77995-canfd", "renesas,rcar-gen3-canfd"; -- cgit From 3b46fa57e350dc4fb72b8e02feb7fb218a3640d1 Mon Sep 17 00:00:00 2001 From: Yoshihiro Kaneko Date: Mon, 15 Oct 2018 11:59:23 +0200 Subject: arm64: dts: renesas: r8a77990: Add Audio-DMAC and Sound device nodes This patch adds Audio-DMAC0 device node and Sound device node for the R8A77990 SoC. Based on work by Takeshi Kihara and Hai Nguyen Pham. Signed-off-by: Yoshihiro Kaneko [simon: dropped include update, which is already present] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 271 ++++++++++++++++++++++++++++++ 1 file changed, 271 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 8c9d7faa9e65..887b066211a2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -25,6 +25,29 @@ i2c7 = &i2c7; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -933,6 +956,254 @@ }; }; + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A77990_CLK_ZA2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma0 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma0 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma0 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma0 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma0 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma0 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma0 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma0 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma0 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma0 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma0 0x02>, + <&audma0 0x15>, <&audma0 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma0 0x04>, + <&audma0 0x49>, <&audma0 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma0 0x06>, + <&audma0 0x63>, <&audma0 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma0 0x08>, + <&audma0 0x6f>, <&audma0 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma0 0x0a>, + <&audma0 0x71>, <&audma0 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma0 0x0c>, + <&audma0 0x73>, <&audma0 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma0 0x0e>, + <&audma0 0x75>, <&audma0 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma0 0x10>, + <&audma0 0x79>, <&audma0 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma0 0x12>, + <&audma0 0x7b>, <&audma0 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma0 0x14>, + <&audma0 0x7d>, <&audma0 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a77990", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, + <&ipmmu_mp 2>, <&ipmmu_mp 3>, + <&ipmmu_mp 4>, <&ipmmu_mp 5>, + <&ipmmu_mp 6>, <&ipmmu_mp 7>, + <&ipmmu_mp 8>, <&ipmmu_mp 9>, + <&ipmmu_mp 10>, <&ipmmu_mp 11>, + <&ipmmu_mp 12>, <&ipmmu_mp 13>, + <&ipmmu_mp 14>, <&ipmmu_mp 15>; + }; + xhci0: usb@ee000000 { compatible = "renesas,xhci-r8a77990", "renesas,rcar-gen3-xhci"; -- cgit From 56629fcba94c698d8c5be3413981506479566869 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Mon, 15 Oct 2018 11:59:24 +0200 Subject: arm64: dts: renesas: ebisu: Enable Audio This patch enables Audio for the Ebisu board on R8A77990 SoC. Signed-off-by: Takeshi Kihara [simon: rebased] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 127 +++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 038664e0cdcb..b178f261d805 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -29,6 +29,16 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; + audio_clkout: audio-clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2000/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + cvbs-in { compatible = "composite-video-connector"; label = "CVBS IN"; @@ -139,6 +149,32 @@ enable-active-high; }; + rsnd_ak4613: sound { + compatible = "simple-scu-audio-card"; + + simple-audio-card,name = "rsnd-ak4613"; + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcpu>; + simple-audio-card,frame-master = <&sndcpu>; + + simple-audio-card,prefix = "ak4613"; + simple-audio-card,routing = "ak4613 Playback", "DAI0 Playback", + "DAI0 Capture", "ak4613 Capture"; + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4613>; + }; + }; + + x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + x13_clk: x13 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -146,6 +182,10 @@ }; }; +&audio_clk_a { + clock-frequency = <22579200>; +}; + &avb { pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; @@ -287,6 +327,37 @@ }; }; +&i2c3 { + status = "okay"; + + ak4613: codec@10 { + compatible = "asahi-kasei,ak4613"; + #sound-dai-cells = <0>; + reg = <0x10>; + clocks = <&rcar_sound 3>; + + asahi-kasei,in1-single-end; + asahi-kasei,in2-single-end; + asahi-kasei,out1-single-end; + asahi-kasei,out2-single-end; + asahi-kasei,out3-single-end; + asahi-kasei,out4-single-end; + asahi-kasei,out5-single-end; + asahi-kasei,out6-single-end; + }; + + cs2000: clk-multiplier@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; +}; + &lvds0 { status = "okay"; @@ -339,6 +410,17 @@ function = "pwm5"; }; + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a", + "audio_clkout_a", "audio_clkout1_a"; + function = "audio_clk"; + }; + usb0_pins: usb { groups = "usb0_b", "usb0_id"; function = "usb0"; @@ -364,6 +446,47 @@ status = "okay"; }; +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <12288000 11289600>; + clkout-lr-synchronous; + + status = "okay"; + + /* update to */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, + <&cpg CPG_CORE R8A77990_CLK_ZA2>; + + rcar_sound,dai { + dai0 { + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; + }; + +}; + &rwdt { timeout-sec = <60>; status = "okay"; @@ -373,6 +496,10 @@ status = "okay"; }; +&ssi1 { + shared-pin; +}; + &usb2_phy0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; -- cgit From cb202e7c5895437fbabd0e575cf2530c65763dde Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 24 Sep 2018 23:13:41 +0300 Subject: arm64: dts: renesas: r8a779{7|8}0: add TMU support Describe TMUs in the R8A779{7|8}0 device trees. Based on the original (and large) patches by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 65 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 65 +++++++++++++++++++++++++++++++ 2 files changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 4abd154bca1f..563428d1cdc2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -329,6 +329,71 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a77970", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a77970", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a77970", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a77970", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a77970", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a77970", "renesas,rcar-gen3-i2c"; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index ce2c9955df75..5bd9b2547c36 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -359,6 +359,71 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a77980", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a77980", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a77980", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a77980", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a77980", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a77980", "renesas,rcar-gen3-i2c"; -- cgit From f0c083b88aa74e273c1c708ccc2d7ff0820cc319 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 5 Nov 2018 13:18:41 +0530 Subject: arm64: allwinner: h6: Add common orangepi nodes into dtsi Based on the information from hardware schematics and orangepi vendor orangepi H6 boards, One Plus and Lite2 shares common nodes like axp805, uart, mmc0 etc. The common differences between them is - One Plus, has Ethernet - Lite2, has Wifi, USB3, CSI port. So, add common orangepi nodes into sun50i-h6-orangepi.dtsi so-that it case use on respective orangepi h6 board dts files. Cc: zhaoyifan Signed-off-by: Jagan Teki Signed-off-by: Maxime Ripard --- .../dts/allwinner/sun50i-h6-orangepi-one-plus.dts | 140 +------------------ .../boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 150 +++++++++++++++++++++ 2 files changed, 151 insertions(+), 139 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts index 0612c19cd994..12e17567ab56 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts @@ -4,147 +4,9 @@ * Author: Jagan Teki */ -/dts-v1/; - -#include "sun50i-h6.dtsi" - -#include +#include "sun50i-h6-orangepi.dtsi" / { model = "OrangePi One Plus"; compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&r_i2c { - status = "okay"; - - axp805: pmic@36 { - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ac200"; - }; - - reg_aldo3: aldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc25-dram"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-bias-pll"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-efuse-pcie-hdmi-io"; - }; - - reg_bldo3: bldo3 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dcxoio"; - }; - - bldo4 { - /* unused */ - }; - - reg_cldo1: cldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <960000>; - regulator-max-microvolt = <960000>; - regulator-name = "vdd-sys"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi new file mode 100644 index 000000000000..0612c19cd994 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2018 Amarula Solutions + * Author: Jagan Teki + */ + +/dts-v1/; + +#include "sun50i-h6.dtsi" + +#include + +/ { + model = "OrangePi One Plus"; + compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_cldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp805: pmic@36 { + compatible = "x-powers,axp805", "x-powers,axp806"; + reg = <0x36>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + x-powers,self-working-mode; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ac200"; + }; + + reg_aldo3: aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc25-dram"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-bias-pll"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-efuse-pcie-hdmi-io"; + }; + + reg_bldo3: bldo3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dcxoio"; + }; + + bldo4 { + /* unused */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <960000>; + regulator-name = "vdd-sys"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; -- cgit From cee98cefbf6d1d651e6bc4fbff43e276f7fbde5f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 5 Nov 2018 13:18:42 +0530 Subject: arm64: allwinner: h6: Add OrangePi Lite2 initial support OrangePi Lite2 is Allwinner H6 based open-source SBC, which support: - Allwinner H6 Quad-core 64-bit ARM Cortex-A53 - GPU Mali-T720 - 1GB LPDDR3 RAM - AXP805 PMIC - AP6356S Wifi/BT - USB 2.0, USB 3.0 Host, OTG - HDMI port - 5V/2A DC power supply Signed-off-by: Jagan Teki Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/Makefile | 1 + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 8d4f97f279e0..38f4a015637c 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -18,5 +18,6 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts new file mode 100644 index 000000000000..e098a2475f2d --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2018 Jagan Teki + */ + +#include "sun50i-h6-orangepi.dtsi" + +/ { + model = "OrangePi Lite2"; + compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6"; +}; -- cgit From b7a1da2193e635373a80238137720e86e8ff4119 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Sun, 21 Oct 2018 06:30:27 +0900 Subject: arm64: dts: renesas: r8a77990: Add all HSCIF nodes This patch adds the device nodes for all HSCIF serial ports to the R8A77990 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 88 +++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 887b066211a2..beb53aaa9e2c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -380,6 +380,94 @@ resets = <&cpg 407>; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77990", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A77990_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a77990", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A77990_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a77990", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A77990_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77990", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A77990_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a77990", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A77990_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + hsusb: usb@e6590000 { compatible = "renesas,usbhs-r8a77990", "renesas,rcar-gen3-usbhs"; -- cgit From 26ff86f7794b9466481ccf29ac79925d327f106d Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Thu, 20 Sep 2018 13:18:47 +0200 Subject: ARM: dts: BCM5301X: Relicense BCM47081/BCM4709 files to the GPL 2.0+ / MIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches licensing used by other BCM5301X files and is preferred as: 1) GPL 2.0+ makes it clearly compatible with Linux kernel 2) MIT is also permissive but preferred over ISC Both files were fully developed by me. Commits touching them were signed by Florian and Hauke due to submitting process only. Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47081.dtsi | 13 +------------ arch/arm/boot/dts/bcm4709.dtsi | 3 +-- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/bcm47081.dtsi b/arch/arm/boot/dts/bcm47081.dtsi index 9829d044aaf4..ed13af028528 100644 --- a/arch/arm/boot/dts/bcm47081.dtsi +++ b/arch/arm/boot/dts/bcm47081.dtsi @@ -1,20 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Broadcom BCM470X / BCM5301X ARM platform code. * DTS for BCM47081 SoC. * * Copyright © 2014 RafaÅ‚ MiÅ‚ecki - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH - * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, - * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM - * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE - * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. */ #include "bcm5301x.dtsi" diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/bcm4709.dtsi index c645fea2b7f7..e1bb8661955f 100644 --- a/arch/arm/boot/dts/bcm4709.dtsi +++ b/arch/arm/boot/dts/bcm4709.dtsi @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (C) 2016 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the ISC license. */ #include "bcm4708.dtsi" -- cgit From d10967344375026ca8762b6080dec2585d895906 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Thu, 20 Sep 2018 13:20:19 +0200 Subject: ARM: dts: BCM5301X: Relicense BCM47094 file to the GPL 2.0+ / MIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches licensing used by other BCM5301X files and is preferred as: 1) GPL 2.0+ makes it clearly compatible with Linux kernel 2) MIT is also permissive but preferred over ISC This file has been developed by me & once modified by Vivek. Signed-off-by: RafaÅ‚ MiÅ‚ecki Acked-by: Vivek Unune Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi index f7c3e274b354..cdc5ff593adb 100644 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (C) 2016 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the ISC license. */ #include "bcm4708.dtsi" -- cgit From 1c9001b4f69a37820862286b3bbcdde152a52dcf Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Thu, 20 Sep 2018 13:37:47 +0200 Subject: ARM: dts: BCM53573: Relicense Tenda AC9 file to the GPL 2.0+ / MIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches licensing used by most of BCM5301X files and is preferred as: 1) GPL 2.0+ makes it clearly compatible with Linux kernel 2) MIT is also permissive but preferred over ISC This file was fully developed by me. Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts index 19e61b5b066c..e15e2a1e9d8c 100644 --- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (C) 2016 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the ISC license. */ /dts-v1/; -- cgit From 2af764dfb5eec71c4d3df81498c171cea917ffe4 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 20 Mar 2015 16:30:21 -0700 Subject: ARM: dts: BCM63xx: enable SATA PHY and AHCI controller Add Device Tree entries for the Broadcom AHCI and SATA PHY controller found on BCM63138 SoCs Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm63138.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index 6df61518776f..f59764008b9c 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -143,6 +143,37 @@ reg = <0x4800e0 0x10>; #reset-cells = <2>; }; + + ahci: sata@8000 { + compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci"; + reg-names = "ahci", "top-ctrl"; + reg = <0xa000 0x9ac>, <0x8040 0x24>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + resets = <&pmb0 3 1>; + reset-names = "ahci"; + status = "disabled"; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy0>; + }; + }; + + sata_phy: sata-phy@8100 { + compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3"; + reg = <0x8100 0x1e00>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; }; /* Legacy UBUS base */ -- cgit From ae269963f99065ab136567f7f2f7c6db3ec01049 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 20 Sep 2018 11:51:27 -0700 Subject: ARM: dts: BCM63xx: Enable SATA AHCI and PHY for BCM963138DVT The Broadcom BCM963138DVT board has an eSATA port which is fully functional, turn on the AHCI controller and the companion SATA PHY. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm963138dvt.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts index c61673638fa8..8dca97eeaf57 100644 --- a/arch/arm/boot/dts/bcm963138dvt.dts +++ b/arch/arm/boot/dts/bcm963138dvt.dts @@ -41,3 +41,11 @@ brcm,nand-oob-sectors-size = <16>; }; }; + +&ahci { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; -- cgit From ca3a6e705cad10662827093d5426abe078861793 Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Thu, 20 Sep 2018 13:39:28 +0200 Subject: ARM: dts: BCM53573: Relicense SoC file to the GPL 2.0+ / MIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This matches licensing used by most of BCM5301X files and is preferred as: 1) GPL 2.0+ makes it clearly compatible with Linux kernel 2) MIT is also permissive but preferred over ISC This file has been developed by me & once modified by Rob dropping a single leading zero in an UART address. Signed-off-by: RafaÅ‚ MiÅ‚ecki Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53573.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index 453a2a37dabd..5054fa9eb0d0 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -1,7 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (C) 2016 RafaÅ‚ MiÅ‚ecki - * - * Licensed under the ISC license. */ #include -- cgit From f60d405a870f9c194a6e3001612d9e8556493440 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 29 Oct 2018 09:55:23 -0700 Subject: ARM: dts: NSP: Move aliases to bcm-nsp.dtsi All boards replicate the aliases node, move the aliases node to bcm-nsp.dtsi and add all the serial and ethernet ports such that a boot program like u-boot can populate MAC addresses accordingly. Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 8 ++++++++ arch/arm/boot/dts/bcm958522er.dts | 4 ---- arch/arm/boot/dts/bcm958525er.dts | 4 ---- arch/arm/boot/dts/bcm958525xmc.dts | 4 ---- arch/arm/boot/dts/bcm958622hr.dts | 4 ---- arch/arm/boot/dts/bcm958623hr.dts | 4 ---- arch/arm/boot/dts/bcm958625hr.dts | 4 ---- arch/arm/boot/dts/bcm958625k.dts | 5 ----- arch/arm/boot/dts/bcm988312hr.dts | 4 ---- 9 files changed, 8 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 2fd111d9d59c..0d2538b46139 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -41,6 +41,14 @@ model = "Broadcom Northstar Plus SoC"; interrupt-parent = <&gic>; + aliases { + serial0 = &uart0; + serial1 = &uart1; + ethernet0 = &amac0; + ethernet1 = &amac1; + ethernet2 = &amac2; + }; + cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts index f9dd342cc2ae..21479b4ce823 100644 --- a/arch/arm/boot/dts/bcm958522er.dts +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -39,10 +39,6 @@ model = "NorthStar Plus SVK (BCM958522ER)"; compatible = "brcm,bcm58522", "brcm,nsp"; - aliases { - serial0 = &uart0; - }; - chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts index 374508a9cfbf..cda3d790965b 100644 --- a/arch/arm/boot/dts/bcm958525er.dts +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -39,10 +39,6 @@ model = "NorthStar Plus SVK (BCM958525ER)"; compatible = "brcm,bcm58525", "brcm,nsp"; - aliases { - serial0 = &uart0; - }; - chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index 403250c5ad8e..f86649812b59 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -39,10 +39,6 @@ model = "NorthStar Plus XMC (BCM958525xmc)"; compatible = "brcm,bcm58525", "brcm,nsp"; - aliases { - serial0 = &uart0; - }; - chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts index ecd05e26c262..df60602b054d 100644 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -39,10 +39,6 @@ model = "NorthStar Plus SVK (BCM958622HR)"; compatible = "brcm,bcm58622", "brcm,nsp"; - aliases { - serial0 = &uart0; - }; - chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index f5e85b301497..3893e7af343a 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -39,10 +39,6 @@ model = "NorthStar Plus SVK (BCM958623HR)"; compatible = "brcm,bcm58623", "brcm,nsp"; - aliases { - serial0 = &uart0; - }; - chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index a53a2f629d74..cf226b02141f 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -39,10 +39,6 @@ model = "NorthStar Plus SVK (BCM958625HR)"; compatible = "brcm,bcm58625", "brcm,nsp"; - aliases { - serial0 = &uart0; - }; - chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 3ea5f739e90b..10b3d512bb33 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -38,11 +38,6 @@ model = "NorthStar Plus SVK (BCM958625K)"; compatible = "brcm,bcm58625", "brcm,nsp"; - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts index ea9a0806b446..e39db14d805e 100644 --- a/arch/arm/boot/dts/bcm988312hr.dts +++ b/arch/arm/boot/dts/bcm988312hr.dts @@ -39,10 +39,6 @@ model = "NorthStar Plus SVK (BCM988312HR)"; compatible = "brcm,bcm88312", "brcm,nsp"; - aliases { - serial0 = &uart0; - }; - chosen { stdout-path = "serial0:115200n8"; }; -- cgit From 505a2fd80b4dcd9e89bcf426ba4314ea339911e8 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 4 Jun 2018 11:36:13 +0200 Subject: arm64: dts: rockchip: add Gru Scarlet devicetrees Gru-Scarlet is a tablet device using ChomeOS, dual-dsi display and Wacom touchscreen with stylus. There exist two variants in the market using different displays that are differentiated via their sku-id. The bootloader on them also determines the correct devicetree to load via the sku-id. So add a common scarlet dtsi and two minimal board devicetrees for the two display variants. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/rockchip.txt | 34 ++ arch/arm64/boot/dts/rockchip/Makefile | 2 + .../boot/dts/rockchip/rk3399-gru-scarlet-inx.dts | 33 ++ .../boot/dts/rockchip/rk3399-gru-scarlet-kd.dts | 33 ++ .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 594 +++++++++++++++++++++ 5 files changed, 696 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 0cc71236d639..7ce7382fedd8 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -152,6 +152,40 @@ Rockchip platforms device tree bindings - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", "google,veyron", "rockchip,rk3288"; +- Google Scarlet - with display from Kingdisplay + Required root node properties: + - compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15", + "google,scarlet-rev14-sku7", "google,scarlet-rev14", + "google,scarlet-rev13-sku7", "google,scarlet-rev13", + "google,scarlet-rev12-sku7", "google,scarlet-rev12", + "google,scarlet-rev11-sku7", "google,scarlet-rev11", + "google,scarlet-rev10-sku7", "google,scarlet-rev10", + "google,scarlet-rev9-sku7", "google,scarlet-rev9", + "google,scarlet-rev8-sku7", "google,scarlet-rev8", + "google,scarlet-rev7-sku7", "google,scarlet-rev7", + "google,scarlet-rev6-sku7", "google,scarlet-rev6", + "google,scarlet-rev5-sku7", "google,scarlet-rev5", + "google,scarlet-rev4-sku7", "google,scarlet-rev4", + "google,scarlet-rev3-sku7", "google,scarlet-rev3", + "google,scarlet", "google,gru", "rockchip,rk3399"; + +- Google Scarlet - with display from Innolux + Required root node properties: + - compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", + "google,scarlet-rev14-sku6", "google,scarlet-rev14", + "google,scarlet-rev13-sku6", "google,scarlet-rev13", + "google,scarlet-rev12-sku6", "google,scarlet-rev12", + "google,scarlet-rev11-sku6", "google,scarlet-rev11", + "google,scarlet-rev10-sku6", "google,scarlet-rev10", + "google,scarlet-rev9-sku6", "google,scarlet-rev9", + "google,scarlet-rev8-sku6", "google,scarlet-rev8", + "google,scarlet-rev7-sku6", "google,scarlet-rev7", + "google,scarlet-rev6-sku6", "google,scarlet-rev6", + "google,scarlet-rev5-sku6", "google,scarlet-rev5", + "google,scarlet-rev4-sku6", "google,scarlet-rev4", + "google,scarlet", "google,gru", "rockchip,rk3399"; + + - Google Speedy (Asus C201 Chromebook): Required root node properties: - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 49042c477870..de0c406c20cc 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -14,6 +14,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts new file mode 100644 index 000000000000..2d721a974790 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Scarlet Rev4+ (SKU-6/Innolux) board device tree source + * + * Copyright 2018 Google, Inc + */ + +/dts-v1/; + +#include "rk3399-gru-scarlet.dtsi" + +/ { + model = "Google Scarlet"; + compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", + "google,scarlet-rev14-sku6", "google,scarlet-rev14", + "google,scarlet-rev13-sku6", "google,scarlet-rev13", + "google,scarlet-rev12-sku6", "google,scarlet-rev12", + "google,scarlet-rev11-sku6", "google,scarlet-rev11", + "google,scarlet-rev10-sku6", "google,scarlet-rev10", + "google,scarlet-rev9-sku6", "google,scarlet-rev9", + "google,scarlet-rev8-sku6", "google,scarlet-rev8", + "google,scarlet-rev7-sku6", "google,scarlet-rev7", + "google,scarlet-rev6-sku6", "google,scarlet-rev6", + "google,scarlet-rev5-sku6", "google,scarlet-rev5", + "google,scarlet-rev4-sku6", "google,scarlet-rev4", + "google,scarlet", "google,gru", "rockchip,rk3399"; +}; + +&mipi_panel { + compatible = "innolux,p097pfg"; + avdd-supply = <&ppvarp_lcd>; + avee-supply = <&ppvarn_lcd>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dts new file mode 100644 index 000000000000..bd7592217270 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Scarlet Rev3+ (SKU-7/Kingdisplay) board device tree source + * + * Copyright 2018 Google, Inc + */ + +/dts-v1/; + +#include "rk3399-gru-scarlet.dtsi" + +/ { + model = "Google Scarlet"; + compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15", + "google,scarlet-rev14-sku7", "google,scarlet-rev14", + "google,scarlet-rev13-sku7", "google,scarlet-rev13", + "google,scarlet-rev12-sku7", "google,scarlet-rev12", + "google,scarlet-rev11-sku7", "google,scarlet-rev11", + "google,scarlet-rev10-sku7", "google,scarlet-rev10", + "google,scarlet-rev9-sku7", "google,scarlet-rev9", + "google,scarlet-rev8-sku7", "google,scarlet-rev8", + "google,scarlet-rev7-sku7", "google,scarlet-rev7", + "google,scarlet-rev6-sku7", "google,scarlet-rev6", + "google,scarlet-rev5-sku7", "google,scarlet-rev5", + "google,scarlet-rev4-sku7", "google,scarlet-rev4", + "google,scarlet-rev3-sku7", "google,scarlet-rev3", + "google,scarlet", "google,gru", "rockchip,rk3399"; +}; + +&mipi_panel { + compatible = "kingdisplay,kd097d04"; + power-supply = <&pp3300_s0>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi new file mode 100644 index 000000000000..fc50b3ef758c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-scarlet board device tree source + * + * Copyright 2018 Google, Inc + */ + +#include "rk3399-gru.dtsi" + +/{ + /* Power tree */ + + /* ppvar_sys children, sorted by name */ + pp1250_s3: pp1250-s3 { + compatible = "regulator-fixed"; + regulator-name = "pp1250_s3"; + + /* EC turns on w/ pp1250_s3_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + + vin-supply = <&ppvar_sys>; + }; + + pp1250_cam: pp1250-dvdd { + compatible = "regulator-fixed"; + regulator-name = "pp1250_dvdd"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1250_cam_en>; + + enable-active-high; + gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; + + /* 740us delay from gpio output high to pp1250 stable, + * rounding up to 1ms for safety. + */ + startup-delay-us = <1000>; + vin-supply = <&pp1250_s3>; + }; + + pp900_s0: pp900-s0 { + compatible = "regulator-fixed"; + regulator-name = "pp900_s0"; + + /* EC turns on w/ pp900_s0_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + ppvarn_lcd: ppvarn-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvarn_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&ppvarn_lcd_en>; + + enable-active-high; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + vin-supply = <&ppvar_sys>; + }; + + ppvarp_lcd: ppvarp-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvarp_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&ppvarp_lcd_en>; + + enable-active-high; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + vin-supply = <&ppvar_sys>; + }; + + /* pp1800 children, sorted by name */ + pp900_s3: pp900-s3 { + compatible = "regulator-fixed"; + regulator-name = "pp900_s3"; + + /* EC turns on w/ pp900_s3_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&pp1800>; + }; + + /* EC turns on pp1800_s3_en */ + pp1800_s3: pp1800 { + }; + + /* pp3300 children, sorted by name */ + pp2800_cam: pp2800-avdd { + compatible = "regulator-fixed"; + regulator-name = "pp2800_avdd"; + pinctrl-names = "default"; + pinctrl-0 = <&pp2800_cam_en>; + + enable-active-high; + gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + vin-supply = <&pp3300>; + }; + + /* EC turns on pp3300_s0_en */ + pp3300_s0: pp3300 { + }; + + /* EC turns on pp3300_s3_en */ + pp3300_s3: pp3300 { + }; + + /* + * See b/66922012 + * + * This is a hack to make sure the Bluetooth part of the QCA6174A + * is reset at boot by toggling BT_EN. At boot BT_EN is first set + * to low when the bt_3v3 regulator is registered (in disabled + * state). The fake regulator is configured as a supply of the + * wlan_3v3 regulator below. When wlan_3v3 is enabled early in + * the boot process it also enables its supply regulator bt_3v3, + * which changes BT_EN to high. + */ + bt_3v3: bt-3v3 { + compatible = "regulator-fixed"; + regulator-name = "bt_3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_1v8_l>; + + enable-active-high; + gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_s3>; + }; + + wlan_3v3: wlan-3v3 { + compatible = "regulator-fixed"; + regulator-name = "wlan_3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_pd_1v8_l>; + + /* + * The WL_EN pin is driven low when the regulator is + * registered, and transitions to high when the PCIe bus + * is powered up. + */ + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + /* + * Require minimum 10ms from power-on (e.g., PD#) to init PCIe. + * TODO (b/64444991): how long to assert PD#? + */ + regulator-enable-ramp-delay = <10000>; + /* See bt_3v3 hack above */ + vin-supply = <&bt_3v3>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwms = <&pwm1 0 1000000 0>; + pwm-delay-us = <10000>; + }; + + dmic: dmic { + compatible = "dmic-codec"; + dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dmic_en>; + wakeup-delay-ms = <250>; + }; +}; + +/* pp900_s0 aliases */ +pp900_ddrpll_ap: &pp900_s0 { +}; +pp900_pcie: &pp900_s0 { +}; +pp900_usb: &pp900_s0 { +}; + +/* pp900_s3 aliases */ +pp900_emmcpll: &pp900_s3 { +}; + +/* EC turns on; alias for pp1800_s0 */ +pp1800_pcie: &pp1800_s0 { +}; + +/* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */ +&ppvar_bigcpu { + ctrl-voltage-range = <800074 1299226>; + regulator-min-microvolt = <800074>; + regulator-max-microvolt = <1299226>; +}; + +&ppvar_bigcpu_pwm { + /* On scarlet ppvar big cpu use pwm3 */ + pwms = <&pwm3 0 3337 0>; + regulator-min-microvolt = <800074>; + regulator-max-microvolt = <1299226>; +}; + +&ppvar_litcpu { + ctrl-voltage-range = <802122 1199620>; + regulator-min-microvolt = <802122>; + regulator-max-microvolt = <1199620>; +}; + +&ppvar_litcpu_pwm { + regulator-min-microvolt = <802122>; + regulator-max-microvolt = <1199620>; +}; + +&ppvar_gpu { + ctrl-voltage-range = <799600 1099600>; + regulator-min-microvolt = <799600>; + regulator-max-microvolt = <1099600>; +}; + +&ppvar_gpu_pwm { + regulator-min-microvolt = <799600>; + regulator-max-microvolt = <1099600>; +}; + +&ppvar_sd_card_io { + states = <1800000 0x0 3300000 0x1>; + regulator-max-microvolt = <3300000>; +}; + +&pp3000_sd_slot { + vin-supply = <&pp3300>; +}; + +ap_i2c_dig: &i2c2 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times. */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + digitizer: digitizer@9 { + compatible = "hid-over-i2c"; + reg = <0x9>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pen_int_odl &pen_reset_l>; + }; +}; + +&ap_i2c_ts { + touchscreen: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int_l &touch_reset_l>; + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; +}; + +camera: &i2c7 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + /* 24M mclk is shared between world and user cameras */ + pinctrl-0 = <&i2c7_xfer &test_clkout1>; +}; + +&cdn_dp { + extcon = <&usbc_extcon0>; + phys = <&tcphy0_dp>; +}; + +&cpu_alert0 { + temperature = <66000>; +}; + +&cpu_alert1 { + temperature = <71000>; +}; + +&cros_ec { + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; +}; + +&cru { + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, + <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, + <&cru PCLK_PERIHP>, + <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, + <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>, + <&cru ACLK_GIC_PRE>, + <&cru PCLK_DDR>, + <&cru ACLK_HDCP>; + assigned-clock-rates = + <600000000>, <1600000000>, + <1000000000>, + <150000000>, <75000000>, + <37500000>, + <100000000>, <100000000>, + <50000000>, <800000000>, + <100000000>, <50000000>, + <400000000>, + <200000000>, + <200000000>, + <400000000>; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>, <&pen_eject_odl>; + + pen-insert { + label = "Pen Insert"; + /* Insert = low, eject = high */ + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; +}; + +&i2c_tunnel { + google,remote-bus = <0>; +}; + +&io_domains { + bt656-supply = <&pp1800_s0>; /* APIO2_VDD; 2a 2b */ + audio-supply = <&pp1800_s0>; /* APIO5_VDD; 3d 4a */ + gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ +}; + +&max98357a { + sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; +}; + +&mipi_dsi { + status = "okay"; + clock-master; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + mipi_panel: panel@0 { + /* 2 different panels are used, compatibles are in dts files */ + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&display_rst_l>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + + port@1 { + reg = <1>; + + mipi1_in_panel: endpoint@1 { + remote-endpoint = <&mipi1_out_panel>; + }; + }; + }; + }; +}; + +&mipi_dsi1 { + status = "okay"; + + ports { + mipi1_out: port@1 { + reg = <1>; + + mipi1_out_panel: endpoint { + remote-endpoint = <&mipi1_in_panel>; + }; + }; + }; +}; + +&pcie0 { + ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + + /* PERST# asserted in S3 */ + pcie-reset-suspend = <1>; + + vpcie3v3-supply = <&wlan_3v3>; + vpcie1v8-supply = <&pp1800_pcie>; +}; + +&sdmmc { + cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +}; + +&sound { + rockchip,codec = <&max98357a &dmic &codec &cdn_dp>; +}; + +&spi2 { + status = "okay"; +}; + +&wake_on_bt { + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; +}; + +/* PINCTRL OVERRIDES */ +&ec_ap_int_l { + rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&ap_fw_wp { + rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&bl_en { + rockchip,pins = <4 21 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&bt_host_wake_l { + rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&ec_ap_int_l { + rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&headset_int_l { + rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&i2s0_8ch_bus { + rockchip,pins = + <3 24 RK_FUNC_1 &pcfg_pull_none_6ma>, + <3 25 RK_FUNC_1 &pcfg_pull_none_6ma>, + <3 26 RK_FUNC_1 &pcfg_pull_none_6ma>, + <3 27 RK_FUNC_1 &pcfg_pull_none_6ma>, + <3 31 RK_FUNC_1 &pcfg_pull_none_6ma>, + <4 0 RK_FUNC_1 &pcfg_pull_none_6ma>; +}; + +/* there is no external pull up, so need to set this pin pull up */ +&sdmmc_cd_gpio { + rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&sd_pwr_1800_sel { + rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&sdmode_en { + rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_down>; +}; + +&touch_reset_l { + rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_down>; +}; + +&touch_int_l { + rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_down>; +}; + +&pinctrl { + pinctrl-0 = < + &ap_pwroff /* AP will auto-assert this when in S3 */ + &clk_32k /* This pin is always 32k on gru boards */ + &wlan_rf_kill_1v8_l + >; + + pcfg_pull_none_6ma: pcfg-pull-none-6ma { + bias-disable; + drive-strength = <6>; + }; + + camera { + pp1250_cam_en: pp1250-dvdd { + rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pp2800_cam_en: pp2800-avdd { + rockchip,pins = <2 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ucam_rst: ucam_rst { + rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wcam_rst: wcam_rst { + rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + digitizer { + pen_int_odl: pen-int-odl { + rockchip,pins = <1 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pen_reset_l: pen-reset-l { + rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + discrete-regulators { + display_rst_l: display-rst-l { + rockchip,pins = <4 25 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ppvarp_lcd_en: ppvarp-lcd-en { + rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ppvarn_lcd_en: ppvarn-lcd-en { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dmic { + dmic_en: dmic-en { + rockchip,pins = <4 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pen { + pen_eject_odl: pen-eject-odl { + rockchip,pins = <1 1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + tpm { + h1_int_od_l: h1-int-od-l { + rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&wifi { + bt_en_1v8_l: bt-en-1v8-l { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_pd_1v8_l: wlan-pd-1v8-l { + rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* Default pull-up, but just to be clear */ + wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_perst_l: wifi-perst-l { + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_host_wake_l: wlan-host-wake-l { + rockchip,pins = <1 3 RK_FUNC_GPIO &pcfg_pull_up>; + }; +}; -- cgit From 9fd609ff6380a7a583fee162b2dcf9be1576847f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 26 Sep 2018 13:24:20 +0200 Subject: arm64: dts: zynqmp: Use mmc@ instead sdhci@ mmc name is recommended based on devicetree specification. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 29ce23422acf..dacabde6ff7e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -484,7 +484,7 @@ interrupts = <0 133 4>; }; - sdhci0: sdhci@ff160000 { + sdhci0: mmc@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -493,7 +493,7 @@ clock-names = "clk_xin", "clk_ahb"; }; - sdhci1: sdhci@ff170000 { + sdhci1: mmc@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; -- cgit From 1696acf44e9f26454f15877bee3a9a39ec6e6ee5 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Wed, 24 Oct 2018 12:45:40 +0100 Subject: arm64: dts: zynqmp: replace gpio-key,wakeup with wakeup-source property Most of the legacy "gpio-key,wakeup" boolean property is already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. This patch replaces the legacy properties with the unified "wakeup-source" property introduced by: "Input: gpio_keys - switch to using generic device properties" (sha1: 700a38b27eefc582099fdf69effacfad0ad738a4) Cc: Michal Simek Signed-off-by: Sudeep Holla Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index eb5e8bddb610..527b4d0f88e2 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -49,7 +49,7 @@ label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 25dd57485323..0397bf66b2e7 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -46,7 +46,7 @@ label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 259f21b0c001..7238f022a671 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -46,7 +46,7 @@ label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index a61b3cc6f4c9..fa055e718d4b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -46,7 +46,7 @@ label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; -- cgit From e7abd89466df421d22ebda095e00d36976dbdacb Mon Sep 17 00:00:00 2001 From: Manish Narani Date: Thu, 25 Oct 2018 11:37:00 +0530 Subject: arm64: dts: zynqmp: Add DDRC node Add ddrc memory controller node in dts. The size mentioned in dts is 0x30000, because we need to access DDR_QOS INTR registers located at 0xFD090208 from this driver. Signed-off-by: Manish Narani Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index dacabde6ff7e..07f2dd13ab33 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -355,6 +355,13 @@ xlnx,bus-width = <64>; }; + mc: memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0x0 0xfd070000 0x0 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; + }; + gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; -- cgit From 5f65328df3f5cd25af741638153929d3c7ad4d8a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 4 Nov 2018 21:37:07 +0100 Subject: arm64: dts: renesas: Switch eMMC bus to 1V8 on Salvator-X and ULCB The eMMC card has two supplies, VCC and VCCQ. The VCC supplies the NAND array and the VCCQ supplies the bus. On Salvator-X and ULCB, the VCC is connected to 3.3V rail, while the VCCQ is connected to 1.8V rail. Adjust the pinmux to match the bus, which is always operating in 1.8V mode. While at it, deduplicate the pinmux entries, which are now the same for both default and UHS modes. We still need the two pinctrl entries to match the bindings though. Signed-off-by: Marek Vasut Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 8 +------- arch/arm64/boot/dts/renesas/ulcb.dtsi | 8 +------- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index a3e89504e044..f66d990b92f1 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -605,12 +605,6 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; @@ -763,7 +757,7 @@ &sdhi2 { /* used for on-board 8bit eMMC */ pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-1 = <&sdhi2_pins>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 89daca7356df..de694fdae067 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -330,12 +330,6 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; - function = "sdhi2"; - power-source = <3300>; - }; - - sdhi2_pins_uhs: sd2_uhs { groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; @@ -426,7 +420,7 @@ &sdhi2 { /* used for on-board 8bit eMMC */ pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-1 = <&sdhi2_pins>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; -- cgit From a2aabe5f3c57fabefe369b636db3df86874218be Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 17 Sep 2018 09:22:22 +0100 Subject: dt-bindings: soc: Document "brcm,bcm2836-vchiq" "brcm,bcm2836-vchiq" should be used on BCM2836 and BCM2837 to ensure correct operation. Signed-off-by: Phil Elwell Acked-by: Stefan Wahren Signed-off-by: Stefan Wahren --- Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt index 8dd7b3a7de65..f331316183f6 100644 --- a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt +++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt @@ -2,7 +2,8 @@ Broadcom VCHIQ firmware services Required properties: -- compatible: Should be "brcm,bcm2835-vchiq" +- compatible: Should be "brcm,bcm2835-vchiq" on BCM2835, otherwise + "brcm,bcm2836-vchiq". - reg: Physical base address and length of the doorbell register pair - interrupts: The interrupt number See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt -- cgit From 499770ede3f829e80539f46b59b5f460dc327aa6 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 17 Sep 2018 09:22:23 +0100 Subject: ARM: dts: bcm283x: Correct vchiq compatible string To allow VCHIQ to determine the correct cache line size, use the new "brcm,bcm2836-vchiq" compatible string on BCM2836 and BCM2837. Signed-off-by: Phil Elwell Acked-by: Stefan Wahren Signed-off-by: Stefan Wahren --- arch/arm/boot/dts/bcm2835-rpi.dtsi | 2 +- arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 2 +- arch/arm/boot/dts/bcm2836-rpi.dtsi | 6 ++++++ arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 2 +- arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi | 2 +- 6 files changed, 11 insertions(+), 5 deletions(-) create mode 100644 arch/arm/boot/dts/bcm2836-rpi.dtsi diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index cb2d6d78a7fb..215d8cc4f96b 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -30,7 +30,7 @@ #power-domain-cells = <1>; }; - mailbox@7e00b840 { + vchiq: mailbox@7e00b840 { compatible = "brcm,bcm2835-vchiq"; reg = <0x7e00b840 0xf>; interrupts = <0 2>; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index 2fef70a09953..ac4408b34b58 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2836.dtsi" -#include "bcm2835-rpi.dtsi" +#include "bcm2836-rpi.dtsi" #include "bcm283x-rpi-smsc9514.dtsi" #include "bcm283x-rpi-usb-host.dtsi" diff --git a/arch/arm/boot/dts/bcm2836-rpi.dtsi b/arch/arm/boot/dts/bcm2836-rpi.dtsi new file mode 100644 index 000000000000..c4c858b984c6 --- /dev/null +++ b/arch/arm/boot/dts/bcm2836-rpi.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm2835-rpi.dtsi" + +&vchiq { + compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq"; +}; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index 4adb85e66be3..eca36e3ae6c2 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2837.dtsi" -#include "bcm2835-rpi.dtsi" +#include "bcm2836-rpi.dtsi" #include "bcm283x-rpi-lan7515.dtsi" #include "bcm283x-rpi-usb-host.dtsi" diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index c318bcbc6ba7..a0ba0f68d22b 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2837.dtsi" -#include "bcm2835-rpi.dtsi" +#include "bcm2836-rpi.dtsi" #include "bcm283x-rpi-smsc9514.dtsi" #include "bcm283x-rpi-usb-host.dtsi" diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi index 7b7ab6aea988..4a89a1885a3d 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2837.dtsi" -#include "bcm2835-rpi.dtsi" +#include "bcm2836-rpi.dtsi" / { memory { -- cgit From 227fa865061470a568858baa404a508f6c030fe4 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Mon, 17 Sep 2018 09:22:24 +0100 Subject: ARM: dts: bcm283x: Correct mailbox register sizes The size field in a Device Tree "reg" property is encoded in bytes, not words. Fixes: 614fa22119d6 ("ARM: dts: bcm2835: Add VCHIQ node to the Raspberry Pi boards. (v3)") Signed-off-by: Phil Elwell Acked-by: Stefan Wahren Signed-off-by: Stefan Wahren --- arch/arm/boot/dts/bcm2835-rpi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index 215d8cc4f96b..29f970f864dc 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -32,7 +32,7 @@ vchiq: mailbox@7e00b840 { compatible = "brcm,bcm2835-vchiq"; - reg = <0x7e00b840 0xf>; + reg = <0x7e00b840 0x3c>; interrupts = <0 2>; }; }; -- cgit From 209065c5fd72300c09b400369956c7bb4476147a Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 4 Nov 2018 19:27:04 +0100 Subject: arm64: dts: allwinner: h6: Add HDMI pipeline This commit adds all entries needed for HDMI to function properly. Signed-off-by: Jernej Skrabec [added DE3 bus] Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 201 +++++++++++++++++++++++++++ 1 file changed, 201 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 11f7ce7d1876..45bbb5116446 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -6,8 +6,11 @@ #include #include #include +#include +#include #include #include +#include / { interrupt-parent = <&gic>; @@ -47,6 +50,12 @@ }; }; + de: display-engine { + compatible = "allwinner,sun50i-h6-display-engine"; + allwinner,pipelines = <&mixer0>; + status = "disabled"; + }; + iosc: internal-osc-clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -92,6 +101,51 @@ #size-cells = <1>; ranges; + display-engine@1000000 { + compatible = "allwinner,sun50i-h6-de3", + "allwinner,sun50i-a64-de2"; + reg = <0x1000000 0x400000>; + allwinner,sram = <&de2_sram 1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000000 0x400000>; + + display_clocks: clock@0 { + compatible = "allwinner,sun50i-h6-de3-clk"; + reg = <0x0 0x10000>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@100000 { + compatible = "allwinner,sun50i-h6-de3-mixer-0"; + reg = <0x100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + + mixer0_out_tcon_top_mixer0: endpoint { + remote-endpoint = <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + }; + syscon: syscon@3000000 { compatible = "allwinner,sun50i-h6-system-control", "allwinner,sun50i-a64-system-control"; @@ -157,6 +211,11 @@ drive-strength = <40>; }; + hdmi_pins: hdmi-pins { + pins = "PH8", "PH9", "PH10"; + function = "hdmi"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -286,6 +345,148 @@ }; }; + hdmi: hdmi@6000000 { + compatible = "allwinner,sun50i-h6-dw-hdmi"; + reg = <0x06000000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, + <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; + clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", + "hdcp-bus"; + resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; + reset-names = "ctrl", "hdcp"; + phys = <&hdmi_phy>; + phy-names = "hdmi-phy"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon_top: endpoint { + remote-endpoint = <&tcon_top_hdmi_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@6010000 { + compatible = "allwinner,sun50i-h6-hdmi-phy"; + reg = <0x06010000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_HDMI>; + reset-names = "phy"; + #phy-cells = <0>; + }; + + tcon_top: tcon-top@6510000 { + compatible = "allwinner,sun50i-h6-tcon-top"; + reg = <0x06510000 0x1000>; + clocks = <&ccu CLK_BUS_TCON_TOP>, + <&ccu CLK_TCON_TV0>; + clock-names = "bus", + "tcon-tv0"; + clock-output-names = "tcon-top-tv0"; + resets = <&ccu RST_BUS_TCON_TOP>; + reset-names = "rst"; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon_top_mixer0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_top_mixer0_out_tcon_tv: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; + }; + }; + + tcon_top_hdmi_in: port@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + tcon_top_hdmi_in_tcon_tv: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_tv_out_tcon_top>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg = <5>; + + tcon_top_hdmi_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_tcon_top>; + }; + }; + }; + }; + + tcon_tv: lcd-controller@6515000 { + compatible = "allwinner,sun50i-h6-tcon-tv", + "allwinner,sun8i-r40-tcon-tv"; + reg = <0x06515000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_TV0>, + <&tcon_top CLK_TCON_TOP_TV0>; + clock-names = "ahb", + "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV0>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv_in: port@0 { + reg = <0>; + + tcon_tv_in_tcon_top_mixer0: endpoint { + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; + }; + }; + + tcon_tv_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_tv_out_tcon_top: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; + }; + }; + }; + }; + r_ccu: clock@7010000 { compatible = "allwinner,sun50i-h6-r-ccu"; reg = <0x07010000 0x400>; -- cgit From 7d5bca1cca18e522ba214efead58a4400a7e53a9 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 4 Nov 2018 19:27:05 +0100 Subject: arm64: dts: allwinner: h6: Enable HDMI output on Pine H64 board Pine H64 board has HDMI type A connector. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index fcf3c1de4aa2..59e5464742b0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -22,6 +22,17 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -60,6 +71,20 @@ }; }; +&de { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; -- cgit From 279e57c39efe0c4308425ebb5f96a98e618777bb Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 21 Oct 2018 21:30:48 +0300 Subject: ARM: dts: tegra20: Add interrupt entry to External Memory Controller Add interrupt entry into the EMC DT node. Signed-off-by: Dmitry Osipenko Acked-by: Peter De Schrijver Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 20869757d32f..526f623f201a 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -632,6 +632,7 @@ memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; }; -- cgit From cd9f69800b2a7a47981c397e008f6040fadc4523 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 21 Oct 2018 21:30:49 +0300 Subject: ARM: dts: tegra20: Add clock entry to External Memory Controller Add clock entry into the EMC DT node. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 526f623f201a..dcad6d6128cf 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -633,6 +633,7 @@ compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; }; -- cgit From ad348c3f55962c86adf9c8cb3712825fb7db5336 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 28 Sep 2018 15:11:46 +0100 Subject: dt-bindings: usb: xhci-tegra: Add power-domain details Add details for power-domains to the Tegra xHCI bindings so that generic power-domains can be used for inconjunction with the xHCI driver. Signed-off-by: Jon Hunter Acked-by: Thierry Reding Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt index 3eee9e505400..4156c3e181c5 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt @@ -59,6 +59,14 @@ For Tegra210: - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V. - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V. - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V. +- power-domains: A list of PM domain specifiers that reference each power-domain + used by the xHCI controller. This list must comprise of a specifier for the + XUSBA and XUSBC power-domains. See ../power/power_domain.txt and + ../arm/tegra/nvidia,tegra20-pmc.txt for details. +- power-domain-names: A list of names that represent each of the specifiers in + the 'power-domains' property. Must include 'xusb_ss' and 'xusb_host' which + represent the power-domains XUSBA and XUSBC, respectively. See + ../power/power_domain.txt for details. Optional properties: -------------------- -- cgit From a6cb8ef03cb0f03e3567f91ab9aeb2f0f6337810 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 21 Oct 2018 21:30:45 +0300 Subject: dt: bindings: tegra20-emc: Document interrupt property EMC has a dedicated interrupt that is used to notify about completion of HW operations. Document the interrupt property. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Acked-by: Peter De Schrijver Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt index 4c33b29dc660..a6fe401d0d48 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt @@ -10,6 +10,7 @@ Properties: and chosen using the ramcode board selector. If omitted, only one set of tables can be present and said tables will be used irrespective of ram-code configuration. +- interrupts : Should contain EMC General interrupt. Child device nodes describe the memory settings for different configurations and clock rates. @@ -20,6 +21,7 @@ Example: #size-cells = < 0 >; compatible = "nvidia,tegra20-emc"; reg = <0x7000f4000 0x200>; + interrupts = <0 78 0x04>; } -- cgit From 28016aa1652e64e143b88baacbb13f121894f260 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 21 Oct 2018 21:30:46 +0300 Subject: dt: bindings: tegra20-emc: Document clock property Embedded memory controller has a corresponding clock, document the clock property. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt index a6fe401d0d48..add95367640b 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt @@ -11,6 +11,7 @@ Properties: set of tables can be present and said tables will be used irrespective of ram-code configuration. - interrupts : Should contain EMC General interrupt. +- clocks : Should contain EMC clock. Child device nodes describe the memory settings for different configurations and clock rates. @@ -22,6 +23,7 @@ Example: compatible = "nvidia,tegra20-emc"; reg = <0x7000f4000 0x200>; interrupts = <0 78 0x04>; + clocks = <&tegra_car TEGRA20_CLK_EMC>; } -- cgit From 94ba4a5f16710eaa3a675761a7900bb9f79715db Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 21 Oct 2018 21:30:47 +0300 Subject: dt: bindings: Move tegra20-emc binding to memory-controllers directory Move tegra20-emc binding to the memory-controllers directory for consistency with the other Tegra memory bindings. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/arm/tegra/nvidia,tegra20-emc.txt | 104 --------------------- .../memory-controllers/nvidia,tegra20-emc.txt | 104 +++++++++++++++++++++ 2 files changed, 104 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt deleted file mode 100644 index add95367640b..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ /dev/null @@ -1,104 +0,0 @@ -Embedded Memory Controller - -Properties: -- name : Should be emc -- #address-cells : Should be 1 -- #size-cells : Should be 0 -- compatible : Should contain "nvidia,tegra20-emc". -- reg : Offset and length of the register set for the device -- nvidia,use-ram-code : If present, the sub-nodes will be addressed - and chosen using the ramcode board selector. If omitted, only one - set of tables can be present and said tables will be used - irrespective of ram-code configuration. -- interrupts : Should contain EMC General interrupt. -- clocks : Should contain EMC clock. - -Child device nodes describe the memory settings for different configurations and clock rates. - -Example: - - memory-controller@7000f400 { - #address-cells = < 1 >; - #size-cells = < 0 >; - compatible = "nvidia,tegra20-emc"; - reg = <0x7000f4000 0x200>; - interrupts = <0 78 0x04>; - clocks = <&tegra_car TEGRA20_CLK_EMC>; - } - - -Embedded Memory Controller ram-code table - -If the emc node has the nvidia,use-ram-code property present, then the -next level of nodes below the emc table are used to specify which settings -apply for which ram-code settings. - -If the emc node lacks the nvidia,use-ram-code property, this level is omitted -and the tables are stored directly under the emc node (see below). - -Properties: - -- name : Should be emc-tables -- nvidia,ram-code : the binary representation of the ram-code board strappings - for which this node (and children) are valid. - - - -Embedded Memory Controller configuration table - -This is a table containing the EMC register settings for the various -operating speeds of the memory controller. They are always located as -subnodes of the emc controller node. - -There are two ways of specifying which tables to use: - -* The simplest is if there is just one set of tables in the device tree, - and they will always be used (based on which frequency is used). - This is the preferred method, especially when firmware can fill in - this information based on the specific system information and just - pass it on to the kernel. - -* The slightly more complex one is when more than one memory configuration - might exist on the system. The Tegra20 platform handles this during - early boot by selecting one out of possible 4 memory settings based - on a 2-pin "ram code" bootstrap setting on the board. The values of - these strappings can be read through a register in the SoC, and thus - used to select which tables to use. - -Properties: -- name : Should be emc-table -- compatible : Should contain "nvidia,tegra20-emc-table". -- reg : either an opaque enumerator to tell different tables apart, or - the valid frequency for which the table should be used (in kHz). -- clock-frequency : the clock frequency for the EMC at which this - table should be used (in kHz). -- nvidia,emc-registers : a 46 word array of EMC registers to be programmed - for operation at the 'clock-frequency' setting. - The order and contents of the registers are: - RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, - WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, - PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, - TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, - ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, - ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, - CFG_CLKTRIM_1, CFG_CLKTRIM_2 - - emc-table@166000 { - reg = <166000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 166000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; - - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 333000 >; - nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 >; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt new file mode 100644 index 000000000000..add95367640b --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -0,0 +1,104 @@ +Embedded Memory Controller + +Properties: +- name : Should be emc +- #address-cells : Should be 1 +- #size-cells : Should be 0 +- compatible : Should contain "nvidia,tegra20-emc". +- reg : Offset and length of the register set for the device +- nvidia,use-ram-code : If present, the sub-nodes will be addressed + and chosen using the ramcode board selector. If omitted, only one + set of tables can be present and said tables will be used + irrespective of ram-code configuration. +- interrupts : Should contain EMC General interrupt. +- clocks : Should contain EMC clock. + +Child device nodes describe the memory settings for different configurations and clock rates. + +Example: + + memory-controller@7000f400 { + #address-cells = < 1 >; + #size-cells = < 0 >; + compatible = "nvidia,tegra20-emc"; + reg = <0x7000f4000 0x200>; + interrupts = <0 78 0x04>; + clocks = <&tegra_car TEGRA20_CLK_EMC>; + } + + +Embedded Memory Controller ram-code table + +If the emc node has the nvidia,use-ram-code property present, then the +next level of nodes below the emc table are used to specify which settings +apply for which ram-code settings. + +If the emc node lacks the nvidia,use-ram-code property, this level is omitted +and the tables are stored directly under the emc node (see below). + +Properties: + +- name : Should be emc-tables +- nvidia,ram-code : the binary representation of the ram-code board strappings + for which this node (and children) are valid. + + + +Embedded Memory Controller configuration table + +This is a table containing the EMC register settings for the various +operating speeds of the memory controller. They are always located as +subnodes of the emc controller node. + +There are two ways of specifying which tables to use: + +* The simplest is if there is just one set of tables in the device tree, + and they will always be used (based on which frequency is used). + This is the preferred method, especially when firmware can fill in + this information based on the specific system information and just + pass it on to the kernel. + +* The slightly more complex one is when more than one memory configuration + might exist on the system. The Tegra20 platform handles this during + early boot by selecting one out of possible 4 memory settings based + on a 2-pin "ram code" bootstrap setting on the board. The values of + these strappings can be read through a register in the SoC, and thus + used to select which tables to use. + +Properties: +- name : Should be emc-table +- compatible : Should contain "nvidia,tegra20-emc-table". +- reg : either an opaque enumerator to tell different tables apart, or + the valid frequency for which the table should be used (in kHz). +- clock-frequency : the clock frequency for the EMC at which this + table should be used (in kHz). +- nvidia,emc-registers : a 46 word array of EMC registers to be programmed + for operation at the 'clock-frequency' setting. + The order and contents of the registers are: + RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT, + WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR, + PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW, + TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE, + ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE, + ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0, + CFG_CLKTRIM_1, CFG_CLKTRIM_2 + + emc-table@166000 { + reg = <166000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 166000 >; + nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 >; + }; + + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 333000 >; + nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 >; + }; -- cgit From f3962b824af9fe9c372dcedde68bbbe86a361bc6 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Mon, 5 Nov 2018 22:38:59 +0100 Subject: arm64: dts: renesas: ebisu: Add serial console pins This patch adds pin control for SCIF2 on R8A77990 E3 Ebisu. Signed-off-by: Takeshi Kihara Signed-off-by: Marek Vasut Reviewed-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index b178f261d805..f9c592adbbd3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -421,6 +421,11 @@ function = "audio_clk"; }; + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + usb0_pins: usb { groups = "usb0_b", "usb0_id"; function = "usb0"; @@ -493,6 +498,9 @@ }; &scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + status = "okay"; }; -- cgit From 9aa3558a02f0bb074d02ef2956fee60a5ee57a47 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Tue, 6 Nov 2018 21:46:47 +0100 Subject: arm64: dts: renesas: ebisu: Add and enable SDHI device nodes This patch adds SDHI{0,1,3} device nodes for the r8a77990 SoC and enables SD card slot connected to SDHI0, micro SD card slot connected to SDHI1 and eMMC connected to SDHI3 on the Ebisu board using the R8A77990 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Marek Vasut Cc: Geert Uytterhoeven Cc: Simon Horman Cc: Wolfram Sang Cc: Yoshihiro Shimoda Cc: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 130 +++++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 36 +++++++ 2 files changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index f9c592adbbd3..2f1cbcde8ae0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -129,6 +129,15 @@ }; }; + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + reg_3p3v: regulator1 { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; @@ -180,6 +189,54 @@ #clock-cells = <0>; clock-frequency = <74250000>; }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; }; &audio_clk_a { @@ -410,6 +467,36 @@ function = "pwm5"; }; + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + + sdhi3_pins: sd3 { + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; + function = "sdhi3"; + power-source = <1800>; + }; + sound_pins: sound { groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data"; function = "ssi"; @@ -531,3 +618,46 @@ status = "okay"; }; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi3 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index beb53aaa9e2c..e0092fb27ec0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1351,6 +1351,42 @@ status = "disabled"; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a77990", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a77990", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a77990", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit From 5e53dbf4edb4d0d1cc97318139f2c20338f207c8 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Mon, 5 Nov 2018 14:12:43 +0100 Subject: arm64: dts: renesas: r8a77990: Fix VIN endpoint numbering The VIN driver bindings dictates fixed numbering for VIN endpoints connected to CSI-2 endpoints, even when a single endpoint exists. Without proper endpoint numbering the VIN driver fails to probe. Based on a patch in BSP from Koji Matsuoka Fixes: ec70407ae7d7 ("arm64: dts: renesas: r8a77990: Add VIN and CSI-2 device nodes") Signed-off-by: Koji Matsuoka Signed-off-by: Takeshi Kihara Signed-off-by: Jacopo Mondi Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index e0092fb27ec0..a2524fc138a2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1011,9 +1011,13 @@ #size-cells = <0>; port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; - vin4csi40: endpoint { + vin4csi40: endpoint@2 { + reg = <2>; remote-endpoint= <&csi40vin4>; }; }; @@ -1035,9 +1039,13 @@ #size-cells = <0>; port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; - vin5csi40: endpoint { + vin5csi40: endpoint@2 { + reg = <2>; remote-endpoint= <&csi40vin5>; }; }; -- cgit From da90dd849dc22e920388d18a0f877366bd4d2b7f Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 8 Nov 2018 02:13:36 +0000 Subject: arm64: dts: renesas: r8a7795: add SSIU support for sound rsnd driver supports SSIU now, let's use it. Then, BUSIF DMA settings on rcar_sound,ssi (= rxu, txu) are no longer needed. To avoid git merge timing issue / git bisect issue, this patch doesn't remove it so far, but will be removed in the future. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 211 +++++++++++++++++++++++++++++++ 1 file changed, 211 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 27faaccd0cae..660fd54d384b 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1920,6 +1920,217 @@ }; }; + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + ssiu02: ssiu-2 { + dmas = <&audma0 0x37>, <&audma1 0x38>; + dma-names = "rx", "tx"; + }; + ssiu03: ssiu-3 { + dmas = <&audma0 0x47>, <&audma1 0x48>; + dma-names = "rx", "tx"; + }; + ssiu04: ssiu-4 { + dmas = <&audma0 0x3F>, <&audma1 0x40>; + dma-names = "rx", "tx"; + }; + ssiu05: ssiu-5 { + dmas = <&audma0 0x43>, <&audma1 0x44>; + dma-names = "rx", "tx"; + }; + ssiu06: ssiu-6 { + dmas = <&audma0 0x4F>, <&audma1 0x50>; + dma-names = "rx", "tx"; + }; + ssiu07: ssiu-7 { + dmas = <&audma0 0x53>, <&audma1 0x54>; + dma-names = "rx", "tx"; + }; + ssiu10: ssiu-8 { + dmas = <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx"; + }; + ssiu11: ssiu-9 { + dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dma-names = "rx", "tx"; + }; + ssiu12: ssiu-10 { + dmas = <&audma0 0x57>, <&audma1 0x58>; + dma-names = "rx", "tx"; + }; + ssiu13: ssiu-11 { + dmas = <&audma0 0x59>, <&audma1 0x5A>; + dma-names = "rx", "tx"; + }; + ssiu14: ssiu-12 { + dmas = <&audma0 0x5F>, <&audma1 0x60>; + dma-names = "rx", "tx"; + }; + ssiu15: ssiu-13 { + dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dma-names = "rx", "tx"; + }; + ssiu16: ssiu-14 { + dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dma-names = "rx", "tx"; + }; + ssiu17: ssiu-15 { + dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dma-names = "rx", "tx"; + }; + ssiu20: ssiu-16 { + dmas = <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx"; + }; + ssiu21: ssiu-17 { + dmas = <&audma0 0x67>, <&audma1 0x68>; + dma-names = "rx", "tx"; + }; + ssiu22: ssiu-18 { + dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dma-names = "rx", "tx"; + }; + ssiu23: ssiu-19 { + dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dma-names = "rx", "tx"; + }; + ssiu24: ssiu-20 { + dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dma-names = "rx", "tx"; + }; + ssiu25: ssiu-21 { + dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dma-names = "rx", "tx"; + }; + ssiu26: ssiu-22 { + dmas = <&audma0 0xED>, <&audma1 0xEE>; + dma-names = "rx", "tx"; + }; + ssiu27: ssiu-23 { + dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dma-names = "rx", "tx"; + }; + ssiu30: ssiu-24 { + dmas = <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx"; + }; + ssiu31: ssiu-25 { + dmas = <&audma0 0x21>, <&audma1 0x22>; + dma-names = "rx", "tx"; + }; + ssiu32: ssiu-26 { + dmas = <&audma0 0x23>, <&audma1 0x24>; + dma-names = "rx", "tx"; + }; + ssiu33: ssiu-27 { + dmas = <&audma0 0x25>, <&audma1 0x26>; + dma-names = "rx", "tx"; + }; + ssiu34: ssiu-28 { + dmas = <&audma0 0x27>, <&audma1 0x28>; + dma-names = "rx", "tx"; + }; + ssiu35: ssiu-29 { + dmas = <&audma0 0x29>, <&audma1 0x2A>; + dma-names = "rx", "tx"; + }; + ssiu36: ssiu-30 { + dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dma-names = "rx", "tx"; + }; + ssiu37: ssiu-31 { + dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dma-names = "rx", "tx"; + }; + ssiu40: ssiu-32 { + dmas = <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx"; + }; + ssiu41: ssiu-33 { + dmas = <&audma0 0x17>, <&audma1 0x18>; + dma-names = "rx", "tx"; + }; + ssiu42: ssiu-34 { + dmas = <&audma0 0x19>, <&audma1 0x1A>; + dma-names = "rx", "tx"; + }; + ssiu43: ssiu-35 { + dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dma-names = "rx", "tx"; + }; + ssiu44: ssiu-36 { + dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dma-names = "rx", "tx"; + }; + ssiu45: ssiu-37 { + dmas = <&audma0 0x1F>, <&audma1 0x20>; + dma-names = "rx", "tx"; + }; + ssiu46: ssiu-38 { + dmas = <&audma0 0x31>, <&audma1 0x32>; + dma-names = "rx", "tx"; + }; + ssiu47: ssiu-39 { + dmas = <&audma0 0x33>, <&audma1 0x34>; + dma-names = "rx", "tx"; + }; + ssiu50: ssiu-40 { + dmas = <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx"; + }; + ssiu60: ssiu-41 { + dmas = <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx"; + }; + ssiu70: ssiu-42 { + dmas = <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx"; + }; + ssiu80: ssiu-43 { + dmas = <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx"; + }; + ssiu90: ssiu-44 { + dmas = <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx"; + }; + ssiu91: ssiu-45 { + dmas = <&audma0 0x7F>, <&audma1 0x80>; + dma-names = "rx", "tx"; + }; + ssiu92: ssiu-46 { + dmas = <&audma0 0x81>, <&audma1 0x82>; + dma-names = "rx", "tx"; + }; + ssiu93: ssiu-47 { + dmas = <&audma0 0x83>, <&audma1 0x84>; + dma-names = "rx", "tx"; + }; + ssiu94: ssiu-48 { + dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dma-names = "rx", "tx"; + }; + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + }; + rcar_sound,ssi { ssi0: ssi-0 { interrupts = ; -- cgit From 10aee7aeebe8107cd0cc6fefadc1df67ed670461 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 31 Oct 2018 09:02:18 -0700 Subject: ARM: dts: Use dra7 mcasp compatible for mcasp instances Looks like dra7 needs optional clocks enabled for mcasp unlike am33xx and am437x do. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index efca29aff633..7e5c0d4f438e 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -2718,7 +2718,7 @@ }; target-module@60000 { /* 0x48460000, ap 9 0e.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; ti,hwmods = "mcasp1"; reg = <0x60000 0x4>, <0x60004 0x4>; @@ -2752,7 +2752,7 @@ }; target-module@64000 { /* 0x48464000, ap 11 1e.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; ti,hwmods = "mcasp2"; reg = <0x64000 0x4>, <0x64004 0x4>; @@ -2786,7 +2786,7 @@ }; target-module@68000 { /* 0x48468000, ap 13 26.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; ti,hwmods = "mcasp3"; reg = <0x68000 0x4>, <0x68004 0x4>; @@ -2819,7 +2819,7 @@ }; target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; ti,hwmods = "mcasp4"; reg = <0x6c000 0x4>, <0x6c004 0x4>; @@ -2852,7 +2852,7 @@ }; target-module@70000 { /* 0x48470000, ap 19 36.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; ti,hwmods = "mcasp5"; reg = <0x70000 0x4>, <0x70004 0x4>; @@ -2885,7 +2885,7 @@ }; target-module@74000 { /* 0x48474000, ap 35 14.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; ti,hwmods = "mcasp6"; reg = <0x74000 0x4>, <0x74004 0x4>; @@ -2918,7 +2918,7 @@ }; target-module@78000 { /* 0x48478000, ap 39 0c.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; ti,hwmods = "mcasp7"; reg = <0x78000 0x4>, <0x78004 0x4>; @@ -2951,7 +2951,7 @@ }; target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ - compatible = "ti,sysc-omap4-simple", "ti,sysc"; + compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; ti,hwmods = "mcasp8"; reg = <0x7c000 0x4>, <0x7c004 0x4>; -- cgit From 4c387984618fe65d87384ca2725661715607bec9 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 9 Nov 2018 13:41:13 -0800 Subject: ARM: dts: omap5: Add l4 interconnect hierarchy and ti-sysc data Similar to commit 8f42cb7f64c7 ("ARM: dts: omap4: Add l4 interconnect hierarchy and ti-sysc data"), let's add proper interconnect hierarchy for l4 interconnect instances with the related ti-sysc interconnect module data as in Documentation/devicetree/bindings/bus/ti-sysc.txt. Using ti-sysc driver binding allows us to start dropping legacy platform data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of ti-sysc dts data. This data is generated based on platform data from a booted system and the interconnect acces protection registers for ranges. To avoid regressions, we initially validate the device tree provided data against the existing platform data on boot. Cc: devicetree@vger.kernel.org Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-l4.dtsi | 2462 +++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap5.dtsi | 688 +---------- 2 files changed, 2468 insertions(+), 682 deletions(-) create mode 100644 arch/arm/boot/dts/omap5-l4.dtsi diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi new file mode 100644 index 000000000000..5e00147522b6 --- /dev/null +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -0,0 +1,2462 @@ +&l4_cfg { /* 0x4a000000 */ + compatible = "ti,omap5-l4-cfg", "simple-bus"; + reg = <0x4a000000 0x800>, + <0x4a000800 0x800>, + <0x4a001000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ + <0x00080000 0x4a080000 0x080000>, /* segment 1 */ + <0x00100000 0x4a100000 0x080000>, /* segment 2 */ + <0x00180000 0x4a180000 0x080000>, /* segment 3 */ + <0x00200000 0x4a200000 0x080000>, /* segment 4 */ + <0x00280000 0x4a280000 0x080000>, /* segment 5 */ + <0x00300000 0x4a300000 0x080000>; /* segment 6 */ + + segment@0 { /* 0x4a000000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00002000 0x00002000 0x001000>, /* ap 3 */ + <0x00003000 0x00003000 0x001000>, /* ap 4 */ + <0x00004000 0x00004000 0x001000>, /* ap 5 */ + <0x00005000 0x00005000 0x001000>, /* ap 6 */ + <0x00056000 0x00056000 0x001000>, /* ap 7 */ + <0x00057000 0x00057000 0x001000>, /* ap 8 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 9 */ + <0x00058000 0x00058000 0x001000>, /* ap 10 */ + <0x00062000 0x00062000 0x001000>, /* ap 11 */ + <0x00063000 0x00063000 0x001000>, /* ap 12 */ + <0x00008000 0x00008000 0x002000>, /* ap 21 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 22 */ + <0x00066000 0x00066000 0x001000>, /* ap 23 */ + <0x00067000 0x00067000 0x001000>, /* ap 24 */ + <0x0005e000 0x0005e000 0x002000>, /* ap 69 */ + <0x00060000 0x00060000 0x001000>, /* ap 70 */ + <0x00064000 0x00064000 0x001000>, /* ap 71 */ + <0x00065000 0x00065000 0x001000>, /* ap 72 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 77 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 78 */ + <0x00070000 0x00070000 0x004000>, /* ap 79 */ + <0x00074000 0x00074000 0x001000>, /* ap 80 */ + <0x00075000 0x00075000 0x001000>, /* ap 81 */ + <0x00076000 0x00076000 0x001000>, /* ap 82 */ + <0x00020000 0x00020000 0x020000>, /* ap 109 */ + <0x00040000 0x00040000 0x001000>, /* ap 110 */ + <0x00059000 0x00059000 0x001000>; /* ap 111 */ + + target-module@2000 { /* 0x4a002000, ap 3 44.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x2000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + + scm_core: scm@0 { + compatible = "ti,omap5-scm-core", "simple-bus"; + reg = <0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x800>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + scm_padconf_core: scm@800 { + compatible = "ti,omap5-scm-padconf-core", + "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x800 0x800>; + + omap5_pmx_core: pinmux@40 { + compatible = "ti,omap5-padconf", + "pinctrl-single"; + reg = <0x40 0x01b6>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap5_padconf_global: omap5_padconf_global@5a0 { + compatible = "syscon", + "simple-bus"; + reg = <0x5a0 0xec>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5a0 0xec>; + + pbias_regulator: pbias_regulator@60 { + compatible = "ti,pbias-omap5", "ti,pbias-omap"; + reg = <0x60 0x4>; + syscon = <&omap5_padconf_global>; + pbias_mmc_reg: pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + }; + }; + + target-module@4000 { /* 0x4a004000, ap 5 5c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x4000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + cm_core_aon: cm_core_aon@0 { + compatible = "ti,omap5-cm-core-aon", + "simple-bus"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + + cm_core_aon_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_aon_clockdomains: clockdomains { + }; + }; + }; + + target-module@8000 { /* 0x4a008000, ap 21 4c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x8000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x2000>; + + cm_core: cm_core@0 { + compatible = "ti,omap5-cm-core", "simple-bus"; + reg = <0x0 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + cm_core_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_clockdomains: clockdomains { + }; + }; + }; + + target-module@20000 { /* 0x4a020000, ap 109 08.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "usb_otg_ss"; + reg = <0x20000 0x4>, + <0x20010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x20000>; + + usb3: omap_dwc3@0 { + compatible = "ti,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges = <0 0 0x20000>; + dwc3: dwc3@4a030000 { + compatible = "snps,dwc3"; + reg = <0x10000 0x10000>; + interrupts = , + , + ; + interrupt-names = "peripheral", + "host", + "otg"; + phys = <&usb2_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "peripheral"; + }; + }; + }; + + target-module@56000 { /* 0x4a056000, ap 7 02.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "dma_system"; + reg = <0x56000 0x4>, + <0x5602c 0x4>, + <0x56028 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */ + clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x56000 0x1000>; + + sdma: dma-controller@0 { + compatible = "ti,omap4430-sdma"; + reg = <0x0 0x1000>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <127>; + }; + }; + + target-module@58000 { /* 0x4a058000, ap 10 06.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00058000 0x00001000>, + <0x00001000 0x00059000 0x00001000>, + <0x00002000 0x0005a000 0x00001000>, + <0x00003000 0x0005b000 0x00001000>; + }; + + target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5e000 0x2000>; + }; + + target-module@62000 { /* 0x4a062000, ap 11 0e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "usb_tll_hs"; + reg = <0x62000 0x4>, + <0x62010 0x4>, + <0x62014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x62000 0x1000>; + + usbhstll: usbhstll@0 { + compatible = "ti,usbhs-tll"; + reg = <0x0 0x1000>; + interrupts = ; + }; + }; + + target-module@64000 { /* 0x4a064000, ap 71 1e.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "usb_host_hs"; + reg = <0x64000 0x4>, + <0x64010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x64000 0x1000>; + + usbhshost: usbhshost@0 { + compatible = "ti,usbhs-host"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1000>; + clocks = <&l3init_60m_fclk>, + <&xclk60mhsp1_ck>, + <&xclk60mhsp2_ck>; + clock-names = "refclk_60m_int", + "refclk_60m_ext_p1", + "refclk_60m_ext_p2"; + + usbhsohci: ohci@4a064800 { + compatible = "ti,ohci-omap3"; + reg = <0x800 0x400>; + interrupts = ; + remote-wakeup-connected; + }; + + usbhsehci: ehci@4a064c00 { + compatible = "ti,ehci-omap"; + reg = <0xc00 0x400>; + interrupts = ; + }; + }; + }; + + target-module@66000 { /* 0x4a066000, ap 23 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "mmu_dsp"; + reg = <0x66000 0x4>, + <0x66010 0x4>, + <0x66014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */ + clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x66000 0x1000>; + + /* mmu_dsp cannot be moved before reset driver */ + status = "disabled"; + }; + + target-module@70000 { /* 0x4a070000, ap 79 2e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x70000 0x4000>; + }; + + target-module@75000 { /* 0x4a075000, ap 81 32.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x75000 0x1000>; + }; + }; + + segment@80000 { /* 0x4a080000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */ + <0x0005a000 0x000da000 0x001000>, /* ap 14 */ + <0x0005b000 0x000db000 0x001000>, /* ap 15 */ + <0x0005c000 0x000dc000 0x001000>, /* ap 16 */ + <0x0005d000 0x000dd000 0x001000>, /* ap 17 */ + <0x0005e000 0x000de000 0x001000>, /* ap 18 */ + <0x00060000 0x000e0000 0x001000>, /* ap 19 */ + <0x00061000 0x000e1000 0x001000>, /* ap 20 */ + <0x00074000 0x000f4000 0x001000>, /* ap 25 */ + <0x00075000 0x000f5000 0x001000>, /* ap 26 */ + <0x00076000 0x000f6000 0x001000>, /* ap 27 */ + <0x00077000 0x000f7000 0x001000>, /* ap 28 */ + <0x00036000 0x000b6000 0x001000>, /* ap 65 */ + <0x00037000 0x000b7000 0x001000>, /* ap 66 */ + <0x0004d000 0x000cd000 0x001000>, /* ap 67 */ + <0x0004e000 0x000ce000 0x001000>, /* ap 68 */ + <0x00000000 0x00080000 0x004000>, /* ap 83 */ + <0x00004000 0x00084000 0x001000>, /* ap 84 */ + <0x00005000 0x00085000 0x001000>, /* ap 85 */ + <0x00006000 0x00086000 0x001000>, /* ap 86 */ + <0x00007000 0x00087000 0x001000>, /* ap 87 */ + <0x00008000 0x00088000 0x001000>, /* ap 88 */ + <0x00010000 0x00090000 0x004000>, /* ap 89 */ + <0x00014000 0x00094000 0x001000>, /* ap 90 */ + <0x00015000 0x00095000 0x001000>, /* ap 91 */ + <0x00016000 0x00096000 0x001000>, /* ap 92 */ + <0x00017000 0x00097000 0x001000>, /* ap 93 */ + <0x00018000 0x00098000 0x001000>, /* ap 94 */ + <0x00020000 0x000a0000 0x004000>, /* ap 95 */ + <0x00024000 0x000a4000 0x001000>, /* ap 96 */ + <0x00025000 0x000a5000 0x001000>, /* ap 97 */ + <0x00026000 0x000a6000 0x001000>, /* ap 98 */ + <0x00027000 0x000a7000 0x001000>, /* ap 99 */ + <0x00028000 0x000a8000 0x001000>; /* ap 100 */ + + target-module@0 { /* 0x4a080000, ap 83 28.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "ocp2scp1"; + reg = <0x0 0x4>, + <0x10 0x4>, + <0x14 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x00004000>, + <0x00004000 0x00004000 0x00001000>, + <0x00005000 0x00005000 0x00001000>, + <0x00006000 0x00006000 0x00001000>, + <0x00007000 0x00007000 0x00001000>; + + ocp2scp@0 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x20>; + }; + + usb2_phy: usb2phy@4000 { + compatible = "ti,omap-usb2"; + reg = <0x4000 0x7c>; + syscon-phy-power = <&scm_conf 0x300>; + clocks = <&usb_phy_cm_clk32k>, + <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + }; + + usb3_phy: usb3phy@4400 { + compatible = "ti,omap-usb3"; + reg = <0x4400 0x80>, + <0x4800 0x64>, + <0x4c00 0x40>; + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + syscon-phy-power = <&scm_conf 0x370>; + clocks = <&usb_phy_cm_clk32k>, + <&sys_clkin>, + <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; + clock-names = "wkupclk", + "sysclk", + "refclk"; + #phy-cells = <0>; + }; + }; + + target-module@10000 { /* 0x4a090000, ap 89 36.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "ocp2scp3"; + reg = <0x10000 0x4>, + <0x10010 0x4>, + <0x10014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00010000 0x00004000>, + <0x00004000 0x00014000 0x00001000>, + <0x00005000 0x00015000 0x00001000>, + <0x00006000 0x00016000 0x00001000>, + <0x00007000 0x00017000 0x00001000>; + + ocp2scp@0 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x20>; + ranges = <0 0 0x4000>; + sata_phy: phy@4a096000 { + compatible = "ti,phy-pipe3-sata"; + reg = <0x6000 0x80>, /* phy_rx */ + <0x4A096400 0x64>, /* phy_tx */ + <0x4A096800 0x40>; /* pll_ctrl */ + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + syscon-phy-power = <&scm_conf 0x374>; + clocks = <&sys_clkin>, + <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; + clock-names = "sysclk", "refclk"; + #phy-cells = <0>; + }; + }; + }; + + target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00020000 0x00004000>, + <0x00004000 0x00024000 0x00001000>, + <0x00005000 0x00025000 0x00001000>, + <0x00006000 0x00026000 0x00001000>, + <0x00007000 0x00027000 0x00001000>; + }; + + target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + }; + + target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4d000 0x1000>; + }; + + target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + }; + + target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + }; + + target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + }; + + target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + }; + + target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mailbox"; + reg = <0x74000 0x4>, + <0x74010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x74000 0x1000>; + + mailbox: mailbox@0 { + compatible = "ti,omap4-mailbox"; + reg = <0x0 0x200>; + interrupts = ; + #mbox-cells = <1>; + ti,mbox-num-users = <3>; + ti,mbox-num-fifos = <8>; + mbox_ipu: mbox_ipu { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_dsp: mbox_dsp { + ti,mbox-tx = <3 0 0>; + ti,mbox-rx = <2 0 0>; + }; + }; + }; + + target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "spinlock"; + reg = <0x76000 0x4>, + <0x76010 0x4>, + <0x76014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */ + clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x76000 0x1000>; + + hwspinlock: spinlock@0 { + compatible = "ti,omap4-hwspinlock"; + reg = <0x0 0x1000>; + #hwlock-cells = <1>; + }; + }; + }; + + segment@100000 { /* 0x4a100000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */ + <0x00003000 0x00103000 0x001000>, /* ap 60 */ + <0x00008000 0x00108000 0x001000>, /* ap 61 */ + <0x00009000 0x00109000 0x001000>, /* ap 62 */ + <0x0000a000 0x0010a000 0x001000>, /* ap 63 */ + <0x0000b000 0x0010b000 0x001000>, /* ap 64 */ + <0x00040000 0x00140000 0x010000>, /* ap 101 */ + <0x00050000 0x00150000 0x001000>; /* ap 102 */ + + target-module@2000 { /* 0x4a102000, ap 59 2c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@8000 { /* 0x4a108000, ap 61 26.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@a000 { /* 0x4a10a000, ap 63 22.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@40000 { /* 0x4a140000, ap 101 16.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x10000>; + }; + }; + + segment@180000 { /* 0x4a180000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; + + segment@200000 { /* 0x4a200000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */ + <0x0001f000 0x0021f000 0x001000>, /* ap 30 */ + <0x0000a000 0x0020a000 0x001000>, /* ap 31 */ + <0x0000b000 0x0020b000 0x001000>, /* ap 32 */ + <0x00006000 0x00206000 0x001000>, /* ap 33 */ + <0x00007000 0x00207000 0x001000>, /* ap 34 */ + <0x00004000 0x00204000 0x001000>, /* ap 35 */ + <0x00005000 0x00205000 0x001000>, /* ap 36 */ + <0x00012000 0x00212000 0x001000>, /* ap 37 */ + <0x00013000 0x00213000 0x001000>, /* ap 38 */ + <0x0000c000 0x0020c000 0x001000>, /* ap 39 */ + <0x0000d000 0x0020d000 0x001000>, /* ap 40 */ + <0x00010000 0x00210000 0x001000>, /* ap 41 */ + <0x00011000 0x00211000 0x001000>, /* ap 42 */ + <0x00016000 0x00216000 0x001000>, /* ap 43 */ + <0x00017000 0x00217000 0x001000>, /* ap 44 */ + <0x00014000 0x00214000 0x001000>, /* ap 45 */ + <0x00015000 0x00215000 0x001000>, /* ap 46 */ + <0x00018000 0x00218000 0x001000>, /* ap 47 */ + <0x00019000 0x00219000 0x001000>, /* ap 48 */ + <0x00020000 0x00220000 0x001000>, /* ap 49 */ + <0x00021000 0x00221000 0x001000>, /* ap 50 */ + <0x00026000 0x00226000 0x001000>, /* ap 51 */ + <0x00027000 0x00227000 0x001000>, /* ap 52 */ + <0x00028000 0x00228000 0x001000>, /* ap 53 */ + <0x00029000 0x00229000 0x001000>, /* ap 54 */ + <0x0002a000 0x0022a000 0x001000>, /* ap 55 */ + <0x0002b000 0x0022b000 0x001000>, /* ap 56 */ + <0x0001c000 0x0021c000 0x001000>, /* ap 57 */ + <0x0001d000 0x0021d000 0x001000>, /* ap 58 */ + <0x0001a000 0x0021a000 0x001000>, /* ap 73 */ + <0x0001b000 0x0021b000 0x001000>, /* ap 74 */ + <0x00024000 0x00224000 0x001000>, /* ap 75 */ + <0x00025000 0x00225000 0x001000>, /* ap 76 */ + <0x00002000 0x00202000 0x001000>, /* ap 103 */ + <0x00003000 0x00203000 0x001000>, /* ap 104 */ + <0x00008000 0x00208000 0x001000>, /* ap 105 */ + <0x00009000 0x00209000 0x001000>, /* ap 106 */ + <0x00022000 0x00222000 0x001000>, /* ap 107 */ + <0x00023000 0x00223000 0x001000>; /* ap 108 */ + + target-module@2000 { /* 0x4a202000, ap 103 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@4000 { /* 0x4a204000, ap 35 46.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + }; + + target-module@6000 { /* 0x4a206000, ap 33 4e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x1000>; + }; + + target-module@8000 { /* 0x4a208000, ap 105 34.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + }; + + target-module@a000 { /* 0x4a20a000, ap 31 30.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + }; + + target-module@c000 { /* 0x4a20c000, ap 39 14.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + }; + + target-module@10000 { /* 0x4a210000, ap 41 56.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000 0x1000>; + }; + + target-module@12000 { /* 0x4a212000, ap 37 52.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x12000 0x1000>; + }; + + target-module@14000 { /* 0x4a214000, ap 45 1c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x14000 0x1000>; + }; + + target-module@16000 { /* 0x4a216000, ap 43 42.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x16000 0x1000>; + }; + + target-module@18000 { /* 0x4a218000, ap 47 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000 0x1000>; + }; + + target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + + target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1c000 0x1000>; + }; + + target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000 0x1000>; + }; + + target-module@20000 { /* 0x4a220000, ap 49 4a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + }; + + target-module@22000 { /* 0x4a222000, ap 107 3a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x22000 0x1000>; + }; + + target-module@24000 { /* 0x4a224000, ap 75 48.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + }; + + target-module@26000 { /* 0x4a226000, ap 51 24.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x1000>; + }; + + target-module@28000 { /* 0x4a228000, ap 53 38.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x28000 0x1000>; + }; + + target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2a000 0x1000>; + }; + }; + + segment@280000 { /* 0x4a280000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; + + segment@300000 { /* 0x4a300000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&l4_per { /* 0x48000000 */ + compatible = "ti,omap5-l4-per", "simple-bus"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ + <0x00200000 0x48200000 0x200000>; /* segment 1 */ + + segment@0 { /* 0x48000000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x000400>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00020000 0x00020000 0x001000>, /* ap 3 */ + <0x00021000 0x00021000 0x001000>, /* ap 4 */ + <0x00032000 0x00032000 0x001000>, /* ap 5 */ + <0x00033000 0x00033000 0x001000>, /* ap 6 */ + <0x00034000 0x00034000 0x001000>, /* ap 7 */ + <0x00035000 0x00035000 0x001000>, /* ap 8 */ + <0x00036000 0x00036000 0x001000>, /* ap 9 */ + <0x00037000 0x00037000 0x001000>, /* ap 10 */ + <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ + <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ + <0x00055000 0x00055000 0x001000>, /* ap 13 */ + <0x00056000 0x00056000 0x001000>, /* ap 14 */ + <0x00057000 0x00057000 0x001000>, /* ap 15 */ + <0x00058000 0x00058000 0x001000>, /* ap 16 */ + <0x00059000 0x00059000 0x001000>, /* ap 17 */ + <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ + <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ + <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ + <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ + <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ + <0x00060000 0x00060000 0x001000>, /* ap 23 */ + <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ + <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ + <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ + <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ + <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ + <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ + <0x00070000 0x00070000 0x001000>, /* ap 30 */ + <0x00071000 0x00071000 0x001000>, /* ap 31 */ + <0x00072000 0x00072000 0x001000>, /* ap 32 */ + <0x00073000 0x00073000 0x001000>, /* ap 33 */ + <0x00061000 0x00061000 0x001000>, /* ap 34 */ + <0x00053000 0x00053000 0x001000>, /* ap 35 */ + <0x00054000 0x00054000 0x001000>, /* ap 36 */ + <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ + <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ + <0x00078000 0x00078000 0x001000>, /* ap 39 */ + <0x00079000 0x00079000 0x001000>, /* ap 40 */ + <0x00086000 0x00086000 0x001000>, /* ap 41 */ + <0x00087000 0x00087000 0x001000>, /* ap 42 */ + <0x00088000 0x00088000 0x001000>, /* ap 43 */ + <0x00089000 0x00089000 0x001000>, /* ap 44 */ + <0x00051000 0x00051000 0x001000>, /* ap 45 */ + <0x00052000 0x00052000 0x001000>, /* ap 46 */ + <0x00098000 0x00098000 0x001000>, /* ap 47 */ + <0x00099000 0x00099000 0x001000>, /* ap 48 */ + <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ + <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ + <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ + <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ + <0x00068000 0x00068000 0x001000>, /* ap 53 */ + <0x00069000 0x00069000 0x001000>, /* ap 54 */ + <0x00090000 0x00090000 0x002000>, /* ap 55 */ + <0x00092000 0x00092000 0x001000>, /* ap 56 */ + <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ + <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ + <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ + <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ + <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ + <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ + <0x00066000 0x00066000 0x001000>, /* ap 63 */ + <0x00067000 0x00067000 0x001000>, /* ap 64 */ + <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ + <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ + <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ + <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ + <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ + <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ + <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ + <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ + <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ + <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ + <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ + <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ + <0x00001400 0x00001400 0x000400>, /* ap 77 */ + <0x00001800 0x00001800 0x000400>, /* ap 78 */ + <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ + <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ + <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ + <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ + <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ + <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ + + target-module@20000 { /* 0x48020000, ap 3 04.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart3"; + reg = <0x20050 0x4>, + <0x20054 0x4>, + <0x20058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; + ti,no-idle-on-init; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + + uart3: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@32000 { /* 0x48032000, ap 5 3e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer2"; + reg = <0x32000 0x4>, + <0x32010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x32000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; + }; + + target-module@34000 { /* 0x48034000, ap 7 46.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer3"; + reg = <0x34000 0x4>, + <0x34010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x34000 0x1000>; + + timer3: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; + }; + + target-module@36000 { /* 0x48036000, ap 9 4e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer4"; + reg = <0x36000 0x4>, + <0x36010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x36000 0x1000>; + + timer4: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + }; + }; + + target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer9"; + reg = <0x3e000 0x4>, + <0x3e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x3e000 0x1000>; + + timer9: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-pwm; + }; + }; + + target-module@51000 { /* 0x48051000, ap 45 2e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio7"; + reg = <0x51000 0x4>, + <0x51010 0x4>, + <0x51114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x51000 0x1000>; + + gpio7: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@53000 { /* 0x48053000, ap 35 36.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio8"; + reg = <0x53000 0x4>, + <0x53010 0x4>, + <0x53114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x53000 0x1000>; + + gpio8: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@55000 { /* 0x48055000, ap 13 0e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio2"; + reg = <0x55000 0x4>, + <0x55010 0x4>, + <0x55114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x55000 0x1000>; + + gpio2: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@57000 { /* 0x48057000, ap 15 06.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio3"; + reg = <0x57000 0x4>, + <0x57010 0x4>, + <0x57114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x57000 0x1000>; + + gpio3: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@59000 { /* 0x48059000, ap 17 16.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio4"; + reg = <0x59000 0x4>, + <0x59010 0x4>, + <0x59114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x59000 0x1000>; + + gpio4: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio5"; + reg = <0x5b000 0x4>, + <0x5b010 0x4>, + <0x5b114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5b000 0x1000>; + + gpio5: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio6"; + reg = <0x5d000 0x4>, + <0x5d010 0x4>, + <0x5d114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>, + <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5d000 0x1000>; + + gpio6: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@60000 { /* 0x48060000, ap 23 24.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c3"; + reg = <0x60000 0x8>, + <0x60010 0x8>, + <0x60090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x60000 0x1000>; + + i2c3: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@66000 { /* 0x48066000, ap 63 4c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart5"; + reg = <0x66050 0x4>, + <0x66054 0x4>, + <0x66058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x66000 0x1000>; + + uart5: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@68000 { /* 0x48068000, ap 53 54.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart6"; + reg = <0x68050 0x4>, + <0x68054 0x4>, + <0x68058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x68000 0x1000>; + + uart6: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart1"; + reg = <0x6a050 0x4>, + <0x6a054 0x4>, + <0x6a058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6a000 0x1000>; + + uart1: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@6c000 { /* 0x4806c000, ap 26 22.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart2"; + reg = <0x6c050 0x4>, + <0x6c054 0x4>, + <0x6c058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6c000 0x1000>; + + uart2: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@6e000 { /* 0x4806e000, ap 28 44.1 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "uart4"; + reg = <0x6e050 0x4>, + <0x6e054 0x4>, + <0x6e058 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6e000 0x1000>; + + uart4: serial@0 { + compatible = "ti,omap4-uart"; + reg = <0x0 0x100>; + interrupts = ; + clock-frequency = <48000000>; + }; + }; + + target-module@70000 { /* 0x48070000, ap 30 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c1"; + reg = <0x70000 0x8>, + <0x70010 0x8>, + <0x70090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x70000 0x1000>; + + i2c1: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@72000 { /* 0x48072000, ap 32 1c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c2"; + reg = <0x72000 0x8>, + <0x72010 0x8>, + <0x72090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x72000 0x1000>; + + i2c2: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@78000 { /* 0x48078000, ap 39 12.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x78000 0x1000>; + }; + + target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c4"; + reg = <0x7a000 0x8>, + <0x7a010 0x8>, + <0x7a090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7a000 0x1000>; + + i2c4: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@7c000 { /* 0x4807c000, ap 83 34.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "i2c5"; + reg = <0x7c000 0x8>, + <0x7c010 0x8>, + <0x7c090 0x8>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7c000 0x1000>; + + i2c5: i2c@0 { + compatible = "ti,omap4-i2c"; + reg = <0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + target-module@86000 { /* 0x48086000, ap 41 5e.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer10"; + reg = <0x86000 0x4>, + <0x86010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x86000 0x1000>; + + timer10: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-pwm; + }; + }; + + target-module@88000 { /* 0x48088000, ap 43 66.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer11"; + reg = <0x88000 0x4>, + <0x88010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x88000 0x1000>; + + timer11: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-pwm; + }; + }; + + target-module@90000 { /* 0x48090000, ap 55 1a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x90000 0x2000>; + }; + + target-module@98000 { /* 0x48098000, ap 47 08.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi1"; + reg = <0x98000 0x4>, + <0x98010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000 0x1000>; + + mcspi1: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <4>; + dmas = <&sdma 35>, + <&sdma 36>, + <&sdma 37>, + <&sdma 38>, + <&sdma 39>, + <&sdma 40>, + <&sdma 41>, + <&sdma 42>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; + }; + + target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi2"; + reg = <0x9a000 0x4>, + <0x9a010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9a000 0x1000>; + + mcspi2: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma 43>, + <&sdma 44>, + <&sdma 45>, + <&sdma 46>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; + }; + + target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc1"; + reg = <0x9c000 0x4>, + <0x9c010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x9c000 0x1000>; + + mmc1: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,dual-volt; + ti,needs-special-reset; + dmas = <&sdma 61>, <&sdma 62>; + dma-names = "tx", "rx"; + pbias-supply = <&pbias_mmc_reg>; + }; + }; + + target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa2000 0x1000>; + }; + + target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x000a4000 0x00001000>, + <0x00001000 0x000a5000 0x00001000>; + }; + + target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa8000 0x4000>; + }; + + target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc3"; + reg = <0xad000 0x4>, + <0xad010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xad000 0x1000>; + + mmc3: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 77>, <&sdma 78>; + dma-names = "tx", "rx"; + }; + }; + + target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb2000 0x1000>; + }; + + target-module@b4000 { /* 0x480b4000, ap 65 42.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc2"; + reg = <0xb4000 0x4>, + <0xb4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */ + clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb4000 0x1000>; + + mmc2: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 47>, <&sdma 48>; + dma-names = "tx", "rx"; + }; + }; + + target-module@b8000 { /* 0x480b8000, ap 67 32.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi3"; + reg = <0xb8000 0x4>, + <0xb8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xb8000 0x1000>; + + mcspi3: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <2>; + dmas = <&sdma 15>, <&sdma 16>; + dma-names = "tx0", "rx0"; + }; + }; + + target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mcspi4"; + reg = <0xba000 0x4>, + <0xba010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xba000 0x1000>; + + mcspi4: spi@0 { + compatible = "ti,omap4-mcspi"; + reg = <0x0 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + ti,spi-num-cs = <1>; + dmas = <&sdma 70>, <&sdma 71>; + dma-names = "tx0", "rx0"; + }; + }; + + target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc4"; + reg = <0xd1000 0x4>, + <0xd1010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd1000 0x1000>; + + mmc4: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 57>, <&sdma 58>; + dma-names = "tx", "rx"; + }; + }; + + target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "mmc5"; + reg = <0xd5000 0x4>, + <0xd5010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-midle = , + , + , + ; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */ + clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd5000 0x1000>; + + mmc5: mmc@0 { + compatible = "ti,omap4-hsmmc"; + reg = <0x0 0x400>; + interrupts = ; + ti,needs-special-reset; + dmas = <&sdma 59>, <&sdma 60>; + dma-names = "tx", "rx"; + }; + }; + }; + + segment@200000 { /* 0x48200000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&l4_wkup { /* 0x4ae00000 */ + compatible = "ti,omap5-l4-wkup", "simple-bus"; + reg = <0x4ae00000 0x800>, + <0x4ae00800 0x800>, + <0x4ae01000 0x1000>; + reg-names = "ap", "la", "ia0"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ + <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ + <0x00020000 0x4ae20000 0x010000>; /* segment 2 */ + + segment@0 { /* 0x4ae00000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ + <0x00001000 0x00001000 0x001000>, /* ap 1 */ + <0x00000800 0x00000800 0x000800>, /* ap 2 */ + <0x00006000 0x00006000 0x002000>, /* ap 3 */ + <0x00008000 0x00008000 0x001000>, /* ap 4 */ + <0x0000a000 0x0000a000 0x001000>, /* ap 15 */ + <0x0000b000 0x0000b000 0x001000>, /* ap 16 */ + <0x00004000 0x00004000 0x001000>, /* ap 17 */ + <0x00005000 0x00005000 0x001000>, /* ap 18 */ + <0x0000c000 0x0000c000 0x001000>, /* ap 19 */ + <0x0000d000 0x0000d000 0x001000>; /* ap 20 */ + + target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "counter_32k"; + reg = <0x4000 0x4>, + <0x4010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0x0 0x40>; + }; + }; + + target-module@6000 { /* 0x4ae06000, ap 3 08.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x6000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x6000 0x2000>; + + prm: prm@0 { + compatible = "ti,omap5-prm", "simple-bus"; + reg = <0x0 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2000>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + }; + + target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xa000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xa000 0x1000>; + + scrm: scrm@0 { + compatible = "ti,omap5-scrm"; + reg = <0x0 0x1000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + }; + + target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */ + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0xc000 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + + omap5_pmx_wkup: pinmux@840 { + compatible = "ti,omap5-padconf", + "pinctrl-single"; + reg = <0x840 0x003c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 { + compatible = "ti,omap5-scm-wkup-pad-conf", + "simple-bus"; + reg = <0xda0 0x60>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x60>; + + scm_wkup_pad_conf: scm_conf@0 { + compatible = "syscon", "simple-bus"; + reg = <0x0 0x60>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x60>; + + scm_wkup_pad_conf_clocks: clocks@0 { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + }; + + segment@10000 { /* 0x4ae10000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ + <0x00001000 0x00011000 0x001000>, /* ap 6 */ + <0x00004000 0x00014000 0x001000>, /* ap 7 */ + <0x00005000 0x00015000 0x001000>, /* ap 8 */ + <0x00008000 0x00018000 0x001000>, /* ap 9 */ + <0x00009000 0x00019000 0x001000>, /* ap 10 */ + <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ + <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ + + target-module@0 { /* 0x4ae10000, ap 5 10.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "gpio1"; + reg = <0x0 0x4>, + <0x10 0x4>, + <0x114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>, + <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>; + clock-names = "fck", "dbclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + + gpio1: gpio@0 { + compatible = "ti,omap4-gpio"; + reg = <0x0 0x200>; + interrupts = ; + ti,gpio-always-on; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + target-module@4000 { /* 0x4ae14000, ap 7 14.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "wd_timer2"; + reg = <0x4000 0x4>, + <0x4010 0x4>, + <0x4014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + wdt2: wdt@0 { + compatible = "ti,omap5-wdt", "ti,omap3-wdt"; + reg = <0x0 0x80>; + interrupts = ; + }; + }; + + target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + ti,hwmods = "timer1"; + reg = <0x8000 0x4>, + <0x8010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | + SYSC_OMAP4_SOFTRESET)>; + ti,sysc-sidle = , + , + , + ; + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap5430-timer"; + reg = <0x0 0x80>; + clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; + clock-names = "fck"; + interrupts = ; + ti,timer-alwon; + }; + }; + + target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "kbd"; + reg = <0xc000 0x4>, + <0xc010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_SOFTRESET)>; + ti,sysc-sidle = , + , + ; + /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */ + clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc000 0x1000>; + + keypad: keypad@0 { + compatible = "ti,omap4-keypad"; + reg = <0x0 0x400>; + }; + }; + }; + + segment@20000 { /* 0x4ae20000 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ + <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ + <0x00000000 0x00020000 0x001000>, /* ap 21 */ + <0x00001000 0x00021000 0x001000>, /* ap 22 */ + <0x00002000 0x00022000 0x001000>, /* ap 23 */ + <0x00003000 0x00023000 0x001000>, /* ap 24 */ + <0x00007000 0x00027000 0x000400>, /* ap 25 */ + <0x00008000 0x00028000 0x000800>, /* ap 26 */ + <0x00009000 0x00029000 0x000100>, /* ap 27 */ + <0x00008800 0x00028800 0x000200>, /* ap 28 */ + <0x00008a00 0x00028a00 0x000100>; /* ap 29 */ + + target-module@0 { /* 0x4ae20000, ap 21 04.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2000 0x1000>; + }; + + target-module@6000 { /* 0x4ae26000, ap 13 24.0 */ + compatible = "ti,sysc"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00006000 0x00001000>, + <0x00001000 0x00007000 0x00000400>, + <0x00002000 0x00008000 0x00000800>, + <0x00002800 0x00008800 0x00000200>, + <0x00002a00 0x00008a00 0x00000100>, + <0x00003000 0x00009000 0x00000100>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 574ac11c0489..2fefaafdf901 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -7,6 +7,7 @@ * Based on "omap4.dtsi" */ +#include #include #include #include @@ -151,178 +152,13 @@ interrupts = , ; - l4_cfg: l4@4a000000 { - compatible = "ti,omap5-l4-cfg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4a000000 0x22a000>; - - scm_core: scm@2000 { - compatible = "ti,omap5-scm-core", "simple-bus"; - reg = <0x2000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2000 0x800>; - - scm_conf: scm_conf@0 { - compatible = "syscon"; - reg = <0x0 0x800>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - scm_padconf_core: scm@2800 { - compatible = "ti,omap5-scm-padconf-core", - "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2800 0x800>; - - omap5_pmx_core: pinmux@40 { - compatible = "ti,omap5-padconf", - "pinctrl-single"; - reg = <0x40 0x01b6>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap5_padconf_global: omap5_padconf_global@5a0 { - compatible = "syscon", - "simple-bus"; - reg = <0x5a0 0xec>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5a0 0xec>; - - pbias_regulator: pbias_regulator@60 { - compatible = "ti,pbias-omap5", "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap5_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - }; - - cm_core_aon: cm_core_aon@4000 { - compatible = "ti,omap5-cm-core-aon", - "simple-bus"; - reg = <0x4000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4000 0x2000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - - cm_core: cm_core@8000 { - compatible = "ti,omap5-cm-core", "simple-bus"; - reg = <0x8000 0x3000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8000 0x3000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; + l4_wkup: interconnect@4ae00000 { }; - l4_wkup: l4@4ae00000 { - compatible = "ti,omap5-l4-wkup", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4ae00000 0x2b000>; - - counter32k: counter@4000 { - compatible = "ti,omap-counter32k"; - reg = <0x4000 0x40>; - ti,hwmods = "counter_32k"; - }; - - prm: prm@6000 { - compatible = "ti,omap5-prm", "simple-bus"; - reg = <0x6000 0x3000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x6000 0x3000>; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@a000 { - compatible = "ti,omap5-scrm"; - reg = <0xa000 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - omap5_pmx_wkup: pinmux@c840 { - compatible = "ti,omap5-padconf", - "pinctrl-single"; - reg = <0xc840 0x003c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - - omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 { - compatible = "ti,omap5-scm-wkup-pad-conf", - "simple-bus"; - reg = <0xcda0 0x60>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xcda0 0x60>; - - scm_wkup_pad_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; - reg = <0x0 0x60>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x60>; + l4_cfg: interconnect@4a000000 { + }; - scm_wkup_pad_conf_clocks: clocks@0 { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; + l4_per: interconnect@48000000 { }; ocmcram: ocmcram@40300000 { @@ -330,108 +166,6 @@ reg = <0x40300000 0x20000>; /* 128k */ }; - sdma: dma-controller@4a056000 { - compatible = "ti,omap4430-sdma"; - reg = <0x4a056000 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <127>; - ti,hwmods = "dma_system"; - }; - - gpio1: gpio@4ae10000 { - compatible = "ti,omap4-gpio"; - reg = <0x4ae10000 0x200>; - interrupts = ; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@48055000 { - compatible = "ti,omap4-gpio"; - reg = <0x48055000 0x200>; - interrupts = ; - ti,hwmods = "gpio2"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@48057000 { - compatible = "ti,omap4-gpio"; - reg = <0x48057000 0x200>; - interrupts = ; - ti,hwmods = "gpio3"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@48059000 { - compatible = "ti,omap4-gpio"; - reg = <0x48059000 0x200>; - interrupts = ; - ti,hwmods = "gpio4"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@4805b000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805b000 0x200>; - interrupts = ; - ti,hwmods = "gpio5"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@4805d000 { - compatible = "ti,omap4-gpio"; - reg = <0x4805d000 0x200>; - interrupts = ; - ti,hwmods = "gpio6"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@48051000 { - compatible = "ti,omap4-gpio"; - reg = <0x48051000 0x200>; - interrupts = ; - ti,hwmods = "gpio7"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio8: gpio@48053000 { - compatible = "ti,omap4-gpio"; - reg = <0x48053000 0x200>; - interrupts = ; - ti,hwmods = "gpio8"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - gpmc: gpmc@50000000 { compatible = "ti,omap4430-gpmc"; reg = <0x50000000 0x1000>; @@ -451,217 +185,6 @@ #gpio-cells = <2>; }; - i2c1: i2c@48070000 { - compatible = "ti,omap4-i2c"; - reg = <0x48070000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap4-i2c"; - reg = <0x48072000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap4-i2c"; - reg = <0x48060000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - }; - - i2c4: i2c@4807a000 { - compatible = "ti,omap4-i2c"; - reg = <0x4807a000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c4"; - }; - - i2c5: i2c@4807c000 { - compatible = "ti,omap4-i2c"; - reg = <0x4807c000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c5"; - }; - - hwspinlock: spinlock@4a0f6000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x4a0f6000 0x1000>; - ti,hwmods = "spinlock"; - #hwlock-cells = <1>; - }; - - mcspi1: spi@48098000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48098000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; - dmas = <&sdma 35>, - <&sdma 36>, - <&sdma 37>, - <&sdma 38>, - <&sdma 39>, - <&sdma 40>, - <&sdma 41>, - <&sdma 42>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mcspi2: spi@4809a000 { - compatible = "ti,omap4-mcspi"; - reg = <0x4809a000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi2"; - ti,spi-num-cs = <2>; - dmas = <&sdma 43>, - <&sdma 44>, - <&sdma 45>, - <&sdma 46>; - dma-names = "tx0", "rx0", "tx1", "rx1"; - }; - - mcspi3: spi@480b8000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480b8000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi3"; - ti,spi-num-cs = <2>; - dmas = <&sdma 15>, <&sdma 16>; - dma-names = "tx0", "rx0"; - }; - - mcspi4: spi@480ba000 { - compatible = "ti,omap4-mcspi"; - reg = <0x480ba000 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "mcspi4"; - ti,spi-num-cs = <1>; - dmas = <&sdma 70>, <&sdma 71>; - dma-names = "tx0", "rx0"; - }; - - uart1: serial@4806a000 { - compatible = "ti,omap4-uart"; - reg = <0x4806a000 0x100>; - interrupts = ; - ti,hwmods = "uart1"; - clock-frequency = <48000000>; - }; - - uart2: serial@4806c000 { - compatible = "ti,omap4-uart"; - reg = <0x4806c000 0x100>; - interrupts = ; - ti,hwmods = "uart2"; - clock-frequency = <48000000>; - }; - - uart3: serial@48020000 { - compatible = "ti,omap4-uart"; - reg = <0x48020000 0x100>; - interrupts = ; - ti,hwmods = "uart3"; - clock-frequency = <48000000>; - }; - - uart4: serial@4806e000 { - compatible = "ti,omap4-uart"; - reg = <0x4806e000 0x100>; - interrupts = ; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; - - uart5: serial@48066000 { - compatible = "ti,omap4-uart"; - reg = <0x48066000 0x100>; - interrupts = ; - ti,hwmods = "uart5"; - clock-frequency = <48000000>; - }; - - uart6: serial@48068000 { - compatible = "ti,omap4-uart"; - reg = <0x48068000 0x100>; - interrupts = ; - ti,hwmods = "uart6"; - clock-frequency = <48000000>; - }; - - mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x4809c000 0x400>; - interrupts = ; - ti,hwmods = "mmc1"; - ti,dual-volt; - ti,needs-special-reset; - dmas = <&sdma 61>, <&sdma 62>; - dma-names = "tx", "rx"; - pbias-supply = <&pbias_mmc_reg>; - }; - - mmc2: mmc@480b4000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480b4000 0x400>; - interrupts = ; - ti,hwmods = "mmc2"; - ti,needs-special-reset; - dmas = <&sdma 47>, <&sdma 48>; - dma-names = "tx", "rx"; - }; - - mmc3: mmc@480ad000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480ad000 0x400>; - interrupts = ; - ti,hwmods = "mmc3"; - ti,needs-special-reset; - dmas = <&sdma 77>, <&sdma 78>; - dma-names = "tx", "rx"; - }; - - mmc4: mmc@480d1000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480d1000 0x400>; - interrupts = ; - ti,hwmods = "mmc4"; - ti,needs-special-reset; - dmas = <&sdma 57>, <&sdma 58>; - dma-names = "tx", "rx"; - }; - - mmc5: mmc@480d5000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x480d5000 0x400>; - interrupts = ; - ti,hwmods = "mmc5"; - ti,needs-special-reset; - dmas = <&sdma 59>, <&sdma 60>; - dma-names = "tx", "rx"; - }; - mmu_dsp: mmu@4a066000 { compatible = "ti,omap4-iommu"; reg = <0x4a066000 0x100>; @@ -679,12 +202,6 @@ ti,iommu-bus-err-back; }; - keypad: keypad@4ae1c000 { - compatible = "ti,omap4-keypad"; - reg = <0x4ae1c000 0x400>; - ti,hwmods = "kbd"; - }; - mcpdm: mcpdm@40132000 { compatible = "ti,omap4-mcpdm"; reg = <0x40132000 0x7f>, /* MPU private access */ @@ -755,55 +272,6 @@ status = "disabled"; }; - mailbox: mailbox@4a0f4000 { - compatible = "ti,omap4-mailbox"; - reg = <0x4a0f4000 0x200>; - interrupts = ; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <3>; - ti,mbox-num-fifos = <8>; - mbox_ipu: mbox_ipu { - ti,mbox-tx = <0 0 0>; - ti,mbox-rx = <1 0 0>; - }; - mbox_dsp: mbox_dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <2 0 0>; - }; - }; - - timer1: timer@4ae18000 { - compatible = "ti,omap5430-timer"; - reg = <0x4ae18000 0x80>; - interrupts = ; - ti,hwmods = "timer1"; - ti,timer-alwon; - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; - clock-names = "fck"; - }; - - timer2: timer@48032000 { - compatible = "ti,omap5430-timer"; - reg = <0x48032000 0x80>; - interrupts = ; - ti,hwmods = "timer2"; - }; - - timer3: timer@48034000 { - compatible = "ti,omap5430-timer"; - reg = <0x48034000 0x80>; - interrupts = ; - ti,hwmods = "timer3"; - }; - - timer4: timer@48036000 { - compatible = "ti,omap5430-timer"; - reg = <0x48036000 0x80>; - interrupts = ; - ti,hwmods = "timer4"; - }; - timer5: timer@40138000 { compatible = "ti,omap5430-timer"; reg = <0x40138000 0x80>, @@ -843,37 +311,6 @@ ti,timer-pwm; }; - timer9: timer@4803e000 { - compatible = "ti,omap5430-timer"; - reg = <0x4803e000 0x80>; - interrupts = ; - ti,hwmods = "timer9"; - ti,timer-pwm; - }; - - timer10: timer@48086000 { - compatible = "ti,omap5430-timer"; - reg = <0x48086000 0x80>; - interrupts = ; - ti,hwmods = "timer10"; - ti,timer-pwm; - }; - - timer11: timer@48088000 { - compatible = "ti,omap5430-timer"; - reg = <0x48088000 0x80>; - interrupts = ; - ti,hwmods = "timer11"; - ti,timer-pwm; - }; - - wdt2: wdt@4ae14000 { - compatible = "ti,omap5-wdt", "ti,omap3-wdt"; - reg = <0x4ae14000 0x80>; - interrupts = ; - ti,hwmods = "wd_timer2"; - }; - dmm@4e000000 { compatible = "ti,omap5-dmm"; reg = <0x4e000000 0x800>; @@ -905,99 +342,6 @@ hw-caps-temp-alert; }; - usb3: omap_dwc3@4a020000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss"; - reg = <0x4a020000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - dwc3: dwc3@4a030000 { - compatible = "snps,dwc3"; - reg = <0x4a030000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - phys = <&usb2_phy>, <&usb3_phy>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "peripheral"; - }; - }; - - ocp2scp@4a080000 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x4a080000 0x20>; - ranges; - ti,hwmods = "ocp2scp1"; - usb2_phy: usb2phy@4a084000 { - compatible = "ti,omap-usb2"; - reg = <0x4a084000 0x7c>; - syscon-phy-power = <&scm_conf 0x300>; - clocks = <&usb_phy_cm_clk32k>, - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - }; - - usb3_phy: usb3phy@4a084400 { - compatible = "ti,omap-usb3"; - reg = <0x4a084400 0x80>, - <0x4a084800 0x64>, - <0x4a084c00 0x40>; - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x370>; - clocks = <&usb_phy_cm_clk32k>, - <&sys_clkin>, - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; - clock-names = "wkupclk", - "sysclk", - "refclk"; - #phy-cells = <0>; - }; - }; - - usbhstll: usbhstll@4a062000 { - compatible = "ti,usbhs-tll"; - reg = <0x4a062000 0x1000>; - interrupts = ; - ti,hwmods = "usb_tll_hs"; - }; - - usbhshost: usbhshost@4a064000 { - compatible = "ti,usbhs-host"; - reg = <0x4a064000 0x800>; - ti,hwmods = "usb_host_hs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&l3init_60m_fclk>, - <&xclk60mhsp1_ck>, - <&xclk60mhsp2_ck>; - clock-names = "refclk_60m_int", - "refclk_60m_ext_p1", - "refclk_60m_ext_p2"; - - usbhsohci: ohci@4a064800 { - compatible = "ti,ohci-omap3"; - reg = <0x4a064800 0x400>; - interrupts = ; - remote-wakeup-connected; - }; - - usbhsehci: ehci@4a064c00 { - compatible = "ti,ehci-omap"; - reg = <0x4a064c00 0x400>; - interrupts = ; - }; - }; - bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc @@ -1010,27 +354,6 @@ }; /* OCP2SCP3 */ - ocp2scp@4a090000 { - compatible = "ti,omap-ocp2scp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x4a090000 0x20>; - ranges; - ti,hwmods = "ocp2scp3"; - sata_phy: phy@4a096000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x4A096000 0x80>, /* phy_rx */ - <0x4A096400 0x64>, /* phy_tx */ - <0x4A096800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin>, - <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; - clock-names = "sysclk", "refclk"; - #phy-cells = <0>; - }; - }; - sata: sata@4a141100 { compatible = "snps,dwc-ahci"; reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; @@ -1184,6 +507,7 @@ coefficients = <65 (-1791)>; }; +#include "omap5-l4.dtsi" #include "omap54xx-clocks.dtsi" &gpu_thermal { -- cgit From 3f9d8677b73bbf62f7e53a165a88f953d1dca926 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 25 Jul 2018 17:55:16 +0200 Subject: ARM: dts: exynos: Add compatible for s2mps11 clocks node on Exynos542x The bindings for s2mps11/s5m8767 clocks driver require a compatible for clocks node. Parent MFD sec-core driver will also use it when instantiating children. The compatible is not needed for proper working because device will be anyway created by parent MFD device. Add it for correctness. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 1 + arch/arm/boot/dts/exynos5420-smdk5420.dts | 1 + arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index cdda614e417e..3447160e1fbf 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -89,6 +89,7 @@ pinctrl-0 = <&s2mps11_irq>; s2mps11_osc: clocks { + compatible = "samsung,s2mps11-clk"; #clock-cells = <1>; clock-output-names = "s2mps11_ap", "s2mps11_cp", "s2mps11_bt"; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 831c7336f237..3cf905047893 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -141,6 +141,7 @@ reg = <0x66>; s2mps11_osc: clocks { + compatible = "samsung,s2mps11-clk"; #clock-cells = <1>; clock-output-names = "s2mps11_ap", "s2mps11_cp", "s2mps11_bt"; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 2fac4baf1eb4..192789a6bead 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -141,6 +141,7 @@ pinctrl-0 = <&s2mps11_irq>; s2mps11_osc: clocks { + compatible = "samsung,s2mps11-clk"; #clock-cells = <1>; clock-output-names = "s2mps11_ap", "s2mps11_cp", "s2mps11_bt"; -- cgit From 56403a43c1557d8d0e475d020e1a20b068bd2791 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 25 Jul 2018 17:55:17 +0200 Subject: ARM: dts: exynos: Add compatible for s5m8767 clocks node on Itop Core The bindings for s2mps11/s5m8767 clocks driver require a compatible for clocks node. Parent MFD sec-core driver will also use it when instantiating children. The compatible is not needed for proper working because device will be anyway created by parent MFD device. Add it for correctness. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index ab7affab7f1c..8fdfd80c3acc 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -446,6 +446,7 @@ }; s5m8767_osc: clocks { + compatible = "samsung,s5m8767-clk"; #clock-cells = <1>; clock-output-names = "s5m8767_ap", "s5m8767_cp", "s5m8767_bt"; -- cgit From c353b80ee59574b228a6d3dcef5142c80c403c36 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 9 Nov 2018 15:59:40 +0100 Subject: ARM: dts: exynos: Add missing clocks to RTC node for Arndale board Add missing clocks to SoC build-in RTC device to make it fully operational on Exynos5250-based Arndale board. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250-arndale.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 7d1f2dc59038..e2e5b3f28686 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -10,6 +10,7 @@ #include #include #include +#include #include "exynos5250.dtsi" / { @@ -264,6 +265,12 @@ <&gpx2 4 GPIO_ACTIVE_HIGH>, <&gpx2 5 GPIO_ACTIVE_HIGH>; + s5m8767_osc: clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "s5m8767_ap", "unused1", "unused2"; + }; + regulators { ldo1_reg: LDO1 { regulator-name = "VDD_ALIVE_1.0V"; @@ -601,6 +608,8 @@ }; &rtc { + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; status = "okay"; }; -- cgit From aeee3d9cb776542f5700425f703fa78c70a1dcd0 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 7 Nov 2018 15:24:26 +0000 Subject: arm64: dts: renesas: r8a774a1: Replace power magic numbers Now that include/dt-bindings/power/r8a774a1-sysc.h is in Linus' master branch we can replace power related magic numbers with the corresponding labels. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 201 +++++++++++++++--------------- 1 file changed, 101 insertions(+), 100 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 78ac8e3cda6e..d549755a4025 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { compatible = "renesas,r8a774a1"; @@ -63,7 +64,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; - power-domains = <&sysc 0>; + power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; clocks = <&cpg CPG_CORE 0>; @@ -73,7 +74,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x1>; device_type = "cpu"; - power-domains = <&sysc 1>; + power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; clocks = <&cpg CPG_CORE 0>; @@ -83,7 +84,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x100>; device_type = "cpu"; - power-domains = <&sysc 5>; + power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks =<&cpg CPG_CORE 1>; @@ -93,7 +94,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x101>; device_type = "cpu"; - power-domains = <&sysc 6>; + power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks =<&cpg CPG_CORE 1>; @@ -103,7 +104,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x102>; device_type = "cpu"; - power-domains = <&sysc 7>; + power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks =<&cpg CPG_CORE 1>; @@ -113,7 +114,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x103>; device_type = "cpu"; - power-domains = <&sysc 8>; + power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks =<&cpg CPG_CORE 1>; @@ -121,14 +122,14 @@ L2_CA57: cache-controller-0 { compatible = "cache"; - power-domains = <&sysc 12>; + power-domains = <&sysc R8A774A1_PD_CA57_SCU>; cache-unified; cache-level = <2>; }; L2_CA53: cache-controller-1 { compatible = "cache"; - power-domains = <&sysc 21>; + power-domains = <&sysc R8A774A1_PD_CA53_SCU>; cache-unified; cache-level = <2>; }; @@ -195,7 +196,7 @@ "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 402>; status = "disabled"; }; @@ -211,7 +212,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 912>; }; @@ -226,7 +227,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 911>; }; @@ -241,7 +242,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 910>; }; @@ -256,7 +257,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 909>; }; @@ -271,7 +272,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 908>; }; @@ -286,7 +287,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 907>; }; @@ -301,7 +302,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 906>; }; @@ -316,7 +317,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 905>; }; @@ -355,7 +356,7 @@ , ; clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 522>; #thermal-sensor-cells = <1>; }; @@ -372,7 +373,7 @@ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 407>; }; @@ -384,7 +385,7 @@ reg = <0 0xe6500000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 931>; dmas = <&dmac1 0x91>, <&dmac1 0x90>, <&dmac2 0x91>, <&dmac2 0x90>; @@ -401,7 +402,7 @@ reg = <0 0xe6508000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 930>; dmas = <&dmac1 0x93>, <&dmac1 0x92>, <&dmac2 0x93>, <&dmac2 0x92>; @@ -418,7 +419,7 @@ reg = <0 0xe6510000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 929>; dmas = <&dmac1 0x95>, <&dmac1 0x94>, <&dmac2 0x95>, <&dmac2 0x94>; @@ -435,7 +436,7 @@ reg = <0 0xe66d0000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 928>; dmas = <&dmac0 0x97>, <&dmac0 0x96>; dma-names = "tx", "rx"; @@ -451,7 +452,7 @@ reg = <0 0xe66d8000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 927>; dmas = <&dmac0 0x99>, <&dmac0 0x98>; dma-names = "tx", "rx"; @@ -467,7 +468,7 @@ reg = <0 0xe66e0000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 919>; dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; dma-names = "tx", "rx"; @@ -483,7 +484,7 @@ reg = <0 0xe66e8000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 918>; dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; dma-names = "tx", "rx"; @@ -500,7 +501,7 @@ reg = <0 0xe60b0000 0 0x425>; interrupts = ; clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 926>; dmas = <&dmac0 0x11>, <&dmac0 0x10>; dma-names = "tx", "rx"; @@ -520,7 +521,7 @@ dmas = <&dmac1 0x31>, <&dmac1 0x30>, <&dmac2 0x31>, <&dmac2 0x30>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 520>; status = "disabled"; }; @@ -538,7 +539,7 @@ dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 519>; status = "disabled"; }; @@ -556,7 +557,7 @@ dmas = <&dmac1 0x35>, <&dmac1 0x34>, <&dmac2 0x35>, <&dmac2 0x34>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 518>; status = "disabled"; }; @@ -573,7 +574,7 @@ clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x37>, <&dmac0 0x36>; dma-names = "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 517>; status = "disabled"; }; @@ -590,7 +591,7 @@ clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x38>; dma-names = "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 516>; status = "disabled"; }; @@ -607,7 +608,7 @@ renesas,buswait = <11>; phys = <&usb2_phy0>; phy-names = "usb"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 704>; status = "disabled"; }; @@ -620,7 +621,7 @@ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 330>; #dma-cells = <1>; dma-channels = <2>; @@ -634,7 +635,7 @@ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ch0", "ch1"; clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 331>; #dma-cells = <1>; dma-channels = <2>; @@ -647,7 +648,7 @@ clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, <&usb_extal_clk>; clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 328>; #phy-cells = <0>; status = "disabled"; @@ -681,7 +682,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <16>; @@ -715,7 +716,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <16>; @@ -749,7 +750,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 217>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <16>; @@ -759,7 +760,7 @@ compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -767,7 +768,7 @@ compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -775,7 +776,7 @@ compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -784,7 +785,7 @@ reg = <0 0xe67b0000 0 0x1000>; interrupts = , ; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -792,7 +793,7 @@ compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -800,7 +801,7 @@ compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -808,7 +809,7 @@ compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfd950000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -816,7 +817,7 @@ compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc 14>; + power-domains = <&sysc R8A774A1_PD_A3VC>; #iommu-cells = <1>; }; @@ -824,7 +825,7 @@ compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -865,7 +866,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; #address-cells = <1>; @@ -880,7 +881,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 916>, <&can_clk>; clock-names = "clkp1", "can_clk"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 916>; status = "disabled"; }; @@ -892,7 +893,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 915>, <&can_clk>; clock-names = "clkp1", "can_clk"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 915>; status = "disabled"; }; @@ -903,7 +904,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; @@ -913,7 +914,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; @@ -923,7 +924,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; @@ -933,7 +934,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; @@ -943,7 +944,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; @@ -953,7 +954,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; @@ -963,7 +964,7 @@ #pwm-cells = <2>; clocks = <&cpg CPG_MOD 523>; resets = <&cpg 523>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; status = "disabled"; }; @@ -979,7 +980,7 @@ dmas = <&dmac1 0x51>, <&dmac1 0x50>, <&dmac2 0x51>, <&dmac2 0x50>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 207>; status = "disabled"; }; @@ -996,7 +997,7 @@ dmas = <&dmac1 0x53>, <&dmac1 0x52>, <&dmac2 0x53>, <&dmac2 0x52>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 206>; status = "disabled"; }; @@ -1010,7 +1011,7 @@ <&cpg CPG_CORE 19>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 310>; status = "disabled"; }; @@ -1026,7 +1027,7 @@ clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x57>, <&dmac0 0x56>; dma-names = "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 204>; status = "disabled"; }; @@ -1042,7 +1043,7 @@ clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x59>, <&dmac0 0x58>; dma-names = "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 203>; status = "disabled"; }; @@ -1059,7 +1060,7 @@ dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, <&dmac2 0x5b>, <&dmac2 0x5a>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 202>; status = "disabled"; }; @@ -1073,7 +1074,7 @@ dmas = <&dmac1 0x41>, <&dmac1 0x40>, <&dmac2 0x41>, <&dmac2 0x40>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 211>; #address-cells = <1>; #size-cells = <0>; @@ -1089,7 +1090,7 @@ dmas = <&dmac1 0x43>, <&dmac1 0x42>, <&dmac2 0x43>, <&dmac2 0x42>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 210>; #address-cells = <1>; #size-cells = <0>; @@ -1104,7 +1105,7 @@ clocks = <&cpg CPG_MOD 209>; dmas = <&dmac0 0x45>, <&dmac0 0x44>; dma-names = "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 209>; #address-cells = <1>; #size-cells = <0>; @@ -1119,7 +1120,7 @@ clocks = <&cpg CPG_MOD 208>; dmas = <&dmac0 0x47>, <&dmac0 0x46>; dma-names = "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; @@ -1131,7 +1132,7 @@ reg = <0 0xe6ef0000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 811>; renesas,id = <0>; status = "disabled"; @@ -1163,7 +1164,7 @@ reg = <0 0xe6ef1000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 810>; renesas,id = <1>; status = "disabled"; @@ -1195,7 +1196,7 @@ reg = <0 0xe6ef2000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 809>; renesas,id = <2>; status = "disabled"; @@ -1227,7 +1228,7 @@ reg = <0 0xe6ef3000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 808>; renesas,id = <3>; status = "disabled"; @@ -1259,7 +1260,7 @@ reg = <0 0xe6ef4000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 807>; renesas,id = <4>; status = "disabled"; @@ -1291,7 +1292,7 @@ reg = <0 0xe6ef5000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 806>; renesas,id = <5>; status = "disabled"; @@ -1323,7 +1324,7 @@ reg = <0 0xe6ef6000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 805>; renesas,id = <6>; status = "disabled"; @@ -1355,7 +1356,7 @@ reg = <0 0xe6ef7000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 804>; renesas,id = <7>; status = "disabled"; @@ -1431,7 +1432,7 @@ "ctu.1", "ctu.0", "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 1005>, <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, @@ -1617,7 +1618,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <16>; @@ -1651,7 +1652,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <16>; @@ -1663,7 +1664,7 @@ reg = <0 0xee000000 0 0xc00>; interrupts = ; clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 328>; status = "disabled"; }; @@ -1674,7 +1675,7 @@ reg = <0 0xee020000 0 0x400>; interrupts = ; clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 328>; status = "disabled"; }; @@ -1686,7 +1687,7 @@ clocks = <&cpg CPG_MOD 703>; phys = <&usb2_phy0>; phy-names = "usb"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 703>; status = "disabled"; }; @@ -1698,7 +1699,7 @@ clocks = <&cpg CPG_MOD 702>; phys = <&usb2_phy1>; phy-names = "usb"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 702>; status = "disabled"; }; @@ -1711,7 +1712,7 @@ phys = <&usb2_phy0>; phy-names = "usb"; companion = <&ohci0>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 703>; status = "disabled"; }; @@ -1724,7 +1725,7 @@ phys = <&usb2_phy1>; phy-names = "usb"; companion = <&ohci1>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 702>; status = "disabled"; }; @@ -1735,7 +1736,7 @@ reg = <0 0xee080200 0 0x700>; interrupts = ; clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 703>; #phy-cells = <0>; status = "disabled"; @@ -1746,7 +1747,7 @@ "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0a0200 0 0x700>; clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 702>; #phy-cells = <0>; status = "disabled"; @@ -1759,7 +1760,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 314>; max-frequency = <200000000>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 314>; status = "disabled"; }; @@ -1771,7 +1772,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 313>; max-frequency = <200000000>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 313>; status = "disabled"; }; @@ -1783,7 +1784,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 312>; max-frequency = <200000000>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 312>; status = "disabled"; }; @@ -1795,7 +1796,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 311>; max-frequency = <200000000>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 311>; status = "disabled"; }; @@ -1813,7 +1814,7 @@ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 408>; }; @@ -1821,7 +1822,7 @@ compatible = "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>; clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc 14>; + power-domains = <&sysc R8A774A1_PD_A3VC>; resets = <&cpg 615>; }; @@ -1829,7 +1830,7 @@ compatible = "renesas,fcpv"; reg = <0 0xfe96f000 0 0x200>; clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc 14>; + power-domains = <&sysc R8A774A1_PD_A3VC>; resets = <&cpg 607>; }; @@ -1837,7 +1838,7 @@ compatible = "renesas,fcpv"; reg = <0 0xfea27000 0 0x200>; clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 603>; iommus = <&ipmmu_vi0 8>; }; @@ -1846,7 +1847,7 @@ compatible = "renesas,fcpv"; reg = <0 0xfea2f000 0 0x200>; clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 602>; iommus = <&ipmmu_vi0 9>; }; @@ -1855,7 +1856,7 @@ compatible = "renesas,fcpv"; reg = <0 0xfea37000 0 0x200>; clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 601>; iommus = <&ipmmu_vi0 10>; }; @@ -1864,7 +1865,7 @@ compatible = "renesas,fcpv"; reg = <0 0xfe9af000 0 0x200>; clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc 14>; + power-domains = <&sysc R8A774A1_PD_A3VC>; resets = <&cpg 611>; iommus = <&ipmmu_vc0 19>; }; @@ -1874,7 +1875,7 @@ reg = <0 0xfea80000 0 0x10000>; interrupts = ; clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 714>; status = "disabled"; @@ -1929,7 +1930,7 @@ reg = <0 0xfeaa0000 0 0x10000>; interrupts = ; clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 716>; status = "disabled"; -- cgit From 8ebb50389eed04b989a0d5532f9208c338bf66b8 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 7 Nov 2018 15:24:27 +0000 Subject: arm64: dts: renesas: r8a774a1: Replace clock magic numbers Now that include/dt-bindings/clock/r8a774a1-cpg-mssr.h is in Linus' master branch we can replace clock related magic numbers with the corresponding labels. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven [simon: corrected whitespace] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++---------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index d549755a4025..20745a8528c5 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -7,7 +7,7 @@ #include #include -#include +#include #include / { @@ -67,7 +67,7 @@ power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; - clocks = <&cpg CPG_CORE 0>; + clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; }; a57_1: cpu@1 { @@ -77,7 +77,7 @@ power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; - clocks = <&cpg CPG_CORE 0>; + clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; }; a53_0: cpu@100 { @@ -87,7 +87,7 @@ power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; - clocks =<&cpg CPG_CORE 1>; + clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; }; a53_1: cpu@101 { @@ -97,7 +97,7 @@ power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; - clocks =<&cpg CPG_CORE 1>; + clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; }; a53_2: cpu@102 { @@ -107,7 +107,7 @@ power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; - clocks =<&cpg CPG_CORE 1>; + clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; }; a53_3: cpu@103 { @@ -117,7 +117,7 @@ power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; - clocks =<&cpg CPG_CORE 1>; + clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; }; L2_CA57: cache-controller-0 { @@ -515,7 +515,7 @@ reg = <0 0xe6540000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x31>, <&dmac1 0x30>, @@ -533,7 +533,7 @@ reg = <0 0xe6550000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x33>, <&dmac1 0x32>, @@ -551,7 +551,7 @@ reg = <0 0xe6560000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x35>, <&dmac1 0x34>, @@ -569,7 +569,7 @@ reg = <0 0xe66a0000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x37>, <&dmac0 0x36>; @@ -586,7 +586,7 @@ reg = <0 0xe66b0000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x38>; @@ -974,7 +974,7 @@ reg = <0 0xe6e60000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x51>, <&dmac1 0x50>, @@ -991,7 +991,7 @@ reg = <0 0xe6e68000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x53>, <&dmac1 0x52>, @@ -1008,7 +1008,7 @@ reg = <0 0xe6e88000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -1022,7 +1022,7 @@ reg = <0 0xe6c50000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x57>, <&dmac0 0x56>; @@ -1038,7 +1038,7 @@ reg = <0 0xe6c40000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x59>, <&dmac0 0x58>; @@ -1054,7 +1054,7 @@ reg = <0 0xe6f30000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A774A1_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, @@ -1420,7 +1420,7 @@ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE 10>; + <&cpg CPG_CORE R8A774A1_CLK_S0D4>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", -- cgit From 703c605fac82d580822dc39f5eff9e2fe66ed63d Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Mon, 22 Oct 2018 22:15:48 +0200 Subject: ARM: dts: bcm2835-rpi-zero: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 8 +------- arch/arm/boot/dts/bcm2835-rpi-zero.dts | 8 +------- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index b7f79f1c431a..644d907bafbb 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017 Stefan Wahren - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ /dts-v1/; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index 70362405c595..00323ba8f7de 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -1,12 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Stefan Wahren - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ /dts-v1/; -- cgit From f68b18fd1c4b64859712dde3fa93a7716220201b Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 18 Sep 2018 10:16:53 +0200 Subject: arm64: dts: exynos: Update DWC3 modules on Exynos5433 SoCs Update DWC3 hardware modules to Exynos5433 specific variant: change compatible name and add all required clocks (both to the glue node and DWC3 core node). Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 2131f12364cb..84446f95b2eb 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1559,10 +1559,12 @@ }; usbdrd30: usbdrd { - compatible = "samsung,exynos5250-dwusb3"; + compatible = "samsung,exynos5433-dwusb3"; clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, - <&cmu_fsys CLK_SCLK_USBDRD30>; - clock-names = "usbdrd30", "usbdrd30_susp_clk"; + <&cmu_fsys CLK_SCLK_USBDRD30>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>; + clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk"; #address-cells = <1>; #size-cells = <1>; ranges; @@ -1570,6 +1572,10 @@ usbdrd_dwc3: dwc3@15400000 { compatible = "snps,dwc3"; + clocks = <&cmu_fsys CLK_SCLK_USBDRD30>, + <&cmu_fsys CLK_ACLK_USBDRD30>, + <&cmu_fsys CLK_SCLK_USBDRD30>; + clock-names = "ref", "bus_early", "suspend"; reg = <0x15400000 0x10000>; interrupts = ; phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>; @@ -1606,10 +1612,12 @@ }; usbhost30: usbhost { - compatible = "samsung,exynos5250-dwusb3"; + compatible = "samsung,exynos5433-dwusb3"; clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, - <&cmu_fsys CLK_SCLK_USBHOST30>; - clock-names = "usbdrd30", "usbdrd30_susp_clk"; + <&cmu_fsys CLK_SCLK_USBHOST30>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>; + clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk"; #address-cells = <1>; #size-cells = <1>; ranges; @@ -1617,6 +1625,10 @@ usbhost_dwc3: dwc3@15a00000 { compatible = "snps,dwc3"; + clocks = <&cmu_fsys CLK_SCLK_USBHOST30>, + <&cmu_fsys CLK_ACLK_USBHOST30>, + <&cmu_fsys CLK_SCLK_USBHOST30>; + clock-names = "ref", "bus_early", "suspend"; reg = <0x15a00000 0x10000>; interrupts = ; phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>; -- cgit From 25e5566e2b6e3ea0768505f75db887d7176150ce Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Thu, 27 Sep 2018 14:07:33 +0000 Subject: ARM: dts: exynos: Add UHS-I bus speed support to Odroid XU3/XU4/HC1 Add support for UHS-I bus speed tuning for SDR50, DDR50 and SDR104 to Odroid XU3/XU4/HC1 family boards. Signed-off-by: Anand Moon Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 192789a6bead..7aeb9c3f934f 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -504,6 +504,9 @@ cap-sd-highspeed; vmmc-supply = <&ldo19_reg>; vqmmc-supply = <&ldo13_reg>; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; }; &nocp_mem0_0 { -- cgit From 8fe325fa9d065aa54db4914fdaccab2169fd67a8 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Thu, 27 Sep 2018 14:07:34 +0000 Subject: ARM: dts: exynos: Fix LDO13 min values on Odroid XU3/XU4/HC1 From Odroid XU3/XU4/HC1 schematics the LDO13 regulator for SD2, can be set on 1.8V or 2.8V so the minimal value should be fixed to 1.8V. This is necessary to support UHS-I tuning (otherwise card won't be detected during boot). Signed-off-by: Anand Moon Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 7aeb9c3f934f..018ccde1e878 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -232,7 +232,7 @@ ldo13_reg: LDO13 { regulator-name = "vddq_mmc2"; - regulator-min-microvolt = <2800000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2800000>; }; -- cgit From c60b3f77f497d2720f7b841e78acfcf24fee071a Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Thu, 27 Sep 2018 14:07:35 +0000 Subject: ARM: dts: exynos: Update maximum frequency for SD card to 200MHz on Odroid XU3/XU4/HC1 Set the SD max-frequency to 200MHz for optimal performance on Odroid XU3/XU4/HC1 family of boards. Signed-off-by: Anand Moon Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 018ccde1e878..916dec4c6174 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -502,6 +502,7 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + max-frequency = <200000000>; vmmc-supply = <&ldo19_reg>; vqmmc-supply = <&ldo13_reg>; sd-uhs-sdr50; -- cgit From 4289c86c4cd7a848590e1e2c3e0e3274136b6848 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Thu, 27 Sep 2018 14:07:37 +0000 Subject: ARM: dts: exynos: Update maximum frequency for eMMC to 200MHz on Odroid XU3/XU4 Set the eMMC max-frequency to 200MHz for optimal performance on Odroid XU3/XU4 family of boards. Signed-off-by: Anand Moon Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index e522edb2bb82..1f2d3987dde1 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -392,6 +392,7 @@ cap-mmc-highspeed; mmc-hs200-1_8v; mmc-hs400-1_8v; + max-frequency = <200000000>; vmmc-supply = <&ldo18_reg>; vqmmc-supply = <&ldo3_reg>; }; -- cgit From 6135ee70cb1314681772645242beee46fcf5d185 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Thu, 27 Sep 2018 14:07:36 +0000 Subject: ARM: dts: exynos: Add pin configuration for SD write protect on Odroid XU3/XU4/HC1 Add SD card write-protect pin configuration to be sure that it will be properly pulled down to indicate write access. Suggested-by: Krzysztof Kozlowski Signed-off-by: Anand Moon Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 7 +++++++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index dda8ca2d2324..b82af7c89654 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -289,6 +289,13 @@ samsung,pin-pud = ; samsung,pin-drv = ; }; + + sd2_wp: sd2-wp { + samsung,pins = "gpc4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pinctrl_2 { diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 916dec4c6174..60e91b98ad30 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -499,7 +499,7 @@ samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; max-frequency = <200000000>; -- cgit From bdccbb79e4f0732ef49d6f2e6fb13cea5879354b Mon Sep 17 00:00:00 2001 From: Martin Kaiser Date: Thu, 1 Nov 2018 18:32:47 +0100 Subject: ARM: dts: i.MX25: add the clocks for the EPIT blocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The i.MX25 contains two EPIT (Enhanced Periodic Interrupt Timer) function blocks. Add their ipg and per clocks to the device tree. Signed-off-by: Martin Kaiser Acked-by: Clément Péron Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index b25309d26ea5..e80101847aff 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -388,12 +388,16 @@ epit1: timer@53f94000 { compatible = "fsl,imx25-epit"; reg = <0x53f94000 0x4000>; + clocks = <&clks 83>, <&clks 43>; + clock-names = "ipg", "per"; interrupts = <28>; }; epit2: timer@53f98000 { compatible = "fsl,imx25-epit"; reg = <0x53f98000 0x4000>; + clocks = <&clks 84>, <&clks 43>; + clock-names = "ipg", "per"; interrupts = <27>; }; -- cgit From 3c84c05b8b909cae497360a79766877995d2ec68 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Wed, 1 Aug 2018 02:15:26 +0530 Subject: MAINTAINERS: Add entry for Qualcomm TSENS thermal drivers Create an entry for the TSENS drivers and mark them as maintained Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke Acked-by: Rajendra Nayak Acked-by: Bjorn Andersson Signed-off-by: Andy Gross --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f4855974f325..d6999567c0dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12359,6 +12359,13 @@ L: linux-arm-msm@vger.kernel.org S: Maintained F: drivers/iommu/qcom_iommu.c +QUALCOMM TSENS THERMAL DRIVER +M: Amit Kucheria +L: linux-pm@vger.kernel.org +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: drivers/thermal/qcom/ + QUALCOMM VENUS VIDEO ACCELERATOR DRIVER M: Stanimir Varbanov L: linux-media@vger.kernel.org -- cgit From 58443fd91057f073306cbbfc9db3b6a292fd51e5 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Thu, 6 Sep 2018 15:24:12 +0530 Subject: ARM: dts: msm8974: thermal: split address space into two We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for msm8974 that has a similar register layout. Since tsens-common.c/init_common() currently only registers one address space, the order is important (TM before SROT). This is OK since the code doesn't really use the SROT functionality yet. Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke Acked-by: Andy Gross Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8974.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index aba159d5a95a..35d3d5240996 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -427,9 +427,10 @@ }; }; - tsens: thermal-sensor@fc4a8000 { + tsens: thermal-sensor@fc4a9000 { compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a8000 0x2000>; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; #thermal-sensor-cells = <1>; -- cgit From e9d753b820e578745d2d0e558b3797fccef190e6 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Fri, 10 Aug 2018 10:38:09 +0530 Subject: ARM: dts: msm8974: thermal: Add "qcom,sensors" property This new property allows the number of sensors to be configured from DT instead of being hardcoded in platform data. Use it. Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke Reviewed-by: Bjorn Andersson Acked-by: Andy Gross Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 35d3d5240996..c3470f9ec747 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -433,6 +433,7 @@ <0xfc4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; + #qcom,sensors = <11>; #thermal-sensor-cells = <1>; }; -- cgit From 95b0ddfd21ed516b8af3375948e0c1e6f409894b Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Thu, 6 Sep 2018 15:26:39 +0530 Subject: arm64: dts: msm8916: thermal: split address space into two We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for msm8916 that has a similar register layout. Since tsens-common.c/init_common() currently only registers one address space, the order is important (TM before SROT). This is OK since the code doesn't really use the SROT functionality yet. Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke Acked-by: Andy Gross Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d302d8d639a1..1bf19a24ffa7 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -758,9 +758,10 @@ }; }; - tsens: thermal-sensor@4a8000 { + tsens: thermal-sensor@4a9000 { compatible = "qcom,msm8916-tsens"; - reg = <0x4a8000 0x2000>; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; nvmem-cell-names = "calib", "calib_sel"; #thermal-sensor-cells = <1>; -- cgit From 2b4e5fc0edfe071c7ac625038d38dd7682fe7c5f Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Thu, 6 Sep 2018 15:44:34 +0530 Subject: arm64: dts: msm8916: thermal: Add "qcom,sensors" property This new property allows the number of sensors to be configured from DT instead of being hardcoded in platform data. Use it. Signed-off-by: Amit Kucheria Reviewed-by: Bjorn Andersson Acked-by: Andy Gross Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 1bf19a24ffa7..2288826de3cd 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -764,6 +764,7 @@ <0x4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; nvmem-cell-names = "calib", "calib_sel"; + #qcom,sensors = <5>; #thermal-sensor-cells = <1>; }; -- cgit From 154233c8988a1549d6f7fc41197c73d8bb4a4670 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Mon, 10 Sep 2018 12:39:53 +0530 Subject: arm64: dts: msm8916: Add gpu thermal zone Initialise the gpu thermal zone to export temperature to userspace. Signed-off-by: Amit Kucheria Acked-by: Andy Gross Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 2288826de3cd..392223e68b00 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -234,6 +234,26 @@ }; }; + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + gpu_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; cpu_opp_table: cpu_opp_table { -- cgit From 9ee80560a32932873548bb867a46970cdfd1ca40 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Mon, 20 Aug 2018 15:36:26 +0530 Subject: arm64: dts: msm8916: Add camera thermal zone Initialise the camera thermal zone to export temperature to userspace. Signed-off-by: Amit Kucheria Acked-by: Andy Gross Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 392223e68b00..42e72a3164b9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -254,6 +254,27 @@ }; }; + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + cam_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cam_crit: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + }; + }; cpu_opp_table: cpu_opp_table { -- cgit From 4884788b7ba1a2136f8eff5396d33246af7e55f2 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Tue, 12 Jun 2018 15:26:54 +0300 Subject: arm64: dts: sdm845: enable tsens thermal zones One thermal zone per cpu is defined Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke Tested-by: Matthias Kaehlcke Acked-by: Andy Gross Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++++++++++++++++++++++++++++++++++ 1 file changed, 170 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b72bdb0a31a5..98d054043266 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1404,4 +1404,174 @@ }; }; }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpu_alert4: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit4: trip1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu_alert5: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit5: trip1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu_alert6: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit6: trip1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu_alert7: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit7: trip1 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; }; -- cgit From b59b94f76e7fa257e92d8e8b0c79755493356861 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 12 Nov 2018 14:11:25 -0800 Subject: dt-bindings: iio: vadc: Add unit address to ADC channel node in example The node has a reg property, therefore its name should include a unit address. Also change the name from 'usb_id_nopull' to 'adc-chan', which is the preferred name for ADC channel nodes. Include headers for constants used in the example. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt index b3c86f4ac7cd..c81993f8d8c3 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt @@ -140,6 +140,10 @@ VADC_GND_REF and VADC_VDD_VADC. Example: +#include +#include +/* ... */ + /* VADC node */ pmic_vadc: vadc@3100 { compatible = "qcom,spmi-vadc"; @@ -151,7 +155,7 @@ Example: io-channel-ranges; /* Channel node */ - usb_id_nopull { + adc-chan@VADC_LR_MUX10_USB_ID { reg = ; qcom,decimation = <512>; qcom,ratiometric; -- cgit From a789fd0bab57d5883e441a09596e1a77f698e62c Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Mon, 12 Nov 2018 14:11:26 -0800 Subject: arm64: dts: qcom: pm8998: Add die temperature channel node to the ADC Add a channel node for the die temperature to the ADC. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pm8998.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 048f19fa0150..f1025a50c227 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -75,6 +75,11 @@ #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; + + adc-chan@ADC5_DIE_TEMP { + reg = ; + label = "die_temp"; + }; }; rtc@6000 { -- cgit From e55b892e1848e220f5248583b99bdcde63fe8f05 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Oct 2018 13:35:13 +0100 Subject: dt-bindings: timer: meson6_timer: document all interrupts The meson6_timer IP block supports four timers - each of them has it's own interrupt line. Update the documentation to reflect that all four interrupts should be passed. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt index a092053f7902..dbdda92cffb7 100644 --- a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt +++ b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt @@ -4,12 +4,15 @@ Required properties: - compatible : should be "amlogic,meson6-timer" - reg : Specifies base physical address and size of the registers. -- interrupts : The interrupt of the first timer +- interrupts : The four interrupts, one for each timer event Example: timer@c1109940 { compatible = "amlogic,meson6-timer"; reg = <0xc1109940 0x14>; - interrupts = <0 10 1>; + interrupts = , + , + , + ; }; -- cgit From be215b92703bd730fe3968ae8ee1de2e22ba5b1d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Oct 2018 13:35:14 +0100 Subject: dt-bindings: timer: meson6_timer: document the clock inputs The Meson Timer IP has two clock inputs: - pclk which is used as "system clock" timebase of Timer E - xtal which is used for the 1us, 10us, 100us and 1ms timebases of Timer A, B, C, D and E The IP block has four internal dividers (XTAL is running at 24MHz): - "xtal div 24" for 1us resolution - "xtal div 240" for 10us resolution - "xtal div 2400" for 100us resolution - "xtal div 24000" for 1ms resolution Suggested-by: Jianxin Pan Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt index dbdda92cffb7..a9da22bda912 100644 --- a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt +++ b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt @@ -5,6 +5,8 @@ Required properties: - compatible : should be "amlogic,meson6-timer" - reg : Specifies base physical address and size of the registers. - interrupts : The four interrupts, one for each timer event +- clocks : phandles to the pclk (system clock) and XTAL clocks +- clock-names : must contain "pclk" and "xtal" Example: @@ -15,4 +17,6 @@ timer@c1109940 { , , ; + clocks = <&xtal>, <&clk81>; + clock-names = "xtal", "pclk"; }; -- cgit From eabb3d424b6df102c6f6fd42323ef37f1f96f010 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 4 Oct 2018 20:28:49 +0800 Subject: arm64: dts: allwinner: h6: add USB2-related device nodes Allwinner H6 has two USB2 ports, one OTG and one host-only. Add device tree nodes related to them. Signed-off-by: Icenowy Zheng Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 82 ++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 45bbb5116446..e28a0fc4c8fa 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -345,6 +345,88 @@ }; }; + usb2otg: usb@5100000 { + compatible = "allwinner,sun50i-h6-musb", + "allwinner,sun8i-a33-musb"; + reg = <0x05100000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usb2phy 0>; + phy-names = "usb"; + extcon = <&usb2phy 0>; + status = "disabled"; + }; + + usb2phy: phy@5100400 { + compatible = "allwinner,sun50i-h6-usb-phy"; + reg = <0x05100400 0x24>, + <0x05101800 0x4>, + <0x05311800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu3"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY3>; + clock-names = "usb0_phy", + "usb3_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY3>; + reset-names = "usb0_reset", + "usb3_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@5101000 { + compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; + reg = <0x05101000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + status = "disabled"; + }; + + ohci0: usb@5101400 { + compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; + reg = <0x05101400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + + ehci3: usb@5311000 { + compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; + reg = <0x05311000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI3>, + <&ccu CLK_BUS_EHCI3>, + <&ccu CLK_USB_OHCI3>; + resets = <&ccu RST_BUS_OHCI3>, + <&ccu RST_BUS_EHCI3>; + phys = <&usb2phy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci3: usb@5311400 { + compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; + reg = <0x05311400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI3>, + <&ccu CLK_USB_OHCI3>; + resets = <&ccu RST_BUS_OHCI3>; + phys = <&usb2phy 3>; + phy-names = "usb"; + status = "disabled"; + }; + hdmi: hdmi@6000000 { compatible = "allwinner,sun50i-h6-dw-hdmi"; reg = <0x06000000 0x10000>; -- cgit From 44eb589cf40aa80a345d5178907856e4b9308b01 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 4 Oct 2018 20:28:50 +0800 Subject: arm64: dts: allwinner: h6: add USB Vbus regulator for Pine H64 The 5V output of the USB ports on Pine H64 is controlled via a GPIO. Add the USB Vbus regulator device tree node. Signed-off-by: Icenowy Zheng Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index 59e5464742b0..9f127c611587 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -51,6 +51,16 @@ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ }; }; + + reg_usb_vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "usb-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &emac { -- cgit From 3bfa011d3a47a776c7a9273782da41bf123d26ad Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 4 Oct 2018 20:28:51 +0800 Subject: arm64: dts: allwinner: h6: enable USB2 on Pine H64 Pine H64 board has both the USB2 OTG pins and the USB2 host pins on H6 SoC wired out to USB Type-A ports. Enable them. Signed-off-by: Icenowy Zheng Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Signed-off-by: Chen-Yu Tsai --- .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index 9f127c611587..bdb8470fc8dc 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -95,6 +95,14 @@ }; }; +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -115,6 +123,14 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + &r_i2c { status = "okay"; @@ -240,3 +256,14 @@ pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; + +&usb2otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb2phy { + usb0_vbus-supply = <®_usb_vbus>; + usb3_vbus-supply = <®_usb_vbus>; + status = "okay"; +}; -- cgit From b380ae0db6039131fd0ad985b760c5b3f5096dfc Mon Sep 17 00:00:00 2001 From: Gaku Inami Date: Thu, 8 Nov 2018 16:24:54 +0900 Subject: arm64: dts: renesas: Add CPU topology on R-Car Gen3 SoCs This patch adds the "cpu-map" into r8a7795/r8a7796 composed of multi-cluster. This definition is used to parse the cpu topology. Signed-off-by: Gaku Inami Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 26 ++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 660fd54d384b..408ff4e8170a 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -116,6 +116,38 @@ #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a57_0>; + }; + core1 { + cpu = <&a57_1>; + }; + core2 { + cpu = <&a57_2>; + }; + core3 { + cpu = <&a57_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&a53_0>; + }; + core1 { + cpu = <&a53_1>; + }; + core2 { + cpu = <&a53_2>; + }; + core3 { + cpu = <&a53_3>; + }; + }; + }; + a57_0: cpu@0 { compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 3baee26ae372..b12bf73bb03b 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -127,6 +127,32 @@ #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a57_0>; + }; + core1 { + cpu = <&a57_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&a53_0>; + }; + core1 { + cpu = <&a53_1>; + }; + core2 { + cpu = <&a53_2>; + }; + core3 { + cpu = <&a53_3>; + }; + }; + }; + a57_0: cpu@0 { compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; -- cgit From 2250d856b279d992c392170860a78c2482b1859c Mon Sep 17 00:00:00 2001 From: Gaku Inami Date: Thu, 8 Nov 2018 16:24:55 +0900 Subject: arm64: dts: renesas: Add CPU capacity-dmips-mhz Set the capacity-dmips-mhz for R-Car Gen3 SoCs, that is based on dhrystone. The average in 10 times of dhrystone result as follows: r8a7795 SoC (A57x4 + A53x4) CPU max-freq dhrystone --------------------------------- A57 1500 MHz 11470943 lps/s A53 1200 MHz 4798583 lps/s r8a7796 SoC (A57x2 + A53x4) CPU max-freq dhrystone --------------------------------- A57 1500 MHz 11463526 lps/s A53 1200 MHz 4793276 lps/s Based on above, capacity-dmips-mhz values are calculated as follows: r8a7795 SoC A57 : 1024 / (11470943 / 1500) * (11470943 / 1500) = 1024 A53 : 1024 / (11470943 / 1500) * ( 4798583 / 1200) = 535 r8a7796 SoC A57 : 1024 / (11463526 / 1500) * (11463526 / 1500) = 1024 A53 : 1024 / (11463526 / 1500) * ( 4793276 / 1200) = 535 However, since each CPUs have different max frequencies, the final CPU capacities of A53 are scaled by this difference, the values are as follows. [r8a7795 SoC] $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 <---- CPU capacity of A57 1024 1024 1024 428 <---- CPU capacity of A53 428 428 428 [r8a7796 SoC] $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 <---- CPU capacity of A57 1024 428 <---- CPU capacity of A53 428 428 428 Signed-off-by: Gaku Inami Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 ++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 408ff4e8170a..e94a5f2dbd08 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -157,6 +157,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -169,6 +170,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -181,6 +183,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -193,6 +196,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -205,6 +209,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; }; a53_1: cpu@101 { @@ -216,6 +221,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; }; a53_2: cpu@102 { @@ -227,6 +233,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; }; a53_3: cpu@103 { @@ -238,6 +245,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; }; L2_CA57: cache-controller-0 { diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index b12bf73bb03b..369d0bccc651 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -162,6 +162,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -174,6 +175,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -186,6 +188,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; }; a53_1: cpu@101 { @@ -197,6 +200,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; }; a53_2: cpu@102 { @@ -208,6 +212,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; }; a53_3: cpu@103 { @@ -219,6 +224,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; }; L2_CA57: cache-controller-0 { -- cgit From 03d9f8fa2bfdc791865624d3adc29070cf67814e Mon Sep 17 00:00:00 2001 From: John Keeping Date: Tue, 13 Nov 2018 15:24:13 +0000 Subject: ARM: dts: rockchip: Fix rk3288-rock2 vcc_flash name There is no functional change from this, but it is confusing to find two copies of vcc_sys and no vcc_flash when looking in /sys/class/regulator/*/name. Signed-off-by: John Keeping Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-rock2-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index 50325489c0ce..32e1ab336662 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -25,7 +25,7 @@ vcc_flash: flash-regulator { compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; + regulator-name = "vcc_flash"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; startup-delay-us = <150>; -- cgit From 6e382cc7ba2931d3e2683787a2d9279e4c31c4df Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 1 Oct 2018 11:51:50 +0530 Subject: arm64: dts: msm8996: add prng-ee node RNG hardware in 8996 features (Execution Environment) EE for HLOS to use, add the node for prng-ee for msm8996. Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index b29fe80d7288..13bb96444df0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -370,6 +370,13 @@ reg = <0x68000 0x6000>; }; + rng: rng@83000 { + compatible = "qcom,prng-ee"; + reg = <0x00083000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + tcsr_mutex_regs: syscon@740000 { compatible = "syscon"; reg = <0x740000 0x20000>; -- cgit From 6e17f8140521a73844721af8a2ff03ad00519ab8 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 1 Oct 2018 11:51:51 +0530 Subject: arm64: dts: sdm845: add prng-ee node RNG hardware in SDM845 features (Execution Environment) EE for HLOS to use, add the node for prng-ee for sdm845. Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 98d054043266..1419b0098cb3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -357,6 +358,13 @@ }; }; + rng: rng@793000 { + compatible = "qcom,prng-ee"; + reg = <0x00793000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x8c0000 0x6000>; -- cgit From 51152f65bb89b6c2bfd335c514a58d9035c08fc0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Oct 2018 15:03:41 +0100 Subject: ARM: dts: meson6: atv1200: add the /chosen/stdout-path property Support for Meson6 SoCs is currently very limited. It's often unclear why such a device does not boot. To debug this the "earlycon" kernel parameter can be used (without any arguments). However, this requires the board to define a /chosen/stdout-path property in it's .dts. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson6-atv1200.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts index 9444b0d9628f..fc48cff71ddf 100644 --- a/arch/arm/boot/dts/meson6-atv1200.dts +++ b/arch/arm/boot/dts/meson6-atv1200.dts @@ -56,6 +56,10 @@ serial0 = &uart_AO; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x40000000 0x80000000>; }; -- cgit From 42196c98a965bcf9bc7c14e58d52b7ac026b9655 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Oct 2018 15:03:42 +0100 Subject: ARM: dts: meson8: minix-neo-x8: add the /chosen/stdout-path property Support for this board is currently very limited. To debug any potential issues on this board the "earlycon" kernel parameter can be used (without any arguments). However, this requires the board to define a /chosen/stdout-path property in it's .dts. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8-minix-neo-x8.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts index 8bceb8d343f6..55fb090a40ef 100644 --- a/arch/arm/boot/dts/meson8-minix-neo-x8.dts +++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts @@ -52,6 +52,10 @@ serial0 = &uart_AO; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x40000000 0x80000000>; }; -- cgit From 340cda67ed80d976c6bec143979cb34bef4c9c85 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Oct 2018 15:03:43 +0100 Subject: ARM: dts: meson8b: mxq: add the /chosen/stdout-path property Support for this board is currently very limited. To debug any potential issues on this board the "earlycon" kernel parameter can be used (without any arguments). However, this requires the board to define a /chosen/stdout-path property in it's .dts. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-mxq.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts index c7fdaeabbe7b..5c9b76af8d42 100644 --- a/arch/arm/boot/dts/meson8b-mxq.dts +++ b/arch/arm/boot/dts/meson8b-mxq.dts @@ -55,6 +55,10 @@ serial0 = &uart_AO; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x40000000 0x40000000>; }; -- cgit From eed5afc6fc194b9615c1f8239ed1391fb3ee50aa Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 30 Oct 2018 11:22:30 +0100 Subject: arm64: dts: meson-gx: add efuse pclk Add the required peripheral clock for the efuse device. Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 1ade7e486828..524f533e41d4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -282,6 +282,10 @@ compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; }; +&efuse { + clocks = <&clkc CLKID_EFUSE>; +}; + ðmac { clocks = <&clkc CLKID_ETH>, <&clkc CLKID_FCLK_DIV2>, diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 8f0bb3c44bd6..8ccab9a1ebcc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -75,6 +75,10 @@ }; }; +&efuse { + clocks = <&clkc CLKID_EFUSE>; +}; + ðmac { reg = <0x0 0xc9410000 0x0 0x10000 0x0 0xc8834540 0x0 0x4>; -- cgit From 7dd9c42f2668821141690346ca58ecffdaa281f0 Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Sun, 4 Nov 2018 08:19:38 +0200 Subject: ARM: dts: imx6q-bx50v3: user-space watchdog GPIO configuration Leave b{4,6}50v3 GPIO expander pca953x pins P05,P10,P11 unconfigured as they are now used to implement an additional watchdog mechanism in user space. P10,P11 pins remain unused (and therefore hogged) on b850v3. Signed-off-by: Ian Ray Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-b450v3.dts | 7 ------- arch/arm/boot/dts/imx6q-b650v3.dts | 7 ------- arch/arm/boot/dts/imx6q-b850v3.dts | 16 ++++++++++++++++ arch/arm/boot/dts/imx6q-bx50v3.dtsi | 14 -------------- 4 files changed, 16 insertions(+), 28 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts index 3ec58500e9c2..95b8f2d71821 100644 --- a/arch/arm/boot/dts/imx6q-b450v3.dts +++ b/arch/arm/boot/dts/imx6q-b450v3.dts @@ -98,13 +98,6 @@ line-name = "PCA9539-P04"; }; - P05 { - gpio-hog; - gpios = <5 0>; - output-low; - line-name = "PCA9539-P05"; - }; - P07 { gpio-hog; gpios = <7 0>; diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts index 5650a9b11091..611cb7ae7e55 100644 --- a/arch/arm/boot/dts/imx6q-b650v3.dts +++ b/arch/arm/boot/dts/imx6q-b650v3.dts @@ -91,13 +91,6 @@ }; &pca9539 { - P05 { - gpio-hog; - gpios = <5 0>; - output-low; - line-name = "PCA9539-P05"; - }; - P07 { gpio-hog; gpios = <7 0>; diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts index 044a5bebe1c5..e4cb118f88c6 100644 --- a/arch/arm/boot/dts/imx6q-b850v3.dts +++ b/arch/arm/boot/dts/imx6q-b850v3.dts @@ -209,6 +209,22 @@ }; }; +&pca9539 { + P10 { + gpio-hog; + gpios = <8 0>; + output-low; + line-name = "PCA9539-P10"; + }; + + P11 { + gpio-hog; + gpios = <9 0>; + output-low; + line-name = "PCA9539-P11"; + }; +}; + &pci_root { /* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */ bridge@1,0 { diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index d3cba09be0cb..fa27dcdf06f1 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -233,20 +233,6 @@ interrupt-parent = <&gpio2>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - P10 { - gpio-hog; - gpios = <8 0>; - output-low; - line-name = "PCA9539-P10"; - }; - - P11 { - gpio-hog; - gpios = <9 0>; - output-low; - line-name = "PCA9539-P11"; - }; - P12 { gpio-hog; gpios = <10 0>; -- cgit From 8ab9c127bf7235ad568c13e1525ea6e8f4f3a0ef Mon Sep 17 00:00:00 2001 From: Xiaowei Bao Date: Mon, 5 Nov 2018 16:46:49 +0800 Subject: ARM: dts: ls1021a: Add the status property disable PCIe Add the status property disable the PCIe, the property will be enable by bootloader. Signed-off-by: Xiaowei Bao Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index bdd6e66a79ad..b769e0e40553 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -736,6 +736,7 @@ <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; pcie@3500000 { @@ -759,6 +760,7 @@ <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; can0: can@2a70000 { -- cgit From 9d60e0f031e4b4fe2ad3250b3c1e02d77ed44786 Mon Sep 17 00:00:00 2001 From: Alex Gonzalez Date: Mon, 5 Nov 2018 11:43:42 +0100 Subject: ARM: dts: imx6ul: ccimx6ulsom: Add support for wireless SOM variant The wireless variants of the ConnecCore 6UL SOM include a Qualcomm QCA6564 wireless chip with dual WiFi and Bluetooth. Both the ConnectCore 6UL SBC Express and Pro boards fit a wireless SOM. The Wifi is connected through the SDIO interface on usdhc1 and the Bluetooth is connected via uart1. Reviewed-by: Fabio Estevam Signed-off-by: Alex Gonzalez Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi | 64 +++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi index c71a84da1af0..ef26b2389c8f 100644 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi @@ -161,6 +161,25 @@ }; }; +/* UART1 (Bluetooth) */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +/* USDHC1 (Wireless) */ +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifibt_ctrl>; + pinctrl-1 = <&pinctrl_usdhc1_sleep &pinctrl_wifibt_ctrl_sleep>; + non-removable; + no-1-8-v; + bus-width = <4>; + status = "okay"; +}; + &iomuxc { pinctrl_gpmi_nand: gpmigrp { fsl,pins = < @@ -188,6 +207,51 @@ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 >; }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17051 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_sleep: usdhc1grp-sleep { + fsl,pins = < + MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x3000 + MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x3000 + MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x3000 + MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x3000 + MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x3000 + MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x3000 + >; + }; + + pinctrl_wifibt_ctrl: wifibt-ctrl-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x08a0 + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x08a0 + >; + }; + + pinctrl_wifibt_ctrl_sleep: wifibt-ctrl-grp-sleep { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x3000 + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3000 + >; + }; }; ®_arm { -- cgit From 381aafc016f072af3602deeec4bb7b3e1194a8b1 Mon Sep 17 00:00:00 2001 From: Alex Gonzalez Date: Mon, 5 Nov 2018 11:48:04 +0100 Subject: ARM: dts: imx6ul: ccimx6ulsom: Fix indentation on iomuxc nodes This patch corrects indentation problems in the gpmigrp and i2c1grp nodes. Signed-off-by: Alex Gonzalez Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi index ef26b2389c8f..c41ecee68ad9 100644 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi @@ -198,15 +198,15 @@ MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb0b1 - >; - }; + >; + }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 - >; - }; + >; + }; pinctrl_uart1: uart1grp { fsl,pins = < -- cgit From 749a5068f2e2453a38777b1d5fc322d503cabf1d Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 5 Nov 2018 18:31:56 +0100 Subject: ARM: dts: imx6: RDU2: fix eGalax touchscreen node Use the correct compatible for the new protocol used by the firmware on the touch controller, the GPIO wakeup isn't used in that case. Also eGalax touch needs axis swapping, just as with the RMI4 touch. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 85e79a33bcd4..69942c7ff89d 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -609,13 +609,14 @@ }; touchscreen@2a { - compatible = "eeti,egalax_ts"; + compatible = "eeti,exc3000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ts>; reg = <0x2a>; interrupt-parent = <&gpio1>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - wakeup-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; status = "disabled"; }; -- cgit From 4951c2da1a3a8b56d4ef0659d80938942307a8a3 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 5 Nov 2018 18:34:02 +0100 Subject: ARM: dts: imx6: add thermal sensor and cooling cells This allows a board to specify a custom thermal zone configuration involving the SoC internal sensor, CPU and GPU nodes without having to change those nodes. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q.dtsi | 1 + arch/arm/boot/dts/imx6qdl.dtsi | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 8381d24eff7d..d038f4117024 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -202,6 +202,7 @@ <&clks IMX6QDL_CLK_GPU2D_CORE>; clock-names = "bus", "core"; power-domains = <&pd_pu>; + #cooling-cells = <2>; }; ipu2: ipu@2800000 { diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index f782dc020f5b..ae94113d037e 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -77,6 +77,7 @@ fsl,tempmon = <&anatop>; fsl,tempmon-data = <&ocotp>; clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + #thermal-sensor-cells = <0>; }; ldb: ldb { @@ -216,6 +217,7 @@ <&clks IMX6QDL_CLK_GPU3D_SHADER>; clock-names = "bus", "core", "shader"; power-domains = <&pd_pu>; + #cooling-cells = <2>; }; gpu_2d: gpu@134000 { @@ -226,6 +228,7 @@ <&clks IMX6QDL_CLK_GPU2D_CORE>; clock-names = "bus", "core"; power-domains = <&pd_pu>; + #cooling-cells = <2>; }; timer@a00600 { -- cgit From 4556b160a1195343ea36f7e4bf7ca28c45835fac Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 8 Nov 2018 14:30:34 +0100 Subject: arm64: dts: zynqmp: Add missing gpio-controller to ps gpio Add missing gpio-controller property to ps gpio. This was found via DT schema validation. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 07f2dd13ab33..ae3c1b929648 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -410,6 +410,7 @@ compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; + gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; -- cgit From d1d4445abffb2b17e841d37b555b6f1364b571c1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 8 Nov 2018 10:06:53 +0100 Subject: arm64: dts: zynqmp: Fix node names which contain "_" s/_/-/ for node names. It fixes warnings like this: ... Warning (node_name_chars_strict): /cpu_opp_table: Character '_' not recommended in node name ... Issues reported by make dtbs W=12 Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 10 +++++----- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++-- 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi index 9c09baca7dd7..306ad2157c98 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi @@ -58,13 +58,13 @@ clock-accuracy = <100>; }; - dpdma_clk: dpdma_clk { + dpdma_clk: dpdma-clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; - drm_clock: drm_clock { + drm_clock: drm-clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 527b4d0f88e2..13a0a028df98 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -82,7 +82,7 @@ linux,default-trigger = "bluetooth-power"; }; - vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ + vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; @@ -98,7 +98,7 @@ regulator-boot-on; }; - sdio_pwrseq: sdio_pwrseq { + sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 0397bf66b2e7..cef81671f3ab 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -53,7 +53,7 @@ leds { compatible = "gpio-leds"; - heartbeat_led { + heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -139,25 +139,25 @@ * 7, 10 - 17 - not connected */ - gtr_sel0 { + gtr-sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; - gtr_sel1 { + gtr-sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; - gtr_sel2 { + gtr-sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; - gtr_sel3 { + gtr-sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 7238f022a671..94cf5094df64 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -53,7 +53,7 @@ leds { compatible = "gpio-leds"; - heartbeat_led { + heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index fa055e718d4b..460adc378295 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -53,7 +53,7 @@ leds { compatible = "gpio-leds"; - heartbeat_led { + heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index ae3c1b929648..fa4fd777d90e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -71,7 +71,7 @@ }; }; - cpu_opp_table: cpu_opp_table { + cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { @@ -124,7 +124,7 @@ <1 10 0xf08>; }; - amba_apu: amba_apu@0 { + amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; -- cgit From 6e2422ff9492514a618746f490ff816d65c68f3b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 13 Nov 2018 20:46:26 +0100 Subject: ARM: dts: exynos: Clarify comment explaining purpose of Odroid XU3 DTSI There are two common DTSI files for Exynos5422 Odroid XU3 family of boards. One is shared between all of them (XU3, XU3-Lite, XU4 and HC1) and the second skips HC1. Document this in the files. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 60e91b98ad30..bf09eab90f8a 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Hardkernel Odroid XU3/XU4/HC1 boards core device tree source + * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source * * Copyright (c) 2017 Marek Szyprowski * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd. diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 1f2d3987dde1..e1b6a30b4ec7 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Hardkernel Odroid XU3 board device tree source + * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source * * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com -- cgit From b4d82f4d00d12a0977f08d37a9c73ad0580114af Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 9 Nov 2018 15:14:00 +0530 Subject: arm64: dts: qcom: qcs404: add base dts files Add base dts files for QCS404 chipset along with cpu, timer, gcc and uart2 nodes. Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 175 +++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs404.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi new file mode 100644 index 000000000000..91abcdc78505 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, Linaro Limited + +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc@0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-qcs404"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + + assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; + assigned-clock-rates = <19200000>; + }; + + blsp1_uart2: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b1000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "okay"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + clock-frequency = <19200000>; + + frame@b121000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = ; + reg = <0x0b123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = ; + reg = <0x0b124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = ; + reg = <0x0b125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = ; + reg = <0x0b126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = ; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = ; + reg = <0x0b128000 0x1000>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; -- cgit From cac8e787fe182bf62bde77b723ba24a771807f70 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 9 Nov 2018 15:14:01 +0530 Subject: arm64: dts: qcom: qcs404-evb: add dts files for EVBs QCS404 has two EVBs, EVB-1000 and EVB-4000. These boards are mostly similar with few differences in the peripherals used. So use a common qcs404-evb.dtsi which contains the common parts and use qcs404-evb-1000.dts and qcs404-evb-4000.dts for diffs Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts | 11 +++++++++++ arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts | 11 +++++++++++ arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 14 ++++++++++++++ 4 files changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts create mode 100644 arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts create mode 100644 arch/arm64/boot/dts/qcom/qcs404-evb.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index a658c07652a7..21d548f02d39 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -8,3 +8,5 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts new file mode 100644 index 000000000000..2c14903d808e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, Linaro Limited + +/dts-v1/; + +#include "qcs404-evb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS404 EVB 1000"; + compatible = "qcom,qcs404-evb"; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts new file mode 100644 index 000000000000..11269ad3de0d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, Linaro Limited + +/dts-v1/; + +#include "qcs404-evb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS404 EVB 4000"; + compatible = "qcom,qcs404-evb"; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi new file mode 100644 index 000000000000..91ecbdf0ecda --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, Linaro Limited + +#include "qcs404.dtsi" + +/ { + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; +}; -- cgit From d59117abacddff816d7a62a6a91192a44ac9fea8 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 9 Nov 2018 15:14:02 +0530 Subject: arm64: dts: qcom: qcs404: Add reserved-memory regions Add the reserved memory regions in QCS404 Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 41 ++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 91abcdc78505..d40f3923ed69 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -73,6 +73,47 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + memory@85600000 { + reg = <0 0x85600000 0 0x90000>; + no-map; + }; + + smem_region: memory@85f00000 { + reg = <0 0x85f00000 0 0x200000>; + no-map; + }; + + memory@86100000 { + reg = <0 0x86100000 0 0x300000>; + no-map; + }; + + wlan_fw_mem: memory@86400000 { + reg = <0 0x86400000 0 0x1c00000>; + no-map; + }; + + adsp_fw_mem: memory@88000000 { + reg = <0 0x88000000 0 0x1a00000>; + no-map; + }; + + cdsp_fw_mem: memory@89a00000 { + reg = <0 0x89a00000 0 0x600000>; + no-map; + }; + + wlan_msa_mem: memory@8a000000 { + reg = <0 0x8a000000 0 0x100000>; + no-map; + }; + }; + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; -- cgit From 7fc7089d9d56d7592e1f35f68b6323f7c18e191f Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 9 Nov 2018 15:14:03 +0530 Subject: arm64: dts: qcom: qcs404: Add RPM GLINK related nodes Add RPM GLINK node and the RPM message ram, hwspinlock, APCS apps global and smem nodes it depends on. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 44 ++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index d40f3923ed69..6bc0925acda9 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -114,12 +114,45 @@ }; }; + rpm-glink { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: glink-channel { + compatible = "qcom,rpm-qcs404"; + qcom,glink-channels = "rpm_requests"; + }; + }; + + smem { + compatible = "qcom,smem"; + + memory-region = <&smem_region>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + hwlocks = <&tcsr_mutex 3>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + }; + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + rpm_msg_ram: memory@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x6000>; + }; + gcc: clock-controller@1800000 { compatible = "qcom,gcc-qcs404"; reg = <0x01800000 0x80000>; @@ -129,6 +162,11 @@ assigned-clock-rates = <19200000>; }; + tcsr_mutex_regs: syscon@1905000 { + compatible = "syscon"; + reg = <0x01905000 0x20000>; + }; + blsp1_uart2: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b1000 0x200>; @@ -146,6 +184,12 @@ <0x0b002000 0x1000>; }; + apcs_glb: mailbox@b011000 { + compatible = "qcom,qcs404-apcs-apps-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + }; + timer@b120000 { #address-cells = <1>; #size-cells = <1>; -- cgit From 0b363f5b871c2cdae108d272edb4a6bde61a84c5 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 9 Nov 2018 15:14:04 +0530 Subject: arm64: dts: qcom: qcs404: Add PMS405 RPM regulators Add the RPM regulators found in PMS405 which is used in qcs404-evb Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 97 ++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 91ecbdf0ecda..d1ba8b8ece46 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -11,4 +11,101 @@ chosen { stdout-path = "serial0"; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&rpm_requests { + pms405-regulators { + compatible = "qcom,rpm-pms405-regulators"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-l1-l2-supply = <&vreg_s5_1p35>; + vdd-l3-l8-supply = <&vreg_s5_1p35>; + vdd-l4-supply = <&vreg_s5_1p35>; + vdd-l5-l6-supply = <&vreg_s4_1p8>; + vdd-l7-supply = <&vph_pwr>; + vdd-l9-supply = <&vreg_s5_1p35>; + vdd-l10-l11-l12-l13-supply = <&vph_pwr>; + + vreg_s4_1p8: s4 { + regulator-min-microvolt = <1728000>; + regulator-max-microvolt = <1920000>; + }; + + vreg_s5_1p35: s5 { + regulator-min-microvolt = <>; + regulator-max-microvolt = <>; + }; + + vreg_l1_1p3: l1 { + regulator-min-microvolt = <1240000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l2_1p275: l2 { + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1280000>; + }; + + vreg_l3_1p05: l3 { + regulator-min-microvolt = <976000>; + regulator-max-microvolt = <1160000>; + }; + + vreg_l4_1p2: l4 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + }; + + vreg_l5_1p8: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l6_1p8: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vreg_l7_1p8: l7 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <3000000>; + }; + + vreg_l8_1p2: l8 { + regulator-min-microvolt = <1136000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l10_3p3: l10 { + regulator-min-microvolt = <2936000>; + regulator-max-microvolt = <3088000>; + }; + + vreg_l11_sdc2: l11 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l12_3p3: l12 { + regulator-min-microvolt = <2968000>; + regulator-max-microvolt = <3300000>; + }; + + vreg_l13_3p3: l13 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + }; }; -- cgit From afdfb0b36712d752fc6c74b8db044392b037b60c Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 9 Nov 2018 15:14:05 +0530 Subject: arm64: dts: qcom: qcs404: add smp2p nodes Add the smp2p-adsp, smp2p-cdsp and smp2p-wcss nodes found in QCS404. Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 60 ++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 6bc0925acda9..133bcd36f926 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -257,4 +257,64 @@ , ; }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + mboxes = <&apcs_glb 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wcss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs_glb 18>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; -- cgit From 75f6e6d967ded66b909f4dcbda95891893a6f6f9 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 9 Nov 2018 15:14:06 +0530 Subject: arm64: dts: qcom: qcs404: Add TLMM pinctrl node Add the QCS404 TLMM pinctrl node with its three tiles. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 133bcd36f926..d32b91480dc1 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -153,6 +153,20 @@ reg = <0x00060000 0x6000>; }; + tlmm: pinctrl@1000000 { + compatible = "qcom,qcs404-pinctrl"; + reg = <0x01000000 0x200000>, + <0x01300000 0x200000>, + <0x07b00000 0x200000>; + reg-names = "south", "north", "east"; + interrupts = ; + gpio-ranges = <&tlmm 0 0 120>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gcc: clock-controller@1800000 { compatible = "qcom,gcc-qcs404"; reg = <0x01800000 0x80000>; -- cgit From 7241ab944da3ee1e6e6278c3423a59eda516c362 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 9 Nov 2018 15:14:07 +0530 Subject: arm64: dts: qcom: qcs404: Add sdcc1 node Add the sdcc1 node and enable it for the QCS404-EVB. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 64 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 17 +++++++++ 2 files changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index d1ba8b8ece46..358d6d5f7d85 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -109,3 +109,67 @@ }; }; }; + +&sdcc1 { + status = "ok"; + + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&tlmm { + sdc1_on: sdc1-on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + dreive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1-off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + dreive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index d32b91480dc1..1b3e21c1fed9 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -181,6 +181,23 @@ reg = <0x01905000 0x20000>; }; + sdcc1: sdcc@7804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x07804000 0x1000>, <0x7805000 0x1000>; + reg-names = "hc_mem", "cmdq_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + status = "disabled"; + }; + blsp1_uart2: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b1000 0x200>; -- cgit From 06e2ddbaa096a997243395f104bbf6b07834c7f1 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 9 Nov 2018 15:14:08 +0530 Subject: arm64: dts: qcom: pms405: add spmi node Add the pms405 DT file with spmi node. Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pms405.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pms405.dtsi diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi new file mode 100644 index 000000000000..7b8104e21507 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018, Linaro Limited + +#include + +&spmi_bus { + pms405_0: pms405@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + }; +}; -- cgit From 1a94b65b67d05639845afb0b4c1b169e2082d3f4 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 9 Nov 2018 15:14:09 +0530 Subject: arm64: dts: qcom: qcs404: add spmi node PMS405 is used in QCS405-EVB so include that with SPMI nodes Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 1 + arch/arm64/boot/dts/qcom/qcs404.dtsi | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 358d6d5f7d85..db035fef67d9 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -2,6 +2,7 @@ // Copyright (c) 2018, Linaro Limited #include "qcs404.dtsi" +#include "pms405.dtsi" / { aliases { diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 1b3e21c1fed9..0101cd5896b3 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -181,6 +181,24 @@ reg = <0x01905000 0x20000>; }; + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + sdcc1: sdcc@7804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x7805000 0x1000>; -- cgit From dc294716049695fc743c83e9b3037c1a75d5846c Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 9 Nov 2018 15:14:10 +0530 Subject: arm64: dts: qcom: pms405: add rtc node RTC is found on PMIC PMS405 and is same as other PMIC used, so add the rtc node with compatible as qcom,pm8941-rtc Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pms405.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 7b8104e21507..2b275bbdafa3 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -10,5 +10,11 @@ #address-cells = <1>; #size-cells = <0>; + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; }; }; -- cgit From dbc5c766691f5a6e171b861992cc18df68756f41 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 9 Nov 2018 15:14:11 +0530 Subject: arm64: dts: qcom: pms405: add gpios Add the GPIOs present on PMS405 chip. Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pms405.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 2b275bbdafa3..8e5a8573430e 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -10,6 +10,25 @@ #address-cells = <1>; #size-cells = <0>; + pms405_gpios: gpio@c000 { + compatible = "qcom,pms405-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>, + <0 0xc4 0 IRQ_TYPE_NONE>, + <0 0xc5 0 IRQ_TYPE_NONE>, + <0 0xc6 0 IRQ_TYPE_NONE>, + <0 0xc7 0 IRQ_TYPE_NONE>, + <0 0xc8 0 IRQ_TYPE_NONE>, + <0 0xc9 0 IRQ_TYPE_NONE>, + <0 0xca 0 IRQ_TYPE_NONE>, + <0 0xcb 0 IRQ_TYPE_NONE>; + }; + rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>; -- cgit From e7fd184f559f28fa04ef2fff322ee383ea3b7c3c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 9 Nov 2018 15:14:12 +0530 Subject: arm64: dts: qcom: qcs404: Add scm firmware node Add the scm firmware node to QCS404 Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 0101cd5896b3..46fce264c8fe 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -62,6 +62,13 @@ }; }; + firmware { + scm: scm { + compatible = "qcom,scm-qcs404", "qcom,scm"; + #reset-cells = <1>; + }; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ -- cgit From 9395df5f0ecacaf2c380faf10815848dd077451e Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 9 Nov 2018 15:14:13 +0530 Subject: arm64: dts: qcom: qcs404: Add remoteproc nodes Add the TrustZone based remoteproc nodes and their glink edges for adsp, cdsp and wcss. Enable them for EVB common DTS. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 12 +++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 93 ++++++++++++++++++++++++++++++++ 2 files changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index db035fef67d9..a39924efebe4 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -21,6 +21,18 @@ }; }; +&remoteproc_adsp { + status = "ok"; +}; + +&remoteproc_cdsp { + status = "ok"; +}; + +&remoteproc_wcss { + status = "ok"; +}; + &rpm_requests { pms405-regulators { compatible = "qcom,rpm-pms405-regulators"; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 46fce264c8fe..06607419c9d6 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -80,6 +80,99 @@ method = "smc"; }; + remoteproc_adsp: remoteproc-adsp { + compatible = "qcom,qcs404-adsp-pas"; + + interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&adsp_fw_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 8>; + + label = "adsp"; + }; + }; + + remoteproc_cdsp: remoteproc-cdsp { + compatible = "qcom,qcs404-cdsp-pas"; + + interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&cdsp_fw_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + + qcom,remote-pid = <5>; + mboxes = <&apcs_glb 12>; + + label = "cdsp"; + }; + }; + + remoteproc_wcss: remoteproc-wcss { + compatible = "qcom,qcs404-wcss-pas"; + + interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&wlan_fw_mem>; + + qcom,smem-states = <&wcss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 16>; + + label = "wcss"; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; -- cgit From df96c65c3d658ccb37d7d3b49d30d3af9e4a82cc Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 9 Nov 2018 15:14:14 +0530 Subject: arm64: dts: qcom: qcs404: add prng-ee node RNG hardware in QCS404 features (Execution Environment) EE for HLOS to use, add the node for prng-ee for QCS404. Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 06607419c9d6..c58774bb9698 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -253,6 +253,13 @@ reg = <0x00060000 0x6000>; }; + rng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>, -- cgit From e77c52068c63ff9f31d2d26a6786dc01953c91a5 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 9 Nov 2018 15:14:15 +0530 Subject: arm64: dts: qcom: qcs404: Add BAM DMA node Add the BAM DMA instance found in BLSP1 node of the QCS404 Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index c58774bb9698..ef2c4cdc6d27 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -323,6 +323,18 @@ status = "disabled"; }; + blsp1_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x25000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,controlled-remotely = <1>; + qcom,ee = <0>; + status = "okay"; + }; + blsp1_uart2: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b1000 0x200>; -- cgit From aec2a7659ab4e52460c8d299b423be2b2176b208 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 9 Nov 2018 15:14:16 +0530 Subject: arm64: dts: qcom: qcs404: Use BAM DMA for serial uart2 We can use BAM DAM for serial UART data transfers, so add it Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ef2c4cdc6d27..9b5c16562bbe 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -341,6 +341,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; + dma-names = "rx", "tx"; status = "okay"; }; -- cgit From 85bc3096b33f3eb1bfbc4bc13034cd47ae0943da Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 9 Nov 2018 15:14:17 +0530 Subject: arm64: dts: qcom: pms405: Add pon and pwrkey nodes PMS405 also features PON block, so add PON and PWRKEY nodes Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/pms405.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 8e5a8573430e..ad2b62dfc9f6 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -2,6 +2,7 @@ // Copyright (c) 2018, Linaro Limited #include +#include &spmi_bus { pms405_0: pms405@0 { @@ -29,6 +30,21 @@ <0 0xcb 0 IRQ_TYPE_NONE>; }; + pon@800 { + compatible = "qcom,pms405-pon"; + reg = <0x0800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; + }; + rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>; -- cgit From 670734f5581023a2e695e82ea662e4d603fd3e8a Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:31:10 +0530 Subject: ARM: dts: exynos: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-artik5.dtsi | 6 +- arch/arm/boot/dts/exynos3250-monk.dts | 6 +- arch/arm/boot/dts/exynos3250-rinato.dts | 6 +- arch/arm/boot/dts/exynos4210-trats.dts | 4 +- arch/arm/boot/dts/exynos4210.dtsi | 2 +- arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 8 +- arch/arm/boot/dts/exynos4412-midas.dtsi | 8 +- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 8 +- arch/arm/boot/dts/exynos4412-odroidu3.dts | 18 ++-- arch/arm/boot/dts/exynos4412.dtsi | 6 +- arch/arm/boot/dts/exynos5250.dtsi | 7 +- arch/arm/boot/dts/exynos5422-odroidhc1.dts | 106 +++++++++++++-------- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 106 +++++++++++++-------- 13 files changed, 178 insertions(+), 113 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 7c22cbf6f3d4..ace50e194a45 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -36,11 +36,13 @@ cooling-maps { map0 { /* Corresponds to 500MHz */ - cooling-device = <&cpu0 5 5>; + cooling-device = <&cpu0 5 5>, + <&cpu1 5 5>; }; map1 { /* Corresponds to 200MHz */ - cooling-device = <&cpu0 8 8>; + cooling-device = <&cpu0 8 8>, + <&cpu1 8 8>; }; }; }; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 6ffedf4ed9f2..e25765500e99 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -121,11 +121,13 @@ cooling-maps { map0 { /* Correspond to 500MHz at freq_table */ - cooling-device = <&cpu0 5 5>; + cooling-device = <&cpu0 5 5>, + <&cpu1 5 5>; }; map1 { /* Correspond to 200MHz at freq_table */ - cooling-device = <&cpu0 8 8>; + cooling-device = <&cpu0 8 8>, + <&cpu1 8 8>; }; }; }; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 2a6b828c01b7..7479993755da 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -116,11 +116,13 @@ cooling-maps { map0 { /* Corresponds to 500MHz */ - cooling-device = <&cpu0 5 5>; + cooling-device = <&cpu0 5 5>, + <&cpu1 5 5>; }; map1 { /* Corresponds to 200MHz */ - cooling-device = <&cpu0 8 8>; + cooling-device = <&cpu0 8 8>, + <&cpu1 8 8>; }; }; }; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index f9bbc6315cd9..8dbc47d627a5 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -138,11 +138,11 @@ cooling-maps { map0 { /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 2 2>; + cooling-device = <&cpu0 2 2>, <&cpu1 2 2>; }; map1 { /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 4 4>; + cooling-device = <&cpu0 4 4>, <&cpu1 4 4>; }; }; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index b6091c27f155..32ccb5fa14f1 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -51,7 +51,7 @@ #cooling-cells = <2>; /* min followed by max */ }; - cpu@901 { + cpu1: cpu@901 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0x901>; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index 8fdfd80c3acc..0038465f38f1 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -45,11 +45,15 @@ cooling-maps { map0 { /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>; + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; }; map1 { /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>; + cooling-device = <&cpu0 13 13>, + <&cpu1 13 13>, + <&cpu2 13 13>, + <&cpu3 13 13>; }; }; }; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index aed2f2e2b0d1..4c15cb616cdf 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -267,11 +267,15 @@ cooling-maps { map0 { /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>; + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; }; map1 { /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>; + cooling-device = <&cpu0 13 13>, + <&cpu1 13 13>, + <&cpu2 13 13>, + <&cpu3 13 13>; }; }; }; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 2caa3132f34e..3a9eb1e91c45 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -72,11 +72,15 @@ cooling-maps { cooling_map0: map0 { /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>; + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; }; cooling_map1: map1 { /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>; + cooling-device = <&cpu0 13 13>, + <&cpu1 13 13>, + <&cpu2 13 13>, + <&cpu3 13 13>; }; }; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 459919b65df8..2bdf899df436 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -45,24 +45,22 @@ cooling-maps { map0 { trip = <&cpu_alert1>; - cooling-device = <&cpu0 9 9>; + cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, + <&cpu2 9 9>, <&cpu3 9 9>, + <&fan0 1 2>; }; map1 { trip = <&cpu_alert2>; - cooling-device = <&cpu0 15 15>; + cooling-device = <&cpu0 15 15>, + <&cpu1 15 15>, + <&cpu2 15 15>, + <&cpu3 15 15>, + <&fan0 2 3>; }; map2 { trip = <&cpu_alert0>; cooling-device = <&fan0 0 1>; }; - map3 { - trip = <&cpu_alert1>; - cooling-device = <&fan0 1 2>; - }; - map4 { - trip = <&cpu_alert2>; - cooling-device = <&fan0 2 3>; - }; }; }; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 51f72f0327e5..cd04bb4aea5f 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -45,7 +45,7 @@ #cooling-cells = <2>; /* min followed by max */ }; - cpu@a01 { + cpu1: cpu@a01 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA01>; @@ -55,7 +55,7 @@ #cooling-cells = <2>; /* min followed by max */ }; - cpu@a02 { + cpu2: cpu@a02 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA02>; @@ -65,7 +65,7 @@ #cooling-cells = <2>; /* min followed by max */ }; - cpu@a03 { + cpu3: cpu@a03 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0xA03>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 5044f754e6e5..80986b97dfe5 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -59,7 +59,7 @@ operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; @@ -1087,11 +1087,12 @@ cooling-maps { map0 { /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 9 9>; + cooling-device = <&cpu0 9 9>, <&cpu1 9 9>; }; map1 { /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 15 15>; + cooling-device = <&cpu0 15 15>, + <&cpu1 15 15>; }; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts index 8f332be143f7..d271e7548826 100644 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -56,24 +56,30 @@ */ map0 { trip = <&cpu0_alert0>; - cooling-device = <&cpu0 0 2>; - }; - map1 { - trip = <&cpu0_alert0>; - cooling-device = <&cpu4 0 2>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; }; /* * When reaching cpu0_alert1, reduce CPU * further, down to 600 MHz (12 steps for big, * 7 steps for LITTLE). */ - map2 { - trip = <&cpu0_alert1>; - cooling-device = <&cpu0 3 7>; - }; - map3 { + map1 { trip = <&cpu0_alert1>; - cooling-device = <&cpu4 3 12>; + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; }; }; }; @@ -99,19 +105,25 @@ cooling-maps { map0 { trip = <&cpu1_alert0>; - cooling-device = <&cpu0 0 2>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; }; map1 { - trip = <&cpu1_alert0>; - cooling-device = <&cpu4 0 2>; - }; - map2 { - trip = <&cpu1_alert1>; - cooling-device = <&cpu0 3 7>; - }; - map3 { trip = <&cpu1_alert1>; - cooling-device = <&cpu4 3 12>; + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; }; }; }; @@ -137,19 +149,25 @@ cooling-maps { map0 { trip = <&cpu2_alert0>; - cooling-device = <&cpu0 0 2>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; }; map1 { - trip = <&cpu2_alert0>; - cooling-device = <&cpu4 0 2>; - }; - map2 { - trip = <&cpu2_alert1>; - cooling-device = <&cpu0 3 7>; - }; - map3 { trip = <&cpu2_alert1>; - cooling-device = <&cpu4 3 12>; + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; }; }; }; @@ -175,19 +193,25 @@ cooling-maps { map0 { trip = <&cpu3_alert0>; - cooling-device = <&cpu0 0 2>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; }; map1 { - trip = <&cpu3_alert0>; - cooling-device = <&cpu4 0 2>; - }; - map2 { - trip = <&cpu3_alert1>; - cooling-device = <&cpu0 3 7>; - }; - map3 { trip = <&cpu3_alert1>; - cooling-device = <&cpu4 3 12>; + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; }; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index e1b6a30b4ec7..b299e541cac0 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -113,24 +113,30 @@ */ map3 { trip = <&cpu0_alert3>; - cooling-device = <&cpu0 0 2>; - }; - map4 { - trip = <&cpu0_alert3>; - cooling-device = <&cpu4 0 2>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; }; /* * When reaching cpu0_alert4, reduce CPU * further, down to 600 MHz (12 steps for big, * 7 steps for LITTLE). */ - map5 { - trip = <&cpu0_alert4>; - cooling-device = <&cpu0 3 7>; - }; - map6 { + map4 { trip = <&cpu0_alert4>; - cooling-device = <&cpu4 3 12>; + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; }; }; }; @@ -185,19 +191,25 @@ }; map3 { trip = <&cpu1_alert3>; - cooling-device = <&cpu0 0 2>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; }; map4 { - trip = <&cpu1_alert3>; - cooling-device = <&cpu4 0 2>; - }; - map5 { - trip = <&cpu1_alert4>; - cooling-device = <&cpu0 3 7>; - }; - map6 { trip = <&cpu1_alert4>; - cooling-device = <&cpu4 3 12>; + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; }; }; }; @@ -252,19 +264,25 @@ }; map3 { trip = <&cpu2_alert3>; - cooling-device = <&cpu0 0 2>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; }; map4 { - trip = <&cpu2_alert3>; - cooling-device = <&cpu4 0 2>; - }; - map5 { - trip = <&cpu2_alert4>; - cooling-device = <&cpu0 3 7>; - }; - map6 { trip = <&cpu2_alert4>; - cooling-device = <&cpu4 3 12>; + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; }; }; }; @@ -319,19 +337,25 @@ }; map3 { trip = <&cpu3_alert3>; - cooling-device = <&cpu0 0 2>; + cooling-device = <&cpu0 0 2>, + <&cpu1 0 2>, + <&cpu2 0 2>, + <&cpu3 0 2>, + <&cpu4 0 2>, + <&cpu5 0 2>, + <&cpu6 0 2>, + <&cpu7 0 2>; }; map4 { - trip = <&cpu3_alert3>; - cooling-device = <&cpu4 0 2>; - }; - map5 { - trip = <&cpu3_alert4>; - cooling-device = <&cpu0 3 7>; - }; - map6 { trip = <&cpu3_alert4>; - cooling-device = <&cpu4 3 12>; + cooling-device = <&cpu0 3 7>, + <&cpu1 3 7>, + <&cpu2 3 7>, + <&cpu3 3 7>, + <&cpu4 3 12>, + <&cpu5 3 12>, + <&cpu6 3 12>, + <&cpu7 3 12>; }; }; }; -- cgit From 9deffb5ee78e41e2a5d6c448874a24caec6467d0 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:34:25 +0530 Subject: arm64: dts: exynos: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi | 36 +++++++++++++++++--------- 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi index fe3a0b14bee6..81b72393dd0d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi @@ -55,37 +55,44 @@ thermal-zones { map0 { /* Set maximum frequency as 1800MHz */ trip = <&atlas0_alert_0>; - cooling-device = <&cpu4 1 2>; + cooling-device = <&cpu4 1 2>, <&cpu5 1 2>, + <&cpu6 1 2>, <&cpu7 1 2>; }; map1 { /* Set maximum frequency as 1700MHz */ trip = <&atlas0_alert_1>; - cooling-device = <&cpu4 2 3>; + cooling-device = <&cpu4 2 3>, <&cpu5 2 3>, + <&cpu6 2 3>, <&cpu7 2 3>; }; map2 { /* Set maximum frequency as 1600MHz */ trip = <&atlas0_alert_2>; - cooling-device = <&cpu4 3 4>; + cooling-device = <&cpu4 3 4>, <&cpu5 3 4>, + <&cpu6 3 4>, <&cpu7 3 4>; }; map3 { /* Set maximum frequency as 1500MHz */ trip = <&atlas0_alert_3>; - cooling-device = <&cpu4 4 5>; + cooling-device = <&cpu4 4 5>, <&cpu5 4 5>, + <&cpu6 4 5>, <&cpu7 4 5>; }; map4 { /* Set maximum frequency as 1400MHz */ trip = <&atlas0_alert_4>; - cooling-device = <&cpu4 5 7>; + cooling-device = <&cpu4 5 7>, <&cpu5 5 7>, + <&cpu6 5 7>, <&cpu7 5 7>; }; map5 { /* Set maximum frequencyas 1200MHz */ trip = <&atlas0_alert_5>; - cooling-device = <&cpu4 7 9>; + cooling-device = <&cpu4 7 9>, <&cpu5 7 9>, + <&cpu6 7 9>, <&cpu7 7 9>; }; map6 { /* Set maximum frequency as 1000MHz */ trip = <&atlas0_alert_6>; - cooling-device = <&cpu4 9 14>; + cooling-device = <&cpu4 9 14>, <&cpu5 9 14>, + <&cpu6 9 14>, <&cpu7 9 14>; }; }; }; @@ -222,27 +229,32 @@ thermal-zones { map0 { /* Set maximum frequency as 1200MHz */ trip = <&apollo_alert_2>; - cooling-device = <&cpu0 1 2>; + cooling-device = <&cpu0 1 2>, <&cpu1 1 2>, + <&cpu2 1 2>, <&cpu3 1 2>; }; map1 { /* Set maximum frequency as 1100MHz */ trip = <&apollo_alert_3>; - cooling-device = <&cpu0 2 3>; + cooling-device = <&cpu0 2 3>, <&cpu1 2 3>, + <&cpu2 2 3>, <&cpu3 2 3>; }; map2 { /* Set maximum frequency as 1000MHz */ trip = <&apollo_alert_4>; - cooling-device = <&cpu0 3 4>; + cooling-device = <&cpu0 3 4>, <&cpu1 3 4>, + <&cpu2 3 4>, <&cpu3 3 4>; }; map3 { /* Set maximum frequency as 900MHz */ trip = <&apollo_alert_5>; - cooling-device = <&cpu0 4 5>; + cooling-device = <&cpu0 4 5>, <&cpu1 4 5>, + <&cpu2 4 5>, <&cpu3 4 5>; }; map4 { /* Set maximum frequency as 800MHz */ trip = <&apollo_alert_6>; - cooling-device = <&cpu0 5 9>; + cooling-device = <&cpu0 5 9>, <&cpu1 5 9>, + <&cpu2 5 9>, <&cpu3 5 9>; }; }; }; -- cgit From ba3ac35b4896cf291f6fdaf04a505985e5ccce30 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Tue, 13 Nov 2018 20:22:26 +0100 Subject: arm64: dts: renesas: r8a77990: ebisu: Add and enable PCIe device node This patch adds PCI express channel 0 device node to the R8A77990 SoC and enables PCIEC0 PCI express controller on the Ebisu board. Signed-off-by: Takeshi Kihara Signed-off-by: Marek Vasut Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 8 ++++++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 34 ++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 2f1cbcde8ae0..3e4d90b654cc 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -444,6 +444,14 @@ status = "okay"; }; +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec0 { + status = "okay"; +}; + &pfc { avb_pins: avb { mux { diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index a2524fc138a2..46868dacbeef 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -85,6 +85,13 @@ clock-frequency = <0>; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, @@ -1610,6 +1617,33 @@ }; }; + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a77990", + "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; -- cgit From 99935bd4b5b4558beb069222e6d6143fe5830d64 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:31:13 +0530 Subject: ARM: dts: rockchip: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 10 ++++++++-- arch/arm/boot/dts/rk3288-veyron-mickey.dts | 24 ++++++++++++++---------- arch/arm/boot/dts/rk3288.dtsi | 15 ++++++++++++--- 3 files changed, 34 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index cd8f2a3b0e91..29f19076dceb 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -493,12 +493,18 @@ map0 { trip = <&cpu_alert0>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; + <&cpu0 THERMAL_NO_LIMIT 6>, + <&cpu1 THERMAL_NO_LIMIT 6>, + <&cpu2 THERMAL_NO_LIMIT 6>, + <&cpu3 THERMAL_NO_LIMIT 6>; }; map1 { trip = <&cpu_alert1>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts index 1e0158acf895..d889ab3c8235 100644 --- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts +++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts @@ -81,8 +81,10 @@ */ cpu_warm_limit_cpu { trip = <&cpu_alert_warm>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 4>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>, + <&cpu1 THERMAL_NO_LIMIT 4>, + <&cpu2 THERMAL_NO_LIMIT 4>, + <&cpu3 THERMAL_NO_LIMIT 4>; }; /* @@ -103,23 +105,25 @@ */ cpu_almost_hot_limit_cpu { trip = <&cpu_alert_almost_hot>; - cooling-device = - <&cpu0 5 6>; + cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>, + <&cpu3 5 6>; }; cpu_hot_limit_cpu { trip = <&cpu_alert_hot>; - cooling-device = - <&cpu0 7 7>; + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>, + <&cpu3 7 7>; }; cpu_hotter_limit_cpu { trip = <&cpu_alert_hotter>; - cooling-device = - <&cpu0 7 8>; + cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>, + <&cpu3 7 8>; }; cpu_very_hot_limit_cpu { trip = <&cpu_alert_very_hot>; - cooling-device = - <&cpu0 8 THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 8 THERMAL_NO_LIMIT>, + <&cpu1 8 THERMAL_NO_LIMIT>, + <&cpu2 8 THERMAL_NO_LIMIT>, + <&cpu3 8 THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 0840ffb3205c..1da86e82bb57 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -508,12 +508,18 @@ map0 { trip = <&cpu_alert0>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; + <&cpu0 THERMAL_NO_LIMIT 6>, + <&cpu1 THERMAL_NO_LIMIT 6>, + <&cpu2 THERMAL_NO_LIMIT 6>, + <&cpu3 THERMAL_NO_LIMIT 6>; }; map1 { trip = <&cpu_alert1>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -541,7 +547,10 @@ map0 { trip = <&gpu_alert0>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; -- cgit From cdd46460fe278e04d8ee665d975aa2962036838f Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:34:32 +0530 Subject: arm64: dts: rockchip: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 ++++- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 15 ++++++++++++--- arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts | 8 ++++++-- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 +++++++++--- 4 files changed, 31 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index e1a33dd981e0..ecd7f19c3542 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -479,7 +479,10 @@ cooling-maps { map0 { trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <4096>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 9c24de1ba43c..7014d10b954c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -426,12 +426,18 @@ map0 { trip = <&cpu_alert0>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu_alert1>; cooling-device = - <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -459,7 +465,10 @@ map0 { trip = <&gpu_alert0>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts index 2cc7c47d6a85..81e73103fa78 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts @@ -118,13 +118,17 @@ map0 { trip = <&ppvar_bigcpu_alert>; cooling-device = - <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <4096>; }; map1 { trip = <&ppvar_bigcpu_alert>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <1024>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index c0f1cc403670..5bd735637b77 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -780,13 +780,18 @@ map0 { trip = <&cpu_alert0>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu_alert1>; cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -814,7 +819,8 @@ map0 { trip = <&gpu_alert0>; cooling-device = - <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; -- cgit From ef4734500407ce4df3985eb55e25c25a98580ac3 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:31:14 +0530 Subject: ARM: dts: sunxi: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++++++---- arch/arm/boot/dts/sun7i-a20.dtsi | 5 +++-- arch/arm/boot/dts/sun8i-a33.dtsi | 16 +++++++++++----- 3 files changed, 21 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index debc0bf22ea3..1eaa60cd3218 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -115,7 +115,7 @@ #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; @@ -131,7 +131,7 @@ #cooling-cells = <2>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; @@ -147,7 +147,7 @@ #cooling-cells = <2>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; @@ -174,7 +174,10 @@ cooling-maps { map0 { trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 02e40da9f028..b4fd4f5ca66b 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -118,7 +118,7 @@ #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; @@ -148,7 +148,8 @@ cooling-maps { map0 { trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index c1cc8f09dd9a..502de6f44a9a 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -131,14 +131,14 @@ #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; @@ -148,7 +148,7 @@ #cooling-cells = <2>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; @@ -479,11 +479,17 @@ cooling-maps { map0 { trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu_alert1>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map2 { -- cgit From de6777c50e3517725180092e523547dfd29d96ac Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 17 Oct 2018 17:48:16 -0700 Subject: ARM: dts: omap3-gta04: Fix comment block When compiling the kernel with Clang, the following warning appears: arch/arm/boot/dts/omap3-gta04.dtsi:385:56: warning: '/*' within block comment [-Wcomment] /* OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp_clks */ ^ 1 warning generated. Fixes: 3c10507a39e8 ("ARM: dts: omap3-gta04: add mcbsp (audio subsystem) pinmux") Signed-off-by: Nathan Chancellor Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index d5fe55392230..e53d32691308 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -382,7 +382,7 @@ OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */ OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */ /* mcbsp_clks is used as PENIRQ */ - /* OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp_clks */ + /* OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT | MUX_MODE0) mcbsp_clks.mcbsp_clks */ OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */ OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */ >; -- cgit From a18695933b6eae84a8f24738aaefc20d7d651d09 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 30 Oct 2018 19:09:03 -0500 Subject: ARM: dts: am3517-evm: Enable earlycon stdout path As long as the kernel cmdline has "earlycon" in it, this allows seeing debug messages earlier and does not require DEBUG_LL to be enabled. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517-evm.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index d4d33cd7adad..07f593955761 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -20,6 +20,10 @@ display0 = &lcd0; }; + chosen { + stdout-path = &uart3; + }; + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ -- cgit From 865852a6e52f3790ee2ac154c9b57f15a4490a61 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 7 Nov 2018 10:34:15 +0530 Subject: ARM: dts: am437x-gp-evm: Add state for ddr3 vtt toggle pin Add pinctrl data for ddr_vtt_toggle pin so that it is configured for proper state during DeepSleep0. The pin should enter DS0 off mode and hold the line low so VTT regulator is kept off while suspended. It is also important for the PULLUP to be set on this pin so that on removal of isolation, the VTT line is pulled high as a requirement for bringing the DDR3 out of self-refresh. This toggling is dependent on the IO isolation controlled by the wkup_m3. Without placing the IOs into isolation the DS0 states set for the pin will not be latched into effect during suspend. Signed-off-by: Dave Gerlach Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 601bf4daaeb7..d119f2a4f0e7 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -162,9 +162,15 @@ &am43xx_pinmux { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&wlan_pins_default>; + pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default>; pinctrl-1 = <&wlan_pins_sleep>; + ddr3_vtt_toggle_default: ddr_vtt_toggle_default { + pinctrl-single,pins = < + 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */ + >; + }; + i2c0_pins: i2c0_pins { pinctrl-single,pins = < AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ -- cgit From 88f527d0cf0bf1b749d0d2fc245d50f28e078a7b Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 7 Nov 2018 10:34:16 +0530 Subject: ARM: dts: am437x-gp-evm: Add pinctrl for unused_pins There are several pins on this EVM that are not in use but they can still draw power if misconfigured. Create a pinctrl entry for these pins and configure each one for optimal power savings. Signed-off-by: Dave Gerlach [t-kristo@ti.com: converted to use AM4372_IOPAD macro] Signed-off-by: Tero Kristo Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 50 ++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index d119f2a4f0e7..ae6b24e051eb 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -162,7 +162,7 @@ &am43xx_pinmux { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default>; + pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins>; pinctrl-1 = <&wlan_pins_sleep>; ddr3_vtt_toggle_default: ddr_vtt_toggle_default { @@ -532,6 +532,54 @@ >; }; + unused_pins: unused_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7) + AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7) + AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7) + AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE) + AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; }; &uart0 { -- cgit From 7235ed186e12d2e57de969cda55db8a620b0bcbf Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 7 Nov 2018 10:34:17 +0530 Subject: ARM: dts: am437x-gp-evm: Add pinctrl for debugss pins The pins used by debugss are not configued by default, place pulldowns on the pins for maximum power savings during sleep. Signed-off-by: Dave Gerlach [t-kristo@ti.com: converted to use AM4372_IOPAD macro] Signed-off-by: Tero Kristo Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index ae6b24e051eb..9c5e969d05e6 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -162,7 +162,7 @@ &am43xx_pinmux { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins>; + pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>; pinctrl-1 = <&wlan_pins_sleep>; ddr3_vtt_toggle_default: ddr_vtt_toggle_default { @@ -580,6 +580,18 @@ AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; + + debugss_pins: pinmux_debugss_pins { + pinctrl-single,pins = < + AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN) + AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN) + >; + }; }; &uart0 { -- cgit From 74fe9bf45e71a3122831106a19398dc96443181a Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 7 Nov 2018 10:34:18 +0530 Subject: ARM: dts: am437x-gp-evm: Add uart0 pinctrl default and sleep states Currently uart0 uses pinctrl config set by bootloader so create default state that can be restored after a suspend event. Also, modify uart0 pinctrl to include RTS and CTS pins as by default these are not in a mode for optimal power savings. Signed-off-by: Dave Gerlach Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 9c5e969d05e6..e52b0132d43c 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -517,15 +517,6 @@ >; }; - uart0_pins_default: uart0_pins_default { - pinctrl-single,pins = < - AM4372_IOPAD(0x968, PIN_INPUT | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ - AM4372_IOPAD(0x96C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ - AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM4372_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - beeper_pins: beeper_pins { pinctrl-single,pins = < AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */ @@ -592,12 +583,31 @@ AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN) >; }; + + uart0_pins_default: uart0_pins_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ + AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ + AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart0_pins_sleep: uart0_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */ + AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */ + AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; }; &uart0 { status = "okay"; - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart0_pins_default>; + pinctrl-1 = <&uart0_pins_sleep>; }; &i2c0 { -- cgit From 6a156a05bb55de2655505429516bbce040aa89f8 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 7 Nov 2018 10:34:19 +0530 Subject: ARM: dts: am437x-gp-evm: Add pinmux for gpio0 wake Add pinctrl settings so that gpio0 wake from suspend will be supported using buttons SW4 and SW7. Also, add pinctrl configuration for 0x954, spi0_d0, which is an unused pin brought out to a header on the board that in it's default state also connects to the gpio used for wakeup, gpio0_3, which affects the state of the pin and prevents a working wakeup unless we set the mux to a different state. Signed-off-by: Dave Gerlach Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index e52b0132d43c..0127d11d1488 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -67,7 +67,13 @@ debounce-delay-ms = <5>; col-scan-delay-us = <2>; - row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&matrix_keypad_default>; + pinctrl-1 = <&matrix_keypad_sleep>; + + linux,wakeup; + + row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */ &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ @@ -601,6 +607,24 @@ AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ >; }; + + matrix_keypad_default: matrix_keypad_default { + pinctrl-single,pins = < + AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) + AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7) + AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) + AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; + + matrix_keypad_sleep: matrix_keypad_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7) + AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7) + AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) + AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) + >; + }; }; &uart0 { -- cgit From 0ec47be539e323ef4919fd63ea2f4162bf74892e Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 7 Nov 2018 10:34:20 +0530 Subject: ARM: dts: am437x-gp-evm: Add sleep state for beeper pins Add sleep state for beeper pins. Without this there was a power increase during the suspend and standby states on V3_3D domain. Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 0127d11d1488..f4a20cade808 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -161,7 +161,8 @@ beeper: beeper { compatible = "gpio-beeper"; pinctrl-names = "default"; - pinctrl-0 = <&beeper_pins>; + pinctrl-0 = <&beeper_pins_default>; + pinctrl-1 = <&beeper_pins_sleep>; gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; }; }; @@ -523,12 +524,18 @@ >; }; - beeper_pins: beeper_pins { + beeper_pins_default: beeper_pins_default { pinctrl-single,pins = < AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */ >; }; + beeper_pins_sleep: beeper_pins_sleep { + pinctrl-single,pins = < + AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */ + >; + }; + unused_pins: unused_pins { pinctrl-single,pins = < AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) -- cgit From bebaa63f5c4070be025f29d182d2d43aa443b510 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 14 Nov 2018 09:58:36 +0530 Subject: dt-bindings: gpu: mali-utgard: Add compatible for A64 Mali Allwinner A64 has Mali-400MP2, so document the relevant compatible as "allwinner,sun50i-a64-mali" along with reset line. Signed-off-by: Jagan Teki Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 63cd91176a68..3f128e4f95c6 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -11,6 +11,7 @@ Required properties: + allwinner,sun4i-a10-mali + allwinner,sun7i-a20-mali + allwinner,sun8i-h3-mali + + allwinner,sun50i-a64-mali + allwinner,sun50i-h5-mali + amlogic,meson-gxbb-mali + amlogic,meson-gxl-mali @@ -73,6 +74,10 @@ to specify one more vendor-specific compatible, among: Required properties: * resets: phandle to the reset line for the GPU + - allwinner,sun50i-a64-mali + Required properties: + * resets: phandle to the reset line for the GPU + - allwinner,sun50i-h5-mali Required properties: * resets: phandle to the reset line for the GPU -- cgit From 6b683d7640995dc7f68d711160378b0a0f10b5c6 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 14 Nov 2018 09:58:37 +0530 Subject: arm64: dts: allwinner: a64: Add device node for Mali-400 GPU Add support for Allwinner A64 has Mali-400MP2. All interrupt lines are mentioned in the manual so used the same. Signed-off-by: Jagan Teki Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index f3a66f888205..42abfbf56b88 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -807,6 +807,28 @@ }; }; + mali: gpu@1c40000 { + compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, -- cgit From 29ce4e436f27562b366b9dc20ebf5a92f109f729 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 15 Nov 2018 11:15:51 +0800 Subject: arm64: dts: allwinner: h6: fix EMAC compatible string sequence The SoC-specific compatible should come before the fallback compatible string when multiple compatible strings are present, but the sequence is wrong currently on H6 EMAC node (A64 fallback before H6 compatible). Fix the sequence. Fixes: c8ced5516d23 ("arm64: allwinner: h6: add EMAC device nodes") Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index e28a0fc4c8fa..d93a7add67e7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -326,8 +326,8 @@ }; emac: ethernet@5020000 { - compatible = "allwinner,sun50i-a64-emac", - "allwinner,sun50i-h6-emac"; + compatible = "allwinner,sun50i-h6-emac", + "allwinner,sun50i-a64-emac"; syscon = <&syscon>; reg = <0x05020000 0x10000>; interrupts = ; -- cgit From 919d2514641f2672496df144392dc24a62ca261e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 20 Nov 2018 14:53:09 +0800 Subject: arm64: dts: allwinner: h6: orangepi: Add board-wide 5V regulator The Orange Pi Lite 2 and Orange Pi One Plus share the same design for their USB 2.0 ports. VBUS is directly tied to the board wide 5V rail, which is also directly tied to the DC jack. There is no current limiting in this design. This 5V rail also supplies the various inputs to the PMIC. This patch adds a board wide 5V regulator and sets it as the input to the PMIC inputs. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi index 0612c19cd994..f910d5eb9267 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi @@ -21,6 +21,15 @@ chosen { stdout-path = "serial0:115200n8"; }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC jack */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; }; &mmc0 { @@ -43,6 +52,14 @@ interrupt-controller; #interrupt-cells = <1>; x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; regulators { reg_aldo1: aldo1 { -- cgit From 9b8d1ccd6dc546aaef37eabe1b29da5d6b2b8c02 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 20 Nov 2018 14:53:10 +0800 Subject: arm64: dts: allwinner: h6: orangepi: Enable USB 2.0 host and OTG ports The Orange Pi Lite 2 and Orange Pi One Plus share the same design for their USB 2.0 ports. VBUS is directly tied to the board wide 5V rail, which is also directly tied to the DC jack. There is no current limiting in this design. This patch enables all the USB 2.0 related device nodes, and sets the VBUS regulator supplies and OTG ID detection GPIO. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- .../boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi index f910d5eb9267..f16b7ffbe797 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi @@ -32,6 +32,14 @@ }; }; +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -41,6 +49,14 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + &r_i2c { status = "okay"; @@ -165,3 +181,15 @@ pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; + +&usb2otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb2phy { + usb0_id_det-gpios = <&pio 2 6 GPIO_ACTIVE_HIGH>; /* PC6 */ + usb0_vbus-supply = <®_vcc5v>; + usb3_vbus-supply = <®_vcc5v>; + status = "okay"; +}; -- cgit From 1e33e0db826fb48bae9587b6f3a6ea29509bc6ca Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 20 Nov 2018 14:53:11 +0800 Subject: arm64: dts: allwinner: h6: orangepi: Add device nodes for LEDs The Orange Pi Lite 2 and Orange Pi One Plus both have two LEDs, one red and one green. These are driven directly by GPIO lines in an active high arrangement. The red LED is labeled "power", so it is set to be on by default. Note that the default drive current for the GPIO lines makes the LEDs very bright. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi index f16b7ffbe797..b2526dac2fcf 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi @@ -22,6 +22,21 @@ stdout-path = "serial0:115200n8"; }; + leds { + compatible = "gpio-leds"; + + power { + label = "orangepi:red:power"; + gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + default-state = "on"; + }; + + status { + label = "orangepi:green:status"; + gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ + }; + }; + reg_vcc5v: vcc5v { /* board wide 5V supply directly from the DC jack */ compatible = "regulator-fixed"; -- cgit From 55db8ac68d38755d631cffdc4c6cf7d68a63decc Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Wed, 21 Nov 2018 00:32:52 +0100 Subject: arm64: dts: renesas: r8a77965: Add CAN and CANFD controller nodes This patch adds CAN{0,1} and CANFD controller nodes for the R8A77965 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Marek Vasut Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 51 +++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 3a958fb25245..1c86e6f4dc71 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -907,13 +907,60 @@ }; can0: can@e6c30000 { + compatible = "renesas,can-r8a77965", + "renesas,rcar-gen3-can"; reg = <0 0xe6c30000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A77965_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; }; can1: can@e6c38000 { + compatible = "renesas,can-r8a77965", + "renesas,rcar-gen3-can"; reg = <0 0xe6c38000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A77965_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a77965-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77965_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; }; pwm0: pwm@e6e30000 { -- cgit From dcfc827d4449e5c05dce181d8a758b968cc27791 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 8 Jun 2018 13:27:30 +0200 Subject: ARM: dts: at91: sama5d4: switch to new clock bindings Switch sama5d4 boards to the new PMC clock bindings. Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d4ek.dts | 2 +- arch/arm/boot/dts/sama5d4.dtsi | 535 ++++------------------------------- 2 files changed, 49 insertions(+), 488 deletions(-) diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index 0702a2f2b336..12d5af938aa3 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -115,7 +115,7 @@ wm8904: codec@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck2>; + clocks = <&pmc PMC_TYPE_SYSTEM 10>; clock-names = "mclk"; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 7371f2a0460f..2604fd07dd53 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -137,7 +137,7 @@ reg = <0x00400000 0x100000 0xfc02c000 0x4000>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&utmi>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; @@ -264,7 +264,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -273,7 +273,7 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00600000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>; clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; @@ -297,7 +297,7 @@ 0x1 0x0 0x60000000 0x10000000 0x2 0x0 0x70000000 0x10000000 0x3 0x0 0x80000000 0x8000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { @@ -327,7 +327,7 @@ compatible = "atmel,sama5d4-hlcdc"; reg = <0xf0000000 0x4000>; interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; clock-names = "periph_clk","sys_clk", "slow_clk"; status = "disabled"; @@ -356,7 +356,7 @@ reg = <0xf0004000 0x200>; interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; - clocks = <&dma1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 50>; clock-names = "dma_clk"; }; @@ -366,7 +366,7 @@ interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&isi_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; clock-names = "isi_clk"; status = "disabled"; port { @@ -378,7 +378,7 @@ ramc0: ramc@f0010000 { compatible = "atmel,sama5d3-ddramc"; reg = <0xf0010000 0x200>; - clocks = <&ddrck>, <&mpddr_clk>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "ddrck", "mpddr"; }; @@ -387,7 +387,7 @@ reg = <0xf0014000 0x200>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "dma_clk"; }; @@ -395,448 +395,9 @@ compatible = "atmel,sama5d4-pmc", "syscon"; reg = <0xf0018000 0x120>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clock-frequency = <12000000>; - clock-accuracy = <100000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_rc_osc &main_osc>; - }; - - plla: pllack { - compatible = "atmel,sama5d3-clk-pll"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <12000000 12000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <125000000 200000000>; - atmel,clk-divisors = <1 2 4 3>; - }; - - h32ck: h32mxck { - #clock-cells = <0>; - compatible = "atmel,sama5d4-clk-h32mx"; - clocks = <&mck>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - }; - - smd: smdclk { - compatible = "atmel,at91sam9x5-clk-smd"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - - smdck: smdck { - #clock-cells = <0>; - reg = <4>; - clocks = <&smd>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - }; - - periph32ck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&h32ck>; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - icm_clk: icm_clk { - #clock-cells = <0>; - reg = <9>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <12>; - }; - - tdes_clk: tdes_clk { - #clock-cells = <0>; - reg = <14>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <15>; - }; - - matrix1_clk: matrix1_clk { - #clock-cells = <0>; - reg = <17>; - }; - - hsmc_clk: hsmc_clk { - #clock-cells = <0>; - reg = <22>; - }; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <23>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <24>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <25>; - }; - - pioE_clk: pioE_clk { - #clock-cells = <0>; - reg = <26>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <27>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <28>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <29>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <30>; - }; - - usart4_clk: usart4_clk { - #clock-cells = <0>; - reg = <31>; - }; - - twi0_clk: twi0_clk { - reg = <32>; - #clock-cells = <0>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <33>; - }; - - twi2_clk: twi2_clk { - #clock-cells = <0>; - reg = <34>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <35>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <36>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <37>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <38>; - }; - - spi2_clk: spi2_clk { - #clock-cells = <0>; - reg = <39>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <40>; - }; - - tcb1_clk: tcb1_clk { - #clock-cells = <0>; - reg = <41>; - }; - - tcb2_clk: tcb2_clk { - #clock-cells = <0>; - reg = <42>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <43>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <44>; - }; - - dbgu_clk: dbgu_clk { - #clock-cells = <0>; - reg = <45>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <46>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <47>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <48>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <49>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <53>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <54>; - }; - - macb1_clk: macb1_clk { - #clock-cells = <0>; - reg = <55>; - }; - - fuse_clk: fuse_clk { - #clock-cells = <0>; - reg = <57>; - }; - - securam_clk: securam_clk { - #clock-cells = <0>; - reg = <59>; - }; - - smd_clk: smd_clk { - #clock-cells = <0>; - reg = <61>; - }; - - twi3_clk: twi3_clk { - #clock-cells = <0>; - reg = <62>; - }; - - catb_clk: catb_clk { - #clock-cells = <0>; - reg = <63>; - }; - }; - - periph64ck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <8>; - }; - - cpkcc_clk: cpkcc_clk { - #clock-cells = <0>; - reg = <10>; - }; - - aesb_clk: aesb_clk { - #clock-cells = <0>; - reg = <13>; - }; - - mpddr_clk: mpddr_clk { - #clock-cells = <0>; - reg = <16>; - }; - - matrix0_clk: matrix0_clk { - #clock-cells = <0>; - reg = <18>; - }; - - vdec_clk: vdec_clk { - #clock-cells = <0>; - reg = <19>; - }; - - dma1_clk: dma1_clk { - #clock-cells = <0>; - reg = <50>; - }; - - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <51>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <52>; - }; - }; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; }; mmc0: mmc@f8000000 { @@ -852,7 +413,7 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; clock-names = "mci_clk"; }; @@ -869,7 +430,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; clock-names = "usart"; status = "disabled"; }; @@ -887,7 +448,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(27))>; dma-names = "tx", "rx"; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; clock-names = "pclk"; status = "disabled"; }; @@ -897,7 +458,7 @@ reg = <0xf800c000 0x300>; interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; status = "disabled"; }; @@ -916,7 +477,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; clock-names = "spi_clk"; status = "disabled"; }; @@ -936,7 +497,7 @@ pinctrl-0 = <&pinctrl_i2c0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; status = "disabled"; }; @@ -955,7 +516,7 @@ pinctrl-0 = <&pinctrl_i2c1>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; status = "disabled"; }; @@ -965,7 +526,7 @@ #size-cells = <0>; reg = <0xf801c000 0x100>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -977,7 +538,7 @@ pinctrl-0 = <&pinctrl_macb0_rmii>; #address-cells = <1>; #size-cells = <0>; - clocks = <&macb0_clk>, <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>; clock-names = "hclk", "pclk"; status = "disabled"; }; @@ -997,7 +558,7 @@ pinctrl-0 = <&pinctrl_i2c2>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; status = "disabled"; }; @@ -1019,7 +580,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "usart"; status = "disabled"; }; @@ -1037,7 +598,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -1055,7 +616,7 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; clock-names = "mci_clk"; }; @@ -1072,7 +633,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; clock-names = "usart"; status = "disabled"; }; @@ -1090,7 +651,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; clock-names = "usart"; status = "disabled"; }; @@ -1108,7 +669,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; clock-names = "usart"; status = "disabled"; }; @@ -1126,7 +687,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart4>; - clocks = <&usart4_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; clock-names = "usart"; status = "disabled"; }; @@ -1144,7 +705,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(29))>; dma-names = "tx", "rx"; - clocks = <&ssc1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; clock-names = "pclk"; status = "disabled"; }; @@ -1164,7 +725,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; clock-names = "spi_clk"; status = "disabled"; }; @@ -1184,7 +745,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - clocks = <&spi2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; clock-names = "spi_clk"; status = "disabled"; }; @@ -1195,7 +756,7 @@ #size-cells = <0>; reg = <0xfc020000 0x100>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -1205,7 +766,7 @@ #size-cells = <0>; reg = <0xfc024000 0x100>; interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb2_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -1217,7 +778,7 @@ pinctrl-0 = <&pinctrl_macb1_rmii>; #address-cells = <1>; #size-cells = <0>; - clocks = <&macb1_clk>, <&macb1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>; clock-names = "hclk", "pclk"; status = "disabled"; }; @@ -1226,14 +787,14 @@ compatible = "atmel,at91sam9g45-trng"; reg = <0xfc030000 0x100>; interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; }; adc0: adc@fc034000 { compatible = "atmel,at91sam9x5-adc"; reg = <0xfc034000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&adc_clk>, + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; atmel,adc-channels-used = <0x01f>; @@ -1276,7 +837,7 @@ <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>; dma-names = "tx", "rx"; - clocks = <&aes_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "aes_clk"; status = "okay"; }; @@ -1290,7 +851,7 @@ <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(43))>; dma-names = "tx", "rx"; - clocks = <&tdes_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "tdes_clk"; status = "okay"; }; @@ -1302,7 +863,7 @@ dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(44))>; dma-names = "tx"; - clocks = <&sha_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "sha_clk"; status = "okay"; }; @@ -1311,7 +872,7 @@ compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; reg = <0xfc05c000 0x1000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; - clocks = <&hsmc_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -1339,7 +900,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfc068630 0x10>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&h32ck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; }; watchdog: watchdog@fc068640 { @@ -1370,7 +931,7 @@ interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&dbgu_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; clock-names = "usart"; status = "disabled"; }; @@ -1400,7 +961,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; }; pioB: gpio@fc06b000 { @@ -1411,7 +972,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; }; pioC: gpio@fc06c000 { @@ -1422,7 +983,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; }; pioD: gpio@fc068000 { @@ -1433,7 +994,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; }; pioE: gpio@fc06d000 { @@ -1444,7 +1005,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; }; /* pinctrl pin settings */ -- cgit From b60557876849767bad580856d3a7ec0e06d5a6bc Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 12 Jun 2018 20:02:52 +0200 Subject: ARM: dts: at91: sama5d2: switch to new clock binding Switch sama5d2 boards to the new PMC clock bindings. Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 12 +- arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 2 +- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 4 +- arch/arm/boot/dts/sama5d2.dtsi | 670 +++------------------------- 4 files changed, 69 insertions(+), 619 deletions(-) diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts index 363a43d77424..4a258867ddf1 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts @@ -165,7 +165,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&flx1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_i2c>; atmel,fifo-size = <16>; @@ -211,7 +211,7 @@ compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&flx3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "usart"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; @@ -223,7 +223,7 @@ compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&flx3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "spi_clk"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; @@ -240,7 +240,7 @@ compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&flx4_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "usart"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; @@ -252,7 +252,7 @@ compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&flx4_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "spi_clk"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; @@ -268,7 +268,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&flx4_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; atmel,fifo-size = <16>; diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index 2214bfe7aa20..ba7f3e646c26 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -197,7 +197,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&flx0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx0_default>; atmel,fifo-size = <16>; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 518e2b095ccf..fa54e8866f1e 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -258,7 +258,7 @@ compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&flx0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; clock-names = "usart"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx0_default>; @@ -313,7 +313,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&flx4_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; atmel,fifo-size = <16>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index dd0dda6ed44b..dc2280d9127f 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -84,7 +84,7 @@ compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0x740000 0x1000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "apb_pclk"; in-ports { @@ -100,7 +100,7 @@ compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x73C000 0x1000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "apb_pclk"; out-ports { @@ -154,7 +154,7 @@ reg = <0x00300000 0x100000 0xfc02c000 0x400>; interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&utmi>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; @@ -281,7 +281,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00400000 0x100000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -290,7 +290,7 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00500000 0x100000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; @@ -314,7 +314,7 @@ 0x1 0x0 0x60000000 0x10000000 0x2 0x0 0x70000000 0x10000000 0x3 0x0 0x80000000 0x10000000>; - clocks = <&h32ck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; status = "disabled"; nand_controller: nand-controller { @@ -333,7 +333,7 @@ compatible = "atmel,sama5d2-sdhci"; reg = <0xa0000000 0x300>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; clock-names = "hclock", "multclk", "baseclk"; status = "disabled"; }; @@ -342,7 +342,7 @@ compatible = "atmel,sama5d2-sdhci"; reg = <0xb0000000 0x300>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; clock-names = "hclock", "multclk", "baseclk"; status = "disabled"; }; @@ -362,7 +362,7 @@ compatible = "atmel,sama5d2-hlcdc"; reg = <0xf0000000 0x2000>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; clock-names = "periph_clk","sys_clk", "slow_clk"; status = "disabled"; @@ -388,7 +388,7 @@ compatible = "atmel,sama5d2-isc"; reg = <0xf0008000 0x4000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&isc_clk>, <&iscck>, <&isc_gclk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; clock-names = "hclock", "iscck", "gck"; #clock-cells = <0>; clock-output-names = "isc-mck"; @@ -398,7 +398,7 @@ ramc0: ramc@f000c000 { compatible = "atmel,sama5d3-ddramc"; reg = <0xf000c000 0x200>; - clocks = <&ddrck>, <&mpddr_clk>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "ddrck", "mpddr"; }; @@ -407,7 +407,7 @@ reg = <0xf0010000 0x1000>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "dma_clk"; }; @@ -417,7 +417,7 @@ reg = <0xf0004000 0x1000>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; - clocks = <&dma1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "dma_clk"; }; @@ -425,559 +425,9 @@ compatible = "atmel,sama5d2-pmc", "syscon"; reg = <0xf0014000 0x160>; interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clock-frequency = <12000000>; - clock-accuracy = <100000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_rc_osc &main_osc>; - }; - - plla: pllack { - compatible = "atmel,sama5d3-clk-pll"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <12000000 12000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - audio_pll_frac: audiopll_fracck { - compatible = "atmel,sama5d2-clk-audio-pll-frac"; - #clock-cells = <0>; - clocks = <&main>; - }; - - audio_pll_pad: audiopll_padck { - compatible = "atmel,sama5d2-clk-audio-pll-pad"; - #clock-cells = <0>; - clocks = <&audio_pll_frac>; - }; - - audio_pll_pmc: audiopll_pmcck { - compatible = "atmel,sama5d2-clk-audio-pll-pmc"; - #clock-cells = <0>; - clocks = <&audio_pll_frac>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <124000000 166000000>; - atmel,clk-divisors = <1 2 4 3>; - }; - - h32ck: h32mxck { - #clock-cells = <0>; - compatible = "atmel,sama5d4-clk-h32mx"; - clocks = <&mck>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - - iscck: iscck { - #clock-cells = <0>; - reg = <18>; - clocks = <&mck>; - }; - }; - - periph32ck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&h32ck>; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <5>; - atmel,clk-output-range = <0 83000000>; - }; - - tdes_clk: tdes_clk { - #clock-cells = <0>; - reg = <11>; - atmel,clk-output-range = <0 83000000>; - }; - - matrix1_clk: matrix1_clk { - #clock-cells = <0>; - reg = <14>; - }; - - hsmc_clk: hsmc_clk { - #clock-cells = <0>; - reg = <17>; - }; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <18>; - atmel,clk-output-range = <0 83000000>; - }; - - flx0_clk: flx0_clk { - #clock-cells = <0>; - reg = <19>; - atmel,clk-output-range = <0 83000000>; - }; - - flx1_clk: flx1_clk { - #clock-cells = <0>; - reg = <20>; - atmel,clk-output-range = <0 83000000>; - }; - - flx2_clk: flx2_clk { - #clock-cells = <0>; - reg = <21>; - atmel,clk-output-range = <0 83000000>; - }; - - flx3_clk: flx3_clk { - #clock-cells = <0>; - reg = <22>; - atmel,clk-output-range = <0 83000000>; - }; - - flx4_clk: flx4_clk { - #clock-cells = <0>; - reg = <23>; - atmel,clk-output-range = <0 83000000>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <24>; - atmel,clk-output-range = <0 83000000>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <25>; - atmel,clk-output-range = <0 83000000>; - }; - - uart2_clk: uart2_clk { - #clock-cells = <0>; - reg = <26>; - atmel,clk-output-range = <0 83000000>; - }; - - uart3_clk: uart3_clk { - #clock-cells = <0>; - reg = <27>; - atmel,clk-output-range = <0 83000000>; - }; - - uart4_clk: uart4_clk { - #clock-cells = <0>; - reg = <28>; - atmel,clk-output-range = <0 83000000>; - }; - - twi0_clk: twi0_clk { - reg = <29>; - #clock-cells = <0>; - atmel,clk-output-range = <0 83000000>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <30>; - atmel,clk-output-range = <0 83000000>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <33>; - atmel,clk-output-range = <0 83000000>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <34>; - atmel,clk-output-range = <0 83000000>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <35>; - atmel,clk-output-range = <0 83000000>; - }; - - tcb1_clk: tcb1_clk { - #clock-cells = <0>; - reg = <36>; - atmel,clk-output-range = <0 83000000>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <38>; - atmel,clk-output-range = <0 83000000>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <40>; - atmel,clk-output-range = <0 83000000>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <41>; - atmel,clk-output-range = <0 83000000>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <42>; - atmel,clk-output-range = <0 83000000>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <43>; - atmel,clk-output-range = <0 83000000>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <44>; - atmel,clk-output-range = <0 83000000>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <47>; - atmel,clk-output-range = <0 83000000>; - }; - - pdmic_clk: pdmic_clk { - #clock-cells = <0>; - reg = <48>; - atmel,clk-output-range = <0 83000000>; - }; - - securam_clk: securam_clk { - #clock-cells = <0>; - reg = <51>; - }; - - i2s0_clk: i2s0_clk { - #clock-cells = <0>; - reg = <54>; - atmel,clk-output-range = <0 83000000>; - }; - - i2s1_clk: i2s1_clk { - #clock-cells = <0>; - reg = <55>; - atmel,clk-output-range = <0 83000000>; - }; - - can0_clk: can0_clk { - #clock-cells = <0>; - reg = <56>; - atmel,clk-output-range = <0 83000000>; - }; - - can1_clk: can1_clk { - #clock-cells = <0>; - reg = <57>; - atmel,clk-output-range = <0 83000000>; - }; - - classd_clk: classd_clk { - #clock-cells = <0>; - reg = <59>; - atmel,clk-output-range = <0 83000000>; - }; - }; - - periph64ck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - dma1_clk: dma1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <9>; - }; - - aesb_clk: aesb_clk { - #clock-cells = <0>; - reg = <10>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <12>; - }; - - mpddr_clk: mpddr_clk { - #clock-cells = <0>; - reg = <13>; - }; - - matrix0_clk: matrix0_clk { - #clock-cells = <0>; - reg = <15>; - }; - - sdmmc0_hclk: sdmmc0_hclk { - #clock-cells = <0>; - reg = <31>; - }; - - sdmmc1_hclk: sdmmc1_hclk { - #clock-cells = <0>; - reg = <32>; - }; - - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <45>; - }; - - isc_clk: isc_clk { - #clock-cells = <0>; - reg = <46>; - }; - - qspi0_clk: qspi0_clk { - #clock-cells = <0>; - reg = <52>; - }; - - qspi1_clk: qspi1_clk { - #clock-cells = <0>; - reg = <53>; - }; - }; - - gck { - compatible = "atmel,sama5d2-clk-generated"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>; - - sdmmc0_gclk: sdmmc0_gclk { - #clock-cells = <0>; - reg = <31>; - }; - - sdmmc1_gclk: sdmmc1_gclk { - #clock-cells = <0>; - reg = <32>; - }; - - tcb0_gclk: tcb0_gclk { - #clock-cells = <0>; - reg = <35>; - atmel,clk-output-range = <0 83000000>; - }; - - tcb1_gclk: tcb1_gclk { - #clock-cells = <0>; - reg = <36>; - atmel,clk-output-range = <0 83000000>; - }; - - pwm_gclk: pwm_gclk { - #clock-cells = <0>; - reg = <38>; - atmel,clk-output-range = <0 83000000>; - }; - - isc_gclk: isc_gclk { - #clock-cells = <0>; - reg = <46>; - }; - - pdmic_gclk: pdmic_gclk { - #clock-cells = <0>; - reg = <48>; - }; - - i2s0_gclk: i2s0_gclk { - #clock-cells = <0>; - reg = <54>; - }; - - i2s1_gclk: i2s1_gclk { - #clock-cells = <0>; - reg = <55>; - }; - - can0_gclk: can0_gclk { - #clock-cells = <0>; - reg = <56>; - atmel,clk-output-range = <0 80000000>; - }; - - can1_gclk: can1_gclk { - #clock-cells = <0>; - reg = <57>; - atmel,clk-output-range = <0 80000000>; - }; - - classd_gclk: classd_gclk { - #clock-cells = <0>; - reg = <59>; - atmel,clk-output-range = <0 100000000>; - }; - }; - - i2s_clkmux { - compatible = "atmel,sama5d2-clk-i2s-mux"; - #address-cells = <1>; - #size-cells = <0>; - - i2s0muxck: i2s0_muxclk { - clocks = <&i2s0_clk>, <&i2s0_gclk>; - #clock-cells = <0>; - reg = <0>; - }; - - i2s1muxck: i2s1_muxclk { - clocks = <&i2s1_clk>, <&i2s1_gclk>; - #clock-cells = <0>; - reg = <1>; - }; - }; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; }; qspi0: spi@f0020000 { @@ -985,7 +435,7 @@ reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; reg-names = "qspi_base", "qspi_mmap"; interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&qspi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -996,7 +446,7 @@ reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; reg-names = "qspi_base", "qspi_mmap"; interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&qspi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1010,7 +460,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(30))>; dma-names = "tx"; - clocks = <&sha_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "sha_clk"; status = "okay"; }; @@ -1026,7 +476,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(27))>; dma-names = "tx", "rx"; - clocks = <&aes_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "aes_clk"; status = "okay"; }; @@ -1042,7 +492,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(7))>; dma-names = "tx", "rx"; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; clock-names = "spi_clk"; atmel,fifo-size = <16>; #address-cells = <1>; @@ -1061,7 +511,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(22))>; dma-names = "tx", "rx"; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; clock-names = "pclk"; status = "disabled"; }; @@ -1074,7 +524,7 @@ 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ #address-cells = <1>; #size-cells = <0>; - clocks = <&macb0_clk>, <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; clock-names = "hclk", "pclk"; status = "disabled"; }; @@ -1085,7 +535,7 @@ #size-cells = <0>; reg = <0xf800c000 0x100>; interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -1095,7 +545,7 @@ #size-cells = <0>; reg = <0xf8010000 0x100>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -1103,7 +553,7 @@ compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; reg = <0xf8014000 0x1000>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; - clocks = <&hsmc_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -1123,7 +573,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(50))>; dma-names = "rx"; - clocks = <&pdmic_clk>, <&pdmic_gclk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; clock-names = "pclk", "gclk"; status = "disabled"; }; @@ -1139,7 +589,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(36))>; dma-names = "tx", "rx"; - clocks = <&uart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; clock-names = "usart"; status = "disabled"; }; @@ -1155,7 +605,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(38))>; dma-names = "tx", "rx"; - clocks = <&uart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; clock-names = "usart"; status = "disabled"; }; @@ -1171,7 +621,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>; dma-names = "tx", "rx"; - clocks = <&uart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; clock-names = "usart"; status = "disabled"; }; @@ -1189,7 +639,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; atmel,fifo-size = <16>; status = "disabled"; }; @@ -1199,7 +649,7 @@ reg = <0xf802c000 0x4000>; interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; }; sfr: sfr@f8030000 { @@ -1210,7 +660,7 @@ flx0: flexcom@f8034000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xf8034000 0x200>; - clocks = <&flx0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf8034000 0x800>; @@ -1220,7 +670,7 @@ flx1: flexcom@f8038000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xf8038000 0x200>; - clocks = <&flx1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf8038000 0x800>; @@ -1230,7 +680,7 @@ securam: sram@f8044000 { compatible = "atmel,sama5d2-securam", "mmio-sram"; reg = <0xf8044000 0x1420>; - clocks = <&securam_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xf8044000 0x1420>; @@ -1255,7 +705,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xf8048030 0x10>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&h32ck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; }; watchdog@f8048040 { @@ -1292,10 +742,10 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(32))>; dma-names = "tx", "rx"; - clocks = <&i2s0_clk>, <&i2s0_gclk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; clock-names = "pclk", "gclk"; - assigned-clocks = <&i2s0muxck>; - assigned-clock-parents = <&i2s0_gclk>; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; + assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; status = "disabled"; }; @@ -1306,10 +756,10 @@ interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, <64 IRQ_TYPE_LEVEL_HIGH 7>; interrupt-names = "int0", "int1"; - clocks = <&can0_clk>, <&can0_gclk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; clock-names = "hclk", "cclk"; - assigned-clocks = <&can0_gclk>; - assigned-clock-parents = <&utmi>; + assigned-clocks = <&pmc PMC_TYPE_GCK 56>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; assigned-clock-rates = <40000000>; bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; status = "disabled"; @@ -1326,7 +776,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(9))>; dma-names = "tx", "rx"; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; clock-names = "spi_clk"; atmel,fifo-size = <16>; #address-cells = <1>; @@ -1345,7 +795,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(42))>; dma-names = "tx", "rx"; - clocks = <&uart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; clock-names = "usart"; status = "disabled"; }; @@ -1361,7 +811,7 @@ AT91_XDMAC_DT_PERID(44))>; dma-names = "tx", "rx"; interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&uart4_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; clock-names = "usart"; status = "disabled"; }; @@ -1369,7 +819,7 @@ flx2: flexcom@fc010000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xfc010000 0x200>; - clocks = <&flx2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xfc010000 0x800>; @@ -1379,7 +829,7 @@ flx3: flexcom@fc014000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xfc014000 0x200>; - clocks = <&flx3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xfc014000 0x800>; @@ -1389,7 +839,7 @@ flx4: flexcom@fc018000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xfc018000 0x200>; - clocks = <&flx4_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xfc018000 0x800>; @@ -1400,7 +850,7 @@ compatible = "atmel,at91sam9g45-trng"; reg = <0xfc01c000 0x100>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; }; aic: interrupt-controller@fc020000 { @@ -1424,7 +874,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; atmel,fifo-size = <16>; status = "disabled"; }; @@ -1433,7 +883,7 @@ compatible = "atmel,sama5d2-adc"; reg = <0xfc030000 0x100>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&adc_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; clock-names = "adc_clk"; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; dma-names = "rx"; @@ -1466,7 +916,7 @@ #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; }; secumod@fc040000 { @@ -1485,7 +935,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(29))>; dma-names = "tx", "rx"; - clocks = <&tdes_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; clock-names = "tdes_clk"; status = "okay"; }; @@ -1498,7 +948,7 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(47))>; dma-names = "tx"; - clocks = <&classd_clk>, <&classd_gclk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; clock-names = "pclk", "gclk"; status = "disabled"; }; @@ -1514,10 +964,10 @@ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(34))>; dma-names = "tx", "rx"; - clocks = <&i2s1_clk>, <&i2s1_gclk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; clock-names = "pclk", "gclk"; - assigned-clocks = <&i2s1muxck>; - assigned-parrents = <&i2s1_gclk>; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; + assigned-parrents = <&pmc PMC_TYPE_GCK 55>; status = "disabled"; }; @@ -1528,10 +978,10 @@ interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, <65 IRQ_TYPE_LEVEL_HIGH 7>; interrupt-names = "int0", "int1"; - clocks = <&can1_clk>, <&can1_gclk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; clock-names = "hclk", "cclk"; - assigned-clocks = <&can1_gclk>; - assigned-clock-parents = <&utmi>; + assigned-clocks = <&pmc PMC_TYPE_GCK 57>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; assigned-clock-rates = <40000000>; bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>; status = "disabled"; -- cgit From e239e06004118aac16d0f3a7b2fd53bfa5896786 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 16 Aug 2018 18:29:20 +0200 Subject: ARM: dts: at91: at91sam9260: switch to new clock bindings Switch at91sam9260 and at91sam9g20 boards to the new PMC clock bindings. Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9260.dtsi | 308 ++++--------------------------------- arch/arm/boot/dts/at91sam9g20.dtsi | 23 +-- 2 files changed, 31 insertions(+), 300 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 9118e29b6d6a..7cd9c3bc4dfb 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -113,276 +113,28 @@ compatible = "atmel,at91sam9260-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - slow_rc_osc: slow_rc_osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-accuracy = <50000000>; - }; - - clk32k: slck { - compatible = "atmel,at91sam9260-clk-slow"; - #clock-cells = <0>; - clocks = <&slow_rc_osc>, <&slow_xtal>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <80000000 160000000 0 1>, - <150000000 240000000 2 1>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <1000000 5000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; - atmel,clk-output-range = <0 105000000>; - atmel,clk-divisors = <1 2 4 0>; - }; - - usb: usbck { - compatible = "atmel,at91rm9200-clk-usb"; - #clock-cells = <0>; - atmel,clk-divisors = <1 2 4 0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <8>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <9>; - }; - - udc_clk: udc_clk { - #clock-cells = <0>; - reg = <10>; - }; - - twi0_clk: twi0_clk { - reg = <11>; - #clock-cells = <0>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <13>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - tc0_clk: tc0_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tc1_clk: tc1_clk { - #clock-cells = <0>; - reg = <18>; - }; - - tc2_clk: tc2_clk { - #clock-cells = <0>; - reg = <19>; - }; - - ohci_clk: ohci_clk { - #clock-cells = <0>; - reg = <20>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <22>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <23>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <24>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <25>; - }; - - tc3_clk: tc3_clk { - #clock-cells = <0>; - reg = <26>; - }; - - tc4_clk: tc4_clk { - #clock-cells = <0>; - reg = <27>; - }; - - tc5_clk: tc5_clk { - #clock-cells = <0>; - reg = <28>; - }; - }; + #clock-cells = <2>; + clocks = <&slow_xtal>, <&main_xtal>; + clock-names = "slow_xtal", "main_xtal"; }; rstc@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; + clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; }; shdwc@fffffd10 { compatible = "atmel,at91sam9260-shdwc"; reg = <0xfffffd10 0x10>; - clocks = <&clk32k>; + clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; }; pit: timer@fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; tcb0: timer@fffa0000 { @@ -393,7 +145,7 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -405,7 +157,7 @@ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 27 IRQ_TYPE_LEVEL_HIGH 0 28 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -746,7 +498,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff600 { @@ -757,7 +509,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioC: gpio@fffff800 { @@ -768,7 +520,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; }; @@ -778,7 +530,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -791,7 +543,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "usart"; status = "disabled"; }; @@ -804,7 +556,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -817,7 +569,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -830,7 +582,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "usart"; status = "disabled"; }; @@ -843,7 +595,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; clock-names = "usart"; status = "disabled"; }; @@ -856,7 +608,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; clock-names = "usart"; status = "disabled"; }; @@ -867,7 +619,7 @@ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>, <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "hclk", "pclk"; status = "disabled"; }; @@ -876,7 +628,7 @@ compatible = "atmel,at91sam9260-udc"; reg = <0xfffa4000 0x4000>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udc_clk>, <&udpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>; clock-names = "pclk", "hclk"; status = "disabled"; }; @@ -887,7 +639,7 @@ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; status = "disabled"; }; @@ -898,7 +650,7 @@ #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "mci_clk"; status = "disabled"; }; @@ -909,7 +661,7 @@ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "pclk"; status = "disabled"; }; @@ -922,7 +674,7 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "spi_clk"; status = "disabled"; }; @@ -935,7 +687,7 @@ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "spi_clk"; status = "disabled"; }; @@ -946,7 +698,7 @@ compatible = "atmel,at91sam9260-adc"; reg = <0xfffe0000 0x100>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&adc_clk>, <&adc_op_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; atmel,adc-use-external-triggers; atmel,adc-channels-used = <0xf>; @@ -981,7 +733,7 @@ compatible = "atmel,at91sam9260-rtt"; reg = <0xfffffd20 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; + clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; status = "disabled"; }; @@ -989,7 +741,7 @@ compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; + clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; atmel,watchdog-type = "hardware"; atmel,reset-type = "all"; atmel,dbg-halt; @@ -1007,7 +759,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1027,7 +779,7 @@ 0x5 0x0 0x60000000 0x10000000 0x6 0x0 0x70000000 0x10000000 0x7 0x0 0x80000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 90705ee6008b..e976fd6bc6fd 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -40,28 +40,7 @@ }; pmc: pmc@fffffc00 { - plla: pllack { - atmel,clk-input-range = <2000000 32000000>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, - <695000000 750000000 1 0>, - <645000000 700000000 2 0>, - <595000000 650000000 3 0>, - <545000000 600000000 0 1>, - <495000000 550000000 1 1>, - <445000000 500000000 2 1>, - <400000000 450000000 3 1>; - }; - - pllb: pllbck { - compatible = "atmel,at91sam9g20-clk-pllb"; - atmel,clk-input-range = <2000000 32000000>; - atmel,pll-clk-output-ranges = <30000000 100000000 0 0>; - }; - - mck: masterck { - atmel,clk-output-range = <0 133000000>; - atmel,clk-divisors = <1 2 4 6>; - }; + compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon"; }; }; }; -- cgit From 7637d42cb18338fcc93b112a641d3ee77271d44d Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 22 Aug 2018 21:42:51 +0200 Subject: ARM: dts: at91: at91sam9261: switch to new clock bindings Switch at91sam9261 boards to the new PMC clock bindings. Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9261.dtsi | 287 +++---------------------------------- 1 file changed, 23 insertions(+), 264 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 33f09d5ea020..01d700b63b45 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -75,7 +75,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&ohci_clk>, <&hclk0>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 16>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -86,7 +86,7 @@ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fb>; - clocks = <&lcd_clk>, <&hclk1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_SYSTEM 17>; clock-names = "lcdc_clk", "hclk"; status = "disabled"; }; @@ -106,7 +106,7 @@ 0x5 0x0 0x60000000 0x10000000 0x6 0x0 0x70000000 0x10000000 0x7 0x0 0x80000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { @@ -132,7 +132,7 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, <18 IRQ_TYPE_LEVEL_HIGH 0>, <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -140,7 +140,7 @@ compatible = "atmel,at91sam9261-udc"; reg = <0xfffa4000 0x4000>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udc_clk>, <&udpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>; clock-names = "pclk", "hclk"; atmel,matrix = <&matrix>; status = "disabled"; @@ -154,7 +154,7 @@ pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "mci_clk"; status = "disabled"; }; @@ -167,7 +167,7 @@ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; status = "disabled"; }; @@ -179,7 +179,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "usart"; status = "disabled"; }; @@ -192,7 +192,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -205,7 +205,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -216,7 +216,7 @@ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "pclk"; status = "disabled"; }; @@ -227,7 +227,7 @@ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "pclk"; status = "disabled"; }; @@ -238,7 +238,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; - clocks = <&ssc2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "pclk"; status = "disabled"; }; @@ -252,7 +252,7 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "spi_clk"; status = "disabled"; }; @@ -265,7 +265,7 @@ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "spi_clk"; status = "disabled"; }; @@ -299,7 +299,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -563,7 +563,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff600 { @@ -574,7 +574,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioC: gpio@fffff800 { @@ -585,7 +585,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; }; @@ -593,250 +593,9 @@ compatible = "atmel,at91sam9261-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, - <190000000 240000000 2 1>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <1000000 5000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - atmel,clk-output-range = <0 94000000>; - atmel,clk-divisors = <1 2 4 0>; - }; - - usb: usbck { - compatible = "atmel,at91rm9200-clk-usb"; - #clock-cells = <0>; - atmel,clk-divisors = <1 2 4 0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - - prog3: prog3 { - #clock-cells = <0>; - reg = <3>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - - pck3: pck3 { - #clock-cells = <0>; - reg = <11>; - clocks = <&prog3>; - }; - - hclk0: hclk0 { - #clock-cells = <0>; - reg = <16>; - clocks = <&mck>; - }; - - hclk1: hclk1 { - #clock-cells = <0>; - reg = <17>; - clocks = <&mck>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <8>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <9>; - }; - - udc_clk: udc_clk { - #clock-cells = <0>; - reg = <10>; - }; - - twi0_clk: twi0_clk { - reg = <11>; - #clock-cells = <0>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <13>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc2_clk: ssc2_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tc0_clk: tc0_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tc1_clk: tc1_clk { - #clock-cells = <0>; - reg = <18>; - }; - - tc2_clk: tc2_clk { - #clock-cells = <0>; - reg = <19>; - }; - - ohci_clk: ohci_clk { - #clock-cells = <0>; - reg = <20>; - }; - - lcd_clk: lcd_clk { - #clock-cells = <0>; - reg = <21>; - }; - }; + #clock-cells = <2>; + clocks = <&slow_xtal>, <&main_xtal>; + clock-names = "slow_xtal", "main_xtal"; }; rstc@fffffd00 { @@ -855,7 +614,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; rtc@fffffd20 { -- cgit From 7f2fbc1e40a97ad810127247ad41e9afd7380bef Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 21 Aug 2018 18:12:08 +0200 Subject: ARM: dts: at91: at91sam9263: switch to new clock bindings Switch at91sam9263 boards to the new PMC clock bindings. Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9263.dtsi | 315 ++++--------------------------------- 1 file changed, 30 insertions(+), 285 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index af68a86c9973..c5766da4e54e 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -96,264 +96,9 @@ compatible = "atmel,at91sam9263-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, - <190000000 240000000 2 1>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, - <190000000 240000000 2 1>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - atmel,clk-output-range = <0 120000000>; - atmel,clk-divisors = <1 2 4 0>; - }; - - usb: usbck { - compatible = "atmel,at91rm9200-clk-usb"; - #clock-cells = <0>; - atmel,clk-divisors = <1 2 4 0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - - prog3: prog3 { - #clock-cells = <0>; - reg = <3>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - - pck3: pck3 { - #clock-cells = <0>; - reg = <11>; - clocks = <&prog3>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioCDE_clk: pioCDE_clk { - #clock-cells = <0>; - reg = <4>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <9>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <10>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <11>; - }; - - can_clk: can_clk { - #clock-cells = <0>; - reg = <12>; - }; - - twi0_clk: twi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <16>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <17>; - }; - - ac97_clk: ac97_clk { - #clock-cells = <0>; - reg = <18>; - }; - - tcb_clk: tcb_clk { - #clock-cells = <0>; - reg = <19>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <20>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - g2de_clk: g2de_clk { - #clock-cells = <0>; - reg = <23>; - }; - - udc_clk: udc_clk { - #clock-cells = <0>; - reg = <24>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <25>; - }; - - lcd_clk: lcd_clk { - #clock-cells = <0>; - reg = <26>; - }; - - dma_clk: dma_clk { - #clock-cells = <0>; - reg = <27>; - }; - - ohci_clk: ohci_clk { - #clock-cells = <0>; - reg = <29>; - }; - }; + #clock-cells = <2>; + clocks = <&slow_xtal>, <&main_xtal>; + clock-names = "slow_xtal", "main_xtal"; }; ramc0: ramc@ffffe200 { @@ -385,7 +130,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; tcb0: timer@fff7c000 { @@ -394,7 +139,7 @@ #size-cells = <0>; reg = <0xfff7c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>, <&slow_xtal>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; clock-names = "t0_clk", "slow_clk"; }; @@ -736,7 +481,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff400 { @@ -747,7 +492,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioC: gpio@fffff600 { @@ -758,7 +503,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; pioD: gpio@fffff800 { @@ -769,7 +514,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; pioE: gpio@fffffa00 { @@ -780,7 +525,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; }; @@ -790,7 +535,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -803,7 +548,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -816,7 +561,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -829,7 +574,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "usart"; status = "disabled"; }; @@ -840,7 +585,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "pclk"; status = "disabled"; }; @@ -851,7 +596,7 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; clock-names = "pclk"; status = "disabled"; }; @@ -862,7 +607,7 @@ interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ac97>; - clocks = <&ac97_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; clock-names = "ac97_clk"; status = "disabled"; }; @@ -873,7 +618,7 @@ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>, <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "hclk", "pclk"; status = "disabled"; }; @@ -882,7 +627,7 @@ compatible = "atmel,at91sam9263-udc"; reg = <0xfff78000 0x4000>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udc_clk>, <&udpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_SYSTEM 7>; clock-names = "pclk", "hclk"; status = "disabled"; }; @@ -893,7 +638,7 @@ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; status = "disabled"; }; @@ -904,7 +649,7 @@ pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; clock-names = "mci_clk"; status = "disabled"; }; @@ -916,7 +661,7 @@ pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; clock-names = "mci_clk"; status = "disabled"; }; @@ -940,7 +685,7 @@ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "spi_clk"; status = "disabled"; }; @@ -953,7 +698,7 @@ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "spi_clk"; status = "disabled"; }; @@ -963,7 +708,7 @@ reg = <0xfffb8000 0x300>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; clock-names = "pwm_clk"; status = "disabled"; }; @@ -974,7 +719,7 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can_rx_tx>; - clocks = <&can_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "can_clk"; }; @@ -1007,7 +752,7 @@ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fb>; - clocks = <&lcd_clk>, <&lcd_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 26>; clock-names = "lcdc_clk", "hclk"; status = "disabled"; }; @@ -1016,7 +761,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00a00000 0x100000>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1034,7 +779,7 @@ 0x3 0x0 0x40000000 0x10000000 0x4 0x0 0x50000000 0x10000000 0x5 0x0 0x60000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller0: nand-controller { @@ -1055,7 +800,7 @@ reg = <0x80000000 0x20000000>; ranges = <0x0 0x0 0x80000000 0x10000000 0x1 0x0 0x90000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller1: nand-controller { -- cgit From 6cf8f828ef08c1044938bdcdbbe7e95a75405018 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 16 Jul 2018 11:24:17 +0200 Subject: ARM: dts: at91: at91sam9x5: switch to new clock bindings Switch at91sam9x5 boards to the new PMC clock bindings. Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9g15.dtsi | 4 + arch/arm/boot/dts/at91sam9g25.dtsi | 4 + arch/arm/boot/dts/at91sam9g25ek.dts | 4 +- arch/arm/boot/dts/at91sam9g35.dtsi | 4 + arch/arm/boot/dts/at91sam9x25.dtsi | 4 + arch/arm/boot/dts/at91sam9x35.dtsi | 4 + arch/arm/boot/dts/at91sam9x5.dtsi | 326 ++++--------------------------- arch/arm/boot/dts/at91sam9x5_can.dtsi | 18 +- arch/arm/boot/dts/at91sam9x5_isi.dtsi | 11 +- arch/arm/boot/dts/at91sam9x5_lcd.dtsi | 19 +- arch/arm/boot/dts/at91sam9x5_macb0.dtsi | 11 +- arch/arm/boot/dts/at91sam9x5_macb1.dtsi | 11 +- arch/arm/boot/dts/at91sam9x5_usart3.dtsi | 11 +- 13 files changed, 62 insertions(+), 369 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi index 27de7dc0f0e0..b34a6c65bd44 100644 --- a/arch/arm/boot/dts/at91sam9g15.dtsi +++ b/arch/arm/boot/dts/at91sam9g15.dtsi @@ -24,6 +24,10 @@ 0x003fffff 0x003f8000 0x00000000 /* pioD */ >; }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91sam9g15-pmc", "atmel,at91sam9x5-pmc", "syscon"; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi index 0898213f3bb2..d8bb56253e64 100644 --- a/arch/arm/boot/dts/at91sam9g25.dtsi +++ b/arch/arm/boot/dts/at91sam9g25.dtsi @@ -26,6 +26,10 @@ 0x003fffff 0x003f8000 0x00000000 /* pioD */ >; }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon"; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts index 31fecc2cdaf9..ac730812a81d 100644 --- a/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/arch/arm/boot/dts/at91sam9g25ek.dts @@ -32,9 +32,9 @@ pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>; pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>; - clocks = <&pck0>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; clock-names = "xvclk"; - assigned-clocks = <&pck0>; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>; assigned-clock-rates = <25000000>; status = "okay"; diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi index ff4115886f97..333e158feb61 100644 --- a/arch/arm/boot/dts/at91sam9g35.dtsi +++ b/arch/arm/boot/dts/at91sam9g35.dtsi @@ -25,6 +25,10 @@ 0x003fffff 0x003f8000 0x00000000 /* pioD */ >; }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon"; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi index 3c5fa3388997..a99703a262c9 100644 --- a/arch/arm/boot/dts/at91sam9x25.dtsi +++ b/arch/arm/boot/dts/at91sam9x25.dtsi @@ -27,6 +27,10 @@ 0x003fffff 0x003f8000 0x00000000 /* pioD */ >; }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon"; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi index d9054e8167b7..bca274d33f68 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/at91sam9x35.dtsi @@ -26,6 +26,10 @@ 0x003fffff 0x003f8000 0x00000000 /* pioD */ >; }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon"; + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 11c0ef102ab1..07443a387a8f 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -111,7 +111,7 @@ ramc0: ramc@ffffe800 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe800 0x200>; - clocks = <&ddrck>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "ddrck"; }; @@ -124,269 +124,9 @@ compatible = "atmel,at91sam9x5-pmc", "syscon"; reg = <0xfffffc00 0x200>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; - clocks = <&main_rc_osc>, <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0 - 695000000 750000000 1 0 - 645000000 700000000 2 0 - 595000000 650000000 3 0 - 545000000 600000000 0 1 - 495000000 555000000 1 1 - 445000000 500000000 2 1 - 400000000 450000000 3 1>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKU>; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <0 133333333>; - atmel,clk-divisors = <1 2 4 3>; - atmel,master-clk-have-div3-pres; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - smd: smdclk { - compatible = "atmel,at91sam9x5-clk-smd"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - smdck: smdck { - #clock-cells = <0>; - reg = <4>; - clocks = <&smd>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioAB_clk: pioAB_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioCD_clk: pioCD_clk { - #clock-cells = <0>; - reg = <3>; - }; - - smd_clk: smd_clk { - #clock-cells = <0>; - reg = <4>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <7>; - }; - - twi0_clk: twi0_clk { - reg = <9>; - #clock-cells = <0>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <10>; - }; - - twi2_clk: twi2_clk { - #clock-cells = <0>; - reg = <11>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <14>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <15>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <17>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <18>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <19>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <20>; - }; - - dma1_clk: dma1_clk { - #clock-cells = <0>; - reg = <21>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <23>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <26>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <28>; - }; - }; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; }; reset_controller: rstc@fffffe00 { @@ -405,7 +145,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; sckc@fffffe50 { @@ -438,7 +178,7 @@ #size-cells = <0>; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -448,7 +188,7 @@ #size-cells = <0>; reg = <0xf800c000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -457,7 +197,7 @@ reg = <0xffffec00 0x200>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; clock-names = "dma_clk"; }; @@ -466,7 +206,7 @@ reg = <0xffffee00 0x200>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "dma_clk"; }; @@ -864,7 +604,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioAB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff600 { @@ -876,7 +616,7 @@ #gpio-lines = <19>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioAB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioC: gpio@fffff800 { @@ -887,7 +627,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioCD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioD: gpio@fffffa00 { @@ -899,7 +639,7 @@ #gpio-lines = <22>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioCD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; }; @@ -912,7 +652,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; clock-names = "pclk"; status = "disabled"; }; @@ -924,7 +664,7 @@ dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; pinctrl-names = "default"; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; @@ -938,7 +678,7 @@ dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; pinctrl-names = "default"; - clocks = <&mci1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; @@ -954,7 +694,7 @@ dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>, <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>; dma-names = "tx", "rx"; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -968,7 +708,7 @@ dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>, <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; dma-names = "tx", "rx"; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; clock-names = "usart"; status = "disabled"; }; @@ -982,7 +722,7 @@ dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>, <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; dma-names = "tx", "rx"; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "usart"; status = "disabled"; }; @@ -996,7 +736,7 @@ dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>, <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>; dma-names = "tx", "rx"; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -1012,7 +752,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; status = "disabled"; }; @@ -1027,7 +767,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&twi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; status = "disabled"; }; @@ -1042,7 +782,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&twi2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; status = "disabled"; }; @@ -1052,7 +792,7 @@ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "usart"; status = "disabled"; }; @@ -1063,7 +803,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "usart"; status = "disabled"; }; @@ -1074,7 +814,7 @@ compatible = "atmel,at91sam9x5-adc"; reg = <0xf804c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&adc_clk>, + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; atmel,adc-use-external-triggers; @@ -1121,7 +861,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "spi_clk"; status = "disabled"; }; @@ -1137,7 +877,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "spi_clk"; status = "disabled"; }; @@ -1149,7 +889,7 @@ reg = <0x00500000 0x80000 0xf803c000 0x400>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&utmi>, <&udphs_clk>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "hclk", "pclk"; status = "disabled"; @@ -1229,7 +969,7 @@ compatible = "atmel,at91sam9rl-pwm"; reg = <0xf8034000 0x300>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; #pwm-cells = <3>; status = "disabled"; }; @@ -1239,7 +979,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1248,7 +988,7 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; @@ -1266,7 +1006,7 @@ 0x3 0x0 0x40000000 0x10000000 0x4 0x0 0x50000000 0x10000000 0x5 0x0 0x60000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi index 8eb2f9c1b978..125f9e3b49ad 100644 --- a/arch/arm/boot/dts/at91sam9x5_can.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi @@ -13,27 +13,13 @@ / { ahb { apb { - pmc: pmc@fffffc00 { - periphck { - can0_clk: can0_clk { - #clock-cells = <0>; - reg = <29>; - }; - - can1_clk: can1_clk { - #clock-cells = <0>; - reg = <30>; - }; - }; - }; - can0: can@f8000000 { compatible = "atmel,at91sam9x5-can"; reg = <0xf8000000 0x300>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_rx_tx>; - clocks = <&can0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; clock-names = "can_clk"; status = "disabled"; }; @@ -44,7 +30,7 @@ interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_rx_tx>; - clocks = <&can1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; clock-names = "can_clk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi index 8fc45ca4dcb5..c3e45b57b6a2 100644 --- a/arch/arm/boot/dts/at91sam9x5_isi.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi @@ -44,22 +44,13 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <25>; - }; - }; - }; - isi: isi@f8048000 { compatible = "atmel,at91sam9g45-isi"; reg = <0xf8048000 0x4000>; interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&isi_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; clock-names = "isi_clk"; status = "disabled"; port { diff --git a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi index 1629db9dd563..12595fb11691 100644 --- a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi @@ -17,7 +17,7 @@ compatible = "atmel,at91sam9x5-hlcdc"; reg = <0xf8038000 0x4000>; interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; clock-names = "periph_clk","sys_clk", "slow_clk"; status = "disabled"; @@ -143,23 +143,6 @@ }; }; }; - - pmc: pmc@fffffc00 { - periphck { - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <25>; - }; - }; - - systemck { - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - }; - }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi index 73d7e30965ba..57c2e5a4fb53 100644 --- a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi @@ -43,22 +43,13 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <24>; - }; - }; - }; - macb0: ethernet@f802c000 { compatible = "cdns,at91sam9260-macb", "cdns,macb"; reg = <0xf802c000 0x100>; interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_rmii>; - clocks = <&macb0_clk>, <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; clock-names = "hclk", "pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi index d81980c40c7d..59b8da87d3c1 100644 --- a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi @@ -31,22 +31,13 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - macb1_clk: macb1_clk { - #clock-cells = <0>; - reg = <27>; - }; - }; - }; - macb1: ethernet@f8030000 { compatible = "cdns,at91sam9260-macb", "cdns,macb"; reg = <0xf8030000 0x100>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb1_rmii>; - clocks = <&macb1_clk>, <&macb1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; clock-names = "hclk", "pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi index a32d12b406a3..9102dfbed5d8 100644 --- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi @@ -42,15 +42,6 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <8>; - }; - }; - }; - usart3: serial@f8028000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf8028000 0x200>; @@ -60,7 +51,7 @@ dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>, <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>; dma-names = "tx", "rx"; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; -- cgit From 0a4499dfbf8080fcb0a5ead3f3b83d41b8e8ec2d Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 10 Sep 2018 22:02:41 +0200 Subject: ARM: dts: at91: at91sam9rl: switch to new clock bindings Switch at91sam9rl boards to the new PMC clock bindings. Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91sam9rl.dtsi | 239 ++++---------------------------------- 1 file changed, 23 insertions(+), 216 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 8fb22030f00b..3862ff2f26e0 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -88,7 +88,7 @@ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fb>; - clocks = <&lcd_clk>, <&lcd_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "hclk", "lcdc_clk"; status = "disabled"; }; @@ -106,7 +106,7 @@ 0x3 0x0 0x40000000 0x10000000 0x4 0x0 0x50000000 0x10000000 0x5 0x0 0x60000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { @@ -132,7 +132,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, <17 IRQ_TYPE_LEVEL_HIGH 0>, <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>, <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -143,7 +143,7 @@ #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; clock-names = "mci_clk"; status = "disabled"; }; @@ -154,7 +154,7 @@ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; status = "disabled"; }; @@ -175,7 +175,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "usart"; status = "disabled"; }; @@ -188,7 +188,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -201,7 +201,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -214,7 +214,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "usart"; status = "disabled"; }; @@ -242,7 +242,7 @@ reg = <0xfffc8000 0x300>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; clock-names = "pwm_clk"; status = "disabled"; }; @@ -255,7 +255,7 @@ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "spi_clk"; status = "disabled"; }; @@ -266,7 +266,7 @@ compatible = "atmel,at91sam9rl-adc"; reg = <0xfffd0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&adc_clk>, <&adc_op_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; atmel,adc-use-external-triggers; atmel,adc-channels-used = <0x3f>; @@ -304,7 +304,7 @@ reg = <0x00600000 0x100000>, <0xfffd4000 0x4000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&utmi>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; @@ -366,7 +366,7 @@ reg = <0xffffe600 0x200>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "dma_clk"; }; @@ -399,7 +399,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -794,7 +794,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff600 { @@ -805,7 +805,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioC: gpio@fffff800 { @@ -816,7 +816,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; pioD: gpio@fffffa00 { @@ -827,7 +827,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; }; }; @@ -835,202 +835,9 @@ compatible = "atmel,at91sam9rl-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <80000000 200000000 0>, - <190000000 240000000 2>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plla>, <&utmi>; - atmel,clk-output-range = <0 94000000>; - atmel,clk-divisors = <1 2 4 0>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <9>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <10>; - }; - - twi0_clk: twi0_clk { - #clock-cells = <0>; - reg = <11>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - tc0_clk: tc0_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tc1_clk: tc1_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tc2_clk: tc2_clk { - #clock-cells = <0>; - reg = <18>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <19>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <20>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - lcd_clk: lcd_clk { - #clock-cells = <0>; - reg = <23>; - }; - }; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; }; rstc@fffffd00 { @@ -1049,7 +856,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; watchdog@fffffd40 { -- cgit From d8007306f6ad18f2ba0dcad68ffe9b2fd1d56bfb Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Tue, 20 Nov 2018 21:20:43 +0000 Subject: ARM: dts: at91: nattis: initialize the BLON pin as output-low early The pwm-backlight driver initializes BLON (the enable gpio) to output-high if the gpio is input on probe. Initializing the gpio to output-low before the driver probes prevents this action by the pwm-backlight driver and gets rid of a nasty blink of full backlight with an uninitialized panel. Signed-off-by: Peter Rosin Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/at91-nattis-2-natte-2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts index 911d2c7c1500..0f6d335125e2 100644 --- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts +++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts @@ -60,6 +60,8 @@ power-supply = <&bl_reg>; enable-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_blon>; }; panel: panel { @@ -164,6 +166,12 @@ (AT91_PINCTRL_OUTPUT | AT91_PINCTRL_OUTPUT_VAL(0))>; }; + + pinctrl_blon: blon { + atmel,pins = ; + }; }; }; -- cgit From 8cc77e014917c65f05a61503bf67d8a2daa0ed90 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 21 Nov 2018 23:44:47 +0800 Subject: Documentation: ARM: sunxi: Add Allwinner SoC T3. Add Allwinner SoC T3 document and fix format. Signed-off-by: Hao Zhang Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt index e4beec3d9ad3..94b9c12df96d 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.txt +++ b/Documentation/devicetree/bindings/arm/sunxi.txt @@ -14,7 +14,8 @@ using one of the following compatible strings: allwinner,sun8i-a83t allwinner,sun8i-h2-plus allwinner,sun8i-h3 - allwinner-sun8i-r40 + allwinner,sun8i-r40 + allwinner,sun8i-t3 allwinner,sun8i-v3s allwinner,sun9i-a80 allwinner,sun50i-a64 -- cgit From 382744d359167fe83d30c304aefefc03bf15259e Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 21 Nov 2018 23:43:57 +0800 Subject: ARM: dts: sun8i: Add board dts file for t3-cqa3t-bv3. The T3/R40/V40 using the same sdk and config file in allwinner sdk, it seem they are the same SOC just with different name, so compatible with R40. The t3-cqa3t-bv3 based on Allwinner T3 SoC, it has various connectors, leds, buttons, and sell on: https://item.taobao.com/item.htm?spm=2013.1.w4023-4203040713.25.62704cce7UCgLS&id=557154455330 It features: - X-Powers AXP221s PMIC connected to i2c0 - 1/2 GB DDR3 DRAM - 8 GB eMMC - 2x USB 2.0 hosts - 1x USB 2.0 OTG - 2 LVDS connectors - 24 bit RGB LCD connector - HDMI output - DVP camera interface (support 500w cmos camera) - GPIO connectors - 5 TTL uarts and 2 RS232 uarts - 1 RS485 connector - support i2c capacitive tp and usb infrared tp - boot control, reset and user buttons - 3.5mm headphone and 3.5mm mic jack - 100M RJ45 - micro SD card slot - DC power jack - RCT power slot - 1 CVBS TVIN - 1 CVBS TVOUT - 2 customer leds - 1 buzzer - 1 minipcie - I2C output - SPI output - PCM output - wifi and bt connector reserved. Board info can find here: https://github.com/Axl-zhang/Allwinner-V40-T3-R40-manual Signed-off-by: Hao Zhang Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts | 226 +++++++++++++++++++++++++++++++ 2 files changed, 227 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..e1628224aada 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1060,6 +1060,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-nintendo-super-nes-classic.dtb \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtb diff --git a/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts b/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts new file mode 100644 index 000000000000..6931aaab2382 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-t3-cqa3t-bv3.dts @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2017 Chen-Yu Tsai + * Copyright (C) 2017 Icenowy Zheng + * Copyright (C) 2018 Hao Zhang + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-r40.dtsi" + +#include + +/ { + model = "t3-cqa3t-bv3"; + compatible = "qihua,t3-cqa3t-bv3", "allwinner,sun8i-t3", + "allwinner,sun8i-r40"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; +}; + +&ahci { + ahci-supply = <®_dldo4>; + phy-supply = <®_eldo3>; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */ + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pa"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pg"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-dldo3"; +}; + +®_eldo3 { + regulator-always-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-pe"; +}; + +&tcon_tv0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; -- cgit From 6035cbcceb069f87296b3cd0bc4736ad5618bf47 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 20 Nov 2018 16:54:28 +0100 Subject: ARM: dts: exynos: Use Samsung SoC specific compatible for DWC2 module DWC2 hardware module integrated in Samsung SoCs requires some quirks to operate properly, so use Samsung SoC specific compatible to notify driver to apply respective fixes. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 27a1ee28c3bb..608d17454179 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -357,7 +357,7 @@ }; hsotg: hsotg@12480000 { - compatible = "snps,dwc2"; + compatible = "samsung,s3c6400-hsotg", "snps,dwc2"; reg = <0x12480000 0x20000>; interrupts = ; clocks = <&cmu CLK_USBOTG>; -- cgit From 327d1f320872c6c616e4cd369257f31eb48d0401 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 18 Nov 2018 18:34:24 +0100 Subject: arm64: dts: renesas: r8a77990: ebisu: Add and enable CAN,FD device nodes This patch adds CAN0,1 and CANFD device nodes for the r8a77990 SoC and enables CANFD connected to CN10 on the E3 Ebisu board using the R8A77990 SoC. Signed-off-by: Marek Vasut Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 15 ++++++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 64 ++++++++++++++++++++++++++ 2 files changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 3e4d90b654cc..62bdddcbbae7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -260,6 +260,16 @@ }; }; +&canfd { + pinctrl-0 = <&canfd0_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; +}; + &csi40 { status = "okay"; @@ -460,6 +470,11 @@ }; }; + canfd0_pins: canfd0 { + groups = "canfd0_data"; + function = "canfd0"; + }; + du_pins: du { groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; function = "du"; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 46868dacbeef..b0398e05e8ed 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -48,6 +48,13 @@ clock-frequency = <0>; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -773,6 +780,63 @@ status = "disabled"; }; + can0: can@e6c30000 { + compatible = "renesas,can-r8a77990", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A77990_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a77990", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A77990_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a77990-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77990_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; -- cgit From 44ea652a92d209045da9183981b55fd0c2c01971 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Wed, 21 Nov 2018 13:11:39 +0100 Subject: arm64: dts: renesas: r8a77990: Add I2C-DVFS device node This patch adds I2C-DVFS device node for the R8A77990 SoC. v2 * Drop aliases update as in upstream it is not required to configure the BD9571 PMIC for DDR backup, nor is the use of i2c are aliases desired. * Do not describe the device as compatible with "renesas,rcar-gen3-iic" or "renesas,rmobile-iic" fallback compat strings. The absence of automatic transmission registers leads us to declare the r8a77990 IIC controller as incompatible. v2.1 * Reduced register range to reflect documentation Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index b0398e05e8ed..3b334be843f4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -357,6 +357,20 @@ reg = <0 0xe6060000 0 0x508>; }; + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a77990"; + reg = <0 0xe60b0000 0 0x15>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a77990-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- cgit From 8d14bfa074dbd7ad9a1ff1bfbaff9ec5e450a567 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 21 Nov 2018 01:07:11 +0000 Subject: arm64: dts: renesas: r8a7796: add SSIU support for sound rsnd driver supports SSIU now, let's use it. Then, BUSIF DMA settings on rcar_sound,ssi (= rxu, txu) are no longer needed. To avoid git merge timing issue / git bisect issue, this patch doesn't remove it so far, but will be removed in the future. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 211 +++++++++++++++++++++++++++++++ 1 file changed, 211 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 369d0bccc651..e62c1702ab72 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -1826,6 +1826,217 @@ }; }; + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + ssiu02: ssiu-2 { + dmas = <&audma0 0x37>, <&audma1 0x38>; + dma-names = "rx", "tx"; + }; + ssiu03: ssiu-3 { + dmas = <&audma0 0x47>, <&audma1 0x48>; + dma-names = "rx", "tx"; + }; + ssiu04: ssiu-4 { + dmas = <&audma0 0x3F>, <&audma1 0x40>; + dma-names = "rx", "tx"; + }; + ssiu05: ssiu-5 { + dmas = <&audma0 0x43>, <&audma1 0x44>; + dma-names = "rx", "tx"; + }; + ssiu06: ssiu-6 { + dmas = <&audma0 0x4F>, <&audma1 0x50>; + dma-names = "rx", "tx"; + }; + ssiu07: ssiu-7 { + dmas = <&audma0 0x53>, <&audma1 0x54>; + dma-names = "rx", "tx"; + }; + ssiu10: ssiu-8 { + dmas = <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx"; + }; + ssiu11: ssiu-9 { + dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dma-names = "rx", "tx"; + }; + ssiu12: ssiu-10 { + dmas = <&audma0 0x57>, <&audma1 0x58>; + dma-names = "rx", "tx"; + }; + ssiu13: ssiu-11 { + dmas = <&audma0 0x59>, <&audma1 0x5A>; + dma-names = "rx", "tx"; + }; + ssiu14: ssiu-12 { + dmas = <&audma0 0x5F>, <&audma1 0x60>; + dma-names = "rx", "tx"; + }; + ssiu15: ssiu-13 { + dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dma-names = "rx", "tx"; + }; + ssiu16: ssiu-14 { + dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dma-names = "rx", "tx"; + }; + ssiu17: ssiu-15 { + dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dma-names = "rx", "tx"; + }; + ssiu20: ssiu-16 { + dmas = <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx"; + }; + ssiu21: ssiu-17 { + dmas = <&audma0 0x67>, <&audma1 0x68>; + dma-names = "rx", "tx"; + }; + ssiu22: ssiu-18 { + dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dma-names = "rx", "tx"; + }; + ssiu23: ssiu-19 { + dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dma-names = "rx", "tx"; + }; + ssiu24: ssiu-20 { + dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dma-names = "rx", "tx"; + }; + ssiu25: ssiu-21 { + dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dma-names = "rx", "tx"; + }; + ssiu26: ssiu-22 { + dmas = <&audma0 0xED>, <&audma1 0xEE>; + dma-names = "rx", "tx"; + }; + ssiu27: ssiu-23 { + dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dma-names = "rx", "tx"; + }; + ssiu30: ssiu-24 { + dmas = <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx"; + }; + ssiu31: ssiu-25 { + dmas = <&audma0 0x21>, <&audma1 0x22>; + dma-names = "rx", "tx"; + }; + ssiu32: ssiu-26 { + dmas = <&audma0 0x23>, <&audma1 0x24>; + dma-names = "rx", "tx"; + }; + ssiu33: ssiu-27 { + dmas = <&audma0 0x25>, <&audma1 0x26>; + dma-names = "rx", "tx"; + }; + ssiu34: ssiu-28 { + dmas = <&audma0 0x27>, <&audma1 0x28>; + dma-names = "rx", "tx"; + }; + ssiu35: ssiu-29 { + dmas = <&audma0 0x29>, <&audma1 0x2A>; + dma-names = "rx", "tx"; + }; + ssiu36: ssiu-30 { + dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dma-names = "rx", "tx"; + }; + ssiu37: ssiu-31 { + dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dma-names = "rx", "tx"; + }; + ssiu40: ssiu-32 { + dmas = <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx"; + }; + ssiu41: ssiu-33 { + dmas = <&audma0 0x17>, <&audma1 0x18>; + dma-names = "rx", "tx"; + }; + ssiu42: ssiu-34 { + dmas = <&audma0 0x19>, <&audma1 0x1A>; + dma-names = "rx", "tx"; + }; + ssiu43: ssiu-35 { + dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dma-names = "rx", "tx"; + }; + ssiu44: ssiu-36 { + dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dma-names = "rx", "tx"; + }; + ssiu45: ssiu-37 { + dmas = <&audma0 0x1F>, <&audma1 0x20>; + dma-names = "rx", "tx"; + }; + ssiu46: ssiu-38 { + dmas = <&audma0 0x31>, <&audma1 0x32>; + dma-names = "rx", "tx"; + }; + ssiu47: ssiu-39 { + dmas = <&audma0 0x33>, <&audma1 0x34>; + dma-names = "rx", "tx"; + }; + ssiu50: ssiu-40 { + dmas = <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx"; + }; + ssiu60: ssiu-41 { + dmas = <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx"; + }; + ssiu70: ssiu-42 { + dmas = <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx"; + }; + ssiu80: ssiu-43 { + dmas = <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx"; + }; + ssiu90: ssiu-44 { + dmas = <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx"; + }; + ssiu91: ssiu-45 { + dmas = <&audma0 0x7F>, <&audma1 0x80>; + dma-names = "rx", "tx"; + }; + ssiu92: ssiu-46 { + dmas = <&audma0 0x81>, <&audma1 0x82>; + dma-names = "rx", "tx"; + }; + ssiu93: ssiu-47 { + dmas = <&audma0 0x83>, <&audma1 0x84>; + dma-names = "rx", "tx"; + }; + ssiu94: ssiu-48 { + dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dma-names = "rx", "tx"; + }; + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + }; + rcar_sound,ssi { ssi0: ssi-0 { interrupts = ; -- cgit From 8942ce2bfaa162f8d915b50778724be0c5c2662b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 26 Oct 2018 09:25:07 +0100 Subject: arm64: dts: renesas: r8a7796: Add CMT device nodes This patch adds CMT{0|1|2|3} device nodes for r8a7796 SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index e62c1702ab72..e7614b781308 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -433,6 +433,76 @@ reg = <0 0xe6060000 0 0x50c>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a7796-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7796-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a7796-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a7796-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7796-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- cgit From ec4a95409d5c28962e0097e8291aa7048f8b262a Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Thu, 22 Nov 2018 18:23:23 +0800 Subject: arm64: dts: allwinner: a64: add nodes necessary for analog sound support Add nodes for i2s, digital and analog parts of audiocodec on A64. The routing paths listed are entries connecting the digital and analog side of the audio codec together. Due to how device tree works, these must be copied over to each board device tree, in addition to any board level routes. The oversampling rate is set to 128, so that when playing back 192 kHz audio samples, the MCLK runs at the same rate as the module clock, at 24.576 MHz. The user manual suggests using different oversampling rates for different sample rates, but that's not possible without a platform-specific machine driver. Signed-off-by: Vasily Khoruzhick [wens@csie.org: Lowered oversampling rate to 128; expanded commit message] Acked-by: Maxime Ripard Tested-by: Vasily Khoruzhick Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 54 +++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 42abfbf56b88..384c417cb7a2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -155,6 +155,30 @@ method = "smc"; }; + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "sun50i-a64-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&cpudai>; + simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC"; + status = "disabled"; + + cpudai: simple-audio-card,cpu { + sound-dai = <&dai>; + }; + + link_codec: simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + sound_spdif { compatible = "simple-audio-card"; simple-audio-card,name = "On-board SPDIF"; @@ -665,6 +689,30 @@ status = "disabled"; }; + dai: dai@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-a64-codec-i2s"; + reg = <0x01c22c00 0x200>; + interrupts = ; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_CODEC>; + reset-names = "rst"; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + codec: codec@1c22e00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a33-codec"; + reg = <0x01c22e00 0x600>; + interrupts = ; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "bus", "mod"; + status = "disabled"; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; @@ -924,6 +972,12 @@ #reset-cells = <1>; }; + codec_analog: codec-analog@1f015c0 { + compatible = "allwinner,sun50i-a64-codec-analog"; + reg = <0x01f015c0 0x4>; + status = "disabled"; + }; + r_i2c: i2c@1f02400 { compatible = "allwinner,sun50i-a64-i2c", "allwinner,sun6i-a31-i2c"; -- cgit From 498c21f233ed0bd643b5f11ecc19dc8727231c7e Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Thu, 22 Nov 2018 18:23:24 +0800 Subject: arm64: dts: allwinner: a64: enable sound on Pine64 and SoPine This commit enables I2S, digital and analog parts of audiocodec on Pine64 and SoPine boards. Signed-off-by: Vasily Khoruzhick [wens@csie.org: Dropped headphone_amp; added headphone amp regulator supply] Acked-by: Maxime Ripard Tested-by: Vasily Khoruzhick Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 27 ++++++++++++++++++++++ .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 26 +++++++++++++++++++++ .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 4 ++++ 3 files changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index c077b6c1f458..216f2f5db5ef 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -75,6 +75,19 @@ }; }; +&codec { + status = "okay"; +}; + +&codec_analog { + hpvcc-supply = <®_eldo1>; + status = "okay"; +}; + +&dai { + status = "okay"; +}; + &de { status = "okay"; }; @@ -259,6 +272,20 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,widgets = "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "Headphone Jack", "HP", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "MIC2", "Microphone Jack"; + status = "okay"; +}; + /* On Euler connector */ &spdif { status = "disabled"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 53fcc9098df3..2052319b9030 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -80,6 +80,18 @@ }; }; +&codec { + status = "okay"; +}; + +&codec_analog { + status = "okay"; +}; + +&dai { + status = "okay"; +}; + &de { status = "okay"; }; @@ -164,6 +176,20 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,widgets = "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "Headphone Jack", "HP", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "MIC2", "Microphone Jack"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi index 6723b8695e0b..d2651f284aa0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi @@ -47,6 +47,10 @@ #include +&codec_analog { + hpvcc-supply = <®_eldo1>; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; -- cgit From 6de8e717848f1b07b05f1b512dd6b8552677d958 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Thu, 22 Nov 2018 18:23:25 +0800 Subject: arm64: dts: allwinner: a64: enable sound on Pinebook The Pinebook has a headphone jack tied to the HP headphone output of the SoC, and internal speakers connected to the LINEOUT of the SoC, through a standalone amplifier. This commit enables I2S, digital and analog parts of audio codec on Pinebook, along with a device node for the external amplifier. Signed-off-by: Vasily Khoruzhick [wens@csie.org: dropped headphone_amp; added headphone amp regulator supply; fixed speaker_amp node name and sound-name-prefix name] Acked-by: Maxime Ripard Tested-by: Vasily Khoruzhick Signed-off-by: Chen-Yu Tsai --- .../boot/dts/allwinner/sun50i-a64-pinebook.dts | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index ec537c529726..25018d032d51 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -74,6 +74,32 @@ compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; + + speaker_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + /* + * TODO This is actually a fixed regulator controlled by + * the GPIO line on the PMIC. This should be corrected + * once GPIO support is added for this PMIC. + */ + VCC-supply = <®_ldo_io0>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + sound-name-prefix = "Speaker Amp"; + }; + +}; + +&codec { + status = "okay"; +}; + +&codec_analog { + hpvcc-supply = <®_eldo1>; + status = "okay"; +}; + +&dai { + status = "okay"; }; &ehci0 { @@ -277,6 +303,29 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + status = "okay"; + simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; + simple-audio-card,widgets = "Microphone", "Internal Microphone Left", + "Microphone", "Internal Microphone Right", + "Headphone", "Headphone Jack", + "Speaker", "Internal Speaker"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "Speaker Amp INL", "LINEOUT", + "Speaker Amp INR", "LINEOUT", + "Internal Speaker", "Speaker Amp OUTL", + "Internal Speaker", "Speaker Amp OUTR", + "Headphone Jack", "HP", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "Internal Microphone Left", "MBIAS", + "MIC1", "Internal Microphone Left", + "Internal Microphone Right", "HBIAS", + "MIC2", "Internal Microphone Right"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; -- cgit From 8fbe048bd95b560ed5fcb8eaa80456a64aeb66a2 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Sun, 21 Oct 2018 06:35:26 +0900 Subject: arm64: dts: renesas: r8a77990: Enable I2C DMA This patch enables I2C DMA. NOTE: I2C7 DMA is not supported by R-Car Gen3 Hardware User's Manual Rev.0.80E. Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko Tested-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 3b334be843f4..de25eda4f2f4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -250,6 +250,9 @@ clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -264,6 +267,9 @@ clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -278,6 +284,9 @@ clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -292,6 +301,8 @@ clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -306,6 +317,8 @@ clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -320,6 +333,8 @@ clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -334,6 +349,8 @@ clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; -- cgit From 8f1ee2a166f88388fd3b20698958334be357aa52 Mon Sep 17 00:00:00 2001 From: Yoshihiro Kaneko Date: Mon, 15 Oct 2018 23:12:26 +0900 Subject: arm64: dts: renesas: r8a77990: add thermal device support This patch adds the thermal device node and the thermal-zone for the R8A77990 SoC. Signed-off-by: Yoshihiro Kaneko Tested-by: Simon Horman Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index de25eda4f2f4..b2f606e286ce 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -409,6 +409,18 @@ #power-domain-cells = <1>; }; + thermal: thermal@e6190000 { + compatible = "renesas,thermal-r8a77990"; + reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77990", "renesas,irqc"; #interrupt-cells = <2>; @@ -1745,6 +1757,25 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, -- cgit From 275e4eb3f21a09b6b8bd4a353b9a01e500240385 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:34:31 +0530 Subject: arm64: dts: renesas: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 ++++++++++++--- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 6 +++--- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index e94a5f2dbd08..8643ecb1a3f3 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -3115,7 +3115,10 @@ cooling-maps { map0 { trip = <&sensor1_passive>; - cooling-device = <&a57_0 4 4>; + cooling-device = <&a57_0 4 4>, + <&a57_1 4 4>, + <&a57_2 4 4>, + <&a57_3 4 4>; }; }; }; @@ -3141,7 +3144,10 @@ cooling-maps { map0 { trip = <&sensor2_passive>; - cooling-device = <&a57_0 4 4>; + cooling-device = <&a57_0 4 4>, + <&a57_1 4 4>, + <&a57_2 4 4>, + <&a57_3 4 4>; }; }; }; @@ -3167,7 +3173,10 @@ cooling-maps { map0 { trip = <&sensor3_passive>; - cooling-device = <&a57_0 4 4>; + cooling-device = <&a57_0 4 4>, + <&a57_1 4 4>, + <&a57_2 4 4>, + <&a57_3 4 4>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index e7614b781308..afedbf5728ec 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -2839,7 +2839,7 @@ cooling-maps { map0 { trip = <&sensor1_passive>; - cooling-device = <&a57_0 5 5>; + cooling-device = <&a57_0 5 5>, <&a57_1 5 5>; }; }; }; @@ -2865,7 +2865,7 @@ cooling-maps { map0 { trip = <&sensor2_passive>; - cooling-device = <&a57_0 5 5>; + cooling-device = <&a57_0 5 5>, <&a57_1 5 5>; }; }; }; @@ -2891,7 +2891,7 @@ cooling-maps { map0 { trip = <&sensor3_passive>; - cooling-device = <&a57_0 5 5>; + cooling-device = <&a57_0 5 5>, <&a57_1 5 5>; }; }; }; -- cgit From bdd9868153a780ad1463e1d9c4d43d3bc05c55cb Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sun, 25 Nov 2018 19:14:27 -0200 Subject: ARM: dts: rockchip: add rv1108 eMMC pin settings Add the pin settings for the emmc pins so they can be used across multiple boards. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index ed8f6ca52c5b..3a29ea98e577 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -641,6 +641,27 @@ input-enable; }; + emmc { + emmc_bus8: emmc-bus8 { + rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + }; + + emmc_clk: emmc-clk { + rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>, -- cgit From 7d015bd7bc9b35f2d786ec675b4ff5a5b6281c17 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sun, 25 Nov 2018 19:19:00 -0200 Subject: ARM: dts: rockchip: Add rv1108 GMAC support Add GMAC support for RV1108. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 3a29ea98e577..8413d5ca900b 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -516,6 +516,28 @@ status = "disabled"; }; + gmac: eth@30200000 { + compatible = "rockchip,rv1108-gmac"; + reg = <0x30200000 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru SCLK_MAC>, + <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>, + <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; + clock-names = "stmmaceth", + "mac_clk_rx", "mac_clk_tx", + "clk_mac_ref", "clk_mac_refout", + "aclk_mac", "pclk_mac"; + /* rv1108 only supports an rmii interface */ + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + gic: interrupt-controller@32010000 { compatible = "arm,gic-400"; interrupt-controller; @@ -662,6 +684,21 @@ }; }; + gmac { + rmii_pins: rmii-pins { + rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, + <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, + <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, + <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>, -- cgit From 84ea3a131b6813f7d2b5282e3fe93a4a490cfd25 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sun, 25 Nov 2018 19:19:07 -0200 Subject: ARM: dts: rockchip: Pass the 'clock-latency' property on rv1108 Like it is done on cpu nodes of other Rockchip SoCs, pass the 'clock-latency' property to the CPU node, so that cpufreq driver can take the latency into account when switching frequencies. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 8413d5ca900b..e5f8dcc5fbda 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -32,6 +32,7 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; + clock-latency = <40000>; clocks = <&cru ARMCLK>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <75>; -- cgit From 507bc2f580adf97916e8feba643420660e70baf6 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Sun, 25 Nov 2018 19:19:06 -0200 Subject: ARM: dts: rockchip: Pass the 'arm,cpu-registers-not-fw-configured' property on rv1108 Since firmware does not initialize any of the generic timer CPU registers pass the 'arm,cpu-registers-not-fw-configured' property as suggested in Documentation/devicetree/bindings/timer/arm,arch_timer.txt. This also aligns with other Rockchip SoC dtsi files. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index e5f8dcc5fbda..11ab86d6c4a5 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -74,6 +74,7 @@ compatible = "arm,armv7-timer"; interrupts = , ; + arm,cpu-registers-not-fw-configured; clock-frequency = <24000000>; }; -- cgit From 4b5d90f408f82549b5d02f95e5892a5e1545c4b4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 19 Oct 2018 19:30:17 +0900 Subject: dt-bindings: uniphier: add bindings for UniPhier SoC family Document the list of SoCs and boards of UniPhier platform. Signed-off-by: Masahiro Yamada Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/socionext/uniphier.txt | 47 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/uniphier.txt diff --git a/Documentation/devicetree/bindings/arm/socionext/uniphier.txt b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt new file mode 100644 index 000000000000..b3ed1033740e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt @@ -0,0 +1,47 @@ +Socionext UniPhier SoC family +----------------------------- + +Required properties in the root node: + - compatible: should contain board and SoC compatible strings + +SoC and board compatible strings: + (sorted chronologically) + + - LD4 SoC: "socionext,uniphier-ld4" + - Reference Board: "socionext,uniphier-ld4-ref" + + - Pro4 SoC: "socionext,uniphier-pro4" + - Reference Board: "socionext,uniphier-pro4-ref" + - Ace Board: "socionext,uniphier-pro4-ace" + - Sanji Board: "socionext,uniphier-pro4-sanji" + + - sLD8 SoC: "socionext,uniphier-sld8" + - Reference Board: "socionext,uniphier-sld8-ref" + + - PXs2 SoC: "socionext,uniphier-pxs2" + - Gentil Board: "socionext,uniphier-pxs2-gentil" + - Vodka Board: "socionext,uniphier-pxs2-vodka" + + - LD6b SoC: "socionext,uniphier-ld6b" + - Reference Board: "socionext,uniphier-ld6b-ref" + + - LD11 SoC: "socionext,uniphier-ld11" + - Reference Board: "socionext,uniphier-ld11-ref" + - Global Board: "socionext,uniphier-ld11-global" + + - LD20 SoC: "socionext,uniphier-ld20" + - Reference Board: "socionext,uniphier-ld20-ref" + - Global Board: "socionext,uniphier-ld20-global" + + - PXs3 SoC: "socionext,uniphier-pxs3" + - Reference Board: "socionext,uniphier-pxs3-ref" + +Example: + +/dts-v1/; + +/ { + compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20"; + + ... +}; diff --git a/MAINTAINERS b/MAINTAINERS index f4855974f325..1ed6eafdf1df 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2247,6 +2247,7 @@ M: Masahiro Yamada L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git S: Maintained +F: Documentation/devicetree/bindings/arm/socionext/uniphier.txt F: Documentation/devicetree/bindings/gpio/gpio-uniphier.txt F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt F: arch/arm/boot/dts/uniphier* -- cgit From 1c36155a802b6192f3ad532da76a12ad7e2b8158 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 19 Oct 2018 19:30:18 +0900 Subject: dt-bindings: uniphier: move cache-uniphier.txt to vendor directory Now, the Socionext vendor directory is available at Documentation/devicetree/bindings/arm/socionext/ Move cache-uniphier.txt over to it. Signed-off-by: Masahiro Yamada Reviewed-by: Rob Herring --- .../bindings/arm/socionext/cache-uniphier.txt | 60 ++++++++++++++++++++++ .../bindings/arm/uniphier/cache-uniphier.txt | 60 ---------------------- 2 files changed, 60 insertions(+), 60 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt delete mode 100644 Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt diff --git a/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt new file mode 100644 index 000000000000..d27a646f48a9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt @@ -0,0 +1,60 @@ +UniPhier outer cache controller + +UniPhier SoCs are integrated with a full-custom outer cache controller system. +All of them have a level 2 cache controller, and some have a level 3 cache +controller as well. + +Required properties: +- compatible: should be "socionext,uniphier-system-cache" +- reg: offsets and lengths of the register sets for the device. It should + contain 3 regions: control register, revision register, operation register, + in this order. +- cache-unified: specifies the cache is a unified cache. +- cache-size: specifies the size in bytes of the cache +- cache-sets: specifies the number of associativity sets of the cache +- cache-line-size: specifies the line size in bytes +- cache-level: specifies the level in the cache hierarchy. The value should + be 2 for L2 cache, 3 for L3 cache, etc. + +Optional properties: +- next-level-cache: phandle to the next level cache if present. The next level + cache should be also compatible with "socionext,uniphier-system-cache". + +The L2 cache must exist to use the L3 cache; the cache hierarchy must be +indicated correctly with "next-level-cache" properties. + +Example 1 (system with L2): + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + cache-unified; + cache-size = <0x80000>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + +Example 2 (system with L2 and L3): + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, + <0x506c0000 0x400>; + cache-unified; + cache-size = <0x200000>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + l3: l3-cache@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, + <0x506c8000 0x400>; + cache-unified; + cache-size = <0x400000>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; diff --git a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt deleted file mode 100644 index d27a646f48a9..000000000000 --- a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt +++ /dev/null @@ -1,60 +0,0 @@ -UniPhier outer cache controller - -UniPhier SoCs are integrated with a full-custom outer cache controller system. -All of them have a level 2 cache controller, and some have a level 3 cache -controller as well. - -Required properties: -- compatible: should be "socionext,uniphier-system-cache" -- reg: offsets and lengths of the register sets for the device. It should - contain 3 regions: control register, revision register, operation register, - in this order. -- cache-unified: specifies the cache is a unified cache. -- cache-size: specifies the size in bytes of the cache -- cache-sets: specifies the number of associativity sets of the cache -- cache-line-size: specifies the line size in bytes -- cache-level: specifies the level in the cache hierarchy. The value should - be 2 for L2 cache, 3 for L3 cache, etc. - -Optional properties: -- next-level-cache: phandle to the next level cache if present. The next level - cache should be also compatible with "socionext,uniphier-system-cache". - -The L2 cache must exist to use the L3 cache; the cache hierarchy must be -indicated correctly with "next-level-cache" properties. - -Example 1 (system with L2): - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - cache-unified; - cache-size = <0x80000>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - -Example 2 (system with L2 and L3): - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, - <0x506c0000 0x400>; - cache-unified; - cache-size = <0x200000>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, - <0x506c8000 0x400>; - cache-unified; - cache-size = <0x400000>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; -- cgit From aec2c81291b85939d9e885fb1f5e3368a77a1a93 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:31:15 +0530 Subject: ARM: dts: uniphier: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-pxs2.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 8d20e9548e39..06a049f6edf8 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -141,8 +141,10 @@ cooling-maps { map { trip = <&cpu_alert>; - cooling-device = <&cpu0 - THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; -- cgit From c955b7aec510145129ca7aaea6ecbf6d748f5ebf Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 26 Nov 2018 15:35:03 -0200 Subject: ARM: dts: rockchip: Fix the PMU interrupt number for rv1108 According to the Rockchip vendor tree the PMU interrupt number is 76, so fix it accordingly. Signed-off-by: Otavio Salvador Tested-by: Fabio Berton Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 11ab86d6c4a5..611f2fe8e56c 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -67,7 +67,7 @@ arm-pmu { compatible = "arm,cortex-a7-pmu"; - interrupts = ; + interrupts = ; }; timer { -- cgit From efc2e0bd9594060915696a418564aefd0270b1d6 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 26 Nov 2018 15:35:04 -0200 Subject: ARM: dts: rockchip: Assign the proper GPIO clocks for rv1108 It is not correct to assign the 24MHz clock oscillator to the GPIO ports. Fix it by assigning the proper GPIO clocks instead. Signed-off-by: Otavio Salvador Tested-by: Fabio Berton Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 611f2fe8e56c..300de8e1475b 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -565,7 +565,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x20030000 0x100>; interrupts = ; - clocks = <&xin24m>; + clocks = <&cru PCLK_GPIO0_PMU>; gpio-controller; #gpio-cells = <2>; @@ -578,7 +578,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x10310000 0x100>; interrupts = ; - clocks = <&xin24m>; + clocks = <&cru PCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -591,7 +591,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x10320000 0x100>; interrupts = ; - clocks = <&xin24m>; + clocks = <&cru PCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; @@ -604,7 +604,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x10330000 0x100>; interrupts = ; - clocks = <&xin24m>; + clocks = <&cru PCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; -- cgit From 7d2cecb0849fbb4cb27bfa3828a5a52c57a50748 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 26 Nov 2018 15:35:05 -0200 Subject: ARM: dts: rockchip: Add UART DMA support for rv1108 Pass the 'dmas' property to the UART ports so that DMA can be supported. Signed-off-by: Otavio Salvador Tested-by: Fabio Berton Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 300de8e1475b..17dbcf2571fd 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -119,6 +119,8 @@ clock-frequency = <24000000>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; + dmas = <&pdma 6>, <&pdma 7>; + #dma-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&uart2m0_xfer>; status = "disabled"; @@ -133,6 +135,8 @@ clock-frequency = <24000000>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; + dmas = <&pdma 4>, <&pdma 5>; + #dma-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&uart1_xfer>; status = "disabled"; @@ -147,6 +151,8 @@ clock-frequency = <24000000>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; + dmas = <&pdma 2>, <&pdma 3>; + #dma-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; status = "disabled"; -- cgit From c56689e6f2fbbb92d853e1251819f9b5731d7389 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 26 Nov 2018 13:59:46 +0800 Subject: arm64: dts: allwinner: a64: bananapi-m64: Enable audio codec This patch enables audio via the SoC's internal audio codec. All relevant device nodes are enabled, and the routing is set to match the board design. MIC1 is routed to an onboard microphone, with MBIAS providing power. MIC2 and HP are routed to the 3.5mm headset TRRS jack. No phantom power is provided to the headset microphone. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index ef1c90401bb2..83e30e0afe5b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -97,6 +97,19 @@ }; }; +&codec { + status = "okay"; +}; + +&codec_analog { + hpvcc-supply = <®_eldo1>; + status = "okay"; +}; + +&dai { + status = "okay"; +}; + &de { status = "okay"; }; @@ -326,6 +339,22 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + status = "okay"; + simple-audio-card,widgets = "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack", + "Microphone", "Onboard Microphone"; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right", + "AIF1 Slot 0 Left ADC", "Left ADC", + "AIF1 Slot 0 Right ADC", "Right ADC", + "Headphone Jack", "HP", + "MIC2", "Microphone Jack", + "Onboard Microphone", "MBIAS", + "MIC1", "Onboard Microphone"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; -- cgit From 01f965ce9e5d1c865ed1a5e0a484a3246f51502d Mon Sep 17 00:00:00 2001 From: Olliver Schinagl Date: Mon, 26 Nov 2018 17:27:51 +0200 Subject: ARM: dts: sun7i: set proper lradc vref on OLinuXino Lime2 The lradc's analog reference voltage is set to 3.0 volt in the hardware. This is more or less set in copper for at least lradc0. Set the property in the dts to ensure the lradc is referenced properly. Signed-off-by: Olliver Schinagl Signed-off-by: Priit Laes Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index b828677f331d..fbdb6faffcd4 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -154,6 +154,10 @@ }; }; +&lradc { + vref-supply = <®_vcc3v0>; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>; -- cgit From 812b3dc37574ee45ee986fa4f7130b280d7610e9 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 5 Sep 2018 15:48:33 +0200 Subject: ARM: dts: rockchip: add #sound-dai-cells to Cortex-A9 i2s The Rockchip i2s always just requires a sound-dail-cells value of 0, so add them to the core soc dtsi for convenience. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 3 +++ arch/arm/boot/dts/rk3188.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 112d2bf8e998..30dc8af0bdcb 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -71,6 +71,7 @@ clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; rockchip,playback-channels = <8>; rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -88,6 +89,7 @@ clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -105,6 +107,7 @@ clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 7e0dc52630d9..fd896b0a46e3 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -139,6 +139,7 @@ clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; status = "disabled"; }; -- cgit From abcee7a86373144249adec203cbaa98770101ce8 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 10 Oct 2018 11:46:48 +0200 Subject: ARM: dts: rockchip: convert rk3188 to opp-v2 The fact that OPPs specified only on cpu0 work is Linux specific and normally cpu frequencies should be specified for each cpu core. To facilitate this without needing to duplicate the frequency table each time, convert to opp-v2 before adding references to all cores. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188.dtsi | 55 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 44 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index fd896b0a46e3..9d8c4c560e51 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -23,37 +23,70 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; - operating-points = < - /* kHz uV */ - 1608000 1350000 - 1416000 1250000 - 1200000 1150000 - 1008000 1075000 - 816000 975000 - 600000 950000 - 504000 925000 - 312000 875000 - >; clock-latency = <40000>; clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x1>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x3>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <875000>; + clock-latency-ns = <40000>; + }; + opp-504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <925000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000>; + opp-suspend; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <975000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1075000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1150000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1250000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1350000>; }; }; -- cgit From 0222aac4486e7bf5b37defa7fd03e3b2c52fe2be Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 7 Nov 2018 17:12:24 +0100 Subject: ARM: dts: rockchip: add cpu-core resets for rk3188 Specify the reset handles for each cpu core. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 9d8c4c560e51..f1f7a36b46d4 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -26,6 +26,7 @@ clock-latency = <40000>; clocks = <&cru ARMCLK>; operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE0>; }; cpu@1 { device_type = "cpu"; @@ -33,6 +34,7 @@ next-level-cache = <&L2>; reg = <0x1>; operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE1>; }; cpu@2 { device_type = "cpu"; @@ -40,6 +42,7 @@ next-level-cache = <&L2>; reg = <0x2>; operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE2>; }; cpu@3 { device_type = "cpu"; @@ -47,6 +50,7 @@ next-level-cache = <&L2>; reg = <0x3>; operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE3>; }; }; -- cgit From 66dc478a283ca32a9d9c40a53e97fad4d408757c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 15 Oct 2018 14:46:19 +0200 Subject: ARM: dts: rockchip: add phandles to secondary cpu cores Add phandles to secondary cpu cores as we may need to reference these down the road as well. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index f1f7a36b46d4..4acb501dd3f8 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -28,7 +28,7 @@ operating-points-v2 = <&cpu0_opp_table>; resets = <&cru SRST_CORE0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; @@ -36,7 +36,7 @@ operating-points-v2 = <&cpu0_opp_table>; resets = <&cru SRST_CORE1>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; @@ -44,7 +44,7 @@ operating-points-v2 = <&cpu0_opp_table>; resets = <&cru SRST_CORE2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; -- cgit From 584f8ca10c1489be32637e1de1f78c222b569bbd Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 12 Nov 2018 13:27:25 +0100 Subject: ARM: dts: rockchip: update cpu supplies on rk3188 cpu0-supply in cpu0 is deprecated, instead each cpu-core is supposed to list its supply separately. With the added cpu core phandles, update existing rk3188 boards accordingly. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3188-px3-evb.dts | 14 +++++++++++++- arch/arm/boot/dts/rk3188-radxarock.dts | 14 +++++++++++++- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts index 375129b62102..9ae65c767c90 100644 --- a/arch/arm/boot/dts/rk3188-px3-evb.dts +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -44,7 +44,19 @@ }; &cpu0 { - cpu0-supply = <&vdd_cpu>; + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; }; &emmc { diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 4a2890618f6f..94bc81c24049 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -138,7 +138,19 @@ }; &cpu0 { - cpu0-supply = <&vdd_arm>; + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; }; &gpu { -- cgit From f89120b6f554901075bb1636cfc1d14d26adaaa3 Mon Sep 17 00:00:00 2001 From: Mylène Josserand Date: Mon, 18 Sep 2017 10:55:28 +0200 Subject: ARM: dts: sun8i: Add the H3/H5 CSI controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The H3 and H5 features the same CSI controller that was initially found on the A31. Add a DT node for it. Signed-off-by: Mylène Josserand Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 4b1530ebe427..0d9e9eac518c 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -393,6 +393,13 @@ interrupt-controller; #interrupt-cells = <3>; + csi_pins: csi { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", + "PE6", "PE7", "PE8", "PE9", "PE10", + "PE11"; + function = "csi"; + }; + emac_rgmii_pins: emac0 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD7", "PD8", "PD9", "PD10", @@ -744,6 +751,21 @@ interrupts = ; }; + csi: camera@1cb0000 { + compatible = "allwinner,sun8i-h3-csi", + "allwinner,sun6i-a31-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_pins>; + status = "disabled"; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun8i-h3-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"; -- cgit From 34e8b809bf136c0554ba1131c6671ae6339543e0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 23 Nov 2018 13:18:37 +0100 Subject: dt-bindings: thermal: tegra-bpmp: Add Tegra194 support The thermal controller implementation on Tegra194 is very similar to the implementation on Tegra186. Add a compatible string for the new generation. Signed-off-by: Thierry Reding --- .../bindings/thermal/nvidia,tegra186-bpmp-thermal.txt | 3 ++- include/dt-bindings/thermal/tegra194-bpmp-thermal.h | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/thermal/tegra194-bpmp-thermal.h diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt index 276387dd6815..e17c07be270b 100644 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt @@ -15,7 +15,8 @@ Required properties: - compatible: Array of strings. One of: - - "nvidia,tegra186-bpmp-thermal". + - "nvidia,tegra186-bpmp-thermal" + - "nvidia,tegra194-bpmp-thermal" - #thermal-sensor-cells: Cell for sensor index. Single-cell integer. Must be <1>. diff --git a/include/dt-bindings/thermal/tegra194-bpmp-thermal.h b/include/dt-bindings/thermal/tegra194-bpmp-thermal.h new file mode 100644 index 000000000000..aa7fb08135ca --- /dev/null +++ b/include/dt-bindings/thermal/tegra194-bpmp-thermal.h @@ -0,0 +1,15 @@ +/* + * This header provides constants for binding nvidia,tegra194-bpmp-thermal. + */ + +#ifndef _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H +#define _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H + +#define TEGRA194_BPMP_THERMAL_ZONE_CPU 2 +#define TEGRA194_BPMP_THERMAL_ZONE_GPU 3 +#define TEGRA194_BPMP_THERMAL_ZONE_AUX 4 +#define TEGRA194_BPMP_THERMAL_ZONE_PLLX 5 +#define TEGRA194_BPMP_THERMAL_ZONE_AO 6 +#define TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX 7 + +#endif -- cgit From c9b543404c5e1fd51a7ac375294519be5064bf80 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 7 Sep 2018 15:59:30 +0200 Subject: ARM: dts: sun4i: Fix gpio-keys warning Fix the 'unnecessary #address-cells/#size-cells without "ranges" or child "reg" property' DTC warning for the gpio-keys DT node on A10 boards. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 2 -- arch/arm/boot/dts/sun4i-a10-pcduino.dts | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts index 221acd10f6c8..2f0d966f39ad 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts @@ -63,8 +63,6 @@ compatible = "gpio-keys-polled"; pinctrl-names = "default"; pinctrl-0 = <&key_pins_inet9f>; - #address-cells = <1>; - #size-cells = <0>; poll-interval = <20>; left-joystick-left { diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index b97a0f2f20b9..d82a604f3d9c 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -76,8 +76,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; back { label = "Key Back"; -- cgit From 123b796d3fac60d69a3737d81901ab483c4efd6e Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 7 Sep 2018 16:00:22 +0200 Subject: ARM: dts: sun4i: Fix HDMI output DTC warning Our HDMI output endpoint on the A10 DTSI has a warning under DTC: "graph node has single child node 'endpoint', #address-cells/#size-cells are not necessary". Fix this by removing those properties. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun4i-a10.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 3d62a8950720..5d46bb0139fa 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -530,8 +530,6 @@ }; hdmi_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; }; }; -- cgit From d0a595255312ca7a2df51761c1e064255774de87 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 7 Sep 2018 16:05:18 +0200 Subject: ARM: dts: sun5i: Change framebuffer node names to avoid warnings The simple-framebuffer nodes have a unit address, but no reg property which generates a warning when compiling it with DTC. Change the simple-framebuffer node names so that there is no warnings on this anymore. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +- arch/arm/boot/dts/sun5i.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 316cb8b2945b..7f76250f4228 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -60,7 +60,7 @@ #size-cells = <1>; ranges; - framebuffer@2 { + framebuffer-lcd0-hdmi { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 9cd65c46720b..14a7d1cf89b4 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -68,7 +68,7 @@ #size-cells = <1>; ranges; - framebuffer@0 { + framebuffer-lcd0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; @@ -77,7 +77,7 @@ status = "disabled"; }; - framebuffer@1 { + framebuffer-lcd0-tve0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; -- cgit From a2ff5fe12acc22faf2ce22ac744efecf4bd36579 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 7 Sep 2018 16:34:40 +0200 Subject: ARM: dts: sun5i: Change clock node names to avoid warnings Our oscillators clock names have a unit address, but no reg property, which generates a warning in DTC. Change these names to remove those unit addresses. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 14a7d1cf89b4..362e6583fa65 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -93,14 +93,14 @@ #size-cells = <1>; ranges; - osc24M: clk@1c20050 { + osc24M: clk-24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; - osc32k: clk@0 { + osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; -- cgit From 3fb5ff698d53a7f37a4ff281f1bd284c7d6a8835 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 7 Sep 2018 16:41:42 +0200 Subject: ARM: dts: sun5i: Remove skeleton to avoid warnings Using skeleton.dtsi will create a memory node that will generate a warning in DTC. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 -- arch/arm/boot/dts/sun5i-a13.dtsi | 2 -- arch/arm/boot/dts/sun5i.dtsi | 4 ++-- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 7f76250f4228..0c0c5e08520f 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -42,8 +42,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" - #include "sun5i.dtsi" #include diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index b1d827765530..a75ca4504a75 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -42,8 +42,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" - #include "sun5i.dtsi" #include diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 362e6583fa65..b01047f1ec5b 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -42,14 +42,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" - #include #include #include / { interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; cpus { #address-cells = <1>; -- cgit From d6b7baed20023b25d9bfa4a05d388a1bbd2df5ea Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 7 Sep 2018 16:42:42 +0200 Subject: ARM: dts: sun5i: Remove SoC node unit-name to avoid warnings Our main node for all the in-SoC controllers used to have a unit name. The unit-name, in addition to being actually false, would not match any reg property, which generates a warning. Remove it in order to remove those warnings. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +- arch/arm/boot/dts/sun5i-a13.dtsi | 2 +- arch/arm/boot/dts/sun5i-gr8.dtsi | 2 +- arch/arm/boot/dts/sun5i.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 0c0c5e08520f..a2d0ceacf00e 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -74,7 +74,7 @@ allwinner,pipelines = <&fe0>; }; - soc@1c00000 { + soc { hdmi: hdmi@1c16000 { compatible = "allwinner,sun5i-a10s-hdmi"; reg = <0x01c16000 0x1000>; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index a75ca4504a75..ee99f6f23f17 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -86,7 +86,7 @@ allwinner,pipelines = <&fe0>; }; - soc@1c00000 { + soc { pwm: pwm@1c20e00 { compatible = "allwinner,sun5i-a13-pwm"; reg = <0x01c20e00 0xc>; diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi index ef0b7446a99d..d3eea4cfe442 100644 --- a/arch/arm/boot/dts/sun5i-gr8.dtsi +++ b/arch/arm/boot/dts/sun5i-gr8.dtsi @@ -54,7 +54,7 @@ allwinner,pipelines = <&fe0>; }; - soc@1c00000 { + soc { pwm: pwm@1c20e00 { compatible = "allwinner,sun5i-a10s-pwm"; reg = <0x01c20e00 0xc>; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index b01047f1ec5b..5085b658d216 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -123,7 +123,7 @@ }; }; - soc@1c00000 { + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit From 39bfc2311ca24728357b551708f4d8b950fa4e05 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 7 Sep 2018 16:43:04 +0200 Subject: ARM: dts: sun5i: Remove redundant interrupt-controller The interrupt-parent property is set in sun5i.dtsi, so there's no need to repeat it. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 -- arch/arm/boot/dts/sun5i-a13.dtsi | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index a2d0ceacf00e..195a6a1d2c49 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -47,8 +47,6 @@ #include / { - interrupt-parent = <&intc>; - aliases { ethernet0 = &emac; }; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index ee99f6f23f17..ae04955fd9a3 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -47,8 +47,6 @@ #include / { - interrupt-parent = <&intc>; - thermal-zones { cpu_thermal { /* milliseconds */ -- cgit From 7d94610e1612d9d0249425542c2675b68f6f9b36 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 7 Sep 2018 16:48:33 +0200 Subject: ARM: dts: sun5i: Change LRADC node names to avoid warnings One of the usage of the LRADC is to implement buttons. The bindings define that we should have one subnode per button, with their associated voltage as a property. However, there was no reg property but we still used the voltage associated to the button as the unit-address, which eventually generated warnings in DTC. Rename the node names to avoid those warnings. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 10 +++++----- arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 4 ++-- arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 4 ++-- arch/arm/boot/dts/sun5i-a13-licheepi-one.dts | 2 +- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 10 +++++----- arch/arm/boot/dts/sun5i-gr8-evb.dts | 14 +++++++------- 6 files changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 2c902ed2c87a..243319e98cf7 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -152,35 +152,35 @@ vref-supply = <®_vcc3v0>; status = "okay"; - button@191 { + button-191 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <191274>; }; - button@392 { + button-392 { label = "Volume Down"; linux,code = ; channel = <0>; voltage = <392644>; }; - button@601 { + button-601 { label = "Menu"; linux,code = ; channel = <0>; voltage = <601151>; }; - button@795 { + button-795 { label = "Enter"; linux,code = ; channel = <0>; voltage = <795090>; }; - button@987 { + button-987 { label = "Home"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts index 378214d8316e..30a86cadf5a5 100644 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts @@ -105,14 +105,14 @@ vref-supply = <®_ldo2>; status = "okay"; - button@200 { + button-200 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <200000>; }; - button@400 { + button-400 { label = "Volume Down"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts index 7ee0c3f6d7a1..24ac6f167426 100644 --- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -100,14 +100,14 @@ vref-supply = <®_ldo2>; status = "okay"; - button@200 { + button-200 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <200000>; }; - button@400 { + button-400 { label = "Volume Down"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts index bc883893f4a4..93a080e7ba2d 100644 --- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts +++ b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts @@ -124,7 +124,7 @@ vref-supply = <®_ldo2>; status = "okay"; - button@984 { + button-984 { label = "Home"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 437ad913a373..49dcef1090d2 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -153,35 +153,35 @@ vref-supply = <®_vcc3v0>; status = "okay"; - button@191 { + button-191 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <191274>; }; - button@392 { + button-392 { label = "Volume Down"; linux,code = ; channel = <0>; voltage = <392644>; }; - button@601 { + button-601 { label = "Menu"; linux,code = ; channel = <0>; voltage = <601151>; }; - button@795 { + button-795 { label = "Enter"; linux,code = ; channel = <0>; voltage = <795090>; }; - button@987 { + button-987 { label = "Home"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts index 5f0adc0f7bb4..e914915e73d7 100644 --- a/arch/arm/boot/dts/sun5i-gr8-evb.dts +++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts @@ -181,49 +181,49 @@ vref-supply = <®_ldo2>; status = "okay"; - button@190 { + button-190 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <190000>; }; - button@390 { + button-390 { label = "Volume Down"; linux,code = ; channel = <0>; voltage = <390000>; }; - button@600 { + button-600 { label = "Menu"; linux,code = ; channel = <0>; voltage = <600000>; }; - button@800 { + button-800 { label = "Search"; linux,code = ; channel = <0>; voltage = <800000>; }; - button@980 { + button-980 { label = "Home"; linux,code = ; channel = <0>; voltage = <980000>; }; - button@1180 { + button-1180 { label = "Esc"; linux,code = ; channel = <0>; voltage = <1180000>; }; - button@1400 { + button-1400 { label = "Enter"; linux,code = ; channel = <0>; -- cgit From f606c4b3b7e942a975db0e3d835dd245473e6dbd Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 11:14:15 +0100 Subject: ARM: dts: sun5i: Remove all useless pinctrl nodes The gpio pinctrl nodes are redundant and as such useless most of the times. Since they will also generate warnings in DTC, we can simply remove most of them. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 7 ------ arch/arm/boot/dts/sun5i-a10s-mk802.dts | 13 ----------- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 6 ----- arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 6 ----- arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 14 ----------- arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 7 +----- arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 12 ---------- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 6 ----- arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 8 ------- arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 16 ------------- arch/arm/boot/dts/sun5i-gr8-evb.dts | 27 +--------------------- arch/arm/boot/dts/sun5i-r8-chip.dts | 19 --------------- .../boot/dts/sun5i-reference-design-tablet.dtsi | 21 ----------------- 13 files changed, 2 insertions(+), 160 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts index 8d4fb9331212..f103e174cd98 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts @@ -71,8 +71,6 @@ reg_vmmc1: vmmc1 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_vcc_en_pin_t004>; regulator-name = "vmmc1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -139,11 +137,6 @@ bias-pull-up; }; - mmc1_vcc_en_pin_t004: mmc1_vcc_en_pin@0 { - pins = "PB18"; - function = "gpio_out"; - }; - led_pins_t004: led_pins@0 { pins = "PB2"; function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts index dd7fd5c3d76f..b17c036293d6 100644 --- a/arch/arm/boot/dts/sun5i-a10s-mk802.dts +++ b/arch/arm/boot/dts/sun5i-a10s-mk802.dts @@ -59,8 +59,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_mk802>; red { label = "mk802:red:usr"; @@ -114,25 +112,14 @@ }; &pio { - led_pins_mk802: led_pins@0 { - pins = "PB2"; - function = "gpio_out"; - }; - mmc0_cd_pin_mk802: mmc0_cd_pin@0 { pins = "PG1"; function = "gpio_in"; bias-pull-up; }; - - usb1_vbus_pin_mk802: usb1_vbus_pin@0 { - pins = "PB10"; - function = "gpio_out"; - }; }; ®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_mk802>; gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 243319e98cf7..3ffae227bab3 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -241,11 +241,6 @@ drive-strength = <20>; }; - usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 { - pins = "PB10"; - function = "gpio_out"; - }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { pins = "PG12"; function = "gpio_in"; @@ -259,7 +254,6 @@ }; ®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>; gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts index 034853d1c08f..1e713a42e34f 100644 --- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts +++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts @@ -109,15 +109,9 @@ function = "gpio_out"; drive-strength = <20>; }; - - usb1_vbus_pin_r7: usb1_vbus_pin@0 { - pins = "PG13"; - function = "gpio_out"; - }; }; ®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_r7>; gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts index 3f68ef5d92a0..d8bff29f1049 100644 --- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts +++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts @@ -61,8 +61,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_wobo_i5>; blue { label = "a10s-wobo-i5:blue:usr"; @@ -73,8 +71,6 @@ reg_emac_3v3: emac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&emac_power_pin_wobo>; regulator-name = "emac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -143,21 +139,11 @@ }; &pio { - led_pins_wobo_i5: led_pins@0 { - pins = "PB2"; - function = "gpio_out"; - }; - mmc0_cd_pin_wobo_i5: mmc0_cd_pin@0 { pins = "PB3"; function = "gpio_in"; bias-pull-up; }; - - emac_power_pin_wobo: emac_power_pin@0 { - pins = "PA02"; - function = "gpio_out"; - }; }; ®_dcdc2 { diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts index 24ac6f167426..f6211c22e4dc 100644 --- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -144,11 +144,6 @@ function = "gpio_in"; bias-pull-up; }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - pins = "PG1"; - function = "gpio_in"; - }; }; #include "axp209.dtsi" @@ -202,7 +197,7 @@ &usbphy { pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + pinctrl-0 = <&usb0_id_detect_pin>; usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus-supply = <®_usb0_vbus>; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index aa4b34fd9126..0e107ff5cff0 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -135,26 +135,14 @@ function = "gpio_in"; bias-pull-down; }; - - usb0_vbus_pin_olinuxinom: usb0_vbus_pin@0 { - pins = "PG12"; - function = "gpio_out"; - }; - - usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 { - pins = "PG11"; - function = "gpio_out"; - }; }; ®_usb0_vbus { - pinctrl-0 = <&usb0_vbus_pin_olinuxinom>; gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; status = "okay"; }; ®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_olinuxinom>; gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 49dcef1090d2..d963cac2a04d 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -230,11 +230,6 @@ function = "gpio_in"; bias-pull-down; }; - - usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 { - pins = "PG11"; - function = "gpio_out"; - }; }; ®_usb0_vbus { @@ -243,7 +238,6 @@ }; ®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_olinuxino>; gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts index bfdd38d6bfcc..962ec29b1934 100644 --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts @@ -79,10 +79,6 @@ allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */ }; -&codec_pa_pin { - pins = "PG3"; -}; - &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_a>; @@ -128,7 +124,3 @@ /* The P66 uses the uart pins as gpios */ status = "disabled"; }; - -&usb0_vbus_pin_a { - pins = "PB4"; -}; diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts index c55b11a4d3c7..959dd94c7b79 100644 --- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts +++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts @@ -79,8 +79,6 @@ mmc0_pwrseq: mmc0_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_reg_on_pin_chip_pro>; reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ }; }; @@ -157,18 +155,6 @@ status = "okay"; }; -&pio { - usb0_id_pin_chip_pro: usb0-id-pin@0 { - pins = "PG2"; - function = "gpio_in"; - }; - - wifi_reg_on_pin_chip_pro: wifi-reg-on-pin@0 { - pins = "PB10"; - function = "gpio_out"; - }; -}; - &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>; @@ -253,8 +239,6 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pin_chip_pro>; usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_power-supply = <&usb_power_supply>; usb1_vbus-supply = <®_vcc5v0>; diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts index e914915e73d7..5196aeff75aa 100644 --- a/arch/arm/boot/dts/sun5i-gr8-evb.dts +++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts @@ -233,7 +233,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gr8_evb>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ @@ -256,28 +256,6 @@ status = "okay"; }; -&pio { - mmc0_cd_pin_gr8_evb: mmc0-cd-pin@0 { - pins = "PG0"; - function = "gpio_in"; - }; - - usb0_id_pin_gr8_evb: usb0-id-pin@0 { - pins = "PG2"; - function = "gpio_in"; - }; - - usb0_vbus_det_pin_gr8_evb: usb0-vbus-det-pin@0 { - pins = "PG1"; - function = "gpio_in"; - }; - - usb1_vbus_pin_gr8_evb: usb1-vbus-pin@0 { - pins = "PG13"; - function = "gpio_out"; - }; -}; - &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_pins>; @@ -310,7 +288,6 @@ }; ®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_gr8_evb>; gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -356,8 +333,6 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pin_gr8_evb>, <&usb0_vbus_det_pin_gr8_evb>; usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ usb0_vbus_power-supply = <&usb_power_supply>; diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index 879a4b0f3bd5..c97e46e4bb45 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -79,8 +79,6 @@ mmc0_pwrseq: mmc0_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&chip_wifi_reg_on_pin>; reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */ }; @@ -184,20 +182,6 @@ }; &pio { - chip_vbus_pin: chip_vbus_pin@0 { - pins = "PB10"; - function = "gpio_out"; - }; - - chip_wifi_reg_on_pin: chip_wifi_reg_on_pin@0 { - pins = "PC19"; - function = "gpio_out"; - }; - - chip_id_det_pin: chip_id_det_pin@0 { - pins = "PG2"; - function = "gpio_in"; - }; chip_w1_pin: chip_w1_pin@0 { pins = "PD2"; @@ -260,7 +244,6 @@ }; ®_usb0_vbus { - pinctrl-0 = <&chip_vbus_pin>; vin-supply = <®_vcc5v0>; gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ status = "okay"; @@ -303,8 +286,6 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&chip_id_det_pin>; status = "okay"; usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index d2a2eb8b3f26..eafb362e3993 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -63,8 +63,6 @@ }; &codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */ status = "okay"; }; @@ -96,8 +94,6 @@ reg = <0x40>; interrupt-parent = <&pio>; interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */ - pinctrl-names = "default"; - pinctrl-0 = <&ts_power_pin>; power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ /* Tablet dts must provide reg and compatible */ status = "disabled"; @@ -137,24 +133,12 @@ }; &pio { - codec_pa_pin: codec_pa_pin@0 { - pins = "PG10"; - function = "gpio_out"; - }; - mmc0_cd_pin: mmc0_cd_pin@0 { pins = "PG0"; function = "gpio_in"; bias-pull-up; }; - ts_power_pin: ts_power_pin { - pins = "PB3"; - function = "gpio_out"; - drive-strength = <10>; - bias-disable; - }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { pins = "PG1"; function = "gpio_in"; @@ -166,11 +150,6 @@ function = "gpio_in"; bias-pull-up; }; - - usb0_vbus_pin_a: usb0_vbus_pin@0 { - pins = "PG12"; - function = "gpio_out"; - }; }; ®_dcdc2 { -- cgit From 79badc748b44ca0fa5ba51e11a4366953d624218 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 21:03:20 +0100 Subject: ARM: dts: sun5i: Remove card detect pull-up Boards usually have an external pull-up on the card-detect signal, so there's no need to add another one. This also removes a DTC warning. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 8 +------- arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 8 +------- arch/arm/boot/dts/sun5i-a10s-mk802.dts | 10 +--------- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 16 ++-------------- arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 8 +------- arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 10 +--------- arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 8 +------- arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 8 +------- arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 8 +------- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 8 +------- arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi | 8 +------- 11 files changed, 12 insertions(+), 88 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts index 39504d720efc..9e076e748b78 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts @@ -90,7 +90,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t003>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -106,12 +106,6 @@ }; &pio { - mmc0_cd_pin_t003: mmc0_cd_pin@0 { - pins = "PG1"; - function = "gpio_in"; - bias-pull-up; - }; - led_pins_t003: led_pins@0 { pins = "PB2"; function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts index f103e174cd98..4dd98cbd1ddb 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts @@ -99,7 +99,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -131,12 +131,6 @@ bias-pull-up; }; - mmc0_cd_pin_t004: mmc0_cd_pin@0 { - pins = "PG1"; - function = "gpio_in"; - bias-pull-up; - }; - led_pins_t004: led_pins@0 { pins = "PB2"; function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts index b17c036293d6..822f1b2ac6d3 100644 --- a/arch/arm/boot/dts/sun5i-a10s-mk802.dts +++ b/arch/arm/boot/dts/sun5i-a10s-mk802.dts @@ -87,7 +87,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -111,14 +111,6 @@ status = "okay"; }; -&pio { - mmc0_cd_pin_mk802: mmc0_cd_pin@0 { - pins = "PG1"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_usb1_vbus { gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ status = "okay"; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 3ffae227bab3..15889639a841 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -198,7 +198,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -207,7 +207,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; + pinctrl-0 = <&mmc1_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */ @@ -223,18 +223,6 @@ }; &pio { - mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 { - pins = "PG1"; - function = "gpio_in"; - bias-pull-up; - }; - - mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 { - pins = "PG13"; - function = "gpio_in"; - bias-pull-up; - }; - led_pins_olinuxino: led_pins@0 { pins = "PE3"; function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts index 1e713a42e34f..ba2d2e604d54 100644 --- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts +++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts @@ -77,7 +77,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -98,12 +98,6 @@ }; &pio { - mmc0_cd_pin_r7: mmc0_cd_pin@0 { - pins = "PG1"; - function = "gpio_in"; - bias-pull-up; - }; - led_pins_r7: led_pins@0 { pins = "PB2"; function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts index d8bff29f1049..69581f8c4e8f 100644 --- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts +++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts @@ -123,7 +123,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */ @@ -138,14 +138,6 @@ status = "okay"; }; -&pio { - mmc0_cd_pin_wobo_i5: mmc0_cd_pin@0 { - pins = "PB3"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts index 30a86cadf5a5..4b892f609240 100644 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts @@ -122,7 +122,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ @@ -134,12 +134,6 @@ }; &pio { - mmc0_cd_pin_d709: mmc0_cd_pin@0 { - pins = "PG0"; - function = "gpio_in"; - bias-pull-up; - }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { pins = "PG1"; function = "gpio_in"; diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts index f6211c22e4dc..ff845f48c832 100644 --- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -117,7 +117,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ @@ -133,12 +133,6 @@ }; &pio { - mmc0_cd_pin_h702: mmc0_cd_pin@0 { - pins = "PG0"; - function = "gpio_in"; - bias-pull-up; - }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { pins = "PG2"; function = "gpio_in"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index 0e107ff5cff0..8d104a0395dd 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -96,7 +96,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ @@ -112,12 +112,6 @@ }; &pio { - mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 { - pins = "PG0"; - function = "gpio_in"; - bias-pull-up; - }; - led_pins_olinuxinom: led_pins@0 { pins = "PG9"; function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index d963cac2a04d..1703b5379f6b 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -191,7 +191,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ @@ -207,12 +207,6 @@ }; &pio { - mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { - pins = "PG0"; - function = "gpio_in"; - bias-pull-up; - }; - led_pins_olinuxino: led_pins@0 { pins = "PG9"; function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index eafb362e3993..12c80be63693 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -121,7 +121,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ @@ -133,12 +133,6 @@ }; &pio { - mmc0_cd_pin: mmc0_cd_pin@0 { - pins = "PG0"; - function = "gpio_in"; - bias-pull-up; - }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { pins = "PG1"; function = "gpio_in"; -- cgit From 6a9951a18b013b81759f11fd0d30fa5574d30bb6 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 10:58:01 +0100 Subject: ARM: dts: sun5i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 6 +-- arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 8 ++-- arch/arm/boot/dts/sun5i-a10s-mk802.dts | 8 ++-- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 22 +++++------ arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 6 +-- arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 8 ++-- arch/arm/boot/dts/sun5i-a10s.dtsi | 12 +++--- .../boot/dts/sun5i-a13-empire-electronix-d709.dts | 10 ++--- arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 10 ++--- arch/arm/boot/dts/sun5i-a13-licheepi-one.dts | 12 +++--- arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 10 ++--- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 10 ++--- arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 2 +- arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 18 ++++----- arch/arm/boot/dts/sun5i-gr8-evb.dts | 20 +++++----- arch/arm/boot/dts/sun5i-gr8.dtsi | 10 ++--- arch/arm/boot/dts/sun5i-r8-chip.dts | 18 ++++----- .../boot/dts/sun5i-reference-design-tablet.dtsi | 12 +++++- arch/arm/boot/dts/sun5i.dtsi | 44 +++++++++++----------- 19 files changed, 127 insertions(+), 119 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts index 9e076e748b78..30c8e7b5fabc 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts @@ -76,7 +76,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp152: pmic@30 { @@ -90,7 +90,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -125,7 +125,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts index 4dd98cbd1ddb..bae5a35b38a1 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts @@ -85,7 +85,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp152: pmic@30 { @@ -99,7 +99,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -108,7 +108,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vmmc1>; bus-width = <4>; non-removable; @@ -145,7 +145,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts index 822f1b2ac6d3..06b876c50f15 100644 --- a/arch/arm/boot/dts/sun5i-a10s-mk802.dts +++ b/arch/arm/boot/dts/sun5i-a10s-mk802.dts @@ -73,7 +73,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp152: pmic@30 { @@ -87,7 +87,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -96,7 +96,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; @@ -118,7 +118,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 15889639a841..b1fe1226cb1e 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -97,7 +97,7 @@ &emac { pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_b>; + pinctrl-0 = <&emac_pa_pins>; phy = <&phy1>; status = "okay"; }; @@ -118,7 +118,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp152: pmic@30 { @@ -131,7 +131,7 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; at24@50 { @@ -144,7 +144,7 @@ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -198,7 +198,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -207,7 +207,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */ @@ -248,8 +248,8 @@ &spi2 { pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_b>, - <&spi2_cs0_pins_b>; + pinctrl-0 = <&spi2_pb_pins>, + <&spi2_cs0_pb_pin>; status = "okay"; }; @@ -259,19 +259,19 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_b>; + pinctrl-0 = <&uart2_pc_pins>; status = "okay"; }; &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_a>; + pinctrl-0 = <&uart3_pg_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts index ba2d2e604d54..a32025e57592 100644 --- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts +++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts @@ -77,7 +77,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -86,7 +86,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; @@ -112,7 +112,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts index 69581f8c4e8f..5683cc483a49 100644 --- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts +++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts @@ -90,7 +90,7 @@ &emac { pinctrl-names = "default"; - pinctrl-0 = <&emac_pins_a>; + pinctrl-0 = <&emac_pd_pins>; phy = <&phy1>; status = "okay"; }; @@ -101,7 +101,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -123,7 +123,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */ @@ -184,7 +184,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 195a6a1d2c49..7b44a227ba60 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -124,17 +124,17 @@ &pio { compatible = "allwinner,sun5i-a10s-pinctrl"; - uart0_pins_a: uart0@0 { + uart0_pb_pins: uart0-pb-pins { pins = "PB19", "PB20"; function = "uart0"; }; - uart2_pins_b: uart2@1 { + uart2_pc_pins: uart2-pc-pins { pins = "PC18", "PC19"; function = "uart2"; }; - emac_pins_b: emac0@1 { + emac_pa_pins: emac-pa-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", @@ -143,19 +143,19 @@ function = "emac"; }; - mmc1_pins_a: mmc1@0 { + mmc1_pins: mmc1-pins { pins = "PG3", "PG4", "PG5", "PG6", "PG7", "PG8"; function = "mmc1"; drive-strength = <30>; }; - spi2_pins_b: spi2@1 { + spi2_pb_pins: spi2-pb-pins { pins = "PB12", "PB13", "PB14"; function = "spi2"; }; - spi2_cs0_pins_b: spi2_cs0@1 { + spi2_cs0_pb_pin: spi2-cs0-pb-pin { pins = "PB11"; function = "spi2"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts index 4b892f609240..34c932564daf 100644 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts @@ -79,7 +79,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -92,7 +92,7 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; pcf8563: rtc@51 { @@ -122,7 +122,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ @@ -149,7 +149,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -191,7 +191,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; + pinctrl-0 = <&uart1_pg_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts index ff845f48c832..4f5b1247a427 100644 --- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -70,7 +70,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -81,7 +81,7 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; pcf8563: rtc@51 { @@ -92,7 +92,7 @@ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -117,7 +117,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ @@ -180,7 +180,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; + pinctrl-0 = <&uart1_pg_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts index 93a080e7ba2d..f2ecd81a3183 100644 --- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts +++ b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts @@ -95,7 +95,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -110,13 +110,13 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "disabled"; }; @@ -134,7 +134,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; broken-cd; @@ -143,7 +143,7 @@ &mmc2 { pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_a>; + pinctrl-0 = <&mmc2_4bit_pc_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; broken-cd; @@ -204,7 +204,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; + pinctrl-0 = <&uart1_pg_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index 8d104a0395dd..70445d28c20a 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -78,25 +78,25 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; }; &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ @@ -143,7 +143,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; + pinctrl-0 = <&uart1_pg_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 1703b5379f6b..8855ddb78e0b 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -124,7 +124,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -139,13 +139,13 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -191,7 +191,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ @@ -251,7 +251,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; + pinctrl-0 = <&uart1_pg_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts index 962ec29b1934..31a4b61f1d75 100644 --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts @@ -81,7 +81,7 @@ &mmc2 { pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; + pinctrl-0 = <&mmc2_8bit_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts index 959dd94c7b79..7a5ba22c7354 100644 --- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts +++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts @@ -93,7 +93,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -113,19 +113,19 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; }; &i2s0 { pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>; + pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>; status = "disabled"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc0_pwrseq>; bus-width = <4>; @@ -135,7 +135,7 @@ &nfc { pinctrl-names = "default"; - pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; + pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; status = "okay"; nand@0 { @@ -157,7 +157,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>; + pinctrl-0 = <&pwm0_pin>, <&pwm1_pins>; status = "disabled"; }; @@ -206,19 +206,19 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>; + pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>; status = "okay"; }; &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>, <&uart2_cts_rts_pins_a>; + pinctrl-0 = <&uart2_pd_pins>, <&uart2_cts_rts_pd_pins>; status = "disabled"; }; &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_a>, <&uart3_cts_rts_pins_a>; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts index 5196aeff75aa..ea1711a31cce 100644 --- a/arch/arm/boot/dts/sun5i-gr8-evb.dts +++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts @@ -124,7 +124,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -144,7 +144,7 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; wm8978: codec@1a { @@ -161,19 +161,19 @@ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &i2s0 { pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>; + pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; @@ -233,7 +233,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ @@ -242,7 +242,7 @@ &nfc { pinctrl-names = "default"; - pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; + pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; /* MLC Support sucks for now */ status = "disabled"; @@ -258,7 +258,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -298,7 +298,7 @@ &spdif { pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pins_a>; + pinctrl-0 = <&spdif_tx_pin>; status = "okay"; }; @@ -308,7 +308,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>; + pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi index d3eea4cfe442..98a8fd5e89e8 100644 --- a/arch/arm/boot/dts/sun5i-gr8.dtsi +++ b/arch/arm/boot/dts/sun5i-gr8.dtsi @@ -98,28 +98,28 @@ &pio { compatible = "nextthing,gr8-pinctrl"; - i2s0_data_pins_a: i2s0-data@0 { + i2s0_data_pins: i2s0-data-pins { pins = "PB6", "PB7", "PB8", "PB9"; function = "i2s0"; }; - i2s0_mclk_pins_a: i2s0-mclk@0 { + i2s0_mclk_pin: i2s0-mclk-pin { pins = "PB5"; function = "i2s0"; }; - pwm1_pins: pwm1 { + pwm1_pins: pwm1-pin { pins = "PG13"; function = "pwm1"; }; - spdif_tx_pins_a: spdif@0 { + spdif_tx_pin: spdif-tx-pin { pins = "PB10"; function = "spdif"; bias-pull-up; }; - uart1_cts_rts_pins_a: uart1-cts-rts@0 { + uart1_cts_rts_pins: uart1-cts-rts-pins { pins = "PG5", "PG6"; function = "uart1"; }; diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index c97e46e4bb45..a913084c8d20 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -108,7 +108,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -136,13 +136,13 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; xio: gpio@38 { @@ -159,13 +159,13 @@ }; }; -&mmc0_pins_a { +&mmc0_pins { bias-pull-up; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc0_pwrseq>; bus-width = <4>; @@ -251,7 +251,7 @@ &spi2 { pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; + pinctrl-0 = <&spi2_pe_pins>; status = "disabled"; }; @@ -265,14 +265,14 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; + pinctrl-0 = <&uart1_pg_pins>; status = "okay"; }; &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_a>, - <&uart3_cts_rts_pins_a>; + pinctrl-0 = <&uart3_pg_pins>, + <&uart3_cts_rts_pg_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index 12c80be63693..ca7556177c1b 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -76,6 +76,8 @@ }; &i2c0 { + pinctrl-0 = <&i2c0_pins>; + axp209: pmic@34 { reg = <0x34>; interrupts = <0>; @@ -83,6 +85,8 @@ }; &i2c1 { + pinctrl-0 = <&i2c1_pins>; + /* * The gsl1680 is rated at 400KHz and it will not work reliable at * 100KHz, this has been confirmed on multiple different q8 tablets. @@ -121,7 +125,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ @@ -146,6 +150,10 @@ }; }; +&pwm { + pinctrl-0 = <&pwm0_pin>; +}; + ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -184,7 +192,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; + pinctrl-0 = <&uart1_pg_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 5085b658d216..ac287a0685b2 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -446,7 +446,7 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - emac_pins_a: emac0@0 { + emac_pd_pins: emac-pd-pins { pins = "PD6", "PD7", "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD18", "PD19", "PD20", @@ -455,27 +455,27 @@ function = "emac"; }; - i2c0_pins_a: i2c0@0 { + i2c0_pins: i2c0-pins { pins = "PB0", "PB1"; function = "i2c0"; }; - i2c1_pins_a: i2c1@0 { + i2c1_pins: i2c1-pins { pins = "PB15", "PB16"; function = "i2c1"; }; - i2c2_pins_a: i2c2@0 { + i2c2_pins: i2c2-pins { pins = "PB17", "PB18"; function = "i2c2"; }; - ir0_rx_pins_a: ir0@0 { + ir0_rx_pin: ir0-rx-pin { pins = "PB4"; function = "ir0"; }; - lcd_rgb565_pins: lcd_rgb565@0 { + lcd_rgb565_pins: lcd-rgb565-pins { pins = "PD3", "PD4", "PD5", "PD6", "PD7", "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD19", "PD20", "PD21", "PD22", "PD23", @@ -483,7 +483,7 @@ function = "lcd0"; }; - lcd_rgb666_pins: lcd_rgb666@0 { + lcd_rgb666_pins: lcd-rgb666-pins { pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", @@ -491,7 +491,7 @@ function = "lcd0"; }; - mmc0_pins_a: mmc0@0 { + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -499,7 +499,7 @@ bias-pull-up; }; - mmc2_pins_a: mmc2@0 { + mmc2_8bit_pins: mmc2-8bit-pins { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15"; @@ -508,7 +508,7 @@ bias-pull-up; }; - mmc2_4bit_pins_a: mmc2-4bit@0 { + mmc2_4bit_pc_pins: mmc2-4bit-pc-pins { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11"; function = "mmc2"; @@ -516,7 +516,7 @@ bias-pull-up; }; - nand_pins_a: nand-base0@0 { + nand_pins: nand-pins { pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", @@ -524,57 +524,57 @@ function = "nand0"; }; - nand_cs0_pins_a: nand-cs@0 { + nand_cs0_pin: nand-cs0-pin { pins = "PC4"; function = "nand0"; }; - nand_rb0_pins_a: nand-rb@0 { + nand_rb0_pin: nand-rb0-pin { pins = "PC6"; function = "nand0"; }; - spi2_pins_a: spi2@0 { + spi2_pe_pins: spi2-pe-pins { pins = "PE1", "PE2", "PE3"; function = "spi2"; }; - spi2_cs0_pins_a: spi2-cs0@0 { + spi2_cs0_pe_pin: spi2-cs0-pe-pin { pins = "PE0"; function = "spi2"; }; - uart1_pins_a: uart1@0 { + uart1_pe_pins: uart1-pe-pins { pins = "PE10", "PE11"; function = "uart1"; }; - uart1_pins_b: uart1@1 { + uart1_pg_pins: uart1-pg-pins { pins = "PG3", "PG4"; function = "uart1"; }; - uart2_pins_a: uart2@0 { + uart2_pd_pins: uart2-pd-pins { pins = "PD2", "PD3"; function = "uart2"; }; - uart2_cts_rts_pins_a: uart2-cts-rts@0 { + uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins { pins = "PD4", "PD5"; function = "uart2"; }; - uart3_pins_a: uart3@0 { + uart3_pg_pins: uart3-pg-pins { pins = "PG9", "PG10"; function = "uart3"; }; - uart3_cts_rts_pins_a: uart3-cts-rts@0 { + uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { pins = "PG11", "PG12"; function = "uart3"; }; - pwm0_pins: pwm0 { + pwm0_pin: pwm0-pin { pins = "PB2"; function = "pwm"; }; -- cgit From ed5fc60b909427be6ca93d3e07a0a5f296d7000a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 7 Sep 2018 16:00:22 +0200 Subject: ARM: dts: sun5i: a10s: Fix HDMI output DTC warning Our HDMI output endpoint on the A10s DTSI has a warning under DTC: "graph node has single child node 'endpoint', #address-cells/#size-cells are not necessary". Fix this by removing those properties. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 7b44a227ba60..d9fdcd41faa7 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -100,8 +100,6 @@ }; hdmi_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; }; }; -- cgit From ddeec86cb608cc520bd69ab568135ee45d500595 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Thu, 27 Sep 2018 14:59:22 +0100 Subject: ARM: dts: r9a06g032: Add pinctrl node This provides a pinctrl driver for the Renesas R9A06G032 SoC Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r9a06g032.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index eaf94976ed6d..2322268bc862 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -165,6 +165,14 @@ status = "disabled"; }; + pinctrl: pin-controller@40067000 { + compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; + reg = <0x40067000 0x1000>, <0x51000000 0x480>; + clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; + clock-names = "bus"; + status = "okay"; + }; + gic: gic@44101000 { compatible = "arm,cortex-a7-gic", "arm,gic-400"; interrupt-controller; -- cgit From 4f94af57237ad1c9c6328b468fd8fbbd19c2fb78 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 8 Oct 2018 10:52:38 +0100 Subject: ARM: dts: r8a77470: Add I2C[0123] support Add device tree nodes for the I2C[0123] controllers. Also, add the aliases node. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 9ec78d3d0ca8..9611a936e1b8 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -14,6 +14,14 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -237,6 +245,62 @@ reg = <0 0xe6300000 0 0x20000>; }; + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77470", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77470", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77470", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77470", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + i2c4: i2c@e6520000 { #address-cells = <1>; #size-cells = <0>; -- cgit From 15aa5a95e820e8183aa34535131e7c97789b8504 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 8 Oct 2018 09:51:50 +0100 Subject: ARM: dts: r8a77470: Add SDHI0 support RZ/G1C comes with two different types of IP for the SDHI interfaces, SDHI0 and SDHI2 share the same IP type, and such an IP is also compatible with the one found in R-Car Gen2. SDHI1 IP on the other hand is compatible with R-Car Gen3 with internal DMA. This patch completes the SDHI support of the R-Car Gen2 compatible IPs, including fixing the max-frequency definition of SDHI2, as it turns out there is a bug in Section 1.3.9 of the RZ/G1C Hardware User's Manual (Rev. 1.00 Oct. 2017). Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 9611a936e1b8..ab2e0223f8a1 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -490,6 +490,21 @@ status = "disabled"; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a77470", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <156000000>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + sdhi2: sd@ee160000 { compatible = "renesas,sdhi-r8a77470", "renesas,rcar-gen2-sdhi"; @@ -499,7 +514,7 @@ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; + max-frequency = <78000000>; power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; resets = <&cpg 312>; status = "disabled"; -- cgit From 0485da788028ecd525291974c8efe2d072607476 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 8 Oct 2018 09:51:51 +0100 Subject: ARM: dts: r8a77470: Add SDHI1 support Althought interface SDHI1 found on the RZ/G1C SoC (a.k.a. r8a77470) is compatible with the R-Car Gen3 ones, its OF compatibility is restricted to the SoC specific compatible string to avoid confusion, as from a more generic perspective the RZ/G1C is sharing the most similarities with the R-Car Gen2 family of SoCs, and there is a combination of R-Car Gen2 compatible SDHI IPs and R-Car Gen3 compatible SDHI IP on this specific chip. This patch adds the SoC specific part of SDHI1 support, and since SDHI1 comes with internal DMA, its DT node looks fairly different from SDHI0 and SDHI2. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index ab2e0223f8a1..6ac7f467065e 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -505,6 +505,17 @@ status = "disabled"; }; + sdhi1: sd@ee300000 { + compatible = "renesas,sdhi-mmc-r8a77470"; + reg = <0 0xee300000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <156000000>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + sdhi2: sd@ee160000 { compatible = "renesas,sdhi-r8a77470", "renesas,rcar-gen2-sdhi"; -- cgit From 9eb36b945b5c21d57c02a26cc629dd9484ced9aa Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 8 Oct 2018 09:51:52 +0100 Subject: ARM: dts: iwg23s-sbc: Add uSD and eMMC support Add uSD card and eMMC support to the iwg23s single board computer powered by the RZ/G1C SoC (a.k.a. r8a77470). Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 76 +++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 22da819f186b..e5cfb50ddce3 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -6,6 +6,7 @@ */ /dts-v1/; +#include #include "r8a77470.dtsi" / { model = "iWave iW-RainboW-G23S single board computer based on RZ/G1C"; @@ -25,6 +26,37 @@ device_type = "memory"; reg = <0 0x40000000 0 0x20000000>; }; + + reg_1p8v: reg-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: reg-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vccq_sdhi2: regulator-vccq-sdhi2 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI2 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; }; &avb { @@ -46,10 +78,28 @@ }; &pfc { + mmc_pins_uhs: mmc_uhs { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + power-source = <1800>; + }; + scif1_pins: scif1 { groups = "scif1_data_b"; function = "scif1"; }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; }; &scif1 { @@ -58,3 +108,29 @@ status = "okay"; }; + +&sdhi1 { + pinctrl-0 = <&mmc_pins_uhs>; + pinctrl-names = "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi2>; + bus-width = <4>; + cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; + status = "okay"; +}; -- cgit From 89862542fab10fed8a3c2f9c167622ef4287351d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 17 Oct 2018 20:48:01 +0300 Subject: ARM: dts: r8a779[01]: Disable unconnected LVDS encoders The LVDS0 encoder on Koelsh and Porter, and the LVDS1 encoder on Lager, are enabled in DT but have no device connected to their output. This result in spurious messages being printed to the kernel log such as rcar-du feb00000.display: no connector for encoder /soc/lvds@feb90000, skipping Fix it by disabling the encoders. Fixes: 15a1ff30d8f9 ("ARM: dts: r8a7790: Convert to new LVDS DT bindings") Fixes: e5c3f4707f39 ("ARM: dts: r8a7791: Convert to new LVDS DT bindings") Reported-by: Geert Uytterhoeven Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 2 -- arch/arm/boot/dts/r8a7791-koelsch.dts | 2 -- arch/arm/boot/dts/r8a7791-porter.dts | 2 -- 3 files changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 50312e752e2f..7b9508e83d46 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -489,8 +489,6 @@ }; &lvds1 { - status = "okay"; - ports { port@1 { lvds_connector: endpoint { diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index ce22db01fbba..e6580aa0cea3 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -479,8 +479,6 @@ }; &lvds0 { - status = "okay"; - ports { port@1 { lvds_connector: endpoint { diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index f02036e5de01..fefdf8238bbe 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -482,8 +482,6 @@ }; &lvds0 { - status = "okay"; - ports { port@1 { lvds_connector: endpoint { -- cgit From fb09bf59f081940a5bc5109aed184e63b2abdd67 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 22 Oct 2018 03:21:20 +0900 Subject: ARM: dts: r8a7740, emev2, sh73a0: Include SoC name in DTSI Update the R-Mobile A1 (r8a7740), Emma Mobile EV2 (emev2) and SH-Mobile AG5 (sh72a0) DTSI to include product name. Signed-off-by: Magnus Damm [simon: squashed similar patches] Signed-off-by: Simon Horman --- arch/arm/boot/dts/emev2.dtsi | 2 +- arch/arm/boot/dts/r8a7740.dtsi | 2 +- arch/arm/boot/dts/sh73a0.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 373ea8720769..67d86012a85c 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the EMEV2 SoC + * Device Tree Source for the Emma Mobile EV2 SoC * * Copyright (C) 2012 Renesas Solutions Corp. */ diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 383cba68dbba..12ffe73bf2bc 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the r8a7740 SoC + * Device Tree Source for the R-Mobile A1 (R8A77400) SoC * * Copyright (C) 2012 Renesas Solutions Corp. */ diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index e8f0a07c4564..33836990b102 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the SH73A0 SoC + * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC * * Copyright (C) 2012 Renesas Solutions Corp. */ -- cgit From dc7bf8795d848890641387d98c5e1324d397e9c8 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 26 Oct 2018 10:32:26 +0100 Subject: ARM: dts: r8a77470: Add watchdog support to SoC dtsi This patch adds watchdog support to the r8a77470 SoC dtsi. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro [simon: moved node to preserve sort order] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 6ac7f467065e..a703b74cc1f9 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -79,6 +79,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a77470-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77470", "renesas,rcar-gen2-gpio"; -- cgit From e1d31e7ebaa4087ecc7a5e16197f7fa6857aaa75 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 26 Oct 2018 10:32:27 +0100 Subject: ARM: dts: iwg23s-sbc: Enable watchdog support This patch enables watchdog support on the iWave iwg23s sbc. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index e5cfb50ddce3..ffd8216f28c3 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -102,6 +102,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif1 { pinctrl-0 = <&scif1_pins>; pinctrl-names = "default"; -- cgit From 92c3ccd9b847a6cf130e10aa305e9e349626e4f0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 25 Oct 2018 15:53:38 +0100 Subject: ARM: dts: r8a77470: Add USB-DMAC device nodes This patch adds USB DMAC nodes. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 56 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index a703b74cc1f9..0a7ca2ff4dc4 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -325,6 +325,62 @@ status = "disabled"; }; + usb_dmac00: dma-controller@e65a0000 { + compatible = "renesas,r8a77470-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac10: dma-controller@e65b0000 { + compatible = "renesas,r8a77470-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac01: dma-controller@e65a8000 { + compatible = "renesas,r8a77470-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a8000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 326>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 326>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac11: dma-controller@e65b8000 { + compatible = "renesas,r8a77470-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b8000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 327>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 327>; + #dma-cells = <1>; + dma-channels = <2>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a77470", "renesas,rcar-dmac"; -- cgit From 8129890823855fedab15bc0df1f89beaac5653db Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 26 Oct 2018 09:48:28 +0100 Subject: ARM: dts: r8a77470: Add CMT SoC specific support Add CMT[01] support to r8a77470 SoC DT. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 0a7ca2ff4dc4..5c0e48d0449a 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -615,6 +615,38 @@ compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a77470-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a77470-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; + }; }; timer { -- cgit From b5079d767b881b0f516df6627e0c4297137fa5d0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 26 Oct 2018 09:48:29 +0100 Subject: ARM: dts: iwg23s-sbc: Enable cmt0 This patch enables cmt0 support on the iWave iwg23s sbc. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index ffd8216f28c3..18d22631e188 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -73,6 +73,10 @@ }; }; +&cmt0 { + status = "okay"; +}; + &extal_clk { clock-frequency = <20000000>; }; -- cgit From 976a5ccb808da21f77a3bb1123a9e5df6f2d9564 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 7 Nov 2018 12:06:43 +0000 Subject: ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVB Adding pinctrl support for EtherAVB interface. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 18d22631e188..52f23b858885 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -60,6 +60,9 @@ }; &avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + phy-handle = <&phy3>; phy-mode = "gmii"; renesas,no-ether-link; @@ -82,6 +85,11 @@ }; &pfc { + avb_pins: avb { + groups = "avb_mdio", "avb_gmii_tx_rx"; + function = "avb"; + }; + mmc_pins_uhs: mmc_uhs { groups = "mmc_data8", "mmc_ctrl"; function = "mmc"; -- cgit From b6239d4219643bd1ac1d0b5a0faedf69cd2a2bfa Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 8 Nov 2018 17:04:42 +0000 Subject: ARM: dts: r8a77470: Add QSPI support Add QSPI[01] support to the RZ/G1C SoC specific device tree. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 5c0e48d0449a..f4e232bf9d03 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -460,6 +460,38 @@ status = "disabled"; }; + qspi0: spi@e6b10000 { + compatible = "renesas,qspi-r8a77470", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 918>; + status = "disabled"; + }; + + qspi1: spi@ee200000 { + compatible = "renesas,qspi-r8a77470", "renesas,qspi"; + reg = <0 0xee200000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77470", "renesas,rcar-gen2-scif", "renesas,scif"; -- cgit From 91f5c32dd0c8fc662694de4d8c5eeb61e4b4210b Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 8 Nov 2018 17:04:43 +0000 Subject: ARM: dts: iwg23s-sbc: Add QSPI flash support This commit adds QSPI flash support to the iwg23s board specific device tree. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index 52f23b858885..40b7f98d6013 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -96,6 +96,11 @@ power-source = <1800>; }; + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data2"; + function = "qspi0"; + }; + scif1_pins: scif1 { groups = "scif1_data_b"; function = "scif1"; @@ -114,6 +119,27 @@ }; }; +&qspi0 { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "issi,is25lp016d", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; -- cgit From 673df60a880f060e3e94920c7b5f7a9ed8aa65f2 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 21 Nov 2018 10:08:44 +0000 Subject: ARM: dts: r9a06g032: Correct the GIC DT node name Harmless mistake, but it's incorrect. The DT spec provides recommendations for the node names: "The name of a node should be somewhat generic, reflecting the function of the device and not its precise programming model. If appropriate, the name should be one of the following choices: ... interrupt-controller" Signed-off-by: Phil Edworthy Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r9a06g032.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 2322268bc862..4c1ab49c7d39 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -173,7 +173,7 @@ status = "okay"; }; - gic: gic@44101000 { + gic: interrupt-controller@44101000 { compatible = "arm,cortex-a7-gic", "arm,gic-400"; interrupt-controller; #interrupt-cells = <3>; -- cgit From 7038250756c42b2bbe02b04223da14aac3a6f641 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 15:28:28 +0100 Subject: ARM: dts: sunxi: Change default CMA pool node name The CMA node has a unit address, but no reg property which generates a warning in DTC. Change the node name to reflect its usage and drop the unit address. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/media/cedrus.txt | 2 +- arch/arm/boot/dts/sun5i.dtsi | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- arch/arm/boot/dts/sun8i-a33.dtsi | 2 +- arch/arm/boot/dts/sun8i-h3.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/media/cedrus.txt b/Documentation/devicetree/bindings/media/cedrus.txt index a089a0c1ff05..33833a43fff8 100644 --- a/Documentation/devicetree/bindings/media/cedrus.txt +++ b/Documentation/devicetree/bindings/media/cedrus.txt @@ -31,7 +31,7 @@ reserved-memory { ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: cma@4a000000 { + cma_pool: default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index ac287a0685b2..b957b141e502 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -114,7 +114,7 @@ ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: cma@4a000000 { + cma_pool: default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index b4fd4f5ca66b..f7dcf8d21fd2 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -181,7 +181,7 @@ ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: cma@4a000000 { + cma_pool: default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 502de6f44a9a..a8b2c4d14f99 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -196,7 +196,7 @@ ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: cma@4a000000 { + cma_pool: default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 3ecfabb10151..b3921c5171ed 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -124,7 +124,7 @@ #size-cells = <1>; ranges; - cma_pool: cma@4a000000 { + cma_pool: default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; -- cgit From 335d7fcb1d69a5fae9f199b2e9eb3047f1a4dba7 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 15:30:17 +0100 Subject: ARM: dts: sunxi: Remove the CMA node label There's no phandle pointing to the CMA pool, so it's label is unnecessary. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i.dtsi | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- arch/arm/boot/dts/sun8i-a33.dtsi | 2 +- arch/arm/boot/dts/sun8i-h3.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index b957b141e502..5906d43ec4ed 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -114,7 +114,7 @@ ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: default-pool { + default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index f7dcf8d21fd2..1ca1fdff2288 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -181,7 +181,7 @@ ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: default-pool { + default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index a8b2c4d14f99..1c4f7e1930d8 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -196,7 +196,7 @@ ranges; /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - cma_pool: default-pool { + default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index b3921c5171ed..22883f1b80e2 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -124,7 +124,7 @@ #size-cells = <1>; ranges; - cma_pool: default-pool { + default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; alloc-ranges = <0x4a000000 0x6000000>; -- cgit From bc0160655ec32e0b8e46aa29aa5da1430431b3f7 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 8 Nov 2018 11:20:15 +0100 Subject: ARM: dts: sun5i: Remove underscores from nodes names Some GPIO pinctrl nodes cannot be easily removed, because they would also change the pin configuration, for example to add a pull resistor or change the current delivered by the pin. Those nodes still have underscores and unit-addresses in their node names in our DTs, so adjust their name to remove the warnings. Use that occasion to also fix some poorly chosen node-names. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 2 +- arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 4 ++-- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 4 ++-- arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 2 +- arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 4 ++-- arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 2 +- arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 6 +++--- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 6 +++--- arch/arm/boot/dts/sun5i-a13-utoo-p66.dts | 4 ++-- arch/arm/boot/dts/sun5i-r8-chip.dts | 3 +-- arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi | 4 ++-- 11 files changed, 20 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts index 30c8e7b5fabc..f5c50b66290a 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts @@ -106,7 +106,7 @@ }; &pio { - led_pins_t003: led_pins@0 { + led_pins_t003: led-pin { pins = "PB2"; function = "gpio_out"; drive-strength = <20>; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts index bae5a35b38a1..540513686e06 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts @@ -125,13 +125,13 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PG12"; function = "gpio_in"; bias-pull-up; }; - led_pins_t004: led_pins@0 { + led_pins_t004: led-pin { pins = "PB2"; function = "gpio_out"; drive-strength = <20>; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index b1fe1226cb1e..ae6d4a0bb9c9 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -223,13 +223,13 @@ }; &pio { - led_pins_olinuxino: led_pins@0 { + led_pins_olinuxino: led-pin { pins = "PE3"; function = "gpio_out"; drive-strength = <20>; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PG12"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts index a32025e57592..afbda5dd773b 100644 --- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts +++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts @@ -98,7 +98,7 @@ }; &pio { - led_pins_r7: led_pins@0 { + led_pins_r7: led-pin { pins = "PB2"; function = "gpio_out"; drive-strength = <20>; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts index 34c932564daf..49eaa1920088 100644 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts @@ -134,13 +134,13 @@ }; &pio { - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PG1"; function = "gpio_in"; bias-pull-down; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PG2"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts index 4f5b1247a427..082a1501eaf1 100644 --- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -133,7 +133,7 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PG2"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index 70445d28c20a..cf5f730d5efa 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -112,19 +112,19 @@ }; &pio { - led_pins_olinuxinom: led_pins@0 { + led_pins_olinuxinom: led-pin { pins = "PG9"; function = "gpio_out"; drive-strength = <20>; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PG2"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PG1"; function = "gpio_in"; bias-pull-down; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 8855ddb78e0b..ae270eda1a69 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -207,19 +207,19 @@ }; &pio { - led_pins_olinuxino: led_pins@0 { + led_pins_olinuxino: led-pin { pins = "PG9"; function = "gpio_out"; drive-strength = <20>; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PG2"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PG1"; function = "gpio_in"; bias-pull-down; diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts index 31a4b61f1d75..732873cbeedc 100644 --- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts @@ -58,7 +58,7 @@ /delete-property/stdout-path; }; - i2c_lcd: i2c@0 { + i2c_lcd: i2c-gpio { /* The lcd panel i2c interface is hooked up via gpios */ compatible = "i2c-gpio"; pinctrl-names = "default"; @@ -95,7 +95,7 @@ }; &pio { - i2c_lcd_pins: i2c_lcd_pin@0 { + i2c_lcd_pins: i2c-lcd-pin { pins = "PG10", "PG12"; function = "gpio_out"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index a913084c8d20..3c9f4f35d43b 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -182,8 +182,7 @@ }; &pio { - - chip_w1_pin: chip_w1_pin@0 { + chip_w1_pin: chip-w1-pin { pins = "PD2"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index ca7556177c1b..b046436ff773 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -137,13 +137,13 @@ }; &pio { - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PG1"; function = "gpio_in"; bias-pull-down; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PG2"; function = "gpio_in"; bias-pull-up; -- cgit From d7c2d23b6fe66f116ebf8180c8e320cf48e96c8a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 8 Nov 2018 11:21:05 +0100 Subject: ARM: dts: sunxi: Change LRADC node names to avoid warnings One of the usage of the LRADC is to implement buttons. The bindings define that we should have one subnode per button, with their associated voltage as a property. However, there was no reg property but we still used the voltage associated to the button as the unit-address, which eventually generated warnings in DTC. Rename the node names to avoid those warnings. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi index 245d0bcde441..00dc6623f30f 100644 --- a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi @@ -60,14 +60,14 @@ vref-supply = <®_vcc3v0>; status = "okay"; - button@200 { + button-200 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <200000>; }; - button@400 { + button-400 { label = "Volume Down"; linux,code = ; channel = <0>; -- cgit From 17222eb932ad2ec67e583179f507982460d81bde Mon Sep 17 00:00:00 2001 From: Derek Basehore Date: Tue, 27 Nov 2018 15:23:31 -0800 Subject: arm64: dts: rockchip: Add 32k clk on rk3399-gru This adds the 32k clock to the RK3399 Gru board file, which is provided by a Silego oscillator on Gru boards. Even though it's not directly used, muxes will end up traversing the entire clk tree on calls to determine_rate if it doesn't exist. This is because the 32k clk is listed as a possible parent on some clks. Since the clk doesn't know about the 32k clk (it was never registered), it triggers a global search for it. This can happen about 40 times per second, which isn't great for power. Signed-off-by: Derek Basehore Reviewed-by: Douglas Anderson [moved clock position and adapted commit message a bit] Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index ca07f6032200..ea607a601a86 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -262,6 +262,13 @@ pp5000_usb_a_vbus: pp5000 { }; + ap_rtc_clk: ap-rtc-clk { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + gpio_keys: gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; -- cgit From a45207cef8a476be1443df6aeeecdf8495641b23 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 21:32:43 +0100 Subject: ARM: dts: sun5i: A10s: Remove empty SRAM node The SRAM node in the A10s DTSI is empty, remove it. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index d9fdcd41faa7..cd7119273b80 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -159,9 +159,6 @@ }; }; -&sram_a { -}; - &tcon0_out { tcon0_out_hdmi: endpoint@2 { reg = <2>; -- cgit From 1eb3927c207e94e48db76b70a5238d68a8b7bdb2 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 22:03:28 +0100 Subject: ARM: dts: sun5i: Provide default muxing for relevant controllers The I2C's, MMC0 and MMC1 controllers have only one muxing option in the SoC. In such a case, we can just move the muxing into the DTSI, and remove it from the DTS. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 4 ---- arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 6 ------ arch/arm/boot/dts/sun5i-a10s-mk802.dts | 6 ------ arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 10 ---------- arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 4 ---- arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 4 ---- arch/arm/boot/dts/sun5i-a10s.dtsi | 5 +++++ arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 6 ------ arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 8 -------- arch/arm/boot/dts/sun5i-a13-licheepi-one.dts | 8 -------- arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 8 -------- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 8 -------- arch/arm/boot/dts/sun5i-gr8-chip-pro.dts | 6 ------ arch/arm/boot/dts/sun5i-gr8-evb.dts | 8 -------- arch/arm/boot/dts/sun5i-r8-chip.dts | 8 -------- arch/arm/boot/dts/sun5i.dtsi | 8 ++++++++ 16 files changed, 13 insertions(+), 94 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts index f5c50b66290a..64d50fcfcd3a 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts @@ -75,8 +75,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp152: pmic@30 { @@ -89,8 +87,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts index 540513686e06..c88f08984483 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts @@ -84,8 +84,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp152: pmic@30 { @@ -98,8 +96,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -107,8 +103,6 @@ }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vmmc1>; bus-width = <4>; non-removable; diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts index 06b876c50f15..6e90ccb267aa 100644 --- a/arch/arm/boot/dts/sun5i-a10s-mk802.dts +++ b/arch/arm/boot/dts/sun5i-a10s-mk802.dts @@ -72,8 +72,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp152: pmic@30 { @@ -86,8 +84,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -95,8 +91,6 @@ }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index ae6d4a0bb9c9..262c2ffbdcfa 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -117,8 +117,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp152: pmic@30 { @@ -130,8 +128,6 @@ #include "axp152.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; at24@50 { @@ -143,8 +139,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -197,8 +191,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -206,8 +198,6 @@ }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */ diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts index afbda5dd773b..b2a49a216ebf 100644 --- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts +++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts @@ -76,8 +76,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ @@ -85,8 +83,6 @@ }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts index 5683cc483a49..b5ee8fb13a92 100644 --- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts +++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts @@ -100,8 +100,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -122,8 +120,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */ diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index cd7119273b80..09c486b608b2 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -119,6 +119,11 @@ compatible = "allwinner,sun5i-a10s-ccu"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +}; + &pio { compatible = "allwinner,sun5i-a10s-pinctrl"; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts index 49eaa1920088..f3cede9beb63 100644 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts @@ -78,8 +78,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -91,8 +89,6 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; pcf8563: rtc@51 { @@ -121,8 +117,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts index 082a1501eaf1..9369f7453beb 100644 --- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -69,8 +69,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -80,8 +78,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; pcf8563: rtc@51 { @@ -91,8 +87,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -116,8 +110,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ diff --git a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts index f2ecd81a3183..ca8f3fd1ddfe 100644 --- a/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts +++ b/arch/arm/boot/dts/sun5i-a13-licheepi-one.dts @@ -94,8 +94,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -109,14 +107,10 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "disabled"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "disabled"; }; @@ -133,8 +127,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; broken-cd; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index cf5f730d5efa..943868e495bc 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -77,26 +77,18 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index ae270eda1a69..9409c232d48a 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -123,8 +123,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -138,14 +136,10 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -190,8 +184,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts index 7a5ba22c7354..3f70b8c53132 100644 --- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts +++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts @@ -92,8 +92,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -112,8 +110,6 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "disabled"; }; @@ -124,8 +120,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc0_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts index ea1711a31cce..86e46aa59134 100644 --- a/arch/arm/boot/dts/sun5i-gr8-evb.dts +++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts @@ -123,8 +123,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -143,8 +141,6 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; wm8978: codec@1a { @@ -160,8 +156,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -232,8 +226,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index 3c9f4f35d43b..f4298facf9dc 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -107,8 +107,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -135,14 +133,10 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "disabled"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; xio: gpio@38 { @@ -164,8 +158,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc0_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 5906d43ec4ed..5497d985c54a 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -326,6 +326,8 @@ clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; clock-names = "ahb", "mmc"; interrupts = <32>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -678,6 +680,8 @@ reg = <0x01c2ac00 0x400>; interrupts = <7>; clocks = <&ccu CLK_APB1_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -688,6 +692,8 @@ reg = <0x01c2b000 0x400>; interrupts = <8>; clocks = <&ccu CLK_APB1_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -698,6 +704,8 @@ reg = <0x01c2b400 0x400>; interrupts = <9>; clocks = <&ccu CLK_APB1_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- cgit From 86f085c58b984a6cb25a74db5a21ec1997b5ace4 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 09:39:24 +0100 Subject: ARM: dts: sun6i: Remove skeleton and memory to avoid warnings Using skeleton.dtsi will create a memory node that will generate a warning in DTC. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 1eaa60cd3218..b60aaacbab5e 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -42,8 +42,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" - #include #include @@ -52,6 +50,8 @@ / { interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { ethernet0 = &gmac; @@ -199,10 +199,6 @@ }; }; - memory { - reg = <0x40000000 0x80000000>; - }; - pmu { compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; interrupts = , -- cgit From 5e570c04751c16efd30a939b81bbfeba226743fb Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 10:39:42 +0100 Subject: ARM: dts: sun6i: Change framebuffer node names to avoid warnings The simple-framebuffer nodes have a unit address, but no reg property which generates a warning when compiling it with DTC. Change the simple-framebuffer node names so that there is no warnings on this anymore. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun6i-a31.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index b60aaacbab5e..42a963975bde 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -62,7 +62,7 @@ #size-cells = <1>; ranges; - simplefb_hdmi: framebuffer@0 { + simplefb_hdmi: framebuffer-lcd0-hdmi { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; @@ -73,7 +73,7 @@ status = "disabled"; }; - simplefb_lcd: framebuffer@1 { + simplefb_lcd: framebuffer-lcd0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; -- cgit From acfd5bbe2641d34a8c377bac8df9dd4b1a3230d3 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 14:03:42 +0100 Subject: ARM: dts: sun6i: Change clock node names to avoid warnings Our oscillators clock names have a unit address, but no reg property, which generates a warning in DTC. Change these names to remove those unit addresses. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 42a963975bde..297055ffafff 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -212,13 +212,13 @@ #size-cells = <1>; ranges; - osc24M: osc24M { + osc24M: clk-24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; - osc32k: clk@0 { + osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; @@ -234,14 +234,14 @@ * The actual TX clock rate is not controlled by the * gmac_tx clock. */ - mii_phy_tx_clk: clk@1 { + mii_phy_tx_clk: clk-mii-phy-tx { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; clock-output-names = "mii_phy_tx"; }; - gmac_int_tx_clk: clk@2 { + gmac_int_tx_clk: clk-gmac-int-tx { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <125000000>; -- cgit From 1b7e882d30653dd7cf971bdd7de168e23bf6fe68 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 09:40:48 +0100 Subject: ARM: dts: sun6i: Remove SoC node unit-name to avoid warnings Our main node for all the in-SoC controllers used to have a unit name. The unit-name, in addition to being actually false, would not match any reg property, which generates a warning. Remove it in order to remove those warnings. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 297055ffafff..5355213f73b9 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -263,7 +263,7 @@ status = "disabled"; }; - soc@1c00000 { + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit From 97b3d91204899faa2daf742cb9f4b661c6e4274b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 14:14:58 +0100 Subject: ARM: dts: sun6i: Change LRADC node names to avoid warnings One of the usage of the LRADC is to implement buttons. The bindings define that we should have one subnode per button, with their associated voltage as a property. However, there was no reg property but we still used the voltage associated to the button as the unit-address, which eventually generated warnings in DTC. Rename the node names to avoid those warnings. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts | 2 +- arch/arm/boot/dts/sun6i-a31s-inet-q972.dts | 6 +++--- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 4 ++-- arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts index 882a4d89fa22..a2ef7846e2c8 100644 --- a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts +++ b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts @@ -53,7 +53,7 @@ vref-supply = <®_aldo3>; status = "okay"; - button@1000 { + button-1000 { label = "Home"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts b/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts index e584e6b186a7..85dab04be261 100644 --- a/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts +++ b/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts @@ -73,21 +73,21 @@ vref-supply = <®_aldo3>; status = "okay"; - button@200 { + button-200 { label = "Volume Down"; linux,code = ; channel = <0>; voltage = <200000>; }; - button@900 { + button-900 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <900000>; }; - button@1200 { + button-1200 { label = "Back"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index 4cb9664cdb29..ca1c711ed450 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -131,14 +131,14 @@ vref-supply = <®_aldo3>; status = "okay"; - button@158 { + button-158 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <158730>; }; - button@349 { + button-349 { label = "Volume Down"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts index da0ccf5a2c44..3a7e68c46ba7 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts @@ -147,14 +147,14 @@ vref-supply = <®_aldo3>; status = "okay"; - button@158 { + button-158 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <158730>; }; - button@349 { + button-349 { label = "Volume Down"; linux,code = ; channel = <0>; -- cgit From 8f9e10524902d0b476bcda18cec1925fba6ce2df Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 11:14:15 +0100 Subject: ARM: dts: sun6i: Remove all useless pinctrl nodes The gpio pinctrl nodes are redundant and as such useless most of the times. Since they will also generate warnings in DTC, we can simply remove most of them. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 8 -------- arch/arm/boot/dts/sun6i-a31-colombus.dts | 7 ------- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 13 ++----------- arch/arm/boot/dts/sun6i-a31-i7.dts | 14 -------------- arch/arm/boot/dts/sun6i-a31-m9.dts | 14 -------------- arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 14 -------------- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 7 ------- arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 7 ------- arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 23 +---------------------- 9 files changed, 3 insertions(+), 104 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts index 7f34323a668c..f26b84b61daf 100644 --- a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts +++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts @@ -65,15 +65,7 @@ status = "okay"; }; -&pio { - usb1_vbus_pin_a: usb1_vbus_pin@0 { - pins = "PH27"; - function = "gpio_out"; - }; -}; - ®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_a>; gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index 939c497a6f70..557d4a988d9a 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -132,11 +132,6 @@ bias-pull-up; }; - usb2_vbus_pin_colombus: usb2_vbus_pin@0 { - pins = "PH24"; - function = "gpio_out"; - }; - i2c_lcd_pins: i2c_lcd_pin@0 { pins = "PA23", "PA24"; function = "gpio_out"; @@ -145,8 +140,6 @@ }; ®_usb2_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_pin_colombus>; gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index ce4f9e9834bf..fc49d14059b1 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -160,7 +160,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_hummingbird>; + pinctrl-0 = <&gmac_pins_rgmii_a>; phy = <&phy1>; phy-mode = "rgmii"; snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; @@ -229,7 +229,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_hummingbird>; + pinctrl-0 = <&mmc1_pins_a>; vmmc-supply = <®_aldo1>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; @@ -242,21 +242,12 @@ }; &pio { - gmac_phy_reset_pin_hummingbird: gmac_phy_reset_pin@0 { - pins = "PA21"; - function = "gpio_out"; - }; - mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 { pins = "PA8"; function = "gpio_in"; bias-pull-up; }; - wifi_reset_pin_hummingbird: wifi_reset_pin@0 { - pins = "PG10"; - function = "gpio_out"; - }; }; &p2wi { diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/sun6i-a31-i7.dts index d659be9dbc50..679f0fa7e50c 100644 --- a/arch/arm/boot/dts/sun6i-a31-i7.dts +++ b/arch/arm/boot/dts/sun6i-a31-i7.dts @@ -71,8 +71,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_i7>; blue { label = "i7:blue:usr"; @@ -154,26 +152,14 @@ }; &pio { - led_pins_i7: led_pins@0 { - pins = "PH13"; - function = "gpio_out"; - }; - mmc0_cd_pin_i7: mmc0_cd_pin@0 { pins = "PH22"; function = "gpio_in"; bias-pull-up; }; - - usb1_vbus_pin_i7: usb1_vbus_pin@0 { - pins = "PC27"; - function = "gpio_out"; - }; }; ®_usb1_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_i7>; gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts index 9698f6d38d03..87ae3031aa89 100644 --- a/arch/arm/boot/dts/sun6i-a31-m9.dts +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -60,8 +60,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_m9>; blue { label = "m9:blue:pwr"; @@ -125,21 +123,11 @@ #include "axp22x.dtsi" &pio { - led_pins_m9: led_pins@0 { - pins = "PH13"; - function = "gpio_out"; - }; - mmc0_cd_pin_m9: mmc0_cd_pin@0 { pins = "PH22"; function = "gpio_in"; bias-pull-up; }; - - usb1_vbus_pin_m9: usb1_vbus_pin@0 { - pins = "PC27"; - function = "gpio_out"; - }; }; ®_aldo1 { @@ -215,8 +203,6 @@ }; ®_usb1_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_m9>; gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts index bb14b171b160..0711f55945e0 100644 --- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts +++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts @@ -60,8 +60,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_m9>; blue { label = "a1000g:blue:pwr"; @@ -125,21 +123,11 @@ #include "axp22x.dtsi" &pio { - led_pins_m9: led_pins@0 { - pins = "PH13"; - function = "gpio_out"; - }; - mmc0_cd_pin_m9: mmc0_cd_pin@0 { pins = "PH22"; function = "gpio_in"; bias-pull-up; }; - - usb1_vbus_pin_m9: usb1_vbus_pin@0 { - pins = "PC27"; - function = "gpio_out"; - }; }; ®_aldo1 { @@ -215,8 +203,6 @@ }; ®_usb1_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_m9>; gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index ca1c711ed450..dd6ede6a8377 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -101,8 +101,6 @@ status = "okay"; ctp@5d { - pinctrl-names = "default"; - pinctrl-0 = <>911_int_primo81>; compatible = "goodix,gt911"; reg = <0x5d>; interrupt-parent = <&pio>; @@ -156,11 +154,6 @@ }; &pio { - gt911_int_primo81: gt911_int_pin@0 { - pins = "PA3"; - function = "gpio_in"; - }; - mma8452_int_primo81: mma8452_int_pin@0 { pins = "PA9"; function = "gpio_in"; diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts index 3a7e68c46ba7..1b07a950cb45 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts @@ -66,8 +66,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pin_sina31s>; status { label = "sina31s:status:usr"; @@ -176,11 +174,6 @@ }; &pio { - led_pin_sina31s: led_pin@0 { - pins = "PH13"; - function = "gpio_out"; - }; - mmc0_cd_pin_sina31s: mmc0_cd_pin@0 { pins = "PA4"; function = "gpio_in"; diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts index b8b79c0e9ee0..ea29af15125b 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts @@ -58,8 +58,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_bpi_m2>; blue { label = "bpi-m2:blue:usr"; @@ -79,8 +77,6 @@ mmc2_pwrseq: mmc2_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pwrseq_pin_bpi_m2>; reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */ }; }; @@ -95,7 +91,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_bpi_m2>; + pinctrl-0 = <&gmac_pins_rgmii_a>; phy = <&phy1>; phy-mode = "rgmii"; phy-supply = <®_dldo1>; @@ -168,16 +164,6 @@ }; &pio { - gmac_phy_reset_pin_bpi_m2: gmac_phy_reset_pin@0 { - pins = "PA21"; - function = "gpio_out"; - }; - - led_pins_bpi_m2: led_pins@0 { - pins = "PG5", "PG10", "PG11"; - function = "gpio_out"; - }; - mmc0_cd_pin_bpi_m2: mmc0_cd_pin@0 { pins = "PA4"; function = "gpio_in"; @@ -185,13 +171,6 @@ }; }; -&r_pio { - mmc2_pwrseq_pin_bpi_m2: mmc2_pwrseq_pin@0 { - pins = "PL8"; - function = "gpio_out"; - }; -}; - #include "axp22x.dtsi" ®_aldo1 { -- cgit From d491714e8187bd5c3254971074d6c96875f0b957 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 21:03:20 +0100 Subject: ARM: dts: sun6i: Remove card detect pull-up Boards usually have an external pull-up on the card-detect signal, so there's no need to add another one. This also removes a DTC warning. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun6i-a31-colombus.dts | 8 +------- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 11 +---------- arch/arm/boot/dts/sun6i-a31-i7.dts | 10 +--------- arch/arm/boot/dts/sun6i-a31-m9.dts | 10 +--------- arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 10 +--------- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 8 +------- arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 10 +--------- arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 10 +--------- arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 10 +--------- arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi | 8 +------- 10 files changed, 10 insertions(+), 85 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index 557d4a988d9a..21584c2f968f 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -114,7 +114,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ @@ -126,12 +126,6 @@ }; &pio { - mmc0_cd_pin_colombus: mmc0_cd_pin@0 { - pins = "PA8"; - function = "gpio_in"; - bias-pull-up; - }; - i2c_lcd_pins: i2c_lcd_pin@0 { pins = "PA23", "PA24"; function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index fc49d14059b1..5a3b0face30e 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -215,7 +215,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ @@ -241,15 +241,6 @@ status = "okay"; }; -&pio { - mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 { - pins = "PA8"; - function = "gpio_in"; - bias-pull-up; - }; - -}; - &p2wi { status = "okay"; diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/sun6i-a31-i7.dts index 679f0fa7e50c..f3e95d08fefc 100644 --- a/arch/arm/boot/dts/sun6i-a31-i7.dts +++ b/arch/arm/boot/dts/sun6i-a31-i7.dts @@ -144,21 +144,13 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_i7>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ status = "okay"; }; -&pio { - mmc0_cd_pin_i7: mmc0_cd_pin@0 { - pins = "PH22"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_usb1_vbus { gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts index 87ae3031aa89..90fb1f603820 100644 --- a/arch/arm/boot/dts/sun6i-a31-m9.dts +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -102,7 +102,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ @@ -122,14 +122,6 @@ #include "axp22x.dtsi" -&pio { - mmc0_cd_pin_m9: mmc0_cd_pin@0 { - pins = "PH22"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_aldo1 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts index 0711f55945e0..3dcf44580839 100644 --- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts +++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts @@ -102,7 +102,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ @@ -122,14 +122,6 @@ #include "axp22x.dtsi" -&pio { - mmc0_cd_pin_m9: mmc0_cd_pin@0 { - pins = "PH22"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_aldo1 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index dd6ede6a8377..55d60c68694e 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -146,7 +146,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_primo81>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ @@ -159,12 +159,6 @@ function = "gpio_in"; bias-pull-up; }; - - mmc0_cd_pin_primo81: mmc0_cd_pin@0 { - pins = "PA8"; - function = "gpio_in"; - bias-pull-up; - }; }; &p2wi { diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts index 1b07a950cb45..02c9a90fe876 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts @@ -162,7 +162,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina31s>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ @@ -173,14 +173,6 @@ status = "okay"; }; -&pio { - mmc0_cd_pin_sina31s: mmc0_cd_pin@0 { - pins = "PA4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_dldo1 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts index ea29af15125b..016b23831cec 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts @@ -113,7 +113,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ @@ -163,14 +163,6 @@ }; }; -&pio { - mmc0_cd_pin_bpi_m2: mmc0_cd_pin@0 { - pins = "PA4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - #include "axp22x.dtsi" ®_aldo1 { diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts index aab6c1720ef7..2d8dc4321b7b 100644 --- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts @@ -89,17 +89,9 @@ status = "okay"; }; -&pio { - mmc0_cd_pin_bs1078v2: mmc0_cd_pin@0 { - pins = "PA8"; - function = "gpio_in"; - bias-pull-up; - }; -}; - &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bs1078v2>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi index 4e72e4f3ef96..77f952b12188 100644 --- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi @@ -66,7 +66,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ @@ -74,12 +74,6 @@ }; &pio { - mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 { - pins = "PA8"; - function = "gpio_in"; - bias-pull-up; - }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { pins = "PA15"; function = "gpio_in"; -- cgit From dea296bc62a45826629a046b6fec7f06d57989cd Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 10:44:54 +0100 Subject: ARM: dts: sun6i: Remove redundant MMC pinmux tuning Some boards override the MMC pin muxing settings in order to enable the pull-ups and change the drive strength to a value higher than the default. While this was needed in the earlier days, this is now the default setting for those pins, and therefore we don't need those board-specific settings anymore. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun6i-a31-colombus.dts | 4 ---- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 5 ----- arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 8 -------- arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 4 ---- 4 files changed, 21 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index 21584c2f968f..f9c4169a875d 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -121,10 +121,6 @@ status = "okay"; }; -&mmc0_pins_a { - bias-pull-up; -}; - &pio { i2c_lcd_pins: i2c_lcd_pin@0 { pins = "PA23", "PA24"; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 5a3b0face30e..21bceecc952d 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -222,11 +222,6 @@ status = "okay"; }; -&mmc0_pins_a { - /* external pull-ups missing for some pins */ - bias-pull-up; -}; - &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>; diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts index 016b23831cec..14e27e81ddf8 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts @@ -120,10 +120,6 @@ status = "okay"; }; -&mmc0_pins_a { - bias-pull-up; -}; - &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_a>; @@ -142,10 +138,6 @@ }; }; -&mmc2_pins_a { - bias-pull-up; -}; - &ohci0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts index 2d8dc4321b7b..153e40d6f4c5 100644 --- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts @@ -98,10 +98,6 @@ status = "okay"; }; -&mmc0_pins_a { - bias-pull-up; -}; - &p2wi { status = "okay"; -- cgit From 9b60a3bfd8406f3143fe30bf797b5851b7d5ff88 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 10:58:01 +0100 Subject: ARM: dts: sun6i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 2 +- arch/arm/boot/dts/sun6i-a31-colombus.dts | 12 ++++---- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 16 +++++----- arch/arm/boot/dts/sun6i-a31-i7.dts | 10 +++---- arch/arm/boot/dts/sun6i-a31-m9.dts | 8 ++--- arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 8 ++--- arch/arm/boot/dts/sun6i-a31.dtsi | 34 +++++++++++----------- arch/arm/boot/dts/sun6i-a31s-cs908.dts | 6 ++-- arch/arm/boot/dts/sun6i-a31s-inet-q972.dts | 2 +- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 8 ++--- arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 2 +- arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 8 ++--- arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 10 +++---- .../dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 8 ++--- .../boot/dts/sun6i-reference-design-tablet.dtsi | 2 +- 15 files changed, 68 insertions(+), 68 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts index f26b84b61daf..32d22025ac99 100644 --- a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts +++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts @@ -72,7 +72,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index f9c4169a875d..d7a19664bae9 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -77,7 +77,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; status = "okay"; @@ -89,19 +89,19 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "fail"; }; &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; mma8452: mma8452@1d { @@ -114,7 +114,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ @@ -136,7 +136,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 21bceecc952d..7035ad63a045 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -160,7 +160,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; @@ -185,20 +185,20 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; /* pull-ups and devices require AXP221 DLDO3 */ status = "failed"; }; &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; pcf8563: rtc@51 { @@ -209,13 +209,13 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&s_ir_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ @@ -224,7 +224,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_aldo1>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; @@ -331,7 +331,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/sun6i-a31-i7.dts index f3e95d08fefc..6f2bba8b7dd0 100644 --- a/arch/arm/boot/dts/sun6i-a31-i7.dts +++ b/arch/arm/boot/dts/sun6i-a31-i7.dts @@ -116,7 +116,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_mii_pins>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -138,13 +138,13 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&s_ir_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ @@ -158,7 +158,7 @@ &spdif { pinctrl-names = "default"; - pinctrl-0 = <&spdif_pins_a>; + pinctrl-0 = <&spdif_tx_pin>; spdif-out = "okay"; status = "okay"; }; @@ -169,7 +169,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts index 90fb1f603820..b65aa90a9167 100644 --- a/arch/arm/boot/dts/sun6i-a31-m9.dts +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -83,7 +83,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_mii_pins>; phy = <&phy1>; phy-mode = "mii"; phy-supply = <®_dldo1>; @@ -96,13 +96,13 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&s_ir_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ @@ -201,7 +201,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts index 3dcf44580839..c3a85aac44d5 100644 --- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts +++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts @@ -83,7 +83,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_mii_pins>; phy = <&phy1>; phy-mode = "mii"; phy-supply = <®_dldo1>; @@ -96,13 +96,13 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&s_ir_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ @@ -201,7 +201,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 5355213f73b9..cd095fb369e5 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -606,7 +606,7 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - gmac_pins_gmii_a: gmac_gmii@0 { + gmac_gmii_pins: gmac-gmii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", "PA11", @@ -622,7 +622,7 @@ drive-strength = <30>; }; - gmac_pins_mii_a: gmac_mii@0 { + gmac_mii_pins: gmac-mii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA8", "PA9", "PA11", "PA12", "PA13", "PA14", "PA19", @@ -631,7 +631,7 @@ function = "gmac"; }; - gmac_pins_rgmii_a: gmac_rgmii@0 { + gmac_rgmii_pins: gmac-rgmii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA19", @@ -644,22 +644,22 @@ drive-strength = <40>; }; - i2c0_pins_a: i2c0@0 { + i2c0_pins: i2c0-pins { pins = "PH14", "PH15"; function = "i2c0"; }; - i2c1_pins_a: i2c1@0 { + i2c1_pins: i2c1-pins { pins = "PH16", "PH17"; function = "i2c1"; }; - i2c2_pins_a: i2c2@0 { + i2c2_pins: i2c2-pins { pins = "PH18", "PH19"; function = "i2c2"; }; - lcd0_rgb888_pins: lcd0_rgb888 { + lcd0_rgb888_pins: lcd0-rgb888-pins { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", @@ -670,7 +670,7 @@ function = "lcd0"; }; - mmc0_pins_a: mmc0@0 { + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -678,7 +678,7 @@ bias-pull-up; }; - mmc1_pins_a: mmc1@0 { + mmc1_pins: mmc1-pins { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1"; @@ -686,7 +686,7 @@ bias-pull-up; }; - mmc2_pins_a: mmc2@0 { + mmc2_4bit_pins: mmc2-4bit-pins { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11"; function = "mmc2"; @@ -694,7 +694,7 @@ bias-pull-up; }; - mmc2_8bit_emmc_pins: mmc2@1 { + mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", @@ -704,7 +704,7 @@ bias-pull-up; }; - mmc3_8bit_emmc_pins: mmc3@1 { + mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", @@ -714,12 +714,12 @@ bias-pull-up; }; - spdif_pins_a: spdif@0 { + spdif_tx_pin: spdif-tx-pin { pins = "PH28"; function = "spdif"; }; - uart0_pins_a: uart0@0 { + uart0_ph_pins: uart0-ph-pins { pins = "PH20", "PH21"; function = "uart0"; }; @@ -1372,12 +1372,12 @@ #size-cells = <0>; #gpio-cells = <3>; - ir_pins_a: ir@0 { + s_ir_rx_pin: s-ir-rx-pin { pins = "PL4"; function = "s_ir"; }; - p2wi_pins: p2wi { + s_p2wi_pins: s-p2wi-pins { pins = "PL0", "PL1"; function = "s_p2wi"; }; @@ -1391,7 +1391,7 @@ clock-frequency = <100000>; resets = <&apb0_rst 3>; pinctrl-names = "default"; - pinctrl-0 = <&p2wi_pins>; + pinctrl-0 = <&s_p2wi_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts index 75e578159c3a..72a02c045a38 100644 --- a/arch/arm/boot/dts/sun6i-a31s-cs908.dts +++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts @@ -66,7 +66,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_mii_pins>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -77,7 +77,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&s_ir_rx_pin>; status = "okay"; }; @@ -87,7 +87,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts b/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts index 85dab04be261..cc518740b700 100644 --- a/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts +++ b/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts @@ -55,7 +55,7 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; ft5406ee8: touchscreen@38 { diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index 55d60c68694e..645d405fcfcc 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -91,13 +91,13 @@ &i2c0 { /* pull-ups and device VDDIO use AXP221 DLDO3 */ pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "failed"; }; &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; ctp@5d { @@ -111,7 +111,7 @@ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; accelerometer@1c { @@ -146,7 +146,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi index d7325bc4eeb4..3099491de8c4 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi @@ -135,7 +135,7 @@ /* UART0 pads available on core board */ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts index 02c9a90fe876..0be033f4942d 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts @@ -114,7 +114,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_mii_pins>; phy = <&phy1>; phy-mode = "mii"; phy-supply = <®_dldo1>; @@ -137,7 +137,7 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&s_ir_rx_pin>; status = "okay"; }; @@ -162,7 +162,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ @@ -181,7 +181,7 @@ &spdif { pinctrl-names = "default"; - pinctrl-0 = <&spdif_pins_a>; + pinctrl-0 = <&spdif_tx_pin>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts index 14e27e81ddf8..4ee496c531d7 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts @@ -91,7 +91,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; phy-supply = <®_dldo1>; @@ -107,13 +107,13 @@ &ir { pinctrl-names = "default"; - pinctrl-0 = <&ir_pins_a>; + pinctrl-0 = <&s_ir_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ @@ -122,7 +122,7 @@ &mmc2 { pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; + pinctrl-0 = <&mmc2_4bit_pins>; vmmc-supply = <®_aldo1>; mmc-pwrseq = <&mmc2_pwrseq>; bus-width = <4>; @@ -254,7 +254,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts index 153e40d6f4c5..13525620bab5 100644 --- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts @@ -63,13 +63,13 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -91,7 +91,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ @@ -177,7 +177,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi index 77f952b12188..a506d740dee3 100644 --- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi @@ -66,7 +66,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ -- cgit From e3797192428428c7bc2d18bcad8d894e04c231a3 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 21:42:36 +0100 Subject: ARM: dts: sun6i: Remove underscores from nodes names Some GPIO pinctrl nodes cannot be easily removed, because they would also change the pin configuration, for example to add a pull resistor or change the current delivered by the pin. Those nodes still have underscores and unit-addresses in their node names in our DTs, so adjust their name to remove the warnings. Use that occasion to also fix some poorly chosen node-names. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun6i-a31-colombus.dts | 2 +- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 2 +- arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index d7a19664bae9..99f25b2d5189 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -122,7 +122,7 @@ }; &pio { - i2c_lcd_pins: i2c_lcd_pin@0 { + i2c_lcd_pins: i2c-lcd-pins { pins = "PA23", "PA24"; function = "gpio_out"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index 645d405fcfcc..ba378affd497 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -154,7 +154,7 @@ }; &pio { - mma8452_int_primo81: mma8452_int_pin@0 { + mma8452_int_primo81: mma8452-int-pin { pins = "PA9"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi index a506d740dee3..86143de21c22 100644 --- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi @@ -74,7 +74,7 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PA15"; function = "gpio_in"; bias-pull-up; -- cgit From 403fa08b29dc3d86c4103105953d429f7f6a1ead Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 7 Sep 2018 16:34:40 +0200 Subject: ARM: dts: sun6i: colombus: Change i2c node name to avoid warnings Our I2C GPIO bus node name has a unit address, but no reg property, which generates a warning in DTC. Change the name to remove that unit address. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun6i-a31-colombus.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index 99f25b2d5189..6aa3f5d074bd 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -60,7 +60,7 @@ stdout-path = "serial0:115200n8"; }; - i2c_lcd: i2c@0 { + i2c_lcd: i2c { /* The lcd panel i2c interface is hooked up via gpios */ compatible = "i2c-gpio"; pinctrl-names = "default"; -- cgit From 1f8bed29730273540be248fa45db6410d63c3a69 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 22:03:28 +0100 Subject: ARM: dts: sun6i: Provide default muxing for relevant controllers The I2C and MMC controllers have only one muxing option in the SoC. In such a case, we can just move the muxing into the DTSI, and remove it from the DTS. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun6i-a31-colombus.dts | 8 -------- arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 10 ---------- arch/arm/boot/dts/sun6i-a31-i7.dts | 2 -- arch/arm/boot/dts/sun6i-a31-m9.dts | 2 -- arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 2 -- arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++ arch/arm/boot/dts/sun6i-a31s-inet-q972.dts | 2 -- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 8 -------- arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 2 -- arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2 -- arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 6 ------ 11 files changed, 10 insertions(+), 44 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index 6aa3f5d074bd..0b7bedf85fb9 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -88,20 +88,14 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "fail"; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; mma8452: mma8452@1d { @@ -113,8 +107,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 7035ad63a045..e17a65b3561e 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -184,21 +184,15 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; /* pull-ups and devices require AXP221 DLDO3 */ status = "failed"; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; pcf8563: rtc@51 { @@ -214,8 +208,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ @@ -223,8 +215,6 @@ }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; vmmc-supply = <®_aldo1>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/sun6i-a31-i7.dts index 6f2bba8b7dd0..0832ac5ae3ec 100644 --- a/arch/arm/boot/dts/sun6i-a31-i7.dts +++ b/arch/arm/boot/dts/sun6i-a31-i7.dts @@ -143,8 +143,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts index b65aa90a9167..6eafb6361a26 100644 --- a/arch/arm/boot/dts/sun6i-a31-m9.dts +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -101,8 +101,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts index c3a85aac44d5..ca036f97923a 100644 --- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts +++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts @@ -101,8 +101,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */ diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index cd095fb369e5..2ca4f255adbe 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -388,6 +388,8 @@ resets = <&ccu RST_AHB1_MMC0>; reset-names = "ahb"; interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -407,6 +409,8 @@ resets = <&ccu RST_AHB1_MMC1>; reset-names = "ahb"; interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -878,6 +882,8 @@ interrupts = ; clocks = <&ccu CLK_APB2_I2C0>; resets = <&ccu RST_APB2_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -889,6 +895,8 @@ interrupts = ; clocks = <&ccu CLK_APB2_I2C1>; resets = <&ccu RST_APB2_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -900,6 +908,8 @@ interrupts = ; clocks = <&ccu CLK_APB2_I2C2>; resets = <&ccu RST_APB2_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts b/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts index cc518740b700..c5e2c55cdc63 100644 --- a/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts +++ b/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts @@ -54,8 +54,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; ft5406ee8: touchscreen@38 { diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index ba378affd497..60b355f7184c 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -90,14 +90,10 @@ &i2c0 { /* pull-ups and device VDDIO use AXP221 DLDO3 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "failed"; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; ctp@5d { @@ -110,8 +106,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; accelerometer@1c { @@ -145,8 +139,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts index 0be033f4942d..4865c3271ab0 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts @@ -161,8 +161,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts index 4ee496c531d7..8e724c52feff 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts @@ -112,8 +112,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts index 13525620bab5..2504e7189c54 100644 --- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts @@ -62,14 +62,10 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -90,8 +86,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ -- cgit From 3bb9d5a682c828e747ab2a0815438dc11c2c6d99 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 09:39:24 +0100 Subject: ARM: dts: sun7i: Remove skeleton and memory to avoid warnings Using skeleton.dtsi will create a memory node that will generate a warning in DTC. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 1ca1fdff2288..3ed0575ed301 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -42,8 +42,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" - #include #include #include @@ -52,6 +50,8 @@ / { interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { ethernet0 = &gmac; @@ -171,10 +171,6 @@ }; }; - memory { - reg = <0x40000000 0x80000000>; - }; - reserved-memory { #address-cells = <1>; #size-cells = <1>; -- cgit From 1a8a50ad6c3306a424908c6d65a84368ca3d5791 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 09:40:48 +0100 Subject: ARM: dts: sun7i: Remove SoC node unit-name to avoid warnings Our main node for all the in-SoC controllers used to have a unit name. The unit-name, in addition to being actually false, would not match any reg property, which generates a warning. Remove it in order to remove those warnings. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 3ed0575ed301..2a88ff58fee4 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -258,7 +258,7 @@ status = "disabled"; }; - soc@1c00000 { + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit From 73732b1d0ef15bf6992ca2f7ed0a5f334ea0635d Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 14:03:42 +0100 Subject: ARM: dts: sun7i: Change clock node names to avoid warnings Our oscillators clock names have a unit address, but no reg property, which generates a warning in DTC. Change these names to remove those unit addresses. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 2a88ff58fee4..9e84dcffc978 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -205,14 +205,14 @@ #size-cells = <1>; ranges; - osc24M: clk@1c20050 { + osc24M: clk-24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; - osc32k: clk@0 { + osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; @@ -228,14 +228,14 @@ * The actual TX clock rate is not controlled by the * gmac_tx clock. */ - mii_phy_tx_clk: clk@1 { + mii_phy_tx_clk: clk-mii-phy-tx { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; clock-output-names = "mii_phy_tx"; }; - gmac_int_tx_clk: clk@2 { + gmac_int_tx_clk: clk-gmac-int-tx { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <125000000>; -- cgit From 8ce97caa3b0a326d96e872b8448a5ef64d3759e6 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 10:39:42 +0100 Subject: ARM: dts: sun7i: Change framebuffer node names to avoid warnings The simple-framebuffer nodes have a unit address, but no reg property which generates a warning when compiling it with DTC. Change the simple-framebuffer node names so that there is no warnings on this anymore. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 9e84dcffc978..c5a6b7a65c52 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -62,7 +62,7 @@ #size-cells = <1>; ranges; - framebuffer@0 { + framebuffer-lcd0-hdmi { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-hdmi"; @@ -73,7 +73,7 @@ status = "disabled"; }; - framebuffer@1 { + framebuffer-lcd0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; @@ -83,7 +83,7 @@ status = "disabled"; }; - framebuffer@2 { + framebuffer-lcd0-tve0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; -- cgit From 054da074b1e02f7fa49c84820883bffd6b03cad0 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 11:14:15 +0100 Subject: ARM: dts: sun7i: Remove all useless pinctrl nodes The gpio pinctrl nodes are redundant and as such useless most of the times. Since they will also generate warnings in DTC, we can simply remove most of them. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 21 ------------ arch/arm/boot/dts/sun7i-a20-bananapi.dts | 14 -------- arch/arm/boot/dts/sun7i-a20-bananapro.dts | 33 ------------------ arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 7 ---- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 40 ---------------------- arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 28 --------------- arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 30 ---------------- arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 14 -------- arch/arm/boot/dts/sun7i-a20-m3.dts | 9 ----- arch/arm/boot/dts/sun7i-a20-mk808c.dts | 14 -------- arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 20 ----------- arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 6 ---- .../boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts | 9 ----- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 12 ------- arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 26 -------------- arch/arm/boot/dts/sun7i-a20-orangepi.dts | 26 -------------- arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 19 ---------- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 14 -------- arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 21 ------------ arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 7 ---- 20 files changed, 370 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index 763cb03033c4..a0483bedb6a1 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -73,8 +73,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_bpi_m1p>; green { label = "bananapi-m1-plus:green:usr"; @@ -90,15 +88,11 @@ mmc3_pwrseq: mmc3_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pwrseq_pin_bpi_m1p>; reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */ }; reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_bpi_m1p>; regulator-name = "gmac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -227,26 +221,11 @@ }; &pio { - gmac_power_pin_bpi_m1p: gmac_power_pin@0 { - pins = "PH23"; - function = "gpio_out"; - }; - - led_pins_bpi_m1p: led_pins@0 { - pins = "PH24", "PH25"; - function = "gpio_out"; - }; - mmc0_cd_pin_bpi_m1p: mmc0_cd_pin@0 { pins = "PH10"; function = "gpio_in"; bias-pull-up; }; - - mmc3_pwrseq_pin_bpi_m1p: mmc3_pwrseq_pin@0 { - pins = "PH22"; - function = "gpio_out"; - }; }; ®_dcdc2 { diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index 70dfc4ac0bb5..c5c183a4c0d8 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -76,8 +76,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_bananapi>; green { label = "bananapi:green:usr"; @@ -87,8 +85,6 @@ reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_bananapi>; regulator-name = "gmac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -263,16 +259,6 @@ function = "gpio_in"; bias-pull-up; }; - - gmac_power_pin_bananapi: gmac_power_pin@0 { - pins = "PH23"; - function = "gpio_out"; - }; - - led_pins_bananapi: led_pins@0 { - pins = "PH24"; - function = "gpio_out"; - }; }; #include "axp209.dtsi" diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts index 0898eb6162f5..f442caf91435 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts @@ -62,8 +62,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_bananapro>; blue { label = "bananapro:blue:usr"; @@ -78,15 +76,11 @@ wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&vmmc3_pin_bananapro>; reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; }; reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_bananapro>; regulator-name = "gmac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -189,46 +183,19 @@ }; &pio { - gmac_power_pin_bananapro: gmac_power_pin@0 { - pins = "PH23"; - function = "gpio_out"; - }; - - led_pins_bananapro: led_pins@0 { - pins = "PH24", "PG2"; - function = "gpio_out"; - }; - mmc0_cd_pin_bananapro: mmc0_cd_pin@0 { pins = "PH10"; function = "gpio_in"; bias-pull-up; }; - - usb1_vbus_pin_bananapro: usb1_vbus_pin@0 { - pins = "PH0"; - function = "gpio_out"; - }; - - usb2_vbus_pin_bananapro: usb2_vbus_pin@0 { - pins = "PH1"; - function = "gpio_out"; - }; - - vmmc3_pin_bananapro: vmmc3_pin@0 { - pins = "PH22"; - function = "gpio_out"; - }; }; ®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_bananapro>; gpio = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */ status = "okay"; }; ®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_bananapro>; gpio = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 942ac9dfd4a5..849244e03f3a 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -74,8 +74,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cubieboard2>; blue { label = "cubieboard2:blue:usr"; @@ -182,11 +180,6 @@ }; &pio { - led_pins_cubieboard2: led_pins@0 { - pins = "PH20", "PH21"; - function = "gpio_out"; - }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { pins = "PH4"; function = "gpio_in"; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 5649161de1d7..0adcd0aab0aa 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -74,8 +74,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_cubietruck>; blue { label = "cubietruck:blue:usr"; @@ -100,8 +98,6 @@ mmc3_pwrseq: mmc3_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pwrseq_pin_cubietruck>; reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ }; @@ -245,38 +241,6 @@ status = "okay"; }; -&pio { - ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { - pins = "PH12"; - function = "gpio_out"; - }; - - led_pins_cubietruck: led_pins@0 { - pins = "PH7", "PH11", "PH20", "PH21"; - function = "gpio_out"; - }; - - mmc3_pwrseq_pin_cubietruck: mmc3_pwrseq_pin@0 { - pins = "PH9"; - function = "gpio_out"; - }; - - usb0_vbus_pin_a: usb0_vbus_pin@0 { - pins = "PH17"; - function = "gpio_out"; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - pins = "PH19"; - function = "gpio_in"; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - pins = "PH22"; - function = "gpio_in"; - }; -}; - &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>; @@ -284,7 +248,6 @@ }; ®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_cubietruck>; gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -325,7 +288,6 @@ }; ®_usb0_vbus { - pinctrl-0 = <&usb0_vbus_pin_a>; gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -360,8 +322,6 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */ usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ usb0_vbus_power-supply = <&usb_power_supply>; diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts index 1f0e5ecbf0c4..6ba689354f22 100644 --- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts +++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts @@ -67,8 +67,6 @@ reg_mmc3_vdd: mmc3_vdd { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_vdd_pin_a20_hummingbird>; regulator-name = "mmc3_vdd"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; @@ -78,8 +76,6 @@ reg_gmac_vdd: gmac_vdd { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_vdd_pin_a20_hummingbird>; regulator-name = "gmac_vdd"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; @@ -184,28 +180,6 @@ status = "okay"; }; -&pio { - ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 { - pins = "PH15"; - function = "gpio_out"; - }; - - usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 { - pins = "PH2"; - function = "gpio_out"; - }; - - mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 { - pins = "PH9"; - function = "gpio_out"; - }; - - gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 { - pins = "PH16"; - function = "gpio_out"; - }; -}; - &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_pins_a>; @@ -213,13 +187,11 @@ }; ®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>; gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ status = "okay"; }; ®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>; gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index 2e3f2f29d124..fe2b827cfa76 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -61,8 +61,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_i12_tvbox>; red { label = "i12_tvbox:red:usr"; @@ -77,8 +75,6 @@ reg_vmmc3: vmmc3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&vmmc3_pin_i12_tvbox>; regulator-name = "vmmc3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -88,8 +84,6 @@ reg_vmmc3_io: vmmc3-io { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&vmmc3_io_pin_i12_tvbox>; regulator-name = "vmmc3-io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -101,8 +95,6 @@ reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_i12_tvbox>; regulator-name = "gmac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -194,28 +186,6 @@ status = "okay"; }; -&pio { - vmmc3_pin_i12_tvbox: vmmc3_pin@0 { - pins = "PH2"; - function = "gpio_out"; - }; - - vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 { - pins = "PH12"; - function = "gpio_out"; - }; - - gmac_power_pin_i12_tvbox: gmac_power_pin@0 { - pins = "PH21"; - function = "gpio_out"; - }; - - led_pins_i12_tvbox: led_pins@0 { - pins = "PH9", "PH20"; - function = "gpio_out"; - }; -}; - ®_usb1_vbus { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index b1ab7c1c33e3..66bc413e846b 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -74,8 +74,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_lamobo_r1>; green { label = "lamobo_r1:green:usr"; @@ -85,8 +83,6 @@ reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_lamobo_r1>; regulator-name = "gmac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -251,16 +247,6 @@ function = "gpio_in"; bias-pull-up; }; - - gmac_power_pin_lamobo_r1: gmac_power_pin@0 { - pins = "PH23"; - function = "gpio_out"; - }; - - led_pins_lamobo_r1: led_pins@0 { - pins = "PH24"; - function = "gpio_out"; - }; }; #include "axp209.dtsi" diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts index e91a209850bc..cb8725d95e2b 100644 --- a/arch/arm/boot/dts/sun7i-a20-m3.dts +++ b/arch/arm/boot/dts/sun7i-a20-m3.dts @@ -63,8 +63,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_m3>; blue { label = "m3:blue:usr"; @@ -141,13 +139,6 @@ status = "okay"; }; -&pio { - led_pins_m3: led_pins@0 { - pins = "PH20"; - function = "gpio_out"; - }; -}; - ®_usb1_vbus { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts index 6109f794a9c1..a4c5da733fbc 100644 --- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts +++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts @@ -153,18 +153,6 @@ status = "okay"; }; -&pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { - pins = "PH4"; - function = "gpio_in"; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - pins = "PH5"; - function = "gpio_in"; - }; -}; - ®_usb0_vbus { status = "okay"; }; @@ -195,8 +183,6 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ usb0_vbus-supply = <®_usb0_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index f080f82b58ef..f54820d9b2d9 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -74,8 +74,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_olimex_som_evb>; green { label = "a20-olimex-som-evb:green:usr"; @@ -241,11 +239,6 @@ }; &pio { - ahci_pwr_pin_olimex_som_evb: ahci_pwr_pin@1 { - pins = "PC3"; - function = "gpio_out"; - }; - led_pins_olimex_som_evb: led_pins@0 { pins = "PH2"; function = "gpio_out"; @@ -257,20 +250,9 @@ function = "gpio_in"; bias-pull-up; }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - pins = "PH4"; - function = "gpio_in"; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - pins = "PH5"; - function = "gpio_in"; - }; }; ®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_olimex_som_evb>; gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -352,8 +334,6 @@ }; &usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH04 */ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH05 */ usb0_vbus-supply = <®_usb0_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index d20fd03596e9..46cd00ba8a74 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -175,11 +175,6 @@ }; &pio { - ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - pins = "PC3"; - function = "gpio_out"; - }; - led_pins_olinuxinolime: led_pins@0 { pins = "PH2"; function = "gpio_out"; @@ -200,7 +195,6 @@ }; ®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts index 81f376f2a44d..727dffe1db05 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts @@ -48,20 +48,11 @@ compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20"; mmc2_pwrseq: pwrseq { - pinctrl-0 = <&mmc2_pins_nrst>; - pinctrl-names = "default"; compatible = "mmc-pwrseq-emmc"; reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; }; }; -&pio { - mmc2_pins_nrst: mmc2-rst-pin { - pins = "PC16"; - function = "gpio_out"; - }; -}; - &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index fbdb6faffcd4..ed6f4e1e94b3 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -180,11 +180,6 @@ }; &pio { - ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { - pins = "PC3"; - function = "gpio_out"; - }; - led_pins_olinuxinolime: led_pins@0 { pins = "PH2"; function = "gpio_out"; @@ -202,15 +197,9 @@ function = "gpio_in"; bias-pull-down; }; - - usb0_vbus_pin_lime2: usb0_vbus_pin@0 { - pins = "PC17"; - function = "gpio_out"; - }; }; ®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -258,7 +247,6 @@ }; ®_usb0_vbus { - pinctrl-0 = <&usb0_vbus_pin_lime2>; gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts index f5c7178eb063..b45a61dea108 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts @@ -74,8 +74,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_orangepi>; green { label = "orangepi:green:usr"; @@ -90,8 +88,6 @@ reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_orangepi>; regulator-name = "gmac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -204,26 +200,6 @@ function = "gpio_in"; bias-pull-up; }; - - usb2_vbus_pin_bananapro: usb2_vbus_pin@0 { - pins = "PH22"; - function = "gpio_out"; - }; - - gmac_power_pin_orangepi: gmac_power_pin@0 { - pins = "PH23"; - function = "gpio_out"; - }; - - led_pins_orangepi: led_pins@0 { - pins = "PH24", "PH25"; - function = "gpio_out"; - }; - - usb1_vbus_pin_bananapro: usb1_vbus_pin@0 { - pins = "PH26"; - function = "gpio_out"; - }; }; ®_dcdc2 { @@ -256,13 +232,11 @@ }; ®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_bananapro>; gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ status = "okay"; }; ®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_bananapro>; gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts index 7a4244e57589..a5c5948e44f7 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts @@ -63,8 +63,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_orangepi>; green { label = "orangepi:green:usr"; @@ -74,8 +72,6 @@ reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_orangepi>; regulator-name = "gmac-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -155,26 +151,6 @@ function = "gpio_in"; bias-pull-up; }; - - usb2_vbus_pin_bananapro: usb2_vbus_pin@0 { - pins = "PH22"; - function = "gpio_out"; - }; - - gmac_power_pin_orangepi: gmac_power_pin@0 { - pins = "PH23"; - function = "gpio_out"; - }; - - led_pins_orangepi: led_pins@0 { - pins = "PH24"; - function = "gpio_out"; - }; - - usb1_vbus_pin_bananapro: usb1_vbus_pin@0 { - pins = "PH26"; - function = "gpio_out"; - }; }; ®_dcdc2 { @@ -207,13 +183,11 @@ }; ®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_bananapro>; gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */ status = "okay"; }; ®_usb2_vbus { - pinctrl-0 = <&usb2_vbus_pin_bananapro>; gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */ status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts index bfca960b03e0..5e538a23476c 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts @@ -71,8 +71,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_pcduino3_nano>; /* Marked "LED3" on the PCB. */ usr1 { @@ -175,30 +173,14 @@ }; &pio { - ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin@0 { - pins = "PH2"; - function = "gpio_out"; - }; - - led_pins_pcduino3_nano: led_pins@0 { - pins = "PH16", "PH15"; - function = "gpio_out"; - }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - - usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 { - pins = "PD2"; - function = "gpio_out"; - }; }; ®_ahci_5v { - pinctrl-0 = <&ahci_pwr_pin_pcduino3_nano>; gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ status = "okay"; }; @@ -232,7 +214,6 @@ /* A single regulator (U24) powers both USB host ports. */ ®_usb1_vbus { - pinctrl-0 = <&usb1_vbus_pin_pcduino3_nano>; gpio = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index c576f101fbde..fc5319836752 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -63,8 +63,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_pcduino3>; tx { label = "pcduino3:green:tx"; @@ -79,8 +77,6 @@ gpio_keys { compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&key_pins_pcduino3>; #address-cells = <1>; #size-cells = <0>; button@0 { @@ -176,16 +172,6 @@ }; &pio { - led_pins_pcduino3: led_pins@0 { - pins = "PH15", "PH16"; - function = "gpio_out"; - }; - - key_pins_pcduino3: key_pins@0 { - pins = "PH17", "PH18", "PH19"; - function = "gpio_in"; - }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { pins = "PH4"; function = "gpio_in"; diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts index 8202c87ca6a3..b526890a3203 100644 --- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts +++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts @@ -63,8 +63,6 @@ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_enable_pin>; enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ }; @@ -74,8 +72,6 @@ }; &codec { - pinctrl-names = "default"; - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ status = "okay"; }; @@ -122,8 +118,6 @@ reg = <0x5d>; interrupt-parent = <&pio>; interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; /* EINT21 (PH21) */ - pinctrl-names = "default"; - pinctrl-0 = <&ts_reset_pin>; irq-gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* INT (PH21) */ reset-gpios = <&pio 1 13 GPIO_ACTIVE_HIGH>; /* RST (PB13) */ touchscreen-swapped-x-y; @@ -171,21 +165,6 @@ }; &pio { - bl_enable_pin: bl_enable_pin@0 { - pins = "PH7"; - function = "gpio_out"; - }; - - codec_pa_pin: codec_pa_pin@0 { - pins = "PH15"; - function = "gpio_out"; - }; - - ts_reset_pin: ts_reset_pin@0 { - pins = "PB13"; - function = "gpio_out"; - }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { pins = "PH4"; function = "gpio_in"; diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts index ff5c1086585c..bf4f51160737 100644 --- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -62,8 +62,6 @@ mmc3_pwrseq: mmc3_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&vmmc3_pin_ap6xxx_wl_regon>; reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ }; }; @@ -158,11 +156,6 @@ }; &pio { - vmmc3_pin_ap6xxx_wl_regon: vmmc3_pin@0 { - pins = "PH9"; - function = "gpio_out"; - }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { pins = "PH4"; function = "gpio_in"; -- cgit From 8860687aaccd59f437c165086772f345b5268e15 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 21:03:20 +0100 Subject: ARM: dts: sun7i: Remove card detect pull-up Boards usually have an external pull-up on the card-detect signal, so there's no need to add another one. This also removes a DTC warning. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 10 +--------- arch/arm/boot/dts/sun7i-a20-bananapi.dts | 8 +------- arch/arm/boot/dts/sun7i-a20-bananapro.dts | 10 +--------- arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 8 +------- arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 8 +------- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 8 +------- arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 16 ++-------------- arch/arm/boot/dts/sun7i-a20-orangepi.dts | 8 +------- 8 files changed, 9 insertions(+), 67 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index a0483bedb6a1..ccd7b313448e 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -175,7 +175,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m1p>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -220,14 +220,6 @@ status = "okay"; }; -&pio { - mmc0_cd_pin_bpi_m1p: mmc0_cd_pin@0 { - pins = "PH10"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index c5c183a4c0d8..339c48a477f5 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -177,7 +177,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -253,12 +253,6 @@ function = "gpio_in"; bias-pull-up; }; - - mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { - pins = "PH10"; - function = "gpio_in"; - bias-pull-up; - }; }; #include "axp209.dtsi" diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts index f442caf91435..a4c0a38e1262 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts @@ -149,7 +149,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapro>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -182,14 +182,6 @@ status = "okay"; }; -&pio { - mmc0_cd_pin_bananapro: mmc0_cd_pin@0 { - pins = "PH10"; - function = "gpio_in"; - bias-pull-up; - }; -}; - ®_usb1_vbus { gpio = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */ status = "okay"; diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 66bc413e846b..cccfee6add35 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -220,7 +220,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -241,12 +241,6 @@ function = "gpio_in"; bias-pull-up; }; - - mmc0_cd_pin_lamobo_r1: mmc0_cd_pin@0 { - pins = "PH10"; - function = "gpio_in"; - bias-pull-up; - }; }; #include "axp209.dtsi" diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index f54820d9b2d9..892b84bbf357 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -219,7 +219,7 @@ &mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olimex_som_evb>; + pinctrl-0 = <&mmc3_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */ @@ -244,12 +244,6 @@ function = "gpio_out"; drive-strength = <20>; }; - - mmc3_cd_pin_olimex_som_evb: mmc3_cd_pin@0 { - pins = "PH0"; - function = "gpio_in"; - bias-pull-up; - }; }; ®_ahci_5v { diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 866d230593be..50e7229727a6 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -232,7 +232,7 @@ &mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; + pinctrl-0 = <&mmc3_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ @@ -257,12 +257,6 @@ function = "gmac"; }; - mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { - pins = "PH11"; - function = "gpio_in"; - bias-pull-up; - }; - led_pins_olinuxino: led_pins@0 { pins = "PH2"; function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts index b45a61dea108..c138e39ac072 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts @@ -162,7 +162,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -171,7 +171,7 @@ &mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_orangepi>; + pinctrl-0 = <&mmc3_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ @@ -188,18 +188,6 @@ function = "gpio_in"; bias-pull-up; }; - - mmc0_cd_pin_orangepi: mmc0_cd_pin@0 { - pins = "PH10"; - function = "gpio_in"; - bias-pull-up; - }; - - mmc3_cd_pin_orangepi: mmc3_cd_pin@0 { - pins = "PH11"; - function = "gpio_in"; - bias-pull-up; - }; }; ®_dcdc2 { diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts index a5c5948e44f7..4f4821d6466d 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts @@ -128,7 +128,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -145,12 +145,6 @@ function = "gpio_in"; bias-pull-up; }; - - mmc0_cd_pin_orangepi: mmc0_cd_pin@0 { - pins = "PH10"; - function = "gpio_in"; - bias-pull-up; - }; }; ®_dcdc2 { -- cgit From 0b92b823b8d880c6b1c1136a6e0caa47fc3df14a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 14:14:58 +0100 Subject: ARM: dts: sun7i: Change LRADC node names to avoid warnings One of the usage of the LRADC is to implement buttons. The bindings define that we should have one subnode per button, with their associated voltage as a property. However, there was no reg property but we still used the voltage associated to the button as the unit-address, which eventually generated warnings in DTC. Rename the node names to avoid those warnings. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 14 +++++++------- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 14 +++++++------- arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 4 ++-- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index 892b84bbf357..2aa719338dac 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -158,49 +158,49 @@ vref-supply = <®_vcc3v0>; status = "okay"; - button@190 { + button-190 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <190000>; }; - button@390 { + button-390 { label = "Volume Down"; linux,code = ; channel = <0>; voltage = <390000>; }; - button@600 { + button-600 { label = "Menu"; linux,code = ; channel = <0>; voltage = <600000>; }; - button@800 { + button-800 { label = "Search"; linux,code = ; channel = <0>; voltage = <800000>; }; - button@980 { + button-980 { label = "Home"; linux,code = ; channel = <0>; voltage = <980000>; }; - button@1180 { + button-1180 { label = "Esc"; linux,code = ; channel = <0>; voltage = <1180000>; }; - button@1400 { + button-1400 { label = "Enter"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 50e7229727a6..f78f18fd7c1c 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -171,49 +171,49 @@ vref-supply = <®_vcc3v0>; status = "okay"; - button@191 { + button-191 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <191274>; }; - button@392 { + button-392 { label = "Volume Down"; linux,code = ; channel = <0>; voltage = <392644>; }; - button@601 { + button-601 { label = "Menu"; linux,code = ; channel = <0>; voltage = <601151>; }; - button@795 { + button-795 { label = "Search"; linux,code = ; channel = <0>; voltage = <795090>; }; - button@987 { + button-987 { label = "Home"; linux,code = ; channel = <0>; voltage = <987387>; }; - button@1184 { + button-1184 { label = "Esc"; linux,code = ; channel = <0>; voltage = <1184678>; }; - button@1398 { + button-1398 { label = "Enter"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts index b526890a3203..8fd85c6597bf 100644 --- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts +++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts @@ -128,14 +128,14 @@ vref-supply = <®_vcc3v0>; status = "okay"; - button@571 { + button-571 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <571428>; }; - button@761 { + button-761 { label = "Volume Down"; linux,code = ; channel = <0>; -- cgit From c8fd1584f4df4028e278a95796da0b225b2720cd Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 14:16:29 +0100 Subject: ARM: dts: sun7i: Remove gpio-keys warnings Some gpio-keys definitions in our DTs were having buttons defined with a unit-address and that would generate a DTC warning. Change the buttons node names to remove the warnings. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index fc5319836752..0c0997effdf7 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -75,21 +75,22 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + + back { label = "Key Back"; linux,code = ; gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; }; - button@1 { + + home { label = "Key Home"; linux,code = ; gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; }; - button@2 { + + menu { label = "Key Menu"; linux,code = ; gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; -- cgit From 85a8c520ca41c719d552595d0aac456ac84b8a33 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 10:58:01 +0100 Subject: ARM: dts: sun7i: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 14 ++-- arch/arm/boot/dts/sun7i-a20-bananapi.dts | 22 +++--- arch/arm/boot/dts/sun7i-a20-bananapro.dts | 24 +++--- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 12 +-- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 22 +++--- arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 32 ++++---- arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 14 ++-- arch/arm/boot/dts/sun7i-a20-icnova-swac.dts | 10 +-- arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 8 +- arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 22 +++--- arch/arm/boot/dts/sun7i-a20-m3.dts | 12 +-- arch/arm/boot/dts/sun7i-a20-mk808c.dts | 12 +-- .../arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 26 +++---- .../boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts | 30 ++++---- arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 10 +-- .../boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 10 +-- .../boot/dts/sun7i-a20-olinuxino-micro-emmc.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 26 +++---- arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 12 +-- arch/arm/boot/dts/sun7i-a20-orangepi.dts | 10 +-- arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 10 +-- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 10 +-- arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 12 +-- arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 14 ++-- arch/arm/boot/dts/sun7i-a20.dtsi | 88 +++++++++++----------- arch/arm/boot/dts/sunxi-itead-core-common.dtsi | 2 +- 29 files changed, 236 insertions(+), 236 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index ccd7b313448e..af4418de57be 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -128,7 +128,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; phy-supply = <®_gmac_3v3>; @@ -151,7 +151,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -169,13 +169,13 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -186,7 +186,7 @@ #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; + pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc3_pwrseq>; bus-width = <4>; @@ -203,7 +203,7 @@ }; }; -&mmc3_pins_a { +&mmc3_pins { /* AP6210 requires pull-up */ bias-pull-up; }; @@ -251,7 +251,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index 339c48a477f5..af56ae95c63f 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -130,7 +130,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; phy-supply = <®_gmac_3v3>; @@ -153,7 +153,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -165,19 +165,19 @@ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -296,27 +296,27 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>, - <&spi0_cs1_pins_a>; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>, + <&spi0_cs1_pi_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_b>; + pinctrl-0 = <&uart3_ph_pins>; status = "okay"; }; &uart7 { pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; + pinctrl-0 = <&uart7_pi_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts index a4c0a38e1262..567bf6d493f9 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts @@ -108,7 +108,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; phy-supply = <®_gmac_3v3>; @@ -121,7 +121,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -137,19 +137,19 @@ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -158,7 +158,7 @@ &mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; + pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; @@ -194,27 +194,27 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>, - <&spi0_cs1_pins_a>; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>, + <&spi0_cs1_pi_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; &uart4 { pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; + pinctrl-0 = <&uart4_ph_pins>; status = "okay"; }; &uart7 { pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; + pinctrl-0 = <&uart7_pi_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 849244e03f3a..9a027764cda4 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -114,7 +114,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_mii_pins>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -136,7 +136,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -148,19 +148,19 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -232,7 +232,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 0adcd0aab0aa..20069542336f 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -147,7 +147,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; status = "okay"; @@ -169,7 +169,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -181,25 +181,25 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -208,7 +208,7 @@ &mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; + pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc3_pwrseq>; bus-width = <4>; @@ -224,7 +224,7 @@ }; }; -&mmc3_pins_a { +&mmc3_pins { /* AP6210 requires pull-up */ bias-pull-up; }; @@ -243,7 +243,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>; + pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>; status = "okay"; }; @@ -302,13 +302,13 @@ &spdif { pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pins_a>; + pinctrl-0 = <&spdif_tx_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts index 6ba689354f22..9ce59d49cf49 100644 --- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts +++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts @@ -99,7 +99,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; phy-supply = <®_gmac_vdd>; @@ -117,7 +117,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -132,31 +132,31 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &i2c3 { pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins_a>; + pinctrl-0 = <&i2c3_pins>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -165,7 +165,7 @@ &mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; + pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_mmc3_vdd>; bus-width = <4>; non-removable; @@ -182,7 +182,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -202,38 +202,38 @@ &spi2 { pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_b>, - <&spi2_cs0_pins_b>; + pinctrl-0 = <&spi2_pb_pins>, + <&spi2_cs0_pb_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; + pinctrl-0 = <&uart2_pi_pins>; status = "okay"; }; &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_a>; + pinctrl-0 = <&uart3_pg_pins>; status = "okay"; }; &uart4 { pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; + pinctrl-0 = <&uart4_pg_pins>; status = "okay"; }; &uart5 { pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins_a>; + pinctrl-0 = <&uart5_pi_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index fe2b827cfa76..db708332616e 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -114,7 +114,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_mii_pins>; phy = <&phy1>; phy-mode = "mii"; phy-supply = <®_gmac_3v3>; @@ -127,7 +127,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -143,13 +143,13 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -158,7 +158,7 @@ &mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; + pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vmmc3>; bus-width = <4>; non-removable; @@ -173,7 +173,7 @@ }; }; -&mmc3_pins_a { +&mmc3_pins { /* AP6210 / AP6330 requires pull-up */ bias-pull-up; }; @@ -196,7 +196,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts index 926fa194eb1b..0bf70b22bac4 100644 --- a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts +++ b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts @@ -74,7 +74,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_mii_pins>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -86,7 +86,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -98,13 +98,13 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */ @@ -156,7 +156,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts index 1b05ba466e7d..ad97f6f2cc2c 100644 --- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts +++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts @@ -96,7 +96,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_mii_pins>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -115,13 +115,13 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -142,6 +142,6 @@ &spdif { pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pins_a>; + pinctrl-0 = <&spdif_tx_pin>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index cccfee6add35..32e204fe8c15 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -119,7 +119,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy-mode = "rgmii"; phy-supply = <®_gmac_3v3>; status = "okay"; @@ -196,7 +196,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -208,19 +208,19 @@ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -294,27 +294,27 @@ &spi0 { pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_a>, - <&spi0_cs0_pins_a>, - <&spi0_cs1_pins_a>; + pinctrl-0 = <&spi0_pi_pins>, + <&spi0_cs0_pi_pin>, + <&spi0_cs1_pi_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_b>; + pinctrl-0 = <&uart3_ph_pins>; status = "okay"; }; &uart7 { pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; + pinctrl-0 = <&uart7_pi_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts index cb8725d95e2b..1207e0d897b7 100644 --- a/arch/arm/boot/dts/sun7i-a20-m3.dts +++ b/arch/arm/boot/dts/sun7i-a20-m3.dts @@ -81,7 +81,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_mii_pins>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -93,7 +93,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -109,13 +109,13 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -124,7 +124,7 @@ &mmc2 { pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; + pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; @@ -149,7 +149,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts index a4c5da733fbc..a8d15d01ac1a 100644 --- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts +++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts @@ -107,7 +107,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -122,19 +122,19 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -167,13 +167,13 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins_a>; + pinctrl-0 = <&uart2_pi_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts index 81ebc97b76ee..ea0d620119cb 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts @@ -22,7 +22,7 @@ &mmc2 { pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; + pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc2_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index 2aa719338dac..8f8a77121e80 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -110,7 +110,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; status = "okay"; @@ -132,7 +132,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -144,13 +144,13 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -210,7 +210,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -219,7 +219,7 @@ &mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; + pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */ @@ -292,33 +292,33 @@ &spi1 { pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>, - <&spi1_cs0_pins_a>; + pinctrl-0 = <&spi1_pi_pins>, + <&spi1_cs0_pi_pin>; status = "okay"; }; &spi2 { pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>, - <&spi2_cs0_pins_a>; + pinctrl-0 = <&spi2_pc_pins>, + <&spi2_cs0_pc_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; &uart6 { pinctrl-names = "default"; - pinctrl-0 = <&uart6_pins_a>; + pinctrl-0 = <&uart6_pi_pins>; status = "okay"; }; &uart7 { pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; + pinctrl-0 = <&uart7_pi_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts index c56620a8fb20..093cd32c9a1c 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts @@ -21,7 +21,7 @@ &mmc2 { pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; + pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc2_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts index 3d7b5c848fef..631a80ae958e 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts @@ -78,7 +78,7 @@ &can0 { pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; + pinctrl-0 = <&can_ph_pins>; status = "okay"; }; @@ -104,7 +104,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy3>; phy-mode = "rgmii"; phy-supply = <®_vcc3v3>; @@ -131,7 +131,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -144,7 +144,7 @@ /* Exposed to UEXT1 */ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; eeprom: eeprom@50 { @@ -157,19 +157,19 @@ /* Exposed to UEXT2 */ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; @@ -178,7 +178,7 @@ &mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; + pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&rtl_pwrseq>; bus-width = <4>; @@ -274,22 +274,22 @@ /* Exposed to UEXT1 */ &spi1 { pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>, - <&spi1_cs0_pins_a>; + pinctrl-0 = <&spi1_pi_pins>, + <&spi1_cs0_pi_pin>; status = "okay"; }; /* Exposed to UEXT2 */ &spi2 { pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>, - <&spi2_cs0_pins_a>; + pinctrl-0 = <&spi2_pc_pins>, + <&spi2_cs0_pc_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; @@ -303,14 +303,14 @@ /* Exposed to UEXT1 */ &uart4 { pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; + pinctrl-0 = <&uart4_pg_pins>; status = "okay"; }; /* Exposed to UEXT2 */ &uart7 { pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; + pinctrl-0 = <&uart7_pi_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index 46cd00ba8a74..7d6a90678025 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -105,7 +105,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_mii_pins>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -127,7 +127,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -143,7 +143,7 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; eeprom: eeprom@50 { @@ -155,7 +155,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -213,7 +213,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts index 727dffe1db05..0a2a26f9a5fb 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts @@ -55,7 +55,7 @@ &mmc2 { pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; + pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc3v3>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index ed6f4e1e94b3..9ea84cf6437b 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -110,7 +110,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; status = "okay"; @@ -132,7 +132,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -144,7 +144,7 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; eeprom: eeprom@50 { @@ -160,7 +160,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -261,7 +261,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts index d99e7b193efe..58fd3519ab7d 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts @@ -55,7 +55,7 @@ &mmc2 { pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; + pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index f78f18fd7c1c..4cef69e90b2f 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -117,7 +117,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>, <&gmac_txerr>; + pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -139,7 +139,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -151,7 +151,7 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; eeprom: eeprom@50 { @@ -163,7 +163,7 @@ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -223,7 +223,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -232,7 +232,7 @@ &mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; + pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ @@ -325,33 +325,33 @@ &spi1 { pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>, - <&spi1_cs0_pins_a>; + pinctrl-0 = <&spi1_pi_pins>, + <&spi1_cs0_pi_pin>; status = "okay"; }; &spi2 { pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>, - <&spi2_cs0_pins_a>; + pinctrl-0 = <&spi2_pc_pins>, + <&spi2_cs0_pc_pin>; status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; &uart6 { pinctrl-names = "default"; - pinctrl-0 = <&uart6_pins_a>; + pinctrl-0 = <&uart6_pi_pins>; status = "okay"; }; &uart7 { pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; + pinctrl-0 = <&uart7_pi_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts index c138e39ac072..192d907fee71 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts @@ -119,7 +119,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; phy-supply = <®_gmac_3v3>; @@ -142,7 +142,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -156,13 +156,13 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -171,7 +171,7 @@ &mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; + pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ @@ -231,7 +231,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts index 4f4821d6466d..c71d819cd0af 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts @@ -95,7 +95,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; phy-supply = <®_gmac_3v3>; @@ -108,7 +108,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -122,13 +122,13 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -188,7 +188,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts index 5e538a23476c..1ba1dd6de244 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts @@ -113,7 +113,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; status = "okay"; @@ -135,7 +135,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -147,13 +147,13 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -220,7 +220,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index 0c0997effdf7..77a49e8b3d20 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -121,7 +121,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_mii_a>; + pinctrl-0 = <&gmac_mii_pins>; phy = <&phy1>; phy-mode = "mii"; status = "okay"; @@ -133,7 +133,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -147,13 +147,13 @@ &ir0 { pinctrl-names = "default"; - pinctrl-0 = <&ir0_rx_pins_a>; + pinctrl-0 = <&ir0_rx_pin>; status = "okay"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -220,7 +220,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts index 8fd85c6597bf..23b7d127e14f 100644 --- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts +++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts @@ -90,7 +90,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -104,13 +104,13 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; gt911: touchscreen@5d { @@ -145,7 +145,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -174,7 +174,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins_a>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; @@ -217,7 +217,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts index bf4f51160737..1df18959d2a9 100644 --- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -80,7 +80,7 @@ &gmac { pinctrl-names = "default"; - pinctrl-0 = <&gmac_pins_rgmii_a>; + pinctrl-0 = <&gmac_rgmii_pins>; phy = <&phy1>; phy-mode = "rgmii"; status = "okay"; @@ -92,7 +92,7 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -104,13 +104,13 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -118,7 +118,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -127,7 +127,7 @@ &mmc3 { pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins_a>; + pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc3_pwrseq>; bus-width = <4>; @@ -202,7 +202,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index c5a6b7a65c52..75669fc51de5 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -747,22 +747,22 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - can0_pins_a: can0@0 { + can_ph_pins: can-ph-pins { pins = "PH20", "PH21"; function = "can"; }; - clk_out_a_pins_a: clk_out_a@0 { + clk_out_a_pin: clk-out-a-pin { pins = "PI12"; function = "clk_out_a"; }; - clk_out_b_pins_a: clk_out_b@0 { + clk_out_b_pin: clk-out-b-pin { pins = "PI13"; function = "clk_out_b"; }; - emac_pins_a: emac0@0 { + emac_pa_pins: emac-pa-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", @@ -771,7 +771,7 @@ function = "emac"; }; - gmac_pins_mii_a: gmac_mii@0 { + gmac_mii_pins: gmac-mii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", @@ -780,7 +780,7 @@ function = "gmac"; }; - gmac_pins_rgmii_a: gmac_rgmii@0 { + gmac_rgmii_pins: gmac-rgmii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA10", @@ -794,47 +794,47 @@ drive-strength = <40>; }; - i2c0_pins_a: i2c0@0 { + i2c0_pins: i2c0-pins { pins = "PB0", "PB1"; function = "i2c0"; }; - i2c1_pins_a: i2c1@0 { + i2c1_pins: i2c1-pins { pins = "PB18", "PB19"; function = "i2c1"; }; - i2c2_pins_a: i2c2@0 { + i2c2_pins: i2c2-pins { pins = "PB20", "PB21"; function = "i2c2"; }; - i2c3_pins_a: i2c3@0 { + i2c3_pins: i2c3-pins { pins = "PI0", "PI1"; function = "i2c3"; }; - ir0_rx_pins_a: ir0@0 { + ir0_rx_pin: ir0-rx-pin { pins = "PB4"; function = "ir0"; }; - ir0_tx_pins_a: ir0@1 { + ir0_tx_pin: ir0-tx-pin { pins = "PB3"; function = "ir0"; }; - ir1_rx_pins_a: ir1@0 { + ir1_rx_pin: ir1-rx-pin { pins = "PB23"; function = "ir1"; }; - ir1_tx_pins_a: ir1@1 { + ir1_tx_pin: ir1-tx-pin { pins = "PB22"; function = "ir1"; }; - mmc0_pins_a: mmc0@0 { + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -842,7 +842,7 @@ bias-pull-up; }; - mmc2_pins_a: mmc2@0 { + mmc2_pins: mmc2-pins { pins = "PC6", "PC7", "PC8", "PC9", "PC10", "PC11"; function = "mmc2"; @@ -850,7 +850,7 @@ bias-pull-up; }; - mmc3_pins_a: mmc3@0 { + mmc3_pins: mmc3-pins { pins = "PI4", "PI5", "PI6", "PI7", "PI8", "PI9"; function = "mmc3"; @@ -858,118 +858,118 @@ bias-pull-up; }; - ps20_pins_a: ps20@0 { + ps2_0_pins: ps2-0-pins { pins = "PI20", "PI21"; function = "ps2"; }; - ps21_pins_a: ps21@0 { + ps2_1_ph_pins: ps2-1-ph-pins { pins = "PH12", "PH13"; function = "ps2"; }; - pwm0_pins_a: pwm0@0 { + pwm0_pin: pwm0-pin { pins = "PB2"; function = "pwm"; }; - pwm1_pins_a: pwm1@0 { + pwm1_pin: pwm1-pin { pins = "PI3"; function = "pwm"; }; - spdif_tx_pins_a: spdif@0 { + spdif_tx_pin: spdif-tx-pin { pins = "PB13"; function = "spdif"; bias-pull-up; }; - spi0_pins_a: spi0@0 { + spi0_pi_pins: spi0-pi-pins { pins = "PI11", "PI12", "PI13"; function = "spi0"; }; - spi0_cs0_pins_a: spi0_cs0@0 { + spi0_cs0_pi_pin: spi0-cs0-pi-pin { pins = "PI10"; function = "spi0"; }; - spi0_cs1_pins_a: spi0_cs1@0 { + spi0_cs1_pi_pin: spi0-cs1-pi-pin { pins = "PI14"; function = "spi0"; }; - spi1_pins_a: spi1@0 { + spi1_pi_pins: spi1-pi-pins { pins = "PI17", "PI18", "PI19"; function = "spi1"; }; - spi1_cs0_pins_a: spi1_cs0@0 { + spi1_cs0_pi_pin: spi1-cs0-pi-pin { pins = "PI16"; function = "spi1"; }; - spi2_pins_a: spi2@0 { - pins = "PC20", "PC21", "PC22"; + spi2_pb_pins: spi2-pb-pins { + pins = "PB15", "PB16", "PB17"; function = "spi2"; }; - spi2_pins_b: spi2@1 { - pins = "PB15", "PB16", "PB17"; + spi2_cs0_pb_pin: spi2-cs0-pb-pin { + pins = "PB14"; function = "spi2"; }; - spi2_cs0_pins_a: spi2_cs0@0 { - pins = "PC19"; + spi2_pc_pins: spi2-pc-pins { + pins = "PC20", "PC21", "PC22"; function = "spi2"; }; - spi2_cs0_pins_b: spi2_cs0@1 { - pins = "PB14"; + spi2_cs0_pc_pin: spi2-cs0-pc-pin { + pins = "PC19"; function = "spi2"; }; - uart0_pins_a: uart0@0 { + uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; }; - uart2_pins_a: uart2@0 { + uart2_pi_pins: uart2-pi-pins { pins = "PI16", "PI17", "PI18", "PI19"; function = "uart2"; }; - uart3_pins_a: uart3@0 { + uart3_pg_pins: uart3-pg-pins { pins = "PG6", "PG7", "PG8", "PG9"; function = "uart3"; }; - uart3_pins_b: uart3@1 { + uart3_ph_pins: uart3-ph-pins { pins = "PH0", "PH1"; function = "uart3"; }; - uart4_pins_a: uart4@0 { + uart4_pg_pins: uart4-pg-pins { pins = "PG10", "PG11"; function = "uart4"; }; - uart4_pins_b: uart4@1 { + uart4_ph_pins: uart4-ph-pins { pins = "PH4", "PH5"; function = "uart4"; }; - uart5_pins_a: uart5@0 { + uart5_pi_pins: uart5-pi-pins { pins = "PI10", "PI11"; function = "uart5"; }; - uart6_pins_a: uart6@0 { + uart6_pi_pins: uart6-pi-pins { pins = "PI12", "PI13"; function = "uart6"; }; - uart7_pins_a: uart7@0 { + uart7_pi_pins: uart7-pi-pins { pins = "PI20", "PI21"; function = "uart7"; }; diff --git a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi index ddf4e722ea93..0d002f83a259 100644 --- a/arch/arm/boot/dts/sunxi-itead-core-common.dtsi +++ b/arch/arm/boot/dts/sunxi-itead-core-common.dtsi @@ -121,7 +121,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; -- cgit From bb4d3ec9a7daa327608e69bb45704f76e2d9413c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 22 Nov 2018 11:18:09 +0100 Subject: ARM: dts: sun7i: Split the RTS and CTS pins out of the UART nodes Some UART nodes on the A20 DTSI do not share the same pattern that we use everywhere else, with the RTS and CTS pins split away from the TX and RX pins. Make those pin groups consistent with the rest of our DT. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 4 ++-- arch/arm/boot/dts/sun7i-a20-mk808c.dts | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++-- 3 files changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts index 9ce59d49cf49..a1af7d6726e2 100644 --- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts +++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts @@ -215,13 +215,13 @@ &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&uart2_pi_pins>; + pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; status = "okay"; }; &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&uart3_pg_pins>; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts index a8d15d01ac1a..b4143a91086b 100644 --- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts +++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts @@ -173,7 +173,7 @@ &uart2 { pinctrl-names = "default"; - pinctrl-0 = <&uart2_pi_pins>; + pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 75669fc51de5..bffd3a21bee3 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -935,12 +935,22 @@ }; uart2_pi_pins: uart2-pi-pins { - pins = "PI16", "PI17", "PI18", "PI19"; + pins = "PI18", "PI19"; + function = "uart2"; + }; + + uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins { + pins = "PI16", "PI17"; function = "uart2"; }; uart3_pg_pins: uart3-pg-pins { - pins = "PG6", "PG7", "PG8", "PG9"; + pins = "PG6", "PG7"; + function = "uart3"; + }; + + uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { + pins = "PG8", "PG9"; function = "uart3"; }; -- cgit From 89dddc2cb22fae6ff4e88c756ce8a0c70d1665d8 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 22 Nov 2018 11:19:35 +0100 Subject: ARM: dts: sun7i: som204: Use the UART3 TX and RX pin group The SOM204-EVB doesn't use the CTS pin, and thus was defining its own pinctrl node for the UART3 muxing. Since we split away the TX and RX pin, we can use the global node now, and only have the RTS pin in our local node. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts index 631a80ae958e..249bb57d50e0 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts @@ -203,8 +203,8 @@ }; &pio { - bt_uart_pins: bt_uart_pins@0 { - pins = "PG6", "PG7", "PG8"; + uart3_rts_pin: uart3-rts-pin { + pins = "PG8"; function = "uart3"; }; }; @@ -296,7 +296,7 @@ /* Used for RTL8723BS bluetooth */ &uart3 { pinctrl-names = "default"; - pinctrl-0 = <&bt_uart_pins>; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_pin>; status = "okay"; }; -- cgit From 0356f1ae06e322a309e52276fcf9d3c2e6c52099 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 21:42:36 +0100 Subject: ARM: dts: sun7i: Remove underscores from nodes names Some GPIO pinctrl nodes cannot be easily removed, because they would also change the pin configuration, for example to add a pull resistor or change the current delivered by the pin. Those nodes still have underscores and unit-addresses in their node names in our DTs, so adjust their name to remove the warnings. Use that occasion to also fix some poorly chosen node-names. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-bananapi.dts | 2 +- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 2 +- arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 2 +- arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 2 +- arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 6 +++--- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 6 +++--- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 8 ++++---- arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 2 +- arch/arm/boot/dts/sun7i-a20-orangepi.dts | 2 +- arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 2 +- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 2 +- arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 2 +- arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 2 +- 14 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index af56ae95c63f..c14c517a35af 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -248,7 +248,7 @@ "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "", "", "", "", "", "", "", "", ""; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 9a027764cda4..2982d0521f06 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -180,7 +180,7 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts index ad97f6f2cc2c..2bd4f281f31a 100644 --- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts +++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts @@ -129,7 +129,7 @@ }; &pio { - led_pins_itead_core: led_pins@0 { + led_pins_itead_core: led-pins { pins = "PH20","PH21"; function = "gpio_out"; drive-strength = <20>; diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 32e204fe8c15..3d4cd05813e8 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -236,7 +236,7 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index 8f8a77121e80..cf3a61eed691 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -239,7 +239,7 @@ }; &pio { - led_pins_olimex_som_evb: led_pins@0 { + led_pins_olimex_som_evb: led-pins { pins = "PH2"; function = "gpio_out"; drive-strength = <20>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index 7d6a90678025..454b0c433e75 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -175,19 +175,19 @@ }; &pio { - led_pins_olinuxinolime: led_pins@0 { + led_pins_olinuxinolime: led-pins { pins = "PH2"; function = "gpio_out"; drive-strength = <20>; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index 9ea84cf6437b..0a8e243d8e7b 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -180,19 +180,19 @@ }; &pio { - led_pins_olinuxinolime: led_pins@0 { + led_pins_olinuxinolime: led-pins { pins = "PH2"; function = "gpio_out"; drive-strength = <20>; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 4cef69e90b2f..718b5209643b 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -252,24 +252,24 @@ }; &pio { - gmac_txerr: gmac_txerr@0 { + gmac_txerr: gmac-txerr-pin { pins = "PA17"; function = "gmac"; }; - led_pins_olinuxino: led_pins@0 { + led_pins_olinuxino: led-pins { pins = "PH2"; function = "gpio_out"; drive-strength = <20>; }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; }; - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + usb0_vbus_detect_pin: usb0-vbus-detect-pin { pins = "PH5"; function = "gpio_in"; bias-pull-down; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts index 192d907fee71..ddb713209bb2 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts @@ -183,7 +183,7 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts index c71d819cd0af..d35705345c10 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts @@ -140,7 +140,7 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts index 1ba1dd6de244..6e64315d1a8b 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts @@ -173,7 +173,7 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index 77a49e8b3d20..b6a9cef86c31 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -173,7 +173,7 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts index 23b7d127e14f..3b1fc4cb61d3 100644 --- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts +++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts @@ -165,7 +165,7 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts index 1df18959d2a9..ae4febdea552 100644 --- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -156,7 +156,7 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH4"; function = "gpio_in"; bias-pull-up; -- cgit From 4d9a06979b1ae0c802440cb4433dfcd85fc7bdd3 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 7 Sep 2018 16:00:22 +0200 Subject: ARM: dts: sun7i: Fix HDMI output DTC warning Our HDMI output endpoint on the A10s DTSI has a warning under DTC: "graph node has single child node 'endpoint', #address-cells/#size-cells are not necessary". Fix this by removing those properties. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index bffd3a21bee3..1b247369ec86 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -662,8 +662,6 @@ }; hdmi_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; reg = <1>; }; }; -- cgit From 7dab9adb7d427ffd8ea430f90e2bf4f763c7079d Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 22:03:28 +0100 Subject: ARM: dts: sun7i: Provide default muxing for relevant controllers The I2C and MMC controllers have only one muxing option in the SoC. In such a case, we can just move the muxing into the DTSI, and remove it from the DTS. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 6 ------ arch/arm/boot/dts/sun7i-a20-bananapi.dts | 6 ------ arch/arm/boot/dts/sun7i-a20-bananapro.dts | 8 -------- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 6 ------ arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 9 --------- arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 12 ------------ arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 6 ------ arch/arm/boot/dts/sun7i-a20-icnova-swac.dts | 6 ------ arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 2 -- arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 6 ------ arch/arm/boot/dts/sun7i-a20-m3.dts | 6 ------ arch/arm/boot/dts/sun7i-a20-mk808c.dts | 8 -------- arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts | 2 -- arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 10 ---------- arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts | 2 -- arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts | 10 ---------- arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 6 ------ arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts | 2 -- arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 6 ------ arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts | 2 -- arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 10 ---------- arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 6 ------ arch/arm/boot/dts/sun7i-a20-orangepi.dts | 4 ---- arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 4 ---- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 4 ---- arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 8 -------- arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 10 ---------- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++ 28 files changed, 14 insertions(+), 167 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index af4418de57be..e2e540380c6e 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -150,8 +150,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -174,8 +172,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -185,8 +181,6 @@ &mmc3 { #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc3_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index c14c517a35af..556b1b591c5d 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -152,8 +152,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -164,8 +162,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -176,8 +172,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts index 567bf6d493f9..0176e9de0180 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts @@ -120,8 +120,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -136,8 +134,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -148,8 +144,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -157,8 +151,6 @@ }; &mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 2982d0521f06..200685b0b1cb 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -135,8 +135,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -147,8 +145,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; @@ -159,8 +155,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 20069542336f..95da354cecb7 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -168,8 +168,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -181,13 +179,10 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -198,8 +193,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -207,8 +200,6 @@ }; &mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc3_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts index a1af7d6726e2..fd0153f65685 100644 --- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts +++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts @@ -116,8 +116,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -131,20 +129,14 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; status = "okay"; }; @@ -155,8 +147,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -164,8 +154,6 @@ }; &mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_mmc3_vdd>; bus-width = <4>; non-removable; diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index db708332616e..6313d8a8a37c 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -126,8 +126,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -148,8 +146,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -157,8 +153,6 @@ }; &mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vmmc3>; bus-width = <4>; non-removable; diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts index 0bf70b22bac4..949494730aee 100644 --- a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts +++ b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts @@ -85,8 +85,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -97,14 +95,10 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */ diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts index 2bd4f281f31a..b90a7607d069 100644 --- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts +++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts @@ -120,8 +120,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 3d4cd05813e8..6f8dfa717994 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -195,8 +195,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -207,8 +205,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -219,8 +215,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts index 1207e0d897b7..b8a1aaaf3976 100644 --- a/arch/arm/boot/dts/sun7i-a20-m3.dts +++ b/arch/arm/boot/dts/sun7i-a20-m3.dts @@ -92,8 +92,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -114,8 +112,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -123,8 +119,6 @@ }; &mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts index b4143a91086b..1491c603f661 100644 --- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts +++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts @@ -106,8 +106,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -121,20 +119,14 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts index ea0d620119cb..20bf09b2226c 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts @@ -21,8 +21,6 @@ }; &mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc2_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index cf3a61eed691..f0e6a96e5785 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -131,8 +131,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -143,14 +141,10 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -209,8 +203,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -218,8 +210,6 @@ }; &mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */ diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts index 093cd32c9a1c..a59755a2e7a9 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts @@ -20,8 +20,6 @@ }; &mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc2_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts index 249bb57d50e0..823aabce0462 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts @@ -130,8 +130,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -143,8 +141,6 @@ /* Exposed to UEXT1 */ &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; eeprom: eeprom@50 { @@ -156,8 +152,6 @@ /* Exposed to UEXT2 */ &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -168,8 +162,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; @@ -177,8 +169,6 @@ }; &mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&rtl_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index 454b0c433e75..5e411194bf62 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -126,8 +126,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -142,8 +140,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; eeprom: eeprom@50 { @@ -154,8 +150,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts index 0a2a26f9a5fb..decb014a382b 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts @@ -54,8 +54,6 @@ }; &mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc3v3>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index 0a8e243d8e7b..55c9086e9344 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -131,8 +131,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -143,8 +141,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; eeprom: eeprom@50 { @@ -159,8 +155,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts index 58fd3519ab7d..2337b44a88aa 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro-emmc.dts @@ -54,8 +54,6 @@ }; &mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; non-removable; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 718b5209643b..840ae1194a66 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -138,8 +138,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -150,8 +148,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; eeprom: eeprom@50 { @@ -162,8 +158,6 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; @@ -222,8 +216,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -231,8 +223,6 @@ }; &mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts index ddb713209bb2..15881081cac4 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts @@ -141,8 +141,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -161,8 +159,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ @@ -170,8 +166,6 @@ }; &mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts index d35705345c10..d64de2e73a9f 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts @@ -107,8 +107,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -127,8 +125,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts index 6e64315d1a8b..538ea15fa32f 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts @@ -134,8 +134,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -152,8 +150,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index b6a9cef86c31..a72ed4318d04 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -132,8 +132,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -152,8 +150,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts index 3b1fc4cb61d3..ffade253d129 100644 --- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts +++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts @@ -89,8 +89,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -103,14 +101,10 @@ #include "axp209.dtsi" &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; gt911: touchscreen@5d { @@ -144,8 +138,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts index ae4febdea552..c27e56091fb1 100644 --- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -91,8 +91,6 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; axp209: pmic@34 { @@ -103,22 +101,16 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "okay"; }; #include "axp209.dtsi" &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ @@ -126,8 +118,6 @@ }; &mmc3 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; vmmc-supply = <®_vcc3v3>; mmc-pwrseq = <&mmc3_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 1b247369ec86..86158528ed93 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -514,6 +514,8 @@ "output", "sample"; interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -548,6 +550,8 @@ "output", "sample"; interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -565,6 +569,8 @@ "output", "sample"; interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -1218,6 +1224,8 @@ reg = <0x01c2ac00 0x400>; interrupts = ; clocks = <&ccu CLK_APB1_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -1229,6 +1237,8 @@ reg = <0x01c2b000 0x400>; interrupts = ; clocks = <&ccu CLK_APB1_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -1240,6 +1250,8 @@ reg = <0x01c2b400 0x400>; interrupts = ; clocks = <&ccu CLK_APB1_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -1251,6 +1263,8 @@ reg = <0x01c2b800 0x400>; interrupts = ; clocks = <&ccu CLK_APB1_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- cgit From d02932889b43524ce6515f09ea3b7df19d124074 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 10:44:54 +0100 Subject: ARM: dts: sun7i: Remove redundant MMC pinmux tuning Some boards override the MMC pin muxing settings in order to enable the pull-ups and change the drive strength to a value higher than the default. While this was needed in the earlier days, this is now the default setting for those pins, and therefore we don't need those board-specific settings anymore. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts | 5 ----- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 5 ----- arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 5 ----- 3 files changed, 15 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index e2e540380c6e..e2bfe0058830 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -197,11 +197,6 @@ }; }; -&mmc3_pins { - /* AP6210 requires pull-up */ - bias-pull-up; -}; - &ohci0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 95da354cecb7..15c5eae4ca7b 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -215,11 +215,6 @@ }; }; -&mmc3_pins { - /* AP6210 requires pull-up */ - bias-pull-up; -}; - &ohci0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index 6313d8a8a37c..5f1c4f573d3e 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -167,11 +167,6 @@ }; }; -&mmc3_pins { - /* AP6210 / AP6330 requires pull-up */ - bias-pull-up; -}; - &ohci0 { status = "okay"; }; -- cgit From 5e043563d119d88c0777fffbd7c2eec630b713cb Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 10:02:26 +0100 Subject: ARM: dts: sun7i: lamobo-r1: Remove unused address-cells/size-cells The #address-cells and #size-cells are only relevant for nodes that have childs with reg properties. Otherwise, DTC will emit a warning saying that those properties are unnecessary. Remove them when needed. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 6f8dfa717994..f91e1bee44e8 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -123,6 +123,8 @@ phy-mode = "rgmii"; phy-supply = <®_gmac_3v3>; status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; fixed-link { speed = <1000>; @@ -137,8 +139,6 @@ switch: ethernet-switch@1e { compatible = "brcm,bcm53125"; reg = <30>; - #address-cells = <1>; - #size-cells = <0>; ports { #address-cells = <1>; -- cgit From 7ece96910c5d6aff0ecbd79f729dd0a17642516b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 09:39:24 +0100 Subject: ARM: dts: sun8i: a23/a33: Remove skeleton and memory to avoid warnings Using skeleton.dtsi will create a memory node that will generate a warning in DTC. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 4 ++-- arch/arm/boot/dts/sun8i-a23.dtsi | 4 ---- arch/arm/boot/dts/sun8i-a33.dtsi | 4 ---- 3 files changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index c16ffcc4db7d..a198894a33fd 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -42,8 +42,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" - #include #include @@ -51,6 +49,8 @@ / { interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; chosen { #address-cells = <1>; diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 58e6585b504b..7751c43fc806 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -45,10 +45,6 @@ #include "sun8i-a23-a33.dtsi" / { - memory { - reg = <0x40000000 0x40000000>; - }; - soc@1c00000 { codec: codec@1c22c00 { #sound-dai-cells = <0>; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 1c4f7e1930d8..163c3ff7f670 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -186,10 +186,6 @@ }; }; - memory { - reg = <0x40000000 0x80000000>; - }; - reserved-memory { #address-cells = <1>; #size-cells = <1>; -- cgit From cce55d8c2b00b1909231b8d9c049766eb5a39eb1 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 09:40:48 +0100 Subject: ARM: dts: sun8i: a23/a33: Remove SoC node unit-name to avoid warnings Our main node for all the in-SoC controllers used to have a unit name. The unit-name, in addition to being actually false, would not match any reg property, which generates a warning. Remove it in order to remove those warnings. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- arch/arm/boot/dts/sun8i-a23.dtsi | 2 +- arch/arm/boot/dts/sun8i-a33.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index a198894a33fd..bd8d9e7afcdf 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -118,7 +118,7 @@ }; }; - soc@1c00000 { + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 7751c43fc806..d00055e9eef5 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -45,7 +45,7 @@ #include "sun8i-a23-a33.dtsi" / { - soc@1c00000 { + soc { codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-a23-codec"; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 163c3ff7f670..17d725bd6654 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -223,7 +223,7 @@ }; }; - soc@1c00000 { + soc { tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun8i-a33-tcon"; reg = <0x01c0c000 0x1000>; -- cgit From a858f569b80a69076c521532a289097af905cf1e Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 09:51:04 +0100 Subject: ARM: dts: sun8i: a23/a33: Fix OPP DTC warnings DTC will emit a warning on our OPPs nodes for the common DTSI between the A23 and A33 since those nodes use the frequency as unit addresses, but don't have a matching reg property. Fix this by moving the frequency to the node name instead. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-h3.dtsi | 6 +++--- arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 22883f1b80e2..9db1f58a47de 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -47,19 +47,19 @@ compatible = "operating-points-v2"; opp-shared; - opp@648000000 { + opp-648000000 { opp-hz = /bits/ 64 <648000000>; opp-microvolt = <1040000 1040000 1300000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@816000000 { + opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1100000 1100000 1300000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@1008000000 { + opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000 1200000 1300000>; clock-latency-ns = <244144>; /* 8 32k periods */ diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts index 0dbdb29a8fff..ee7ce3752581 100644 --- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts @@ -103,13 +103,13 @@ }; &cpu0_opp_table { - opp@1104000000 { + opp-1104000000 { opp-hz = /bits/ 64 <1104000000>; opp-microvolt = <1320000>; clock-latency-ns = <244144>; /* 8 32k periods */ }; - opp@1200000000 { + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1320000>; clock-latency-ns = <244144>; /* 8 32k periods */ -- cgit From 6013d660a4784454c87302e5e14388cd983dcbcb Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 10:02:26 +0100 Subject: ARM: dts: sun8i: a23/a33: Remove unused address-cells/size-cells The #address-cells and #size-cells are only relevant for nodes that have childs with reg properties. Otherwise, DTC will emit a warning saying that those properties are unnecessary. Remove them when needed. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index bd8d9e7afcdf..5d79860bef88 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -656,8 +656,6 @@ gpio-controller; interrupt-controller; #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <0>; #gpio-cells = <3>; r_rsb_pins: r_rsb { -- cgit From 5759b8d6f4e01a1dbb220068a1f398b73d18bfe5 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 10:04:39 +0100 Subject: ARM: dts: sun8i: a23/a33: Remove leading zeros from unit-addresses Most of our device trees have had leading zeros for padding as part of the nodes unit-addresses. Remove all these useless zeros that generate warnings Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a33.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 17d725bd6654..72cd1a2431bc 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -265,7 +265,7 @@ }; }; - video-codec@01c0e000 { + video-codec@1c0e000 { compatible = "allwinner,sun8i-a33-video-engine"; reg = <0x01c0e000 0x1000>; clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, -- cgit From 3af4c3eaf8cf32c75803ac625eccaefc3a39efd0 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 10:39:42 +0100 Subject: ARM: dts: sun8i: a23/a33: Change framebuffer node names to avoid warnings The simple-framebuffer nodes have a unit address, but no reg property which generates a warning when compiling it with DTC. Change the simple-framebuffer node names so that there is no warnings on this anymore. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 5d79860bef88..b76b88a45e99 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -57,7 +57,7 @@ #size-cells = <1>; ranges; - simplefb_lcd: framebuffer@0 { + simplefb_lcd: framebuffer-lcd0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; -- cgit From dac89fd27886fdf6aa6ecb9aa29ee6c1039db0e5 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 10:44:54 +0100 Subject: ARM: dts: sun8i: a23/a33: Remove redundant MMC pinmux tuning Some boards override the MMC pin muxing settings in order to enable the pull-ups and change the drive strength to a value higher than the default. While this was needed in the earlier days, this is now the default setting for those pins, and therefore we don't need those board-specific settings anymore. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts | 4 ---- arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts | 4 ---- arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 4 ---- arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 2 -- arch/arm/boot/dts/sun8i-q8-common.dtsi | 4 ---- arch/arm/boot/dts/sun8i-r16-parrot.dts | 1 - 6 files changed, 19 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts index 649e31339662..61a4702b63c1 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts @@ -85,10 +85,6 @@ }; }; -&mmc1_pins_a { - bias-pull-up; -}; - &r_pio { wifi_pwrseq_pin_mid2407: wifi_pwrseq_pin@0 { pins = "PL6"; diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts index 6b3bcae089f2..29a032164e3d 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts @@ -78,10 +78,6 @@ }; }; -&mmc1_pins_a { - bias-pull-up; -}; - &r_pio { wifi_pwrseq_pin_mid2809: wifi_pwrseq_pin@0 { pins = "PL6"; diff --git a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts index 3e05959104f1..f8a72d07467c 100644 --- a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts +++ b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts @@ -70,10 +70,6 @@ }; }; -&mmc1_pins_a { - bias-pull-up; -}; - &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index 541acb4d2b91..ff7244cdfa88 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -161,8 +161,6 @@ &mmc2_8bit_pins { /* Increase drive strength for DDR modes */ drive-strength = <40>; - /* eMMC is missing pull-ups */ - bias-pull-up; }; &ohci0 { diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi index c676940a96da..0b3db925254b 100644 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi @@ -82,10 +82,6 @@ }; }; -&mmc1_pins_a { - bias-pull-up; -}; - &r_pio { wifi_pwrseq_pin_q8: wifi_pwrseq_pin@0 { pins = "PL6", "PL7", "PL11"; diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts index 472c03b7aeab..7322357aab04 100644 --- a/arch/arm/boot/dts/sun8i-r16-parrot.dts +++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts @@ -158,7 +158,6 @@ &mmc2_8bit_pins { drive-strength = <40>; - bias-pull-up; }; &ohci0 { -- cgit From ec6b944c5adbef09aac9b436fb07e91632f75e05 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 11:14:15 +0100 Subject: ARM: dts: sun8i: a23/a33: Remove all useless pinctrl nodes The gpio pinctrl nodes are redundant and as such useless most of the times. Since they will also generate warnings in DTC, we can simply remove most of them. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- .../boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts | 9 --------- .../boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts | 9 --------- arch/arm/boot/dts/sun8i-r16-parrot.dts | 23 +--------------------- .../boot/dts/sun8i-reference-design-tablet.dtsi | 7 ------- 4 files changed, 1 insertion(+), 47 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts index 61a4702b63c1..4a318faa462a 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts @@ -54,8 +54,6 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pwrseq_pin_mid2407>; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ /* The esp8089 needs 200 ms after driving wifi-en high */ post-power-on-delay-ms = <200>; @@ -85,13 +83,6 @@ }; }; -&r_pio { - wifi_pwrseq_pin_mid2407: wifi_pwrseq_pin@0 { - pins = "PL6"; - function = "gpio_out"; - }; -}; - &touchscreen { reg = <0x40>; compatible = "silead,gsl1680"; diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts index 29a032164e3d..22e153d50523 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts @@ -54,8 +54,6 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pwrseq_pin_mid2809>; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ /* The esp8089 needs 200 ms after driving wifi-en high */ post-power-on-delay-ms = <200>; @@ -78,13 +76,6 @@ }; }; -&r_pio { - wifi_pwrseq_pin_mid2809: wifi_pwrseq_pin@0 { - pins = "PL6"; - function = "gpio_out"; - }; -}; - &touchscreen { reg = <0x40>; compatible = "silead,gsl3670"; diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts index 7322357aab04..2c4d892ea9f1 100644 --- a/arch/arm/boot/dts/sun8i-r16-parrot.dts +++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts @@ -63,8 +63,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_parrot>; led1 { label = "parrot:led1:usr"; @@ -138,7 +136,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_parrot>; + pinctrl-0 = <&mmc1_pins_a>; vmmc-supply = <®_aldo1>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; @@ -171,28 +169,11 @@ bias-pull-up; }; - led_pins_parrot: led_pins@0 { - pins = "PE16", "PE17"; - function = "gpio_out"; - }; - usb0_id_det: usb0_id_detect_pin@0 { pins = "PD10"; function = "gpio_in"; bias-pull-up; }; - - usb1_vbus_pin_parrot: usb1_vbus_pin@0 { - pins = "PD12"; - function = "gpio_out"; - }; -}; - -&r_pio { - wifi_reset_pin_parrot: wifi_reset_pin@0 { - pins = "PL6"; - function = "gpio_out"; - }; }; &r_rsb { @@ -318,8 +299,6 @@ }; ®_usb1_vbus { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_vbus_pin_parrot>; gpio = <&pio 3 12 GPIO_ACTIVE_HIGH>; /* PD12 */ status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index 5e8a95af89b8..c5f0f2e627bf 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -73,8 +73,6 @@ reg = <0x40>; interrupt-parent = <&pio>; interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */ - pinctrl-names = "default"; - pinctrl-0 = <&ts_power_pin>; power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ /* Tablet dts must provide reg and compatible */ status = "disabled"; @@ -97,11 +95,6 @@ bias-pull-up; }; - ts_power_pin: ts_power_pin@0 { - pins = "PH1"; - function = "gpio_out"; - }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { pins = "PH8"; function = "gpio_in"; -- cgit From f2a5e42580e9107c20897ac69a83125bf1325883 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 10:57:41 +0100 Subject: ARM: dts: sun8i: a23/a33: Change LRADC node names to avoid warnings One of the usage of the LRADC is to implement buttons. The bindings define that we should have one subnode per button, with their associated voltage as a property. However, there was no reg property but we still used the voltage associated to the button as the unit-address, which eventually generated warnings in DTC. Rename the node names to avoid those warnings. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-evb.dts | 6 +++--- arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts | 2 +- arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts | 2 +- arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 6 +++--- arch/arm/boot/dts/sun8i-r16-parrot.dts | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-evb.dts b/arch/arm/boot/dts/sun8i-a23-evb.dts index 8a93697df3a5..b6aeb23b6ee9 100644 --- a/arch/arm/boot/dts/sun8i-a23-evb.dts +++ b/arch/arm/boot/dts/sun8i-a23-evb.dts @@ -80,21 +80,21 @@ vref-supply = <®_vcc3v0>; status = "okay"; - button@190 { + button-190 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <190000>; }; - button@390 { + button-390 { label = "Volume Down"; linux,code = ; channel = <0>; voltage = <390000>; }; - button@600 { + button-600 { label = "Home"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts b/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts index e3c7a25ca37d..bcbc9b0758f9 100644 --- a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts +++ b/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts @@ -63,7 +63,7 @@ }; &lradc { - button@600 { + button-600 { label = "Back"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts index f71159987cac..9ead5e1b7b65 100644 --- a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts +++ b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts @@ -69,7 +69,7 @@ }; &lradc { - button@600 { + button-600 { label = "Back"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index ff7244cdfa88..9d545f8549be 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -117,21 +117,21 @@ vref-supply = <®_dcdc1>; status = "okay"; - button@200 { + button-200 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <191011>; }; - button@400 { + button-400 { label = "Volume Down"; linux,code = ; channel = <0>; voltage = <391304>; }; - button@600 { + button-600 { label = "Home"; linux,code = ; channel = <0>; diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts index 2c4d892ea9f1..17868b1eff4e 100644 --- a/arch/arm/boot/dts/sun8i-r16-parrot.dts +++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts @@ -109,14 +109,14 @@ vref-supply = <®_aldo3>; status = "okay"; - button@0 { + button-190 { label = "V+"; linux,code = ; channel = <0>; voltage = <190000>; }; - button@1 { + button-390 { label = "V-"; linux,code = ; channel = <0>; -- cgit From 9c2d3d17a9127844a0bb3ba730de493c60d90348 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 11:13:25 +0100 Subject: ARM: dts: sun8i: a23/a33: Reorder the pin groups The pin groups are supposed to be in alphabetical order, and they aren't. Fix this. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 52 ++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index b76b88a45e99..43978625df21 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -298,19 +298,27 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - uart0_pins_a: uart0@0 { - pins = "PF2", "PF4"; - function = "uart0"; + i2c0_pins_a: i2c0@0 { + pins = "PH2", "PH3"; + function = "i2c0"; }; - uart1_pins_a: uart1@0 { - pins = "PG6", "PG7"; - function = "uart1"; + i2c1_pins_a: i2c1@0 { + pins = "PH4", "PH5"; + function = "i2c1"; }; - uart1_pins_cts_rts_a: uart1-cts-rts@0 { - pins = "PG8", "PG9"; - function = "uart1"; + i2c2_pins_a: i2c2@0 { + pins = "PE12", "PE13"; + function = "i2c2"; + }; + + lcd_rgb666_pins: lcd-rgb666@0 { + pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + function = "lcd0"; }; mmc0_pins_a: mmc0@0 { @@ -375,27 +383,19 @@ function = "pwm0"; }; - i2c0_pins_a: i2c0@0 { - pins = "PH2", "PH3"; - function = "i2c0"; - }; - - i2c1_pins_a: i2c1@0 { - pins = "PH4", "PH5"; - function = "i2c1"; + uart0_pins_a: uart0@0 { + pins = "PF2", "PF4"; + function = "uart0"; }; - i2c2_pins_a: i2c2@0 { - pins = "PE12", "PE13"; - function = "i2c2"; + uart1_pins_a: uart1@0 { + pins = "PG6", "PG7"; + function = "uart1"; }; - lcd_rgb666_pins: lcd-rgb666@0 { - pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; + uart1_pins_cts_rts_a: uart1-cts-rts@0 { + pins = "PG8", "PG9"; + function = "uart1"; }; }; -- cgit From 4ead0ad7b21734c03d91659ca60818114fffcf7c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 21:03:20 +0100 Subject: ARM: dts: sun8i: a23/a33: Remove card detect pull-up Boards usually have an external pull-up on the card-detect signal, so there's no need to add another one. This also removes a DTC warning. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-evb.dts | 10 +--------- arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 10 +--------- arch/arm/boot/dts/sun8i-r16-parrot.dts | 8 +------- arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 8 +------- 4 files changed, 4 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-evb.dts b/arch/arm/boot/dts/sun8i-a23-evb.dts index b6aeb23b6ee9..3c994df0ffdf 100644 --- a/arch/arm/boot/dts/sun8i-a23-evb.dts +++ b/arch/arm/boot/dts/sun8i-a23-evb.dts @@ -104,21 +104,13 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_evb>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ status = "okay"; }; -&pio { - mmc0_cd_pin_evb: mmc0_cd_pin@0 { - pins = "PB4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - /* * The RX line has a non-populated resistance. In order to use it, you * need to solder R207 on the back of the board in order to close the diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index 9d545f8549be..775ab6422eeb 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -141,7 +141,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ @@ -167,14 +167,6 @@ status = "okay"; }; -&pio { - mmc0_cd_pin_sina33: mmc0_cd_pin@0 { - pins = "PB4"; - function = "gpio_in"; - bias-pull-up; - }; -}; - &r_rsb { status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts index 17868b1eff4e..ec987f422041 100644 --- a/arch/arm/boot/dts/sun8i-r16-parrot.dts +++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts @@ -127,7 +127,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_parrot>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ bus-width = <4>; @@ -163,12 +163,6 @@ }; &pio { - mmc0_cd_pin_parrot: mmc0_cd_pin@0 { - pins = "PD14"; - function = "gpio_in"; - bias-pull-up; - }; - usb0_id_det: usb0_id_detect_pin@0 { pins = "PD10"; function = "gpio_in"; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index c5f0f2e627bf..6838bce7dd4e 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -81,7 +81,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ @@ -89,12 +89,6 @@ }; &pio { - mmc0_cd_pin: mmc0_cd_pin@0 { - pins = "PB4"; - function = "gpio_in"; - bias-pull-up; - }; - usb0_id_detect_pin: usb0_id_detect_pin@0 { pins = "PH8"; function = "gpio_in"; -- cgit From 090e563c91e6cea86e79659868ad70ef313a884a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 10:58:01 +0100 Subject: ARM: dts: sun8i: a23/a33: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 26 +++++++++++----------- arch/arm/boot/dts/sun8i-a23-evb.dts | 6 ++--- .../boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts | 2 +- .../boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts | 2 +- arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts | 2 +- arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 6 ++--- arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 4 ++-- arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 4 ++-- arch/arm/boot/dts/sun8i-a33.dtsi | 2 +- arch/arm/boot/dts/sun8i-q8-common.dtsi | 2 +- arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 14 ++++++------ .../boot/dts/sun8i-r16-nintendo-nes-classic.dts | 2 +- arch/arm/boot/dts/sun8i-r16-parrot.dts | 8 +++---- .../boot/dts/sun8i-reference-design-tablet.dtsi | 11 ++++++++- 14 files changed, 50 insertions(+), 41 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 43978625df21..bcb5b30a02f0 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -298,22 +298,22 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - i2c0_pins_a: i2c0@0 { + i2c0_pins: i2c0-pins { pins = "PH2", "PH3"; function = "i2c0"; }; - i2c1_pins_a: i2c1@0 { + i2c1_pins: i2c1-pins { pins = "PH4", "PH5"; function = "i2c1"; }; - i2c2_pins_a: i2c2@0 { + i2c2_pins: i2c2-pins { pins = "PE12", "PE13"; function = "i2c2"; }; - lcd_rgb666_pins: lcd-rgb666@0 { + lcd_rgb666_pins: lcd-rgb666-pins { pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", @@ -321,7 +321,7 @@ function = "lcd0"; }; - mmc0_pins_a: mmc0@0 { + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -329,7 +329,7 @@ bias-pull-up; }; - mmc1_pins_a: mmc1@0 { + mmc1_pg_pins: mmc1-pg-pins { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1"; @@ -337,7 +337,7 @@ bias-pull-up; }; - mmc2_8bit_pins: mmc2_8bit { + mmc2_8bit_pins: mmc2-8bit-pins { pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", @@ -378,22 +378,22 @@ bias-pull-up; }; - pwm0_pins: pwm0 { + pwm0_pin: pwm0-pin { pins = "PH0"; function = "pwm0"; }; - uart0_pins_a: uart0@0 { + uart0_pf_pins: uart0-pf-pins { pins = "PF2", "PF4"; function = "uart0"; }; - uart1_pins_a: uart1@0 { + uart1_pg_pins: uart1-pg-pins { pins = "PG6", "PG7"; function = "uart1"; }; - uart1_pins_cts_rts_a: uart1-cts-rts@0 { + uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins { pins = "PG8", "PG9"; function = "uart1"; }; @@ -658,14 +658,14 @@ #interrupt-cells = <3>; #gpio-cells = <3>; - r_rsb_pins: r_rsb { + r_rsb_pins: r-rsb-pins { pins = "PL0", "PL1"; function = "s_rsb"; drive-strength = <20>; bias-pull-up; }; - r_uart_pins_a: r_uart@0 { + r_uart_pins_a: r-uart-pins { pins = "PL2", "PL3"; function = "s_uart"; }; diff --git a/arch/arm/boot/dts/sun8i-a23-evb.dts b/arch/arm/boot/dts/sun8i-a23-evb.dts index 3c994df0ffdf..36896155f2b9 100644 --- a/arch/arm/boot/dts/sun8i-a23-evb.dts +++ b/arch/arm/boot/dts/sun8i-a23-evb.dts @@ -66,13 +66,13 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; }; &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; @@ -104,7 +104,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts index 4a318faa462a..d5f6aebd7216 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts @@ -69,7 +69,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pg_pins>; vmmc-supply = <®_dldo1>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts index 22e153d50523..9f9232a2fefb 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts @@ -62,7 +62,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pg_pins>; vmmc-supply = <®_dldo1>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts index 9ead5e1b7b65..2dfdd0a3151e 100644 --- a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts +++ b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts @@ -79,7 +79,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pg_pins>; vmmc-supply = <®_dldo1>; bus-width = <4>; non-removable; diff --git a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts index f8a72d07467c..42726576a6a9 100644 --- a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts +++ b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts @@ -72,7 +72,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pg_pins>; vmmc-supply = <®_dldo1>; bus-width = <4>; non-removable; @@ -97,7 +97,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>, - <&uart1_pins_cts_rts_a>; + pinctrl-0 = <&uart1_pg_pins>, + <&uart1_cts_rts_pg_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts index a1a1eb64caeb..9ad7eeba9df4 100644 --- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts +++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts @@ -83,7 +83,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ @@ -207,7 +207,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index 775ab6422eeb..2a3ec6871788 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -141,7 +141,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ @@ -268,7 +268,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 72cd1a2431bc..c2c10cd4a210 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -552,7 +552,7 @@ interrupts = , ; - uart0_pins_b: uart0@1 { + uart0_pb_pins: uart0-pb-pins { pins = "PB0", "PB1"; function = "uart0"; }; diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi index 0b3db925254b..e3ca8a94d690 100644 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi @@ -70,7 +70,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pg_pins>; vmmc-supply = <®_dldo1>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts index ee7ce3752581..a44d80c24416 100644 --- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts @@ -127,27 +127,27 @@ /* This is the i2c bus exposed on the DSI connector for the touch panel */ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "disabled"; }; /* This is the i2c bus exposed on the GPIO header */ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; }; /* This is the i2c bus exposed on the CSI connector to control the sensor */ &i2c2 { pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; + pinctrl-0 = <&i2c2_pins>; status = "disabled"; }; &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ @@ -156,7 +156,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pg_pins>; vmmc-supply = <®_aldo1>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; @@ -292,13 +292,13 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>; + pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts index fc0658cfa319..32cf1ab33aab 100644 --- a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts +++ b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts @@ -25,7 +25,7 @@ * PF can also be used for the SD card so PB is preferred. */ pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pf_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts index ec987f422041..3897a91cca47 100644 --- a/arch/arm/boot/dts/sun8i-r16-parrot.dts +++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts @@ -96,7 +96,7 @@ &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; /* @@ -127,7 +127,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ bus-width = <4>; @@ -136,7 +136,7 @@ &mmc1 { pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; + pinctrl-0 = <&mmc1_pg_pins>; vmmc-supply = <®_aldo1>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; @@ -303,7 +303,7 @@ &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index 6838bce7dd4e..12a2ad67844e 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -62,6 +62,7 @@ }; &i2c0 { + pinctrl-0 = <&i2c0_pins>; /* * The gsl1680 is rated at 400KHz and it will not work reliable at * 100KHz, this has been confirmed on multiple different q8 tablets. @@ -79,9 +80,13 @@ }; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; +}; + &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ @@ -96,6 +101,10 @@ }; }; +&pwm { + pinctrl-0 = <&pwm0_pin>; +}; + &r_rsb { status = "okay"; -- cgit From 9e41b5e966fe478bbef3cf795cf07c8d6fcb1ccb Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 21:42:36 +0100 Subject: ARM: dts: sun8i: a23/a33: Remove underscores from nodes names Some GPIO pinctrl nodes cannot be easily removed, because they would also change the pin configuration, for example to add a pull resistor or change the current delivered by the pin. Those nodes still have underscores and unit-addresses in their node names in our DTs, so adjust their name to remove the warnings. Use that occasion to also fix some poorly chosen node-names. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 2 +- arch/arm/boot/dts/sun8i-q8-common.dtsi | 2 +- arch/arm/boot/dts/sun8i-r16-parrot.dts | 2 +- arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts index 42726576a6a9..317763069c0a 100644 --- a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts +++ b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts @@ -84,7 +84,7 @@ }; &r_pio { - led_pin_d978: led_pin_d978@0 { + led_pin_d978: led-pin { pins = "PL5"; function = "gpio_out"; drive-strength = <20>; diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi index e3ca8a94d690..719ad769b837 100644 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi @@ -83,7 +83,7 @@ }; &r_pio { - wifi_pwrseq_pin_q8: wifi_pwrseq_pin@0 { + wifi_pwrseq_pin_q8: wifi-pwrseq-pins { pins = "PL6", "PL7", "PL11"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts index 3897a91cca47..85a0d03fa094 100644 --- a/arch/arm/boot/dts/sun8i-r16-parrot.dts +++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts @@ -163,7 +163,7 @@ }; &pio { - usb0_id_det: usb0_id_detect_pin@0 { + usb0_id_det: usb0-id-detect-pin { pins = "PD10"; function = "gpio_in"; bias-pull-up; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index 12a2ad67844e..787a3121e179 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -94,7 +94,7 @@ }; &pio { - usb0_id_detect_pin: usb0_id_detect_pin@0 { + usb0_id_detect_pin: usb0-id-detect-pin { pins = "PH8"; function = "gpio_in"; bias-pull-up; -- cgit From fbb1f83c15a9c69c66a4312227cc638605eedbda Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 12:05:00 +0100 Subject: ARM: dts: sunxi: reference: Move the muxing back to the common DTSI Now that all the SoCs using the tablet reference design DTSI are using the same pinctrl naming scheme, we can move back the pinctrl phandles to the main DTSI. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi | 8 -------- arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 9 --------- arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi | 6 +++--- 3 files changed, 3 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi index b046436ff773..6202aabedbfe 100644 --- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi @@ -76,8 +76,6 @@ }; &i2c0 { - pinctrl-0 = <&i2c0_pins>; - axp209: pmic@34 { reg = <0x34>; interrupts = <0>; @@ -85,8 +83,6 @@ }; &i2c1 { - pinctrl-0 = <&i2c1_pins>; - /* * The gsl1680 is rated at 400KHz and it will not work reliable at * 100KHz, this has been confirmed on multiple different q8 tablets. @@ -150,10 +146,6 @@ }; }; -&pwm { - pinctrl-0 = <&pwm0_pin>; -}; - ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index 787a3121e179..0111e6c6f177 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -62,7 +62,6 @@ }; &i2c0 { - pinctrl-0 = <&i2c0_pins>; /* * The gsl1680 is rated at 400KHz and it will not work reliable at * 100KHz, this has been confirmed on multiple different q8 tablets. @@ -80,10 +79,6 @@ }; }; -&i2c1 { - pinctrl-0 = <&i2c1_pins>; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -101,10 +96,6 @@ }; }; -&pwm { - pinctrl-0 = <&pwm0_pin>; -}; - &r_rsb { status = "okay"; diff --git a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi index 00dc6623f30f..117198c52e1f 100644 --- a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi @@ -46,13 +46,13 @@ &i2c0 { pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; + pinctrl-0 = <&i2c0_pins>; status = "okay"; }; &i2c1 { pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; + pinctrl-0 = <&i2c1_pins>; status = "okay"; }; @@ -77,6 +77,6 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; + pinctrl-0 = <&pwm0_pin>; status = "okay"; }; -- cgit From ec16a8e7092b416227ad6adb0d831d10255ba116 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 22:03:28 +0100 Subject: ARM: dts: sun8i: a23/a33: Provide default muxing for relevant controllers The I2C's and MMC0 controllers have only one muxing option in the SoC. In such a case, we can just move the muxing into the DTSI, and remove it from the DTS. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 8 ++++++++ arch/arm/boot/dts/sun8i-a23-evb.dts | 6 ------ arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 2 -- arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 2 -- arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 8 -------- arch/arm/boot/dts/sun8i-r16-parrot.dts | 4 ---- arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 -- 7 files changed, 8 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index bcb5b30a02f0..c2ff8975ac60 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -169,6 +169,8 @@ resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -499,6 +501,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C0>; resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -510,6 +514,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -521,6 +527,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun8i-a23-evb.dts b/arch/arm/boot/dts/sun8i-a23-evb.dts index 36896155f2b9..53fb1be0401a 100644 --- a/arch/arm/boot/dts/sun8i-a23-evb.dts +++ b/arch/arm/boot/dts/sun8i-a23-evb.dts @@ -65,14 +65,10 @@ }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "okay"; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; }; @@ -103,8 +99,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v0>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts index 9ad7eeba9df4..3d78169cdeed 100644 --- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts +++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts @@ -82,8 +82,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index 2a3ec6871788..f3667268adde 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -140,8 +140,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts index a44d80c24416..f613889f445b 100644 --- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts @@ -126,28 +126,20 @@ /* This is the i2c bus exposed on the DSI connector for the touch panel */ &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; status = "disabled"; }; /* This is the i2c bus exposed on the GPIO header */ &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "disabled"; }; /* This is the i2c bus exposed on the CSI connector to control the sensor */ &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; status = "disabled"; }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts index 85a0d03fa094..316998e9ec5d 100644 --- a/arch/arm/boot/dts/sun8i-r16-parrot.dts +++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts @@ -95,8 +95,6 @@ }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; status = "okay"; /* @@ -126,8 +124,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ bus-width = <4>; diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index 0111e6c6f177..189e479eb95a 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -80,8 +80,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_dcdc1>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ -- cgit From 9c4273ee02f68ce39916f3c9c10b6c01dd5bfa42 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 11:57:49 +0100 Subject: ARM: dts: sun8i: BPI-M2M: Remove i2c nodes The i2c nodes were pre-populated to ease the use of overlays. However, now that we provide default muxing options for those nodes, the one in the DTS don't provide any content at all. Remove them. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts index f613889f445b..83d32a1a2a63 100644 --- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts @@ -124,21 +124,6 @@ status = "okay"; }; -/* This is the i2c bus exposed on the DSI connector for the touch panel */ -&i2c0 { - status = "disabled"; -}; - -/* This is the i2c bus exposed on the GPIO header */ -&i2c1 { - status = "disabled"; -}; - -/* This is the i2c bus exposed on the CSI connector to control the sensor */ -&i2c2 { - status = "disabled"; -}; - &mmc0 { vmmc-supply = <®_dcdc1>; bus-width = <4>; -- cgit From 420731a25fc57864fd695dd6d9d4dbf0d395486a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 10:04:39 +0100 Subject: ARM: dts: sun8i: h3: Remove leading zeros from unit-addresses Most of our device trees have had leading zeros for padding as part of the nodes unit-addresses. Remove all these useless zeros that generate warnings Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-h3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 9db1f58a47de..c2da3a3d373a 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -156,7 +156,7 @@ }; }; - video-codec@01c0e000 { + video-codec@1c0e000 { compatible = "allwinner,sun8i-h3-video-engine"; reg = <0x01c0e000 0x1000>; clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, -- cgit From 84d794d672001e88d8b877440ede7c739032ad90 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 10:57:41 +0100 Subject: ARM: dts: sun8i: v3s: Change LRADC node names to avoid warnings One of the usage of the LRADC is to implement buttons. The bindings define that we should have one subnode per button, with their associated voltage as a property. However, there was no reg property but we still used the voltage associated to the button as the unit-address, which eventually generated warnings in DTC. Rename the node names to avoid those warnings. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts index ad173605b1b8..db5cd0b8574b 100644 --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts @@ -66,28 +66,28 @@ vref-supply = <®_vcc3v0>; status = "okay"; - button@200 { + button-200 { label = "Volume Up"; linux,code = ; channel = <0>; voltage = <200000>; }; - button@400 { + button-400 { label = "Volume Down"; linux,code = ; channel = <0>; voltage = <400000>; }; - button@600 { + button-600 { label = "Select"; linux,code = ; channel = <0>; voltage = <600000>; }; - button@800 { + button-800 { label = "Start"; linux,code = ; channel = <0>; -- cgit From 438a44ce7e51ce571f942433c6c7cb87c4c0effd Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 7 Nov 2018 10:58:01 +0100 Subject: ARM: dts: sun8i: v3s: Change pinctrl nodes to avoid warning All our pinctrl nodes were using a node name convention with a unit-address to differentiate the different muxing options. However, since those nodes didn't have a reg property, they were generating warnings in DTC. In order to accomodate for this, convert the old nodes to the syntax we've been using for the new SoCs, including removing the letter suffix of the node labels to the bank of those pins to make things more readable. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 4 ++-- arch/arm/boot/dts/sun8i-v3s.dtsi | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts index 387fc2aa546d..333df90e8037 100644 --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts @@ -78,7 +78,7 @@ }; &mmc0 { - pinctrl-0 = <&mmc0_pins_a>; + pinctrl-0 = <&mmc0_pins>; pinctrl-names = "default"; broken-cd; bus-width = <4>; @@ -87,7 +87,7 @@ }; &uart0 { - pinctrl-0 = <&uart0_pins_a>; + pinctrl-0 = <&uart0_pb_pins>; pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 443b083c6adc..92fcb756a08a 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -292,17 +292,17 @@ interrupt-controller; #interrupt-cells = <3>; - i2c0_pins: i2c0 { + i2c0_pins: i2c0-pins { pins = "PB6", "PB7"; function = "i2c0"; }; - uart0_pins_a: uart0@0 { + uart0_pb_pins: uart0-pb-pins { pins = "PB8", "PB9"; function = "uart0"; }; - mmc0_pins_a: mmc0@0 { + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; @@ -310,7 +310,7 @@ bias-pull-up; }; - mmc1_pins: mmc1 { + mmc1_pins: mmc1-pins { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1"; @@ -318,7 +318,7 @@ bias-pull-up; }; - spi0_pins: spi0 { + spi0_pins: spi0-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0"; }; -- cgit From 93870e414d511bbf91a30c052ef291fc8af18eb8 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 20 Nov 2018 22:03:28 +0100 Subject: ARM: dts: sun8i: v3s: Provide default muxing for relevant controllers The MMC0 controllers have only one muxing option in the SoC. In such a case, we can just move the muxing into the DTSI, and remove it from the DTS. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 2 -- arch/arm/boot/dts/sun8i-v3s.dtsi | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts index 333df90e8037..99c8cf7bb86c 100644 --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts @@ -78,8 +78,6 @@ }; &mmc0 { - pinctrl-0 = <&mmc0_pins>; - pinctrl-names = "default"; broken-cd; bus-width = <4>; vmmc-supply = <®_vcc3v3>; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 92fcb756a08a..21e1806ca509 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -192,6 +192,8 @@ resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- cgit From 4403037daf66104a8c81cffd50395fb8a2e7163e Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 21 Nov 2018 09:39:24 +0100 Subject: ARM: dts: sun8i: v3s: Remove skeleton and memory to avoid warnings Our memory node will generate a warning in DTC since the unit address is not matching the reg property. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a83t.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 5617dd387fd3..b099d2fbb5cd 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -187,11 +187,6 @@ status = "disabled"; }; - memory { - reg = <0x40000000 0x80000000>; - device_type = "memory"; - }; - cpu0_opp_table: opp_table0 { compatible = "operating-points-v2"; opp-shared; -- cgit From c00e3f8080d1ad8645ba51ae34817df830b44fa2 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 20 Sep 2018 23:01:01 -0700 Subject: arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC Add clock nodes for HiSilicon Hi3670 SoC. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 43 +++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index c90e6f6a34ec..8a0ee4b08886 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -7,6 +7,7 @@ */ #include +#include / { compatible = "hisilicon,hi3670"; @@ -144,6 +145,48 @@ #size-cells = <2>; ranges; + crg_ctrl: crg_ctrl@fff35000 { + compatible = "hisilicon,hi3670-crgctrl", "syscon"; + reg = <0x0 0xfff35000 0x0 0x1000>; + #clock-cells = <1>; + }; + + pctrl: pctrl@e8a09000 { + compatible = "hisilicon,hi3670-pctrl", "syscon"; + reg = <0x0 0xe8a09000 0x0 0x1000>; + #clock-cells = <1>; + }; + + pmuctrl: crg_ctrl@fff34000 { + compatible = "hisilicon,hi3670-pmuctrl", "syscon"; + reg = <0x0 0xfff34000 0x0 0x1000>; + #clock-cells = <1>; + }; + + sctrl: sctrl@fff0a000 { + compatible = "hisilicon,hi3670-sctrl", "syscon"; + reg = <0x0 0xfff0a000 0x0 0x1000>; + #clock-cells = <1>; + }; + + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3670-iomcu", "syscon"; + reg = <0x0 0xffd7e000 0x0 0x1000>; + #clock-cells = <1>; + }; + + media1_crg: media1_crgctrl@e87ff000 { + compatible = "hisilicon,hi3670-media1-crg", "syscon"; + reg = <0x0 0xe87ff000 0x0 0x1000>; + #clock-cells = <1>; + }; + + media2_crg: media2_crgctrl@e8900000 { + compatible = "hisilicon,hi3670-media2-crg","syscon"; + reg = <0x0 0xe8900000 0x0 0x1000>; + #clock-cells = <1>; + }; + uart6_clk: clk_19_2M { compatible = "fixed-clock"; #clock-cells = <0>; -- cgit From a758dd2e3a5108ab84c33c1069dd838f866b014e Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 20 Sep 2018 23:01:02 -0700 Subject: arm64: dts: hisilicon: Source SoC clock for UART6 Remove fixed clock and source SoC clock for UART6 for HiSilicon Hi3670 SoC. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 8a0ee4b08886..34a2f0dbc6f7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -187,17 +187,12 @@ #clock-cells = <1>; }; - uart6_clk: clk_19_2M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - uart6: serial@fff32000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfff32000 0x0 0x1000>; interrupts = ; - clocks = <&uart6_clk &uart6_clk>; + clocks = <&crg_ctrl HI3670_CLK_UART6>, + <&crg_ctrl HI3670_PCLK>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; -- cgit From 274c516d6490c7f18458afb32cdfd5b6fe9af236 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 24 Oct 2018 00:36:51 +0530 Subject: arm64: dts: hisilicon: Add Pinctrl support for HiKey970 board Add pinctrl support based on "pinctrl-single" driver for HiKey970 development board from HiSilicon. Signed-off-by: Manivannan Sadhasivam Acked-by: Linus Walleij Signed-off-by: Wei Xu --- .../arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi new file mode 100644 index 000000000000..64fb9a3bd707 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl dts file for HiSilicon HiKey970 development board + */ + +#include + +/ { + soc { + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + + pmx0: pinmux@e896c000 { + compatible = "pinctrl-single"; + reg = <0x0 0xe896c000 0x0 0x72c>; + #pinctrl-cells = <1>; + #gpio-range-cells = <0x3>; + pinctrl-single,register-width = <0x20>; + pinctrl-single,function-mask = <0x7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 82 0>; + }; + + pmx2: pinmux@e896c800 { + compatible = "pinconf-single"; + reg = <0x0 0xe896c800 0x0 0x72c>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + }; + + pmx5: pinmux@fc182000 { + compatible = "pinctrl-single"; + reg = <0x0 0xfc182000 0x0 0x028>; + #gpio-range-cells = <3>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + pinctrl-single,function-mask = <0x7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 10 0>; + + }; + + pmx6: pinmux@fc182800 { + compatible = "pinconf-single"; + reg = <0x0 0xfc182800 0x0 0x028>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + }; + + pmx7: pinmux@ff37e000 { + compatible = "pinctrl-single"; + reg = <0x0 0xff37e000 0x0 0x030>; + #gpio-range-cells = <3>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + pinctrl-single,function-mask = <7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 12 0>; + }; + + pmx8: pinmux@ff37e800 { + compatible = "pinconf-single"; + reg = <0x0 0xff37e800 0x0 0x030>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + }; + + pmx1: pinmux@fff11000 { + compatible = "pinctrl-single"; + reg = <0x0 0xfff11000 0x0 0x73c>; + #gpio-range-cells = <0x3>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + pinctrl-single,function-mask = <0x7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 46 0>; + }; + + pmx16: pinmux@fff11800 { + compatible = "pinconf-single"; + reg = <0x0 0xfff11800 0x0 0x73c>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + }; + }; +}; -- cgit From e793b284d7f37c3b41ea8581fb0d0dd48dfac7a8 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Mon, 5 Nov 2018 21:27:27 +0100 Subject: arm: dts: socfpga*.dts*: use SPDX-License-Identifier Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 16 +------- arch/arm/boot/dts/socfpga_arria10.dtsi | 13 +----- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 14 +------ arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts | 13 +----- arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts | 13 +----- arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 14 +------ arch/arm/boot/dts/socfpga_arria5.dtsi | 15 +------ arch/arm/boot/dts/socfpga_arria5_socdk.dts | 16 +------- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 16 +------- .../arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts | 13 +----- arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 14 +------ arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 14 +------ arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 16 +------- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 16 +------- arch/arm/boot/dts/socfpga_cyclone5_socrates.dts | 16 +------- arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 16 +------- arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 46 +--------------------- arch/arm/boot/dts/socfpga_vt.dts | 16 +------- 18 files changed, 28 insertions(+), 269 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2d300396f0ed..2458d6707dc5 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * Copyright (C) 2012 Altera */ #include diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 59ef13e37536..0b1ab88b4039 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright Altera Corporation (C) 2014. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . */ #include diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 64cc86a98771..360dae5a5b12 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . */ #include "socfpga_arria10.dtsi" diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts index d14f9ccb6e10..e36e0a0f8aa6 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2015 Altera Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . */ /dts-v1/; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts index beb2fc6b9eb6..b4c0a76a4d1a 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2016 Intel. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . */ /dts-v1/; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts index 5822fd2085db..df2bab1624d4 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2014-2015 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . */ /dts-v1/; diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index e59461f5416e..22dbf07afcff 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2013 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . + * Copyright (C) 2013 Altera Corporation */ /dts-v1/; diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index aac4feea86f3..90e676e7019f 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2013 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * Copyright (C) 2013 Altera Corporation */ #include "socfpga_arria5.dtsi" diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index 68ced67f8bfb..319a71e41ea4 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * Copyright (C) 2012 Altera Corporation */ /dts-v1/; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts index 31b01a998b2e..67076e1b1c7f 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright Altera Corporation (C) 2015. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . */ #include "socfpga_cyclone5.dtsi" diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi index 3c03da6b8b1d..bd92806ffc12 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015 Marek Vasut - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . */ #include "socfpga_cyclone5.dtsi" diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts index c2eb88aab8b3..ceaec29770c6 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015 Marek Vasut - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . */ #include "socfpga_cyclone5_mcv.dtsi" diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 155829f9eba1..6f138b2b2616 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * Copyright (C) 2012 Altera Corporation */ #include "socfpga_cyclone5.dtsi" diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index a4a555c19d94..c155ff02eb6e 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2013 Steffen Trumtrar - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * Copyright (C) 2013 Steffen Trumtrar */ #include "socfpga_cyclone5.dtsi" diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts index 031c721441ff..8d5d3996f6f2 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014 Steffen Trumtrar - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * Copyright (C) 2014 Steffen Trumtrar */ #include "socfpga_cyclone5.dtsi" diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts index 8860dd2e242c..e54b5f2af74f 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2016 Nobuhiro Iwamatsu - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * Copyright (C) 2016 Nobuhiro Iwamatsu */ #include "socfpga_cyclone5.dtsi" diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index e61efe16e79c..355b3dbf438d 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -1,48 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) /* - * Copyright (C) 2015 Marek Vasut - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2015 Marek Vasut */ #include "socfpga_cyclone5.dtsi" diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 547c38632c68..a77846f73b34 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2013 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * Copyright (C) 2013 Altera Corporation */ /dts-v1/; -- cgit From 3e464ad53ce0ec66212aa001a87f87c362f8d818 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 8 Nov 2018 10:10:57 -0600 Subject: arm: dts: socfpga: remove dma-mask property The dma-mask property has been removed from the NAND driver. Remove the property from the DTS files. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 1 - arch/arm/boot/dts/socfpga_arria10.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2458d6707dc5..a9135d77d7aa 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -746,7 +746,6 @@ <0xffb80000 0x10000>; reg-names = "nand_data", "denali_reg"; interrupts = <0x0 0x90 0x4>; - dma-mask = <0xffffffff>; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; status = "disabled"; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 0b1ab88b4039..e41fa23481c3 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -653,7 +653,6 @@ <0xffb80000 0x10000>; reg-names = "nand_data", "denali_reg"; interrupts = <0 99 4>; - dma-mask = <0xffffffff>; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; status = "disabled"; -- cgit From d23968448f291d9cbb67432ac6bb1a1a25dd4ec8 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Mon, 5 Nov 2018 21:39:00 +0100 Subject: ARM: dts: socfpga: use tabs for indentation In two of the gen5 socfpga devicetree files, there are some lines indented using spaces instead of tabs. Fix this by correctly indenting them with tabs. Signed-off-by: Simon Goldschmidt Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 2 +- arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index a9135d77d7aa..dcb8fba3d709 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -758,7 +758,7 @@ qspi: spi@ff705000 { compatible = "cdns,qspi-nor"; - #address-cells = <1>; + #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, <0xffa00000 0x1000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts index e54b5f2af74f..99a71757cdf4 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts @@ -111,9 +111,9 @@ }; &qspi { - status = "okay"; + status = "okay"; - flash0: n25q512a@0 { + flash0: n25q512a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q512a"; -- cgit From 8bb4f3f55961954154967d4747686ababb67df0d Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 18 Oct 2018 13:57:01 -0500 Subject: arm64: dts: stratix10: use "altr,stratix10-rst-mgr" binding The standard reset-simple driver the uses the "altr,rst-mgr" binding is not getting initialized early enough in the boot process, so timers that the kernel needs are still left in reset. Thus an early reset driver was created. This early reset driver is only for the SoCFPGA 32-bit platform. The Stratix10 platform does not need any of the timers that in reset to boot, thus we don't need to early reset driver. Therefore, use the "altr,stratix10-rst-mgr" binding for the reset-simple platform driver on the Stratix10 platform. Also remove the "altr,modrst-offset" property because the driver no longer needs it. Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 8253a1a9e985..cadf14d03a76 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -308,9 +308,8 @@ rst: rstmgr@ffd11000 { #reset-cells = <1>; - compatible = "altr,rst-mgr"; + compatible = "altr,stratix10-rst-mgr"; reg = <0xffd11000 0x1000>; - altr,modrst-offset = <0x20>; }; spi0: spi@ffda4000 { -- cgit From b4c7bf003cb57220af64b59e887581e74f0ce527 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 21 Sep 2018 12:03:54 +0200 Subject: dt-bindings: tegra186-pmc: Add interrupt controller properties The PMC can be a top-level interrupt controller that provides the top- level controls for wake events. Add optional properties to mark the PMC as interrupt controller. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt index c9fd6d1de57e..2d89cdc39eb0 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt @@ -15,6 +15,9 @@ Required properties: Optional properties: - nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. +- interrupt-controller: Identifies the node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The value must be 2. Example: -- cgit From 36ec29f781a21a5b0599766ba11766837695209b Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 28 Sep 2018 15:11:50 +0100 Subject: arm64: dts: tegra210: Add power-domains for xHCI Populate the power-domain properties for the xHCI device for Tegra210. Signed-off-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 8fe47d6445a5..2205d66b0443 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -879,6 +879,8 @@ resets = <&tegra_car 89>, <&tegra_car 156>, <&tegra_car 143>; reset-names = "xusb_host", "xusb_ss", "xusb_src"; + power-domains = <&pd_xusbhost>, <&pd_xusbss>; + power-domain-names = "xusb_host", "xusb_ss"; nvidia,xusb-padctl = <&padctl>; -- cgit From 6a574ec70c52c9ff5524d95e3061a24ffb202a52 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 21 Sep 2018 11:05:52 +0200 Subject: arm64: tegra: Add PWM controllers on Tegra194 Tegra194 has eight single-channel PWM controllers, one of them in the AON partition. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 96 ++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 9fc14bb9a0af..c2091bb16546 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -209,6 +209,90 @@ status = "disabled"; }; + pwm1: pwm@3280000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x3280000 0x10000>; + clocks = <&bpmp TEGRA194_CLK_PWM1>; + clock-names = "pwm"; + resets = <&bpmp TEGRA194_RESET_PWM1>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm2: pwm@3290000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x3290000 0x10000>; + clocks = <&bpmp TEGRA194_CLK_PWM2>; + clock-names = "pwm"; + resets = <&bpmp TEGRA194_RESET_PWM2>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm3: pwm@32a0000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x32a0000 0x10000>; + clocks = <&bpmp TEGRA194_CLK_PWM3>; + clock-names = "pwm"; + resets = <&bpmp TEGRA194_RESET_PWM3>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm5: pwm@32c0000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x32c0000 0x10000>; + clocks = <&bpmp TEGRA194_CLK_PWM5>; + clock-names = "pwm"; + resets = <&bpmp TEGRA194_RESET_PWM5>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm6: pwm@32d0000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x32d0000 0x10000>; + clocks = <&bpmp TEGRA194_CLK_PWM6>; + clock-names = "pwm"; + resets = <&bpmp TEGRA194_RESET_PWM6>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm7: pwm@32e0000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x32e0000 0x10000>; + clocks = <&bpmp TEGRA194_CLK_PWM7>; + clock-names = "pwm"; + resets = <&bpmp TEGRA194_RESET_PWM7>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm8: pwm@32f0000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x32f0000 0x10000>; + clocks = <&bpmp TEGRA194_CLK_PWM8>; + clock-names = "pwm"; + resets = <&bpmp TEGRA194_RESET_PWM8>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + sdmmc1: sdhci@3400000 { compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03400000 0x10000>; @@ -313,6 +397,18 @@ status = "disabled"; }; + pwm4: pwm@c340000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0xc340000 0x10000>; + clocks = <&bpmp TEGRA194_CLK_PWM4>; + clock-names = "pwm"; + resets = <&bpmp TEGRA194_RESET_PWM4>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + pmc@c360000 { compatible = "nvidia,tegra194-pmc"; reg = <0x0c360000 0x10000>, -- cgit From 585423535cd695bf452d3c485791557439a5a97e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 21 Sep 2018 11:08:28 +0200 Subject: arm64: tegra: Add PWM fan support on Jetson Xavier Enable PWM4 in device tree and use it to drive the PWM fan on the Jetson Xavier. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 9ff3c18280c4..86f05504ca38 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -12,5 +12,14 @@ sdhci@3400000 { status = "okay"; }; + + pwm@c340000 { + status = "okay"; + }; + }; + + fan { + compatible = "pwm-fan"; + pwms = <&pwm4 0 45334>; }; }; -- cgit From 73b551ba8fed31118973c906a31588298d4c0891 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 23 Nov 2018 14:29:31 +0100 Subject: arm64: tegra: Clarify that P2972-0000 is Jetson Xavier The official name for the P2972-0000 board is Jetson AGX Xavier Development Kit. Set that as the model string in the device tree for clarity. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 86f05504ca38..d4cd241b7666 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -4,7 +4,7 @@ #include "tegra194-p2888.dtsi" / { - model = "NVIDIA Tegra194 P2972-0000 Development Board"; + model = "NVIDIA Jetson AGX Xavier Development Kit"; compatible = "nvidia,p2972-0000", "nvidia,tegra194"; cbb { -- cgit From 0567022c019ad1a1d7bb980a99797f7a7a11d7d3 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Wed, 28 Nov 2018 04:53:35 -0500 Subject: ARM: dts: qcom: msm8974-hammerhead: correct gpios property on magnetometer This patch correctly sets the gpios property for the ak8963 magnetometer's DRDY pin so that interrupts work properly. Signed-off-by: Brian Masney Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index ed8f064d0895..51444c53fc72 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -327,8 +327,7 @@ ak8963@f { compatible = "asahi-kasei,ak8963"; reg = <0x0f>; - // Currently only works in polling mode. - // gpios = <&msmgpio 61 0>; + gpios = <&msmgpio 67 0>; vid-supply = <&pm8941_lvs1>; vdd-supply = <&pm8941_l17>; }; -- cgit From 28d13d317bacd7b5316a8bd21488e9850b8e84c1 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 5 Nov 2018 13:09:20 -0800 Subject: ARM: dts: qcom: Add SoC-specific string for sdhci-msm-v4 nodes As per upstream discussion [1], we should have an SoC-specific compatible string for Qualcomm's SDHCI nodes. Let's add it. [1] https://lkml.kernel.org/r/20181105203657.GA32282@bogus Signed-off-by: Douglas Anderson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8084.dtsi | 4 ++-- arch/arm/boot/dts/qcom-msm8974.dtsi | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 0e1e98707e3f..899f28533ed7 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -412,7 +412,7 @@ }; sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <0 123 0>, <0 138 0>; @@ -425,7 +425,7 @@ }; sdhci@f98a4900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <0 125 0>, <0 221 0>; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index c3470f9ec747..ca266a5f021d 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -604,7 +604,7 @@ }; sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = , @@ -618,7 +618,7 @@ }; sdhci@f9864900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = , @@ -632,7 +632,7 @@ }; sdhci@f98a4900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = , -- cgit From 972910948fb6f555e83f37bc6172f51984d738a9 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Thu, 15 Nov 2018 11:35:10 -0800 Subject: ARM: dts: qcom: Remove Arrow SD600 eval board This patch removes support for the APQ8064 based Arrow SD600 eval board. This board was never sold publicly and had very limited distribution. As such, we are removing this board and no longer going to support it. Signed-off-by: Andy Gross Reviewed-by: Bjorn Andersson Reviewed-by: Nicolas Dechesne Acked-by: Olof Johansson --- arch/arm/boot/dts/Makefile | 1 - .../dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi | 53 --- .../arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts | 415 --------------------- 3 files changed, 469 deletions(-) delete mode 100644 arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi delete mode 100644 arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..00d6e65c28f5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -783,7 +783,6 @@ dtb-$(CONFIG_ARCH_OXNAS) += \ ox820-cloudengines-pogoplug-series-3.dtb dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8060-dragonboard.dtb \ - qcom-apq8064-arrow-sd-600eval.dtb \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ qcom-apq8064-sony-xperia-yuga.dtb \ diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi deleted file mode 100644 index 8df73156b73a..000000000000 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -&tlmm_pinmux { - card_detect: card-detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; - }; - - pcie_pins: pcie-pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; - }; - - user_leds: user-leds { - mux { - pins = "gpio3", "gpio7", "gpio10", "gpio11"; - function = "gpio"; - }; - - conf { - pins = "gpio3", "gpio7", "gpio10", "gpio11"; - function = "gpio"; - output-low; - }; - }; - - magneto_pins: magneto-pins { - mux { - pins = "gpio31", "gpio48"; - function = "gpio"; - bias-disable; - }; - }; -}; - -&pm8921_mpps { - mpp_leds: mpp-leds { - pinconf { - pins = "mpp7", "mpp8"; - function = "digital"; - output-low; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts deleted file mode 100644 index 76b56eafaab9..000000000000 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts +++ /dev/null @@ -1,415 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8064-v2.0.dtsi" -#include "qcom-apq8064-arrow-sd-600eval-pins.dtsi" -#include -#include - -/ { - model = "Arrow Electronics, APQ8064 SD_600eval"; - compatible = "arrow,sd_600eval", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - serial1 = &gsbi1_serial; - i2c0 = &gsbi2_i2c; - i2c1 = &gsbi3_i2c; - i2c2 = &gsbi4_i2c; - i2c3 = &gsbi7_i2c; - spi0 = &gsbi5_spi; - }; - - regulators { - compatible = "simple-bus"; - vph: regulator-fixed@1 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <4500000>; - regulator-max-microvolt = <4500000>; - regulator-name = "VPH"; - regulator-type = "voltage"; - regulator-boot-on; - }; - - /* on board fixed 3.3v supply */ - vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - }; - - soc { - rpm@108000 { - regulators { - vdd_s1-supply = <&vph>; - vdd_s2-supply = <&vph>; - vdd_s3-supply = <&vph>; - vdd_s4-supply = <&vph>; - vdd_s5-supply = <&vph>; - vdd_s6-supply = <&vph>; - vdd_s7-supply = <&vph>; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l3_l15_l17-supply = <&vph>; - vdd_l4_l14-supply = <&vph>; - vdd_l5_l8_l16-supply = <&vph>; - vdd_l6_l7-supply = <&vph>; - vdd_l9_l11-supply = <&vph>; - vdd_l10_l22-supply = <&vph>; - vdd_l21_l23_l29-supply = <&vph>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s1>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s2 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <1600000>; - bias-pull-down; - regulator-always-on; - }; - - s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <4800000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <1600000>; - qcom,force-mode = ; - bias-pull-down; - regulator-always-on; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - l3 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - l4 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - regulator-boot-on; - regulator-always-on; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - /** - * 1.8v required on LS expansion - * for mezzanine boards - */ - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - l23 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - - lvs7 { - bias-pull-down; - }; - }; - }; - - gsbi@12440000 { - status = "okay"; - qcom,mode = ; - serial@12450000 { - label = "LS-UART1"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi1_uart_4pins>; - }; - }; - - gsbi@12480000 { - status = "okay"; - qcom,mode = ; - i2c@124a0000 { - /* On Low speed expansion and Sensors */ - label = "LS-I2C0"; - status = "okay"; - lis3mdl_mag@1e { - compatible = "st,lis3mdl-magn"; - reg = <0x1e>; - vdd-supply = <&vcc3v3>; - vddio-supply = <&pm8921_s4>; - pinctrl-names = "default"; - pinctrl-0 = <&magneto_pins>; - interrupt-parent = <&tlmm_pinmux>; - - st,drdy-int-pin = <2>; - interrupts = <48 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ - <31 IRQ_TYPE_EDGE_RISING>; /* INT */ - }; - }; - }; - - gsbi@16200000 { - status = "okay"; - qcom,mode = ; - i2c@16280000 { - /* On Low speed expansion */ - status = "okay"; - label = "LS-I2C1"; - clock-frequency = <200000>; - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <64>; - }; - }; - }; - - gsbi@16300000 { - status = "okay"; - qcom,mode = ; - i2c@16380000 { - /* On High speed expansion */ - label = "HS-CAM-I2C3"; - status = "okay"; - }; - }; - - gsbi@1a200000 { - status = "okay"; - spi@1a280000 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; - }; - }; - - /* DEBUG UART */ - gsbi@16600000 { - status = "okay"; - qcom,mode = ; - serial@16640000 { - label = "LS-UART0"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi7_uart_2pins>; - }; - - i2c@16680000 { - /* On High speed expansion */ - status = "okay"; - label = "HS-CAM-I2C2"; - }; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>, <&mpp_leds>; - - compatible = "gpio-leds"; - - user-led0 { - label = "user0-led"; - gpios = <&tlmm_pinmux 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - user-led1 { - label = "user1-led"; - gpios = <&tlmm_pinmux 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - user-led2 { - label = "user2-led"; - gpios = <&tlmm_pinmux 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - user-led3 { - label = "user3-led"; - gpios = <&tlmm_pinmux 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - }; - - wifi-led { - label = "WiFi-led"; - gpios = <&pm8921_mpps 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - bt-led { - label = "BT-led"; - gpios = <&pm8921_mpps 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pci@1b500000 { - status = "okay"; - vdda-supply = <&pm8921_s3>; - vdda_phy-supply = <&pm8921_lvs6>; - vdda_refclk-supply = <&vcc3v3>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; - }; - - phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - status = "okay"; - target-supply = <&pm8921_lvs7>; - }; - - /* OTG */ - usb@12500000 { - status = "okay"; - dr_mode = "peripheral"; - ulpi { - phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - }; - }; - - usb@12520000 { - status = "okay"; - dr_mode = "otg"; - ulpi { - phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - }; - }; - - usb@12530000 { - status = "okay"; - dr_mode = "otg"; - ulpi { - phy { - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - }; - }; - - amba { - /* eMMC */ - sdcc@12400000 { - status = "okay"; - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - - /* External micro SD card */ - sdcc@12180000 { - status = "okay"; - vmmc-supply = <&pm8921_l6>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - }; - - riva-pil@3204000 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>; - }; - - hdmi-tx@4a00000 { - status = "okay"; - core-vdda-supply = <&pm8921_hdmi_switch>; - hdmi-mux-supply = <&vcc3v3>; - - hpd-gpio = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - - hdmi-phy@4a00400 { - status = "okay"; - core-vdda-supply = <&pm8921_hdmi_switch>; - }; - - mdp@5100000 { - status = "okay"; - - ports { - port@3 { - endpoint { - remote-endpoint = <&hdmi_in>; - }; - }; - }; - }; - }; -}; -- cgit From 7e26335b1a3fb2400fcf6d5eb35328257ea2e139 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 9 Nov 2018 15:04:45 +0100 Subject: ARM: dts: meson: consistently disable pin bias On Amlogic chipsets, the bias set through pinconf applies to the pad itself, not only the GPIO function. This means that even when we change the function of the pad from GPIO to anything else, the bias previously set still applies. As we have seen with the eMMC, depending on the bias type and the function, it may trigger problems. The underlying issue is that we inherit whatever was left by previous user of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual setup we will get is undefined. There is nothing mentioned in the documentation about pad bias and pinmux function, however leaving it undefined is not an option. This change consistently disable the pad bias for every pinmux functions. It seems to work well, we can only assume that the necessary bias (if any) is already provided by the pin function itself. Signed-off-by: Jerome Brunet Acked-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 12 ++++++++++++ arch/arm/boot/dts/meson8b.dtsi | 9 +++++++++ arch/arm/boot/dts/meson8m2.dtsi | 1 + 3 files changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 7162e0ca05b0..08c54cf5420a 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -163,6 +163,7 @@ mux { groups = "uart_tx_ao_a", "uart_rx_ao_a"; function = "uart_ao"; + bias-disable; }; }; @@ -170,6 +171,7 @@ mux { groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; function = "i2c_mst_ao"; + bias-disable; }; }; @@ -177,6 +179,7 @@ mux { groups = "remote_input"; function = "remote"; + bias-disable; }; }; @@ -184,6 +187,7 @@ mux { groups = "pwm_f_ao"; function = "pwm_f_ao"; + bias-disable; }; }; }; @@ -238,6 +242,7 @@ groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a"; function = "sd_a"; + bias-disable; }; }; @@ -246,6 +251,7 @@ groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", "sd_d3_b", "sd_clk_b", "sd_cmd_b"; function = "sd_b"; + bias-disable; }; }; @@ -254,6 +260,7 @@ groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c", "sd_clk_c", "sd_cmd_c"; function = "sd_c"; + bias-disable; }; }; @@ -261,6 +268,7 @@ mux { groups = "nor_d", "nor_q", "nor_c", "nor_cs"; function = "nor"; + bias-disable; }; }; @@ -272,6 +280,7 @@ "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc"; function = "ethernet"; + bias-disable; }; }; @@ -279,6 +288,7 @@ mux { groups = "pwm_e"; function = "pwm_e"; + bias-disable; }; }; @@ -287,6 +297,7 @@ groups = "uart_tx_a1", "uart_rx_a1"; function = "uart_a"; + bias-disable; }; }; @@ -295,6 +306,7 @@ groups = "uart_cts_a1", "uart_rts_a1"; function = "uart_a"; + bias-disable; }; }; }; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index cd1ca9dda126..46b3564a6536 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -146,6 +146,7 @@ mux { groups = "uart_tx_ao_a", "uart_rx_ao_a"; function = "uart_ao"; + bias-disable; }; }; @@ -153,6 +154,7 @@ mux { groups = "remote_input"; function = "remote"; + bias-disable; }; }; }; @@ -220,6 +222,7 @@ "eth_txd2", "eth_txd3"; function = "ethernet"; + bias-disable; }; }; @@ -235,6 +238,7 @@ "eth_mdio_en", "eth_mdc"; function = "ethernet"; + bias-disable; }; }; @@ -242,6 +246,7 @@ mux { groups = "i2c_sda_a", "i2c_sck_a"; function = "i2c_a"; + bias-disable; }; }; @@ -250,6 +255,7 @@ groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", "sd_d3_b", "sd_clk_b", "sd_cmd_b"; function = "sd_b"; + bias-disable; }; }; @@ -257,6 +263,7 @@ mux { groups = "pwm_c1"; function = "pwm_c"; + bias-disable; }; }; @@ -265,6 +272,7 @@ groups = "uart_tx_b0", "uart_rx_b0"; function = "uart_b"; + bias-disable; }; }; @@ -273,6 +281,7 @@ groups = "uart_cts_b0", "uart_rts_b0"; function = "uart_b"; + bias-disable; }; }; }; diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi index 3e1f92273d7b..d1a28c2adac5 100644 --- a/arch/arm/boot/dts/meson8m2.dtsi +++ b/arch/arm/boot/dts/meson8m2.dtsi @@ -45,6 +45,7 @@ "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc"; function = "ethernet"; + bias-disable; }; }; }; -- cgit From 523b8b31d3e1292b69f233e1a1814151878d6ac8 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 16 Nov 2018 21:42:34 +0100 Subject: ARM: dts: meson: add the TIMER B/C/D interrupts The timer on Meson6/Meson8/Meson8b SoCs has four internal timer events. For each of these a separate interrupt exists. Pass these interrupts to allow using the timers other than TIMER A. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 0d9faf1a51ea..f0255450bcb2 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -200,7 +200,10 @@ timer@9940 { compatible = "amlogic,meson6-timer"; reg = <0x9940 0x18>; - interrupts = ; + interrupts = , + , + , + ; }; }; -- cgit From 7b141abe4aa137f362d7324de5a49fd3105f570f Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 16 Nov 2018 21:42:35 +0100 Subject: ARM: dts: meson: add the clock inputs for the Meson timer The Meson Timer IP block has two clock inputs: - clk81 for using the system clock as timebase - xtal for a timebase with 1us, 10us, 100us and 1ms resolution The clocksource driver does not use these yet, but it's still a good idea to add them as this describes how the hardware actually works internally. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 2 +- arch/arm/boot/dts/meson6.dtsi | 5 +++++ arch/arm/boot/dts/meson8.dtsi | 5 +++++ arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 4 files changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index f0255450bcb2..0839da07a75c 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -197,7 +197,7 @@ interrupts = ; }; - timer@9940 { + timer_abcde: timer@9940 { compatible = "amlogic,meson6-timer"; reg = <0x9940 0x18>; interrupts = , diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index 9b463211339f..ca978ab952cd 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -88,6 +88,11 @@ status = "disabled"; }; +&timer_abcde { + clocks = <&xtal>, <&clk81>; + clock-names = "xtal", "pclk"; +}; + &uart_AO { clocks = <&xtal>, <&clk81>, <&clk81>; clock-names = "xtal", "pclk", "baud"; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 08c54cf5420a..3be5fbd07997 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -387,6 +387,11 @@ clocks = <&clkc CLKID_CLK81>; }; +&timer_abcde { + clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk"; +}; + &uart_AO { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 46b3564a6536..587a855f872b 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -370,6 +370,11 @@ clock-names = "core", "clkin"; }; +&timer_abcde { + clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "pclk"; +}; + &uart_AO { compatible = "amlogic,meson8b-uart", "amlogic,meson-uart"; clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; -- cgit From f1fe12c8bf33241e04c57a0fc5b25b16ba77ba2d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 15 Feb 2018 16:12:29 +0100 Subject: ARM: dts: Modernize the Vexpress PL111 integration The Versatile Express was submitted with the actual display bridges unconnected (but defined in the device tree) and mock "panels" encoded in the device tree node of the PL111 controller. This doesn't even remotely describe the actual Versatile Express hardware. Exploit the SiI9022 bridge by connecting the PL111 pads to it, making it use EDID or fallback values to drive the monitor. The also has to use the reserved memory through the CMA pool rather than by open coding a memory region and remapping it explicitly in the driver. To achieve this, a reserved-memory node must exist in the root of the device tree, so we need to pull that out of the motherboard .dtsi include files, and push it into each top-level device tree instead. We do the same manouver for all the Versatile Express boards, taking into account the different location of the video RAM depending on which chip select is used on each platform. This plays nicely with the new PL111 DRM driver and follows the standard ways of assigning bridges and memory pools for graphics. Cc: Sudeep Holla Cc: Lorenzo Pieralisi Cc: Liviu Dudau Cc: Mali DP Maintainers Cc: Robin Murphy Tested-by: Liviu Dudau Signed-off-by: Linus Walleij --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 49 ++++++----------- arch/arm/boot/dts/vexpress-v2m.dtsi | 63 +++++++++++----------- arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 14 +++++ arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 14 +++++ arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 14 +++++ arch/arm/boot/dts/vexpress-v2p-ca9.dts | 43 +++++++-------- arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 23 ++++++++ arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 37 ++----------- .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 14 +++++ 9 files changed, 150 insertions(+), 121 deletions(-) diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index 4488c8fe213a..a9569d15de41 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -43,11 +43,6 @@ bank-width = <4>; }; - v2m_video_ram: vram@2,00000000 { - compatible = "arm,vexpress-vram"; - reg = <2 0x00000000 0x00800000>; - }; - ethernet@2,02000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <2 0x02000000 0x10000>; @@ -223,13 +218,24 @@ v2m_i2c_dvi: i2c@160000 { compatible = "arm,versatile-i2c"; reg = <0x160000 0x1000>; - #address-cells = <1>; #size-cells = <0>; dvi-transmitter@39 { compatible = "sil,sii9022-tpi", "sil,sii9022"; reg = <0x39>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dvi_bridge_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; }; dvi-transmitter@60 { @@ -260,37 +266,16 @@ interrupts = <14>; clocks = <&v2m_oscclk1>, <&smbclk>; clock-names = "clcdclk", "apb_pclk"; - memory-region = <&v2m_video_ram>; - max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */ + /* 800x600 16bpp @36MHz works fine */ + max-memory-bandwidth = <54000000>; + memory-region = <&vram>; port { - v2m_clcd_pads: endpoint { - remote-endpoint = <&v2m_clcd_panel>; + clcd_pads: endpoint { + remote-endpoint = <&dvi_bridge_in>; arm,pl11x,tft-r0g0b0-pads = <0 8 16>; }; }; - - panel { - compatible = "panel-dpi"; - - port { - v2m_clcd_panel: endpoint { - remote-endpoint = <&v2m_clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <40>; - hfront-porch = <24>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <2>; - }; - }; }; }; diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index 4db42f6326a3..fd42e1194179 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -43,11 +43,6 @@ bank-width = <4>; }; - v2m_video_ram: vram@3,00000000 { - compatible = "arm,vexpress-vram"; - reg = <3 0x00000000 0x00800000>; - }; - ethernet@3,02000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <3 0x02000000 0x10000>; @@ -223,13 +218,37 @@ v2m_i2c_dvi: i2c@16000 { compatible = "arm,versatile-i2c"; reg = <0x16000 0x1000>; - #address-cells = <1>; #size-cells = <0>; dvi-transmitter@39 { compatible = "sil,sii9022-tpi", "sil,sii9022"; reg = <0x39>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Both the core tile and the motherboard routes their output + * pads to this transmitter. The motherboard system controller + * can select one of them as input using a mux register in + * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is + * the only platform with this specific set-up. + */ + port@0 { + reg = <0>; + dvi_bridge_in_ct: endpoint { + remote-endpoint = <&clcd_pads_ct>; + }; + }; + port@1 { + reg = <1>; + dvi_bridge_in_mb: endpoint { + remote-endpoint = <&clcd_pads_mb>; + }; + }; + }; }; dvi-transmitter@60 { @@ -253,6 +272,7 @@ reg-shift = <2>; }; + clcd@1f000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x1f000 0x1000>; @@ -260,37 +280,16 @@ interrupts = <14>; clocks = <&v2m_oscclk1>, <&smbclk>; clock-names = "clcdclk", "apb_pclk"; - memory-region = <&v2m_video_ram>; - max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */ + /* 800x600 16bpp @36MHz works fine */ + max-memory-bandwidth = <54000000>; + memory-region = <&vram>; port { - v2m_clcd_pads: endpoint { - remote-endpoint = <&v2m_clcd_panel>; + clcd_pads_mb: endpoint { + remote-endpoint = <&dvi_bridge_in_mb>; arm,pl11x,tft-r0g0b0-pads = <0 8 16>; }; }; - - panel { - compatible = "panel-dpi"; - - port { - v2m_clcd_panel: endpoint { - remote-endpoint = <&v2m_clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <25175000>; - hactive = <640>; - hback-porch = <40>; - hfront-porch = <24>; - hsync-len = <96>; - vactive = <480>; - vback-porch = <32>; - vfront-porch = <11>; - vsync-len = <2>; - }; - }; }; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index 3971427a105b..0dc4277d5f8b 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts @@ -53,6 +53,20 @@ reg = <0 0x80000000 0 0x40000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Chipselect 2 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0 0x18000000 0 0x00800000>; + no-map; + }; + }; + hdlcd@2b000000 { compatible = "arm,hdlcd"; reg = <0 0x2b000000 0 0x1000>; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index ac6b90e9d806..a5136b1adaa2 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -104,6 +104,20 @@ reg = <0 0x80000000 0 0x40000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Chipselect 2 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0 0x18000000 0 0x00800000>; + no-map; + }; + }; + wdt@2a490000 { compatible = "arm,sp805", "arm,primecell"; reg = <0 0x2a490000 0 0x1000>; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts index e5b4a7570a01..d5b47d526f9e 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts @@ -55,6 +55,20 @@ reg = <0x80000000 0x40000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Chipselect 2 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0x18000000 0x00800000>; + no-map; + }; + }; + hdlcd@2a110000 { compatible = "arm,hdlcd"; reg = <0x2a110000 0x1000>; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index fc43873cbdff..d796efaadbe3 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -69,6 +69,20 @@ reg = <0x60000000 0x40000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Chipselect 3 is physically at 0x4c000000 */ + vram: vram@4c000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0x4c000000 0x00800000>; + no-map; + }; + }; + clcd@10020000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x10020000 0x1000>; @@ -76,36 +90,15 @@ interrupts = <0 44 4>; clocks = <&oscclk1>, <&oscclk2>; clock-names = "clcdclk", "apb_pclk"; - max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ + /* 1024x768 16bpp @65MHz */ + max-memory-bandwidth = <95000000>; port { - clcd_pads: endpoint { - remote-endpoint = <&clcd_panel>; + clcd_pads_ct: endpoint { + remote-endpoint = <&dvi_bridge_in_ct>; arm,pl11x,tft-r0g0b0-pads = <0 8 16>; }; }; - - panel { - compatible = "panel-dpi"; - - port { - clcd_panel: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <63500127>; - hactive = <1024>; - hback-porch = <152>; - hfront-porch = <48>; - hsync-len = <104>; - vactive = <768>; - vback-porch = <23>; - vfront-porch = <3>; - vsync-len = <4>; - }; - }; }; memory-controller@100e0000 { diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts index 602f63f72c37..fe4fda473c0a 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts +++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts @@ -78,6 +78,20 @@ <0x00000008 0x80000000 0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Chipselect 2,00000000 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0x00000000 0x18000000 0 0x00800000>; + no-map; + }; + }; + gic: interrupt-controller@2c001000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -107,6 +121,15 @@ <0 63 4>; }; + panel { + compatible = "arm,rtsm-display"; + port { + panel_in: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + }; + smb@8000000 { compatible = "simple-bus"; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index d2dbc3f39263..b25f3cbd3da8 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -24,11 +24,6 @@ bank-width = <4>; }; - v2m_video_ram: vram@2,00000000 { - compatible = "arm,vexpress-vram"; - reg = <2 0x00000000 0x00800000>; - }; - ethernet@2,02000000 { compatible = "smsc,lan91c111"; reg = <2 0x02000000 0x10000>; @@ -187,38 +182,16 @@ interrupts = <14>; clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; clock-names = "clcdclk", "apb_pclk"; - arm,pl11x,framebuffer = <0x18000000 0x00180000>; - memory-region = <&v2m_video_ram>; - max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ + /* 800x600 16bpp @36MHz works fine */ + max-memory-bandwidth = <54000000>; + memory-region = <&vram>; port { - v2m_clcd_pads: endpoint { - remote-endpoint = <&v2m_clcd_panel>; + clcd_pads: endpoint { + remote-endpoint = <&panel_in>; arm,pl11x,tft-r0g0b0-pads = <0 8 16>; }; }; - - panel { - compatible = "panel-dpi"; - - port { - v2m_clcd_panel: endpoint { - remote-endpoint = <&v2m_clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <63500127>; - hactive = <1024>; - hback-porch = <152>; - hfront-porch = <48>; - hsync-len = <104>; - vactive = <768>; - vback-porch = <23>; - vfront-porch = <3>; - vsync-len = <4>; - }; - }; }; virtio-block@130000 { diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts index 38880380e0fa..8981c3d2ff18 100644 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -65,6 +65,20 @@ reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Chipselect 2 is physically at 0x18000000 */ + vram: vram@18000000 { + /* 8 MB of designated video RAM */ + compatible = "shared-dma-pool"; + reg = <0 0x18000000 0 0x00800000>; + no-map; + }; + }; + gic: interrupt-controller@2c001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit From e18813021a11c4f7c7fd21deb69589db8a8f9f8c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 24 Oct 2018 00:36:52 +0530 Subject: arm64: dts: hisilicon: hi3670: Add GPIO controller support Add GPIO controller support for HiSilicon HI3670 SoC based on ARM Primecell PL061 GPIO controller. Signed-off-by: Manivannan Sadhasivam Acked-by: Linus Walleij Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts | 1 + arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 379 ++++++++++++++++++++++ 2 files changed, 380 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts index 4f5118642024..8fdc1dfcb06c 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "hi3670.dtsi" +#include "hikey970-pinctrl.dtsi" / { model = "HiKey970"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 34a2f0dbc6f7..b99f5e0fe577 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -196,5 +196,384 @@ clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; + + gpio0: gpio@e8a0b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a0b000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO0>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@e8a0c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a0c000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO1>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@e8a0d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a0d000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 1 6 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO2>; + clock-names = "apb_pclk"; + }; + + gpio3: gpio@e8a0e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a0e000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO3>; + clock-names = "apb_pclk"; + }; + + gpio4: gpio@e8a0f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a0f000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 18 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO4>; + clock-names = "apb_pclk"; + }; + + gpio5: gpio@e8a10000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a10000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 26 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO5>; + clock-names = "apb_pclk"; + }; + + gpio6: gpio@e8a11000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a11000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 1 34 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO6>; + clock-names = "apb_pclk"; + }; + + gpio7: gpio@e8a12000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a12000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 41 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO7>; + clock-names = "apb_pclk"; + }; + + gpio8: gpio@e8a13000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a13000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 49 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO8>; + clock-names = "apb_pclk"; + }; + + gpio9: gpio@e8a14000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a14000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 57 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO9>; + clock-names = "apb_pclk"; + }; + + gpio10: gpio@e8a15000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a15000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 65 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO10>; + clock-names = "apb_pclk"; + }; + + gpio11: gpio@e8a16000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a16000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 73 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO11>; + clock-names = "apb_pclk"; + }; + + gpio12: gpio@e8a17000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a17000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 81 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO12>; + clock-names = "apb_pclk"; + }; + + gpio13: gpio@e8a18000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a18000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO13>; + clock-names = "apb_pclk"; + }; + + gpio14: gpio@e8a19000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a19000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO14>; + clock-names = "apb_pclk"; + }; + + gpio15: gpio@e8a1a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a1a000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO15>; + clock-names = "apb_pclk"; + }; + + gpio16: gpio@e8a1b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a1b000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx5 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO16>; + clock-names = "apb_pclk"; + }; + + gpio17: gpio@e8a1c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a1c000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx5 0 8 2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO17>; + clock-names = "apb_pclk"; + }; + + gpio18: gpio@fff28000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xfff28000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx1 4 42 4>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3670_PCLK_GPIO18>; + clock-names = "apb_pclk"; + }; + + gpio19: gpio@fff29000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xfff29000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx1 0 61 2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3670_PCLK_GPIO19>; + clock-names = "apb_pclk"; + }; + + gpio20: gpio@e8a1f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a1f000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx7 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO20>; + clock-names = "apb_pclk"; + }; + + gpio21: gpio@e8a20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xe8a20000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx7 0 8 4>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3670_PCLK_GPIO21>; + clock-names = "apb_pclk"; + }; + + gpio22: gpio@fff0b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xfff0b000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO176 */ + gpio-ranges = <&pmx1 2 0 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3670_PCLK_AO_GPIO0>; + clock-names = "apb_pclk"; + }; + + gpio23: gpio@fff0c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xfff0c000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO184 */ + gpio-ranges = <&pmx1 0 6 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3670_PCLK_AO_GPIO1>; + clock-names = "apb_pclk"; + }; + + gpio24: gpio@fff0d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xfff0d000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO192 */ + gpio-ranges = <&pmx1 0 14 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3670_PCLK_AO_GPIO2>; + clock-names = "apb_pclk"; + }; + + gpio25: gpio@fff0e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xfff0e000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO200 */ + gpio-ranges = <&pmx1 0 22 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3670_PCLK_AO_GPIO3>; + clock-names = "apb_pclk"; + }; + + gpio26: gpio@fff0f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xfff0f000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO208 */ + gpio-ranges = <&pmx1 0 30 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3670_PCLK_AO_GPIO4>; + clock-names = "apb_pclk"; + }; + + gpio27: gpio@fff10000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xfff10000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO216 */ + gpio-ranges = <&pmx1 4 31 4>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3670_PCLK_AO_GPIO5>; + clock-names = "apb_pclk"; + }; + + gpio28: gpio@fff1d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xfff1d000 0x0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx1 1 35 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3670_PCLK_AO_GPIO6>; + clock-names = "apb_pclk"; + }; }; }; -- cgit From dd54bb8a0a970188cda8839845920aff2e3da8a4 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 24 Oct 2018 00:36:53 +0530 Subject: arm64: dts: hisilicon: hi3670: Add UART nodes Add UART nodes for HiSilicon HI3670 SoC and also relevant pinmux/pinconf entries. Signed-off-by: Manivannan Sadhasivam Acked-by: Linus Walleij Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 72 ++++++++++ .../arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi | 157 +++++++++++++++++++++ 2 files changed, 229 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index b99f5e0fe577..a5bd6d80b226 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -187,6 +187,76 @@ #clock-cells = <1>; }; + uart0: serial@fdf02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf02000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>, + <&crg_ctrl HI3670_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; + status = "disabled"; + }; + + uart1: serial@fdf00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf00000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>, + <&crg_ctrl HI3670_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart2: serial@fdf03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf03000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>, + <&crg_ctrl HI3670_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; + status = "disabled"; + }; + + uart3: serial@ffd74000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xffd74000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>, + <&crg_ctrl HI3670_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + status = "disabled"; + }; + + uart4: serial@fdf01000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf01000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>, + <&crg_ctrl HI3670_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; + status = "disabled"; + }; + + uart5: serial@fdf05000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf05000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>, + <&crg_ctrl HI3670_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + status = "disabled"; + }; + uart6: serial@fff32000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfff32000 0x0 0x1000>; @@ -194,6 +264,8 @@ clocks = <&crg_ctrl HI3670_CLK_UART6>, <&crg_ctrl HI3670_PCLK>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi index 64fb9a3bd707..67bb52d43619 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi @@ -20,6 +20,47 @@ pinctrl-single,function-mask = <0x7>; /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 82 0>; + + uart0_pmx_func: uart0_pmx_func { + pinctrl-single,pins = < + 0x054 MUX_M2 /* UART0_RXD */ + 0x058 MUX_M2 /* UART0_TXD */ + >; + }; + + uart2_pmx_func: uart2_pmx_func { + pinctrl-single,pins = < + 0x700 MUX_M2 /* UART2_CTS_N */ + 0x704 MUX_M2 /* UART2_RTS_N */ + 0x708 MUX_M2 /* UART2_RXD */ + 0x70c MUX_M2 /* UART2_TXD */ + >; + }; + + uart3_pmx_func: uart3_pmx_func { + pinctrl-single,pins = < + 0x064 MUX_M1 /* UART3_CTS_N */ + 0x068 MUX_M1 /* UART3_RTS_N */ + 0x06c MUX_M1 /* UART3_RXD */ + 0x070 MUX_M1 /* UART3_TXD */ + >; + }; + + uart4_pmx_func: uart4_pmx_func { + pinctrl-single,pins = < + 0x074 MUX_M1 /* UART4_CTS_N */ + 0x078 MUX_M1 /* UART4_RTS_N */ + 0x07c MUX_M1 /* UART4_RXD */ + 0x080 MUX_M1 /* UART4_TXD */ + >; + }; + + uart6_pmx_func: uart6_pmx_func { + pinctrl-single,pins = < + 0x05c MUX_M1 /* UART6_RXD */ + 0x060 MUX_M1 /* UART6_TXD */ + >; + }; }; pmx2: pinmux@e896c800 { @@ -27,6 +68,122 @@ reg = <0x0 0xe896c800 0x0 0x72c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; + + uart0_cfg_func: uart0_cfg_func { + pinctrl-single,pins = < + 0x058 0x0 /* UART0_RXD */ + 0x05c 0x0 /* UART0_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart2_cfg_func: uart2_cfg_func { + pinctrl-single,pins = < + 0x700 0x0 /* UART2_CTS_N */ + 0x704 0x0 /* UART2_RTS_N */ + 0x708 0x0 /* UART2_RXD */ + 0x70c 0x0 /* UART2_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart3_cfg_func: uart3_cfg_func { + pinctrl-single,pins = < + 0x068 0x0 /* UART3_CTS_N */ + 0x06c 0x0 /* UART3_RTS_N */ + 0x070 0x0 /* UART3_RXD */ + 0x074 0x0 /* UART3_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart4_cfg_func: uart4_cfg_func { + pinctrl-single,pins = < + 0x078 0x0 /* UART4_CTS_N */ + 0x07c 0x0 /* UART4_RTS_N */ + 0x080 0x0 /* UART4_RXD */ + 0x084 0x0 /* UART4_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart6_cfg_func: uart6_cfg_func { + pinctrl-single,pins = < + 0x060 0x0 /* UART6_RXD */ + 0x064 0x0 /* UART6_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; }; pmx5: pinmux@fc182000 { -- cgit From 84d9e4df19a7fac4f61dbab9bd9ab2aae71216fc Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 24 Oct 2018 00:36:54 +0530 Subject: arm64: dts: hisilicon: hikey970: Enable on-board UARTs Enable on-board UARTs on HiSilicon HiKey970 board. Signed-off-by: Manivannan Sadhasivam Acked-by: Linus Walleij Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts index 8fdc1dfcb06c..fc851a3177e7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts @@ -17,6 +17,12 @@ compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; serial6 = &uart6; /* console UART */ }; @@ -31,6 +37,20 @@ }; }; +&uart0 { + /* On High speed expansion header */ + label = "HS-UART0"; + status = "okay"; +}; + +&uart2 { + /* On Low speed expansion header */ + label = "LS-UART0"; + status = "okay"; +}; + &uart6 { + /* On Low speed expansion header */ + label = "LS-UART1"; status = "okay"; }; -- cgit From 8aa2fca8342b227842758106028ed33d711959ce Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 24 Oct 2018 00:36:55 +0530 Subject: arm64: dts: hisilicon: hikey970: Add GPIO line names Add GPIO line names for HiSilicon HiKey970 board based on HI3670 SoC. The Line names are derived from "hikey970-schematics.pdf" document and named in conjunction with 96Boards CE Specification v1.0. Signed-off-by: Manivannan Sadhasivam Acked-by: Linus Walleij Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts | 317 ++++++++++++++++++++++ 1 file changed, 317 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts index fc851a3177e7..c9775b66629f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts @@ -37,6 +37,323 @@ }; }; +/* + * Legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * "" = no idea, schematic doesn't say, could be + * unrouted (not connected to any external pin) + * LSEC = Low Speed External Connector + * HSEC = High Speed External Connector + * + * Line names are taken from "hikey970-schematics.pdf" from HiSilicon. + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART2. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ +&gpio0 { + /* GPIO_000-GPIO_007 */ + gpio-line-names = + "", + "TP901", /* TEST_MODE connected to TP901 */ + "", + "GPIO_003_USB_HUB_RESET_N", + "NC", + "[AP_GPS_REF_CLK]", + "[I2C3_SCL]", + "[I2C3_SDA]"; +}; + +&gpio1 { + /* GPIO_008-GPIO_015 */ + gpio-line-names = + "[UART0_CTS]", /* LSEC pin 3: GPIO_008_UART2_CTS_N */ + "[UART0_RTS]", /* LSEC pin 9: GPIO_009_UART2_RTS_N */ + "[UART0_TXD]", /* LSEC pin 5: GPIO_010_UART2_TXD */ + "[UART0_RXD]", /* LSEC pin 7: GPIO_011_UART2_RXD */ + "[USER_LED5]", + "GPIO-I", /* LSEC pin 31: GPIO_013_CAM0_RST_N */ + "[USER_LED3]", + "[USER_LED4]"; +}; + +&gpio2 { + /* GPIO_016-GPIO_023 */ + gpio-line-names = + "GPIO-G", /* LSEC pin 29: GPIO_016_LCD_TE0 */ + "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */ + "[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */ + "GPIO_019_BT_ACTIVE", + "[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */ + "[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */ + "[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */ + "[I2C3_SDA]"; /* HSEC pin 38: ISP_SDA1 */ +}; + +&gpio3 { + /* GPIO_024-GPIO_031 */ + gpio-line-names = + "GPIO_024_WIFI_ACTIVE", + "GPIO_025_PERST_M.2", + "[I2C4_SCL]", + "[I2C4_SDA]", + "NC", + "GPIO-H", /* LSEC pin 30: GPIO_029_LCD_RST_N */ + "[USER_LED1]", + "GPIO-L"; /* LSEC pin 34: GPIO_031 */ +}; + +&gpio4 { + /* GPIO_032-GPIO_039 */ + gpio-line-names = + "GPIO-K", /* LSEC pin 33: GPIO_032_CAM1_RST_N */ + "GPIO_033_PMU1_EN", + "GPIO_034_USBSW_SEL", + /* + * These two pins should be used for SD(IO) data according + * to the 96boards specification but seems to be repurposed + * for UART 0. They are however named according to the spec. + */ + "[SD_DAT1]", /* HSEC pin 3: GPIO_035_UART0_RXD */ + "[SD_DAT2]", /* HSEC pin 5: GPIO_036_UART0_TXD */ + "[UART1_RXD]", /* LSEC pin 13: DEBUG_UART6_RXD */ + "[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */ + "[SOC_GPS_UART3_CTS_N]"; /* TP2304 */ +}; + +&gpio5 { + /* GPIO_040-GPIO_047 */ + gpio-line-names = + "[SOC_GPS_UART3_RTS_N]", /* TP2302 */ + "[SOC_GPS_UART3_RXD]", /* TP2303 */ + "[SOC_GPS_UART3_TXD]", /* TP2305 */ + "[SOC_BT_UART4_CTS_N]", + "[SOC_BT_UART4_RTS_N]", + "[SOC_BT_UART4_RXD]", + "[SOC_BT_UART4_TXD]", + "NC"; +}; + +&gpio6 { + /* GPIO_048-GPIO_055 */ + gpio-line-names = + "NC", + "GPIO_049_USER_LED6", + "GPIO_050_CAN_RST", + "GPIO_051_WIFI_EN", + "GPIO-D", /* LSEC pin 26 */ + "GPIO-J", /* LSEC pin 32 */ + "GPIO_054_BT_EN", + "[GPIO_055_SEL]"; +}; + +&gpio7 { + /* GPIO_056-GPIO_063 */ + gpio-line-names = + "[PCIE_PERST_L]", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio8 { + /* GPIO_064-GPIO_071 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio9 { + /* GPIO_072-GPIO_079 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio10 { + /* GPIO_080-GPIO_087 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio11 { + /* GPIO_088-GPIO_095 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio12 { + /* GPIO_096-GPIO_103 */ + gpio-line-names = "NC", "", "", "", "", "", "", ""; +}; + +&gpio13 { + /* GPIO_104-GPIO_111 */ + gpio-line-names = "", "", "", "", "", "", "", ""; +}; + +&gpio14 { + /* GPIO_112-GPIO_119 */ + gpio-line-names = "", "", "", "", "", "", "", ""; +}; + +&gpio15 { + /* GPIO_120-GPIO_127 */ + gpio-line-names = "", "", "", "", "", "", "", ""; +}; + +&gpio16 { + /* GPIO_128-GPIO_135 */ + gpio-line-names = + "[WL_SDIO_CLK]", + "[WL_SDIO_CMD]", + "[WL_SDIO_DATA0]", + "[WL_SDIO_DATA1]", + "[WL_SDIO_DATA2]", + "[WL_SDIO_DATA3]", + "[ETH_ISOLATE]", + "NC"; +}; + +&gpio17 { + /* GPIO_136-GPIO_143 */ + gpio-line-names = + "[MINI1CLK_EN]", "NC", "", "", "", "", "", ""; +}; + +&gpio18 { + /* GPIO_144-GPIO_151 */ + gpio-line-names = + "[SPI1_SCLK]", /* HSEC pin 9: GPIO_144_SPI3_CLK */ + "[SPI1_DIN]", /* HSEC pin 11: GPIO_145_SPI3_DI */ + "[SPI1_DOUT]", /* HSEC pin 1: GPIO_146_SPI3_DO */ + "[SPI1_CS]", /* HSEC pin 7: GPIO_147_SPI3_CS0_N */ + "[POWER_INT_N]", + "[CDMA_GPS_SYNC]", + "GPIO_150_PEX_INTA", + "GPIO_151_CAN_INT"; +}; + +&gpio19 { + /* GPIO_152-GPIO_159 */ + gpio-line-names = "", "", "", "", "", "", "", ""; +}; + +&gpio20 { + /* GPIO_160-GPIO_167 */ + gpio-line-names = + "[SD_CLK]", + "[SD_CMD]", + "[SD_DATA0]", + "[SD_DATA1]", + "[SD_DATA2]", + "[SD_DATA3]", + "GPIO_166_ETHCLK_EN", + "GPIO_167_USER_LED2"; +}; + +&gpio21 { + /* GPIO_168-GPIO_175 */ + gpio-line-names = + "GPIO_168_GPS_EN", + "GPIO-C", /* LSEC pin 25: GPIO_169_USIM1_CLK */ + "GPIO-E", /* LSEC pin 27: GPIO_170_USIM1_RST */ + "GPIO-B", /* LSEC pin 24: GPIO_171_USIM1_DATA */ + "", "", "", "", ""; +}; + +&gpio22 { + /* GPIO_176-GPIO_183 */ + gpio-line-names = + "[PMU_PWR_HOLD]", + "GPIO_177_WL_WAKEUP_AP", + "[JTAG_TCK]", + "[JTAG_TMS]", + "[JTAG_TDI]", + "[JTAG_TMS]", + "GPIO_182_FATAL_ERR", + "NC"; +}; + +&gpio23 { + /* GPIO_184-GPIO_191 */ + gpio-line-names = + "GPIO_184_JTAG_SEL", + "GPIO-F", /* LSEC pin 28: GPIO_185_LCD_BL_PWM */ + "[I2C0_SCL]", /* LSEC pin 15: GPIO_186_I2C0_SCL */ + "[I2C0_SDA]", /* LSEC pin 17: GPIO_187_I2C0_SDA */ + "[GPIO_188_I2C1_SCL]", /* Actual SoC I2C1_SCL */ + "[GPIO_189_I2C1_SDA]", /* Actual SoC I2C1_SDA */ + "[I2C1_SCL]", /* LSEC pin 19: GPIO_190_I2C2_SCL */ + "[I2C2_SDA]"; /* LSEC pin 21: GPIO_191_I2C2_SDA */ +}; + +&gpio24 { + /* GPIO_192-GPIO_199 */ + gpio-line-names = + "[SD_LED]", + "NC", + "[PCM_DI]", /* LSEC pin 22: GPIO_194_I2S0_DI */ + "[PCM_DO]", /* LSEC pin 20: GPIO_195_I2S0_DO */ + "[PCM_CLK]", /* LSEC pin 18: GPIO_196_I2S0_XCLK */ + "[PCM_FS]", /* LSEC pin 16: GPIO_197_I2S0_XFS */ + "", + "[I2S2_DO]"; +}; + +&gpio25 { + /* GPIO_200-GPIO_207 */ + gpio-line-names = + "[I2S2_XCLK]", + "[I2S2_XFS]", + "GPIO_202_PERST_ETH", + "GPIO_203_PWRON_DET", + "GPIO_204_PMU1_IRQ_N", + "GPIO_205_SD_DET", + "GPIO_206_GPS_MOTION_INT", + "GPIO_207_HDMI_SEL"; +}; + +&gpio26 { + /* GPIO_208-GPIO_215 */ + gpio-line-names = + "GPIO-A", /* LSEC pin 23: GPIO_208_WAKEUP_SOC */ + "GPIO_209_VBUS_TYPEC", + "NC", + "NC", + "NC", + "[SPI0_SCLK]", /* LSEC pin 8: GPIO_213_SPI2_CLK */ + "[SPI0_DIN]", /* LSEC pin 10: GPIO_214_SPI2_DI */ + "[SPI0_DOUT]"; /* LSEC pin 14: GPIO_215_SPI2_DO */ +}; + +&gpio27 { + /* GPIO_216-GPIO_223 */ + gpio-line-names = + "[SPI0_CS]", /* LSEC pin 12: GPIO_216_SPI2_CS0_N */ + "GPIO_217_HDMI_PD", + "GPIO_218_GPS_WAKEUP_AP", + "GPIO_219_M.2CLK_EN", + "GPIO_220_PERST_MINI", + "GPIO_221_CC_INT", + "[PCIE_CLKREQ_L]", + "NC"; +}; + +&gpio28 { + /* GPIO_224-GPIO_231 */ + gpio-line-names = + "[PMU0_INT]", + "[SPMI_DATA]", + "[SPMI_CLK]", + "[CAN_SPI_CLK]", + "[CAN_SPI_DI]", + "[CAN_SPI_DO]", + "[CAN_SPI_CS]", + "GPIO_231_HDMI_INT"; +}; + &uart0 { /* On High speed expansion header */ label = "HS-UART0"; -- cgit From 2e3ea3e7fba98c67639dd65d667b293e452efb9c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 29 Oct 2018 15:12:41 +0530 Subject: arm64: dts: hisilicon: hikey: Standardize LED labels and triggers For all 96Boards, the following standard is used for onboard LEDs. green:user1 default-trigger: heartbeat green:user2 default-trigger: mmc0/disk-activity(onboard-storage) green:user3 default-trigger: mmc1 (SD-card) green:user4 default-trigger: none, panic-indicator yellow:wlan default-trigger: phy0tx blue:bt default-trigger: hci0-power So lets adopt the same for HiKey, which is one of the 96Boards CE platform. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index f4964bee6a1a..610235028cc7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -340,42 +340,43 @@ leds { compatible = "gpio-leds"; - user_led4 { - label = "user_led4"; + + user_led1 { + label = "green:user1"; gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */ linux,default-trigger = "heartbeat"; }; - user_led3 { - label = "user_led3"; + user_led2 { + label = "green:user2"; gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */ linux,default-trigger = "mmc0"; }; - user_led2 { - label = "user_led2"; + user_led3 { + label = "green:user3"; gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */ linux,default-trigger = "mmc1"; }; - user_led1 { - label = "user_led1"; + user_led4 { + label = "green:user4"; gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */ panic-indicator; - linux,default-trigger = "cpu0"; + linux,default-trigger = "none"; }; wlan_active_led { - label = "wifi_active"; + label = "yellow:wlan"; gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */ linux,default-trigger = "phy0tx"; default-state = "off"; }; bt_active_led { - label = "bt_active"; + label = "blue:bt"; gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */ - linux,default-trigger = "hci0rx"; + linux,default-trigger = "hci0-power"; default-state = "off"; }; }; -- cgit From 28b45da9acffd6b5d25018b18dc18ad3376140d8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 29 Oct 2018 15:12:42 +0530 Subject: arm64: dts: hisilicon: hikey960: Standardize LED labels and triggers For all 96Boards, the following standard is used for onboard LEDs. green:user1 default-trigger: heartbeat green:user2 default-trigger: mmc0/disk-activity(onboard-storage) green:user3 default-trigger: mmc1 (SD-card) green:user4 default-trigger: none, panic-indicator yellow:wlan default-trigger: phy0tx blue:bt default-trigger: hci0-power So lets adopt the same for HiKey960 which is one of the 96Boards CE platform. Since there is no trigger available for onboard-storage UFS now, user2 trigger is set to none. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index c98bcbc8dfba..46435466f1ab 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -85,36 +85,36 @@ compatible = "gpio-leds"; user_led1 { - label = "user_led1"; + label = "green:user1"; /* gpio_150_user_led1 */ gpios = <&gpio18 6 0>; linux,default-trigger = "heartbeat"; }; user_led2 { - label = "user_led2"; + label = "green:user2"; /* gpio_151_user_led2 */ gpios = <&gpio18 7 0>; - linux,default-trigger = "mmc0"; + linux,default-trigger = "none"; }; user_led3 { - label = "user_led3"; + label = "green:user3"; /* gpio_189_user_led3 */ gpios = <&gpio23 5 0>; - default-state = "off"; + linux,default-trigger = "mmc0"; }; user_led4 { - label = "user_led4"; + label = "green:user4"; /* gpio_190_user_led4 */ gpios = <&gpio23 6 0>; panic-indicator; - linux,default-trigger = "cpu0"; + linux,default-trigger = "none"; }; wlan_active_led { - label = "wifi_active"; + label = "yellow:wlan"; /* gpio_205_wifi_active */ gpios = <&gpio25 5 0>; linux,default-trigger = "phy0tx"; @@ -122,7 +122,7 @@ }; bt_active_led { - label = "bt_active"; + label = "blue:bt"; gpios = <&gpio25 7 0>; /* gpio_207_user_led1 */ linux,default-trigger = "hci0-power"; -- cgit From 4c7c31104b4706023a2ce6d9aa0a3b3fe7a96f17 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 29 Oct 2018 15:12:43 +0530 Subject: arm64: dts: hisilicon: poplar: Standardize LED labels and triggers For all 96Boards, the following standard is used for onboard LEDs. green:user1 default-trigger: heartbeat green:user2 default-trigger: mmc0/disk-activity(onboard-storage) green:user3 default-trigger: mmc1 (SD-card) green:user4 default-trigger: none, panic-indicator yellow:wlan default-trigger: phy0tx blue:bt default-trigger: hci0-power So lets adopt the same for Poplar, which is one of the 96Boards Enterprise edition platform. Due to absence of WLAN and BT support, corresponding LED nodes are not considered. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts index d30f6eb8a5ee..32716c96b457 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts @@ -35,30 +35,31 @@ compatible = "gpio-leds"; user-led0 { - label = "USER-LED0"; + label = "green:user1"; gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; default-state = "off"; }; user-led1 { - label = "USER-LED1"; + label = "green:user2"; gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; linux,default-trigger = "mmc0"; default-state = "off"; }; user-led2 { - label = "USER-LED2"; + label = "green:user3"; gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; + linux,default-trigger = "mmc1"; default-state = "off"; }; user-led3 { - label = "USER-LED3"; + label = "green:user4"; gpios = <&gpio10 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "cpu0"; + linux,default-trigger = "none"; + panic-indicator; default-state = "off"; }; }; -- cgit From a7a6e2cbb4db370e84948e97adac332b59dd89d8 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:34:27 +0530 Subject: arm64: dts: hi3660: Add missing cooling device properties for CPUs The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index f432b0a88c65..d943a96eedee 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -79,6 +79,7 @@ capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -91,6 +92,7 @@ capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -103,6 +105,7 @@ capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; cpu4: cpu@100 { @@ -129,6 +132,7 @@ capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; }; cpu6: cpu@102 { @@ -141,6 +145,7 @@ capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; }; cpu7: cpu@103 { @@ -153,6 +158,7 @@ capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; }; idle-states { -- cgit From 6ad5506ed191eefec7d205245edabb8b5f7e950f Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:34:28 +0530 Subject: ARM64: dts: hisilicon: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 10 ++++++++-- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 9 ++++++++- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index d943a96eedee..20ae40df61d5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1118,12 +1118,18 @@ map0 { trip = <&target>; contribution = <1024>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&target>; contribution = <512>; - cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 97d5bf2c6ec5..aec9e371c2a7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -893,7 +893,14 @@ cooling-maps { map0 { trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; -- cgit From 3dde5a2342cd204df15b6b0b90ee0ed4542225ca Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 23 Nov 2018 13:04:03 +0100 Subject: ARM: tegra: Add VIC on Tegra124 The Video Image Compositor can be used to perform a variety of image operations. Add a device tree node for it, so that it can be exposed as a host1x channel to userspace. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 183c5acafb22..b113e47b2b2a 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -140,6 +140,18 @@ status = "disabled"; }; + vic@54340000 { + compatible = "nvidia,tegra124-vic"; + reg = <0x0 0x54340000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_VIC03>; + clock-names = "vic"; + resets = <&tegra_car 178>; + reset-names = "vic"; + + iommus = <&mc TEGRA_SWGROUP_VIC>; + }; + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; -- cgit From 5d2632a577baa735ad05ec745a2f95997d5ad9e0 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 29 Nov 2018 11:05:35 -0800 Subject: ARM: dts: Revert am335x mcasp ti-sysc changes Without this McASP FIFO would constantly underflow. EDMA test via dmatest works though. Let's revert the change for now until we know the root cause. Reported-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 28 ++-------------------------- arch/arm/boot/dts/am33xx.dtsi | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 918bf57a520d..fd99e2390541 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -1056,19 +1056,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x38000 0x2000>; - - mcasp0: mcasp@0 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <80>, <81>; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 8 2>, - <&edma 9 2>; - dma-names = "tx", "rx"; - }; + status = "disabled"; }; target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ @@ -1086,19 +1074,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x3c000 0x2000>; - - mcasp1: mcasp@0 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x2000>, - <0x46400000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <82>, <83>; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 10 2>, - <&edma 11 2>; - dma-names = "tx", "rx"; - }; + status = "disabled"; }; target-module@40000 { /* 0x48040000, ap 22 1e.0 */ diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index e5c2f71a7c77..fc07d2d6112e 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -440,7 +440,36 @@ <&edma 5 0>; dma-names = "tx", "rx"; }; + + mcasp0: mcasp@48038000 { + compatible = "ti,am33xx-mcasp-audio"; + ti,hwmods = "mcasp0"; + reg = <0x48038000 0x2000>, + <0x46000000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <80>, <81>; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 8 2>, + <&edma 9 2>; + dma-names = "tx", "rx"; + }; + + mcasp1: mcasp@4803c000 { + compatible = "ti,am33xx-mcasp-audio"; + ti,hwmods = "mcasp1"; + reg = <0x4803C000 0x2000>, + <0x46400000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <82>, <83>; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 10 2>, + <&edma 11 2>; + dma-names = "tx", "rx"; + }; }; + }; #include "am33xx-l4.dtsi" -- cgit From b79e7b3bd1f2b66186278e8df80f371f310138f1 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 28 Nov 2018 12:45:07 +0200 Subject: ARM: dts: dra7: Move the ti,no-idle quirk on proper gmac node Hwmod parses the DT hierarchically from root to search for matching ti,hwmod property. With the introduction of L4 data, we have two nodes with the ti,hwmod = "gmac" declaration, and the hwmod core only matches the first one found, which is the target-module one. This node incorrectly dropped the ti,no-idle flag, which causes number of problems, like ignoring errata i877, and also causing an intermittent boot failure on certain dra7 boards. Fix the issue by moving the ti,no-idle flag to the proper node. Signed-off-by: Tero Kristo Reported-by: Grygorii Strashko Reviewed-by: Grygorii Strashko Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 7e5c0d4f438e..6c01ada9197a 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -3021,6 +3021,14 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x84000 0x4000>; + /* + * Do not allow gating of cpsw clock as workaround + * for errata i877. Keeping internal clock disabled + * causes the device switching characteristics + * to degrade over time and eventually fail to meet + * the data manual delay time/skew specs. + */ + ti,no-idle; mac: ethernet@0 { compatible = "ti,dra7-cpsw","ti,cpsw"; @@ -3039,15 +3047,6 @@ #address-cells = <1>; #size-cells = <1>; - /* - * Do not allow gating of cpsw clock as workaround - * for errata i877. Keeping internal clock disabled - * causes the device switching characteristics - * to degrade over time and eventually fail to meet - * the data manual delay time/skew specs. - */ - ti,no-idle; - /* * rx_thresh_pend * rx_pend -- cgit From dd5297cc8b8b8422b0876b2e7fea8cc2eec4aa2d Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 13 Oct 2018 16:07:06 +0400 Subject: arm64: dts: meson-gxl-s905x-khadas-vim enable Bluetooth This enables Bluetooth support for the following models: - Khadas VIM basic (AP6212) using firmware BCM43438A1.hcd - Khadas VIM pro (AP6255) using firmware BCM4345C0.hcd The AP6212 module used on the VIM basic has an ID clash with another device. To get Bluetooth working you either need to apply a kernel patch to drivers/bluetooth/btbcm.c so 0x2209 loads BCM43438A1 or the BCM43438A1.hcd firmware must be renamed to BCM43430A1.hcd. Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index d32cf3846370..7e0717d982df 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -187,6 +187,13 @@ }; }; +&uart_A { + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; +}; + /* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ &uart_AO { status = "okay"; -- cgit From fbd5cbc5c9fb16ba051d8e6b446d1a3bfeea0baf Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 8 Nov 2018 10:51:56 +0100 Subject: arm64: dts: meson-axg: fix dtc warning about unit address section 2.2.1 of the DT specs says: " If the node has no reg property, the @unit-address must be omitted and the node-name alone differentiates the node from other nodes at the same level in the tree" Simply replace the '@' with a '-' to fix this warning. Cc: Fabio Estevam Cc: Martin Blumenstingl Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 26 +++++++++++++------------- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6 +++--- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 18778ada7bd3..ba44b0419404 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -60,7 +60,7 @@ serial1 = &uart_A; }; - linein: audio-codec@0 { + linein: audio-codec-0 { #sound-dai-cells = <0>; compatible = "everest,es7241"; VDDA-supply = <&vcc_3v3>; @@ -70,7 +70,7 @@ sound-name-prefix = "Linein"; }; - lineout: audio-codec@1 { + lineout: audio-codec-1 { #sound-dai-cells = <0>; compatible = "everest,es7154"; VDD-supply = <&vcc_3v3>; @@ -79,14 +79,14 @@ sound-name-prefix = "Lineout"; }; - spdif_dit: audio-codec@2 { + spdif_dit: audio-codec-2 { #sound-dai-cells = <0>; compatible = "linux,spdif-dit"; status = "okay"; sound-name-prefix = "DIT"; }; - dmics: audio-codec@3 { + dmics: audio-codec-3 { #sound-dai-cells = <0>; compatible = "dmic-codec"; num-channels = <7>; @@ -272,31 +272,31 @@ <393216000>; status = "okay"; - dai-link@0 { + dai-link-0 { sound-dai = <&frddr_a>; }; - dai-link@1 { + dai-link-1 { sound-dai = <&frddr_b>; }; - dai-link@2 { + dai-link-2 { sound-dai = <&frddr_c>; }; - dai-link@3 { + dai-link-3 { sound-dai = <&toddr_a>; }; - dai-link@4 { + dai-link-4 { sound-dai = <&toddr_b>; }; - dai-link@5 { + dai-link-5 { sound-dai = <&toddr_c>; }; - dai-link@6 { + dai-link-6 { sound-dai = <&tdmif_c>; dai-format = "i2s"; dai-tdm-slot-tx-mask-2 = <1 1>; @@ -317,7 +317,7 @@ }; - dai-link@7 { + dai-link-7 { sound-dai = <&spdifout>; codec { @@ -325,7 +325,7 @@ }; }; - dai-link@8 { + dai-link-8 { sound-dai = <&pdm>; codec { diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index df017dbd2e57..eb46db001ce0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -20,7 +20,7 @@ #address-cells = <2>; #size-cells = <2>; - tdmif_a: audio-controller@0 { + tdmif_a: audio-controller-0 { compatible = "amlogic,axg-tdm-iface"; #sound-dai-cells = <0>; sound-name-prefix = "TDM_A"; @@ -31,7 +31,7 @@ status = "disabled"; }; - tdmif_b: audio-controller@1 { + tdmif_b: audio-controller-1 { compatible = "amlogic,axg-tdm-iface"; #sound-dai-cells = <0>; sound-name-prefix = "TDM_B"; @@ -42,7 +42,7 @@ status = "disabled"; }; - tdmif_c: audio-controller@2 { + tdmif_c: audio-controller-2 { compatible = "amlogic,axg-tdm-iface"; #sound-dai-cells = <0>; sound-name-prefix = "TDM_C"; -- cgit From 11fa9774612decea87144d7f950a9c53a4fe3050 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 7 Nov 2018 11:45:47 +0100 Subject: arm64: dts: meson-gxl-libretech-cc: fix GPIO lines names The gpio line names were set in the pinctrl node instead of the gpio node, at the time it was merged, it worked, but was obviously wrong. This patch moves the properties to the gpio nodes. Fixes: 47884c5c746e ("ARM64: dts: meson-gxl-libretech-cc: Add GPIO lines names") Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts index 90a56af967a7..b4dfb9afdef8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -163,7 +163,7 @@ }; }; -&pinctrl_aobus { +&gpio_ao { gpio-line-names = "UART TX", "UART RX", "Blue LED", @@ -178,7 +178,7 @@ "7J1 Header Pin15"; }; -&pinctrl_periphs { +&gpio { gpio-line-names = /* Bank GPIOZ */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", -- cgit From f0783f5edb52af14ecaae6c5ce4f38e0a358f5d8 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 7 Nov 2018 11:45:48 +0100 Subject: arm64: dts: meson-gxbb-nanopi-k2: fix GPIO lines names The gpio line names were set in the pinctrl node instead of the gpio node, at the time it was merged, it worked, but was obviously wrong. This patch moves the properties to the gpio nodes. Fixes: 12ada0513d7a ("ARM64: dts: meson-gxbb-nanopi-k2: Add GPIO lines names") Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index cbe99bd4e06d..8cd50b75171d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -191,7 +191,7 @@ pinctrl-names = "default"; }; -&pinctrl_aobus { +&gpio_ao { gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In", "VCCK En", "CON1 Header Pin31", "I2S Header Pin6", "IR In", "I2S Header Pin7", @@ -201,7 +201,7 @@ ""; }; -&pinctrl_periphs { +&gpio { gpio-line-names = /* Bank GPIOZ */ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", -- cgit From 2165b006b65d609140dafafcb14cce5a4aaacbab Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 7 Nov 2018 11:45:49 +0100 Subject: arm64: dts: meson-gxbb-odroidc2: fix GPIO lines names The gpio line names were set in the pinctrl node instead of the gpio node, at the time it was merged, it worked, but was obviously wrong. This patch moves the properties to the gpio nodes. Fixes: b03c7d6438bb ("ARM64: dts: meson-gxbb-odroidc2: Add GPIO lines names") Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 54954b314a45..00f7be6d83f7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -187,7 +187,7 @@ pinctrl-names = "default"; }; -&pinctrl_aobus { +&gpio_ao { gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En", "USB HUB nRESET", "USB OTG Power En", "J7 Header Pin2", "IR In", "J7 Header Pin4", @@ -197,7 +197,7 @@ ""; }; -&pinctrl_periphs { +&gpio { gpio-line-names = /* Bank GPIOZ */ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", -- cgit From 5b78012636f537344bd551934387f5772c38ba80 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 7 Nov 2018 11:45:50 +0100 Subject: arm64: dts: meson-gxl-khadas-vim: fix GPIO lines names The gpio line names were set in the pinctrl node instead of the gpio node, at the time it was merged, it worked, but was obviously wrong. This patch moves the properties to the gpio nodes. Fixes: 60795933b709 ("ARM64: dts: meson-gxl-khadas-vim: Add GPIO lines names") Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 7e0717d982df..3ce66d0d937f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -112,7 +112,7 @@ linux,rc-map-name = "rc-geekbox"; }; -&pinctrl_aobus { +&gpio_ao { gpio-line-names = "UART TX", "UART RX", "Power Key In", @@ -127,7 +127,7 @@ ""; }; -&pinctrl_periphs { +&gpio { gpio-line-names = /* Bank GPIOZ */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", -- cgit From a708c68563048eb2dce44e4b18347ca342673ee9 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 8 Nov 2018 10:56:40 +0100 Subject: arm64: dts: meson-axg: s400: add cts-rts to the bluetooth uart The uart used with bluetooth chipset on the s400 has flow control available. Let's enable it. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index ba44b0419404..29ccb8ad0de6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -543,8 +543,9 @@ &uart_A { status = "okay"; - pinctrl-0 = <&uart_a_pins>; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; pinctrl-names = "default"; + uart-has-rtscts; }; &uart_AO { -- cgit From 96dc5702acbb203026f1629993037267f432a318 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 8 Nov 2018 14:07:44 +0100 Subject: arm64: dts: meson-axg: add secure monitor Add the secure monitor device to the axg platform. With this, we can read the SoC serial number. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index eb46db001ce0..e3a0bedfebd4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -110,6 +110,10 @@ }; }; + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; -- cgit From e1f2163deac059ad39f07aba9e314ebe605d5a7a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 8 Nov 2018 14:24:38 +0100 Subject: arm64: dts: meson-gx: Add hdmi_5v regulator as hdmi tx supply The hdmi_5v regulator must be enabled to provide power to the physical HDMI PHY and enables the HDMI 5V presence loopback for the monitor. Fixes: b409f625a6d5 ("ARM64: dts: meson-gx: Add HDMI_5V regulator on selected boards") Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 1 + arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 1 + arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts | 1 + arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi index 765247bc4f24..e14e0ce7e89f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi @@ -125,6 +125,7 @@ status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; pinctrl-names = "default"; + hdmi-supply = <&hdmi_5v>; }; &hdmi_tx_tmds_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 3ce66d0d937f..5499e8de5c74 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -78,6 +78,7 @@ status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; pinctrl-names = "default"; + hdmi-supply = <&hdmi_5v>; }; &hdmi_tx_tmds_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts index b4dfb9afdef8..db293440e4ca 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -155,6 +155,7 @@ status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; pinctrl-names = "default"; + hdmi-supply = <&hdmi_5v>; }; &hdmi_tx_tmds_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts index 5896e8a5d86b..2602940c2077 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts @@ -51,6 +51,7 @@ status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; pinctrl-names = "default"; + hdmi-supply = <&hdmi_5v>; }; &hdmi_tx_tmds_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 313f88f8759e..782e9edac805 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -271,6 +271,7 @@ status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; pinctrl-names = "default"; + hdmi-supply = <&hdmi_5v>; }; &hdmi_tx_tmds_port { -- cgit From 9fdff382e3d672231526a7a2d8b575925416aa8d Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 8 Nov 2018 14:53:49 +0100 Subject: arm64: dts: meson-axg: fix mailbox address MHU mailbox address is wrong. Fixing it enables the mailboxes on the A113. These mailboxes are needed for SCPI Fixes: 9d59b708500f ("arm64: dts: meson-axg: add initial A113D SoC DT support") Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index e3a0bedfebd4..74810f3c9be3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -979,9 +979,9 @@ }; }; - mailbox: mailbox@ff63dc00 { + mailbox: mailbox@ff63c404 { compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; - reg = <0 0xff63dc00 0 0x400>; + reg = <0 0xff63c404 0 0x4c>; interrupts = , , ; -- cgit From 9c2d16bbfda645cbcf7191f8822f23f93149ffbe Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 8 Nov 2018 14:53:50 +0100 Subject: arm64: dts: meson-axg: correct sram shared mem unit-address Correct the unit-address in the node name of the SRAM shared memory Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 74810f3c9be3..dfb8f2c8c812 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1560,12 +1560,12 @@ #size-cells = <1>; ranges = <0 0x0 0xfffc0000 0x20000>; - cpu_scp_lpri: scp-shmem@0 { + cpu_scp_lpri: scp-shmem@13000 { compatible = "amlogic,meson-axg-scp-shmem"; reg = <0x13000 0x400>; }; - cpu_scp_hpri: scp-shmem@200 { + cpu_scp_hpri: scp-shmem@13400 { compatible = "amlogic,meson-axg-scp-shmem"; reg = <0x13400 0x400>; }; -- cgit From ef29fcc381814f56b7a6dfef5cb498edee176003 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 8 Nov 2018 14:53:51 +0100 Subject: Documentation: bindings: Add missing Amlogic SCPI sensor bindings amlogic,meson-gxbb-scpi-sensors is both the driver and DT but is not documented. Just add it to amlogic's scpi documentation Signed-off-by: Jerome Brunet Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic,scpi.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt index 7b9a861e9306..5ab59da052df 100644 --- a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt +++ b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt @@ -17,4 +17,11 @@ Required sub-node properties: - compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared memory on Amlogic GXBB SoC. +Sensor bindings for the sensors based on SCPI Message Protocol +-------------------------------------------------------------- +SCPI provides an API to access the various sensors on the SoC. + +Required properties: +- compatible : should be "amlogic,meson-gxbb-scpi-sensors". + [0] Documentation/devicetree/bindings/arm/arm,scpi.txt -- cgit From 2c130695ad5265ce2eb38f55ee0cce26238f7891 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 8 Nov 2018 14:53:52 +0100 Subject: arm64: dts: meson-axg: enable SCPI Enable SCPI on the axg platform, with cpu clock and hwmon (core temperature) support Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index dfb8f2c8c812..b897a379fc75 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -79,6 +79,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu1: cpu@1 { @@ -87,6 +88,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu2: cpu@2 { @@ -95,6 +97,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu3: cpu@3 { @@ -103,6 +106,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; l2: l2-cache0 { @@ -137,6 +141,28 @@ }; }; + scpi { + compatible = "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + scpi_clocks: clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: clock-controller { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "amlogic,meson-gxbb-scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; -- cgit From 920b4d3969ccd51c33b540a1315203c9d90e785b Mon Sep 17 00:00:00 2001 From: He Yangxuan Date: Fri, 9 Nov 2018 20:59:36 +0800 Subject: arm64: dts: meson: p230: disable advertisement EEE for GbE. This patch disable EEE advertisement for P230 board (DWMAC + RTL8211F). If not disable it, the network connection is not stable, will got issues like throughput drop or broken link. Signed-off-by: He Yangxuan Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts index 15014faa2ab2..0c8e8305b1f3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts @@ -86,6 +86,7 @@ max-speed = <1000>; interrupt-parent = <&gpio_intc>; interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + eee-broken-1000t; }; }; -- cgit From ac444768bd998d5a412714b32801d7448fd7f37d Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 9 Nov 2018 14:23:31 +0100 Subject: arm64: dts: meson: s400: add bcm bluetooth device Add broadcom bluetooth device on the s400 Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 29ccb8ad0de6..7759fda3ddfd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -546,6 +546,11 @@ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; pinctrl-names = "default"; uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; + }; }; &uart_AO { -- cgit From 06096d7a8734b0ee3d5353f37a7d2c34fb1a6a26 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 9 Nov 2018 15:04:42 +0100 Subject: arm64: dts: meson: remove extra subnode in mmc clk_gate pinmux In the pinmux of the mmc clk_gate nodes, we define 2 subnodes. One for the function definition, the other for the bias. This is not necessary since we can define the function and the bias in the same subnode. Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 --------- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 9 --------- 3 files changed, 24 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index b897a379fc75..28582a44883b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -310,9 +310,6 @@ mux { groups = "BOOT_8"; function = "gpio_periphs"; - }; - cfg-pull-down { - pins = "BOOT_8"; bias-pull-down; }; }; @@ -543,9 +540,6 @@ mux { groups = "GPIOX_4"; function = "gpio_periphs"; - }; - cfg-pull-down { - pins = "GPIOX_4"; bias-pull-down; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 524f533e41d4..1cb8e7e0d0da 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -377,9 +377,6 @@ mux { groups = "BOOT_8"; function = "gpio_periphs"; - }; - cfg-pull-down { - pins = "BOOT_8"; bias-pull-down; }; }; @@ -426,9 +423,6 @@ mux { groups = "CARD_2"; function = "gpio_periphs"; - }; - cfg-pull-down { - pins = "CARD_2"; bias-pull-down; }; }; @@ -449,9 +443,6 @@ mux { groups = "GPIOX_4"; function = "gpio_periphs"; - }; - cfg-pull-down { - pins = "GPIOX_4"; bias-pull-down; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 8ccab9a1ebcc..7cfee40d89e9 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -324,9 +324,6 @@ mux { groups = "BOOT_8"; function = "gpio_periphs"; - }; - cfg-pull-down { - pins = "BOOT_8"; bias-pull-down; }; }; @@ -373,9 +370,6 @@ mux { groups = "CARD_2"; function = "gpio_periphs"; - }; - cfg-pull-down { - pins = "CARD_2"; bias-pull-down; }; }; @@ -396,9 +390,6 @@ mux { groups = "GPIOX_4"; function = "gpio_periphs"; - }; - cfg-pull-down { - pins = "GPIOX_4"; bias-pull-down; }; }; -- cgit From 96a13691c1ddfafc301d1ee451d91fc2cca48d27 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 9 Nov 2018 15:04:43 +0100 Subject: arm64: dts: meson: disable pad bias for mmc pinmuxes In some cases (such as a boot from SPI) the bootloader or the ROM code may leave a bias pull-down on the mmc pins. If so the MMC will fail during the initialisation. Explicitly disabling the pinmux solves the problem. Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4 ++++ 3 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 28582a44883b..50a05bf9b3dd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -303,6 +303,7 @@ "emmc_cmd", "emmc_ds"; function = "emmc"; + bias-disable; }; }; @@ -533,6 +534,7 @@ "sdio_cmd", "sdio_clk"; function = "sdio"; + bias-disable; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 1cb8e7e0d0da..32ef82321340 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -363,6 +363,7 @@ "emmc_cmd", "emmc_clk"; function = "emmc"; + bias-disable; }; }; @@ -370,6 +371,7 @@ mux { groups = "emmc_ds"; function = "emmc"; + bias-disable; }; }; @@ -416,6 +418,7 @@ "sdcard_cmd", "sdcard_clk"; function = "sdcard"; + bias-disable; }; }; @@ -436,6 +439,7 @@ "sdio_cmd", "sdio_clk"; function = "sdio"; + bias-disable; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 7cfee40d89e9..cfeec5579726 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -310,6 +310,7 @@ "emmc_cmd", "emmc_clk"; function = "emmc"; + bias-disable; }; }; @@ -317,6 +318,7 @@ mux { groups = "emmc_ds"; function = "emmc"; + bias-disable; }; }; @@ -363,6 +365,7 @@ "sdcard_cmd", "sdcard_clk"; function = "sdcard"; + bias-disable; }; }; @@ -383,6 +386,7 @@ "sdio_cmd", "sdio_clk"; function = "sdio"; + bias-disable; }; }; -- cgit From 1c5cc1c805d8a2a348c7434dfde955e8c1483db1 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 9 Nov 2018 15:04:44 +0100 Subject: arm64: dts: meson: consistently disable pin bias On Amlogic chipsets, the bias set through pinconf applies to the pad itself, not only the GPIO function. This means that even when we change the function of the pad from GPIO to anything else, the bias previously set still applies. As we have seen with the eMMC, depending on the bias type and the function, it may trigger problems. The underlying issue is that we inherit whatever was left by previous user of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual setup we will get is undefined. There is nothing mentioned in the documentation about pad bias and pinmux function, however leaving it undefined is not an option. This change consistently disable the pad bias for every pinmux functions. It seems to work well, we can only assume that the necessary bias (if any) is already provided by the pin function itself. Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 103 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 47 +++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 49 +++++++++++++ 3 files changed, 199 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 50a05bf9b3dd..5f512c91471e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -230,6 +230,7 @@ groups = "i2c0_sck", "i2c0_sda"; function = "i2c0"; + bias-disable; }; }; @@ -238,6 +239,7 @@ groups = "i2c1_sck_x", "i2c1_sda_x"; function = "i2c1"; + bias-disable; }; }; @@ -246,6 +248,7 @@ groups = "i2c1_sck_z", "i2c1_sda_z"; function = "i2c1"; + bias-disable; }; }; @@ -254,6 +257,7 @@ groups = "i2c2_sck_a", "i2c2_sda_a"; function = "i2c2"; + bias-disable; }; }; @@ -262,6 +266,7 @@ groups = "i2c2_sck_x", "i2c2_sda_x"; function = "i2c2"; + bias-disable; }; }; @@ -270,6 +275,7 @@ groups = "i2c3_sda_a6", "i2c3_sck_a7"; function = "i2c3"; + bias-disable; }; }; @@ -278,6 +284,7 @@ groups = "i2c3_sda_a12", "i2c3_sck_a13"; function = "i2c3"; + bias-disable; }; }; @@ -286,6 +293,7 @@ groups = "i2c3_sda_a19", "i2c3_sck_a20"; function = "i2c3"; + bias-disable; }; }; @@ -332,6 +340,7 @@ "eth_txd2_rgmii", "eth_txd3_rgmii"; function = "eth"; + bias-disable; }; }; @@ -352,6 +361,7 @@ "eth_txd2_rgmii", "eth_txd3_rgmii"; function = "eth"; + bias-disable; }; }; @@ -367,6 +377,7 @@ "eth_txd0_x", "eth_txd1_x"; function = "eth"; + bias-disable; }; }; @@ -382,6 +393,7 @@ "eth_txd0_y", "eth_txd1_y"; function = "eth"; + bias-disable; }; }; @@ -389,6 +401,7 @@ mux { groups = "mclk_b"; function = "mclk_b"; + bias-disable; }; }; @@ -396,6 +409,7 @@ mux { groups = "mclk_c"; function = "mclk_c"; + bias-disable; }; }; @@ -403,6 +417,7 @@ mux { groups = "pdm_dclk_a14"; function = "pdm"; + bias-disable; }; }; @@ -410,6 +425,7 @@ mux { groups = "pdm_dclk_a19"; function = "pdm"; + bias-disable; }; }; @@ -417,6 +433,7 @@ mux { groups = "pdm_din0"; function = "pdm"; + bias-disable; }; }; @@ -424,6 +441,7 @@ mux { groups = "pdm_din1"; function = "pdm"; + bias-disable; }; }; @@ -431,6 +449,7 @@ mux { groups = "pdm_din2"; function = "pdm"; + bias-disable; }; }; @@ -438,6 +457,7 @@ mux { groups = "pdm_din3"; function = "pdm"; + bias-disable; }; }; @@ -445,6 +465,7 @@ mux { groups = "pwm_a_a"; function = "pwm_a"; + bias-disable; }; }; @@ -452,6 +473,7 @@ mux { groups = "pwm_a_x18"; function = "pwm_a"; + bias-disable; }; }; @@ -459,6 +481,7 @@ mux { groups = "pwm_a_x20"; function = "pwm_a"; + bias-disable; }; }; @@ -466,6 +489,7 @@ mux { groups = "pwm_a_z"; function = "pwm_a"; + bias-disable; }; }; @@ -473,6 +497,7 @@ mux { groups = "pwm_b_a"; function = "pwm_b"; + bias-disable; }; }; @@ -480,6 +505,7 @@ mux { groups = "pwm_b_x"; function = "pwm_b"; + bias-disable; }; }; @@ -487,6 +513,7 @@ mux { groups = "pwm_b_z"; function = "pwm_b"; + bias-disable; }; }; @@ -494,6 +521,7 @@ mux { groups = "pwm_c_a"; function = "pwm_c"; + bias-disable; }; }; @@ -501,6 +529,7 @@ mux { groups = "pwm_c_x10"; function = "pwm_c"; + bias-disable; }; }; @@ -508,6 +537,7 @@ mux { groups = "pwm_c_x17"; function = "pwm_c"; + bias-disable; }; }; @@ -515,6 +545,7 @@ mux { groups = "pwm_d_x11"; function = "pwm_d"; + bias-disable; }; }; @@ -522,6 +553,7 @@ mux { groups = "pwm_d_x16"; function = "pwm_d"; + bias-disable; }; }; @@ -550,6 +582,7 @@ mux { groups = "spdif_in_z"; function = "spdif_in"; + bias-disable; }; }; @@ -557,6 +590,7 @@ mux { groups = "spdif_in_a1"; function = "spdif_in"; + bias-disable; }; }; @@ -564,6 +598,7 @@ mux { groups = "spdif_in_a7"; function = "spdif_in"; + bias-disable; }; }; @@ -571,6 +606,7 @@ mux { groups = "spdif_in_a19"; function = "spdif_in"; + bias-disable; }; }; @@ -578,6 +614,7 @@ mux { groups = "spdif_in_a20"; function = "spdif_in"; + bias-disable; }; }; @@ -585,6 +622,7 @@ mux { groups = "spdif_out_a1"; function = "spdif_out"; + bias-disable; }; }; @@ -592,6 +630,7 @@ mux { groups = "spdif_out_a11"; function = "spdif_out"; + bias-disable; }; }; @@ -599,6 +638,7 @@ mux { groups = "spdif_out_a19"; function = "spdif_out"; + bias-disable; }; }; @@ -606,6 +646,7 @@ mux { groups = "spdif_out_a20"; function = "spdif_out"; + bias-disable; }; }; @@ -613,6 +654,7 @@ mux { groups = "spdif_out_z"; function = "spdif_out"; + bias-disable; }; }; @@ -622,6 +664,7 @@ "spi0_mosi", "spi0_clk"; function = "spi0"; + bias-disable; }; }; @@ -629,6 +672,7 @@ mux { groups = "spi0_ss0"; function = "spi0"; + bias-disable; }; }; @@ -636,6 +680,7 @@ mux { groups = "spi0_ss1"; function = "spi0"; + bias-disable; }; }; @@ -643,6 +688,7 @@ mux { groups = "spi0_ss2"; function = "spi0"; + bias-disable; }; }; @@ -652,6 +698,7 @@ "spi1_mosi_a", "spi1_clk_a"; function = "spi1"; + bias-disable; }; }; @@ -659,6 +706,7 @@ mux { groups = "spi1_ss0_a"; function = "spi1"; + bias-disable; }; }; @@ -666,6 +714,7 @@ mux { groups = "spi1_ss1"; function = "spi1"; + bias-disable; }; }; @@ -675,6 +724,7 @@ "spi1_mosi_x", "spi1_clk_x"; function = "spi1"; + bias-disable; }; }; @@ -682,6 +732,7 @@ mux { groups = "spi1_ss0_x"; function = "spi1"; + bias-disable; }; }; @@ -689,6 +740,7 @@ mux { groups = "tdma_din0"; function = "tdma"; + bias-disable; }; }; @@ -696,6 +748,7 @@ mux { groups = "tdma_dout0_x14"; function = "tdma"; + bias-disable; }; }; @@ -703,6 +756,7 @@ mux { groups = "tdma_dout0_x15"; function = "tdma"; + bias-disable; }; }; @@ -710,6 +764,7 @@ mux { groups = "tdma_dout1"; function = "tdma"; + bias-disable; }; }; @@ -717,6 +772,7 @@ mux { groups = "tdma_din1"; function = "tdma"; + bias-disable; }; }; @@ -724,6 +780,7 @@ mux { groups = "tdma_fs"; function = "tdma"; + bias-disable; }; }; @@ -731,6 +788,7 @@ mux { groups = "tdma_fs_slv"; function = "tdma"; + bias-disable; }; }; @@ -738,6 +796,7 @@ mux { groups = "tdma_sclk"; function = "tdma"; + bias-disable; }; }; @@ -745,6 +804,7 @@ mux { groups = "tdma_sclk_slv"; function = "tdma"; + bias-disable; }; }; @@ -752,6 +812,7 @@ mux { groups = "tdmb_din0"; function = "tdmb"; + bias-disable; }; }; @@ -759,6 +820,7 @@ mux { groups = "tdmb_din1"; function = "tdmb"; + bias-disable; }; }; @@ -766,6 +828,7 @@ mux { groups = "tdmb_din2"; function = "tdmb"; + bias-disable; }; }; @@ -773,6 +836,7 @@ mux { groups = "tdmb_din3"; function = "tdmb"; + bias-disable; }; }; @@ -780,6 +844,7 @@ mux { groups = "tdmb_dout0"; function = "tdmb"; + bias-disable; }; }; @@ -787,6 +852,7 @@ mux { groups = "tdmb_dout1"; function = "tdmb"; + bias-disable; }; }; @@ -794,6 +860,7 @@ mux { groups = "tdmb_dout2"; function = "tdmb"; + bias-disable; }; }; @@ -801,6 +868,7 @@ mux { groups = "tdmb_dout3"; function = "tdmb"; + bias-disable; }; }; @@ -808,6 +876,7 @@ mux { groups = "tdmb_fs"; function = "tdmb"; + bias-disable; }; }; @@ -815,6 +884,7 @@ mux { groups = "tdmb_fs_slv"; function = "tdmb"; + bias-disable; }; }; @@ -822,6 +892,7 @@ mux { groups = "tdmb_sclk"; function = "tdmb"; + bias-disable; }; }; @@ -829,6 +900,7 @@ mux { groups = "tdmb_sclk_slv"; function = "tdmb"; + bias-disable; }; }; @@ -836,6 +908,7 @@ mux { groups = "tdmc_fs"; function = "tdmc"; + bias-disable; }; }; @@ -843,6 +916,7 @@ mux { groups = "tdmc_fs_slv"; function = "tdmc"; + bias-disable; }; }; @@ -850,6 +924,7 @@ mux { groups = "tdmc_sclk"; function = "tdmc"; + bias-disable; }; }; @@ -857,6 +932,7 @@ mux { groups = "tdmc_sclk_slv"; function = "tdmc"; + bias-disable; }; }; @@ -864,6 +940,7 @@ mux { groups = "tdmc_din0"; function = "tdmc"; + bias-disable; }; }; @@ -871,6 +948,7 @@ mux { groups = "tdmc_din1"; function = "tdmc"; + bias-disable; }; }; @@ -878,6 +956,7 @@ mux { groups = "tdmc_din2"; function = "tdmc"; + bias-disable; }; }; @@ -885,6 +964,7 @@ mux { groups = "tdmc_din3"; function = "tdmc"; + bias-disable; }; }; @@ -892,6 +972,7 @@ mux { groups = "tdmc_dout0"; function = "tdmc"; + bias-disable; }; }; @@ -899,6 +980,7 @@ mux { groups = "tdmc_dout1"; function = "tdmc"; + bias-disable; }; }; @@ -906,6 +988,7 @@ mux { groups = "tdmc_dout2"; function = "tdmc"; + bias-disable; }; }; @@ -913,6 +996,7 @@ mux { groups = "tdmc_dout3"; function = "tdmc"; + bias-disable; }; }; @@ -921,6 +1005,7 @@ groups = "uart_tx_a", "uart_rx_a"; function = "uart_a"; + bias-disable; }; }; @@ -929,6 +1014,7 @@ groups = "uart_cts_a", "uart_rts_a"; function = "uart_a"; + bias-disable; }; }; @@ -937,6 +1023,7 @@ groups = "uart_tx_b_x", "uart_rx_b_x"; function = "uart_b"; + bias-disable; }; }; @@ -945,6 +1032,7 @@ groups = "uart_cts_b_x", "uart_rts_b_x"; function = "uart_b"; + bias-disable; }; }; @@ -953,6 +1041,7 @@ groups = "uart_tx_b_z", "uart_rx_b_z"; function = "uart_b"; + bias-disable; }; }; @@ -961,6 +1050,7 @@ groups = "uart_cts_b_z", "uart_rts_b_z"; function = "uart_b"; + bias-disable; }; }; @@ -969,6 +1059,7 @@ groups = "uart_ao_tx_b_z", "uart_ao_rx_b_z"; function = "uart_ao_b_z"; + bias-disable; }; }; @@ -977,6 +1068,7 @@ groups = "uart_ao_cts_b_z", "uart_ao_rts_b_z"; function = "uart_ao_b_z"; + bias-disable; }; }; }; @@ -1265,6 +1357,7 @@ mux { groups = "i2c_ao_sck_4"; function = "i2c_ao"; + bias-disable; }; }; @@ -1272,6 +1365,7 @@ mux { groups = "i2c_ao_sck_8"; function = "i2c_ao"; + bias-disable; }; }; @@ -1279,6 +1373,7 @@ mux { groups = "i2c_ao_sck_10"; function = "i2c_ao"; + bias-disable; }; }; @@ -1286,6 +1381,7 @@ mux { groups = "i2c_ao_sda_5"; function = "i2c_ao"; + bias-disable; }; }; @@ -1293,6 +1389,7 @@ mux { groups = "i2c_ao_sda_9"; function = "i2c_ao"; + bias-disable; }; }; @@ -1300,6 +1397,7 @@ mux { groups = "i2c_ao_sda_11"; function = "i2c_ao"; + bias-disable; }; }; @@ -1307,6 +1405,7 @@ mux { groups = "remote_input_ao"; function = "remote_input_ao"; + bias-disable; }; }; @@ -1315,6 +1414,7 @@ groups = "uart_ao_tx_a", "uart_ao_rx_a"; function = "uart_ao_a"; + bias-disable; }; }; @@ -1323,6 +1423,7 @@ groups = "uart_ao_cts_a", "uart_ao_rts_a"; function = "uart_ao_a"; + bias-disable; }; }; @@ -1331,6 +1432,7 @@ groups = "uart_ao_tx_b", "uart_ao_rx_b"; function = "uart_ao_b"; + bias-disable; }; }; @@ -1339,6 +1441,7 @@ groups = "uart_ao_cts_b", "uart_ao_rts_b"; function = "uart_ao_b"; + bias-disable; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 32ef82321340..6796d250985a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -81,6 +81,7 @@ mux { groups = "uart_tx_ao_a", "uart_rx_ao_a"; function = "uart_ao"; + bias-disable; }; }; @@ -89,6 +90,7 @@ groups = "uart_cts_ao_a", "uart_rts_ao_a"; function = "uart_ao"; + bias-disable; }; }; @@ -96,6 +98,7 @@ mux { groups = "uart_tx_ao_b", "uart_rx_ao_b"; function = "uart_ao_b"; + bias-disable; }; }; @@ -104,6 +107,7 @@ groups = "uart_cts_ao_b", "uart_rts_ao_b"; function = "uart_ao_b"; + bias-disable; }; }; @@ -111,6 +115,7 @@ mux { groups = "remote_input_ao"; function = "remote_input_ao"; + bias-disable; }; }; @@ -119,6 +124,7 @@ groups = "i2c_sck_ao", "i2c_sda_ao"; function = "i2c_ao"; + bias-disable; }; }; @@ -126,6 +132,7 @@ mux { groups = "pwm_ao_a_3"; function = "pwm_ao_a_3"; + bias-disable; }; }; @@ -133,6 +140,7 @@ mux { groups = "pwm_ao_a_6"; function = "pwm_ao_a_6"; + bias-disable; }; }; @@ -140,6 +148,7 @@ mux { groups = "pwm_ao_a_12"; function = "pwm_ao_a_12"; + bias-disable; }; }; @@ -147,6 +156,7 @@ mux { groups = "pwm_ao_b"; function = "pwm_ao_b"; + bias-disable; }; }; @@ -154,6 +164,7 @@ mux { groups = "i2s_am_clk"; function = "i2s_out_ao"; + bias-disable; }; }; @@ -161,6 +172,7 @@ mux { groups = "i2s_out_ao_clk"; function = "i2s_out_ao"; + bias-disable; }; }; @@ -168,6 +180,7 @@ mux { groups = "i2s_out_lr_clk"; function = "i2s_out_ao"; + bias-disable; }; }; @@ -175,6 +188,7 @@ mux { groups = "i2s_out_ch01_ao"; function = "i2s_out_ao"; + bias-disable; }; }; @@ -182,6 +196,7 @@ mux { groups = "i2s_out_ch23_ao"; function = "i2s_out_ao"; + bias-disable; }; }; @@ -189,6 +204,7 @@ mux { groups = "i2s_out_ch45_ao"; function = "i2s_out_ao"; + bias-disable; }; }; @@ -203,6 +219,7 @@ mux { groups = "spdif_out_ao_13"; function = "spdif_out_ao"; + bias-disable; }; }; @@ -210,6 +227,7 @@ mux { groups = "ao_cec"; function = "cec_ao"; + bias-disable; }; }; @@ -217,6 +235,7 @@ mux { groups = "ee_cec"; function = "cec_ao"; + bias-disable; }; }; }; @@ -390,6 +409,7 @@ "nor_c", "nor_cs"; function = "nor"; + bias-disable; }; }; @@ -399,6 +419,7 @@ "spi_mosi", "spi_sclk"; function = "spi"; + bias-disable; }; }; @@ -406,6 +427,7 @@ mux { groups = "spi_ss0"; function = "spi"; + bias-disable; }; }; @@ -455,6 +477,7 @@ mux { groups = "sdio_irq"; function = "sdio"; + bias-disable; }; }; @@ -463,6 +486,7 @@ groups = "uart_tx_a", "uart_rx_a"; function = "uart_a"; + bias-disable; }; }; @@ -471,6 +495,7 @@ groups = "uart_cts_a", "uart_rts_a"; function = "uart_a"; + bias-disable; }; }; @@ -479,6 +504,7 @@ groups = "uart_tx_b", "uart_rx_b"; function = "uart_b"; + bias-disable; }; }; @@ -487,6 +513,7 @@ groups = "uart_cts_b", "uart_rts_b"; function = "uart_b"; + bias-disable; }; }; @@ -495,6 +522,7 @@ groups = "uart_tx_c", "uart_rx_c"; function = "uart_c"; + bias-disable; }; }; @@ -503,6 +531,7 @@ groups = "uart_cts_c", "uart_rts_c"; function = "uart_c"; + bias-disable; }; }; @@ -511,6 +540,7 @@ groups = "i2c_sck_a", "i2c_sda_a"; function = "i2c_a"; + bias-disable; }; }; @@ -519,6 +549,7 @@ groups = "i2c_sck_b", "i2c_sda_b"; function = "i2c_b"; + bias-disable; }; }; @@ -527,6 +558,7 @@ groups = "i2c_sck_c", "i2c_sda_c"; function = "i2c_c"; + bias-disable; }; }; @@ -547,6 +579,7 @@ "eth_txd2", "eth_txd3"; function = "eth"; + bias-disable; }; }; @@ -562,6 +595,7 @@ "eth_txd0", "eth_txd1"; function = "eth"; + bias-disable; }; }; @@ -569,6 +603,7 @@ mux { groups = "pwm_a_x"; function = "pwm_a_x"; + bias-disable; }; }; @@ -576,6 +611,7 @@ mux { groups = "pwm_a_y"; function = "pwm_a_y"; + bias-disable; }; }; @@ -583,6 +619,7 @@ mux { groups = "pwm_b"; function = "pwm_b"; + bias-disable; }; }; @@ -590,6 +627,7 @@ mux { groups = "pwm_d"; function = "pwm_d"; + bias-disable; }; }; @@ -597,6 +635,7 @@ mux { groups = "pwm_e"; function = "pwm_e"; + bias-disable; }; }; @@ -604,6 +643,7 @@ mux { groups = "pwm_f_x"; function = "pwm_f_x"; + bias-disable; }; }; @@ -611,6 +651,7 @@ mux { groups = "pwm_f_y"; function = "pwm_f_y"; + bias-disable; }; }; @@ -618,6 +659,7 @@ mux { groups = "hdmi_hpd"; function = "hdmi_hpd"; + bias-disable; }; }; @@ -625,6 +667,7 @@ mux { groups = "hdmi_sda", "hdmi_scl"; function = "hdmi_i2c"; + bias-disable; }; }; @@ -632,6 +675,7 @@ mux { groups = "i2sout_ch23_y"; function = "i2s_out"; + bias-disable; }; }; @@ -639,6 +683,7 @@ mux { groups = "i2sout_ch45_y"; function = "i2s_out"; + bias-disable; }; }; @@ -646,6 +691,7 @@ mux { groups = "i2sout_ch67_y"; function = "i2s_out"; + bias-disable; }; }; @@ -653,6 +699,7 @@ mux { groups = "spdif_out_y"; function = "spdif_out"; + bias-disable; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index cfeec5579726..ed278097825b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -116,6 +116,7 @@ mux { groups = "uart_tx_ao_a", "uart_rx_ao_a"; function = "uart_ao"; + bias-disable; }; }; @@ -124,6 +125,7 @@ groups = "uart_cts_ao_a", "uart_rts_ao_a"; function = "uart_ao"; + bias-disable; }; }; @@ -131,6 +133,7 @@ mux { groups = "uart_tx_ao_b", "uart_rx_ao_b"; function = "uart_ao_b"; + bias-disable; }; }; @@ -138,6 +141,7 @@ mux { groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1"; function = "uart_ao_b"; + bias-disable; }; }; @@ -146,6 +150,7 @@ groups = "uart_cts_ao_b", "uart_rts_ao_b"; function = "uart_ao_b"; + bias-disable; }; }; @@ -153,6 +158,7 @@ mux { groups = "remote_input_ao"; function = "remote_input_ao"; + bias-disable; }; }; @@ -161,6 +167,7 @@ groups = "i2c_sck_ao", "i2c_sda_ao"; function = "i2c_ao"; + bias-disable; }; }; @@ -168,6 +175,7 @@ mux { groups = "pwm_ao_a_3"; function = "pwm_ao_a"; + bias-disable; }; }; @@ -175,6 +183,7 @@ mux { groups = "pwm_ao_a_8"; function = "pwm_ao_a"; + bias-disable; }; }; @@ -182,6 +191,7 @@ mux { groups = "pwm_ao_b"; function = "pwm_ao_b"; + bias-disable; }; }; @@ -189,6 +199,7 @@ mux { groups = "pwm_ao_b_6"; function = "pwm_ao_b"; + bias-disable; }; }; @@ -196,6 +207,7 @@ mux { groups = "i2s_out_ch23_ao"; function = "i2s_out_ao"; + bias-disable; }; }; @@ -203,6 +215,7 @@ mux { groups = "i2s_out_ch45_ao"; function = "i2s_out_ao"; + bias-disable; }; }; @@ -210,6 +223,7 @@ mux { groups = "spdif_out_ao_6"; function = "spdif_out_ao"; + bias-disable; }; }; @@ -217,6 +231,7 @@ mux { groups = "spdif_out_ao_9"; function = "spdif_out_ao"; + bias-disable; }; }; @@ -224,6 +239,7 @@ mux { groups = "ao_cec"; function = "cec_ao"; + bias-disable; }; }; @@ -231,6 +247,7 @@ mux { groups = "ee_cec"; function = "cec_ao"; + bias-disable; }; }; }; @@ -337,6 +354,7 @@ "nor_c", "nor_cs"; function = "nor"; + bias-disable; }; }; @@ -346,6 +364,7 @@ "spi_mosi", "spi_sclk"; function = "spi"; + bias-disable; }; }; @@ -353,6 +372,7 @@ mux { groups = "spi_ss0"; function = "spi"; + bias-disable; }; }; @@ -402,6 +422,7 @@ mux { groups = "sdio_irq"; function = "sdio"; + bias-disable; }; }; @@ -410,6 +431,7 @@ groups = "uart_tx_a", "uart_rx_a"; function = "uart_a"; + bias-disable; }; }; @@ -418,6 +440,7 @@ groups = "uart_cts_a", "uart_rts_a"; function = "uart_a"; + bias-disable; }; }; @@ -426,6 +449,7 @@ groups = "uart_tx_b", "uart_rx_b"; function = "uart_b"; + bias-disable; }; }; @@ -434,6 +458,7 @@ groups = "uart_cts_b", "uart_rts_b"; function = "uart_b"; + bias-disable; }; }; @@ -442,6 +467,7 @@ groups = "uart_tx_c", "uart_rx_c"; function = "uart_c"; + bias-disable; }; }; @@ -450,6 +476,7 @@ groups = "uart_cts_c", "uart_rts_c"; function = "uart_c"; + bias-disable; }; }; @@ -458,6 +485,7 @@ groups = "i2c_sck_a", "i2c_sda_a"; function = "i2c_a"; + bias-disable; }; }; @@ -466,6 +494,7 @@ groups = "i2c_sck_b", "i2c_sda_b"; function = "i2c_b"; + bias-disable; }; }; @@ -474,6 +503,7 @@ groups = "i2c_sck_c", "i2c_sda_c"; function = "i2c_c"; + bias-disable; }; }; @@ -494,6 +524,7 @@ "eth_txd2", "eth_txd3"; function = "eth"; + bias-disable; }; }; @@ -501,6 +532,7 @@ mux { groups = "eth_link_led"; function = "eth_led"; + bias-disable; }; }; @@ -515,6 +547,7 @@ mux { groups = "pwm_a"; function = "pwm_a"; + bias-disable; }; }; @@ -522,6 +555,7 @@ mux { groups = "pwm_b"; function = "pwm_b"; + bias-disable; }; }; @@ -529,6 +563,7 @@ mux { groups = "pwm_c"; function = "pwm_c"; + bias-disable; }; }; @@ -536,6 +571,7 @@ mux { groups = "pwm_d"; function = "pwm_d"; + bias-disable; }; }; @@ -543,6 +579,7 @@ mux { groups = "pwm_e"; function = "pwm_e"; + bias-disable; }; }; @@ -550,6 +587,7 @@ mux { groups = "pwm_f_clk"; function = "pwm_f"; + bias-disable; }; }; @@ -557,6 +595,7 @@ mux { groups = "pwm_f_x"; function = "pwm_f"; + bias-disable; }; }; @@ -564,6 +603,7 @@ mux { groups = "hdmi_hpd"; function = "hdmi_hpd"; + bias-disable; }; }; @@ -571,6 +611,7 @@ mux { groups = "hdmi_sda", "hdmi_scl"; function = "hdmi_i2c"; + bias-disable; }; }; @@ -578,6 +619,7 @@ mux { groups = "i2s_am_clk"; function = "i2s_out"; + bias-disable; }; }; @@ -585,6 +627,7 @@ mux { groups = "i2s_out_ao_clk"; function = "i2s_out"; + bias-disable; }; }; @@ -592,6 +635,7 @@ mux { groups = "i2s_out_lr_clk"; function = "i2s_out"; + bias-disable; }; }; @@ -599,12 +643,14 @@ mux { groups = "i2s_out_ch01"; function = "i2s_out"; + bias-disable; }; }; i2sout_ch23_z_pins: i2sout_ch23_z { mux { groups = "i2sout_ch23_z"; function = "i2s_out"; + bias-disable; }; }; @@ -612,6 +658,7 @@ mux { groups = "i2sout_ch45_z"; function = "i2s_out"; + bias-disable; }; }; @@ -619,6 +666,7 @@ mux { groups = "i2sout_ch67_z"; function = "i2s_out"; + bias-disable; }; }; @@ -626,6 +674,7 @@ mux { groups = "spdif_out_h"; function = "spdif_out"; + bias-disable; }; }; }; -- cgit From ba1c84ee74d3fa6c99b2471bfac922bf63746591 Mon Sep 17 00:00:00 2001 From: He Yangxuan Date: Sat, 10 Nov 2018 11:39:02 +0800 Subject: arm64: dts: meson-gxl: add support for phicomm n1 This patch adds support for the Phicomm N1. This device based on P230 reference design. And this box doesn't have cvbs, so disable related section in device tree. Signed-off-by: He Yangxuan Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index c31f29d660de..49f3ac5d85a8 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -18,6 +18,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts new file mode 100644 index 000000000000..9a8a8a7e4b53 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 He Yangxuan + */ + +/dts-v1/; + +#include "meson-gxl-s905d-p230.dts" + +/ { + compatible = "phicomm,n1", "amlogic,s905d", "amlogic,meson-gxl"; + model = "Phicomm N1"; + + cvbs-connector { + status = "disabled"; + }; +}; + +&cvbs_vdac_port { + status = "disabled"; +}; -- cgit From 2078231510714578d044b39109f0ab622bf49582 Mon Sep 17 00:00:00 2001 From: He Yangxuan Date: Sat, 10 Nov 2018 11:39:03 +0800 Subject: dt-bindings: Add vendor prefix for PHICOMM Co., Ltd. PHICOMM Co., Ltd. is a hardware provider headquartered in Shanghai, it's product includes router and smart devices. Signed-off-by: He Yangxuan Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 4b1a2a8fcc16..8c413d8cc2a5 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -296,6 +296,7 @@ panasonic Panasonic Corporation parade Parade Technologies Inc. pericom Pericom Technology Inc. pervasive Pervasive Displays, Inc. +phicomm PHICOMM Co., Ltd. phytec PHYTEC Messtechnik GmbH picochip Picochip Ltd pine64 Pine64 -- cgit From bf0fbc8f0f06b9aaef81a42c3223b8998fb33eab Mon Sep 17 00:00:00 2001 From: He Yangxuan Date: Sat, 10 Nov 2018 11:39:04 +0800 Subject: dt-bindings: arm: amlogic: Add Phicomm N1 Add bindings documentation for the Phicomm N1. Signed-off-by: He Yangxuan Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 4498292b833d..93177f38ec19 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -91,6 +91,7 @@ Board compatible values (alphabetically, grouped by SoC): - "amlogic,p230" (Meson gxl s905d) - "amlogic,p231" (Meson gxl s905d) + - "phicomm,n1" (Meson gxl s905d) - "amlogic,p241" (Meson gxl s805x) -- cgit From bc3285052afb7f8405b56831b028e14545d08891 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Fri, 16 Nov 2018 16:15:38 +0100 Subject: dt-bindings: arm: amlogic: add libretech aml-s805x-ac bindings Add bindings for the Libretech aml-s805x-ac board, aka 'La Frite'. Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 93177f38ec19..8dbc259081e4 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -94,6 +94,7 @@ Board compatible values (alphabetically, grouped by SoC): - "phicomm,n1" (Meson gxl s905d) - "amlogic,p241" (Meson gxl s805x) + - "libretech,aml-s805x-ac" (Meson gxl s805x) - "amlogic,p281" (Meson gxl s905w) - "oranth,tx3-mini" (Meson gxl s905w) -- cgit From 0449b8e371acb8609bd6363c91dda464a262f778 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 16 Nov 2018 16:15:39 +0100 Subject: arm64: dts: meson: add libretech aml-s805x-ac board Add Libretech aml-s805x-ac board (aka 'La Frite') support Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Reviewed-by: Peter Korsgaard Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/meson-gxl-s805x-libretech-ac.dts | 248 +++++++++++++++++++++ 2 files changed, 249 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 49f3ac5d85a8..f12efa27c636 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-libretech-ac.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts new file mode 100644 index 000000000000..82b1c4851147 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 BayLibre, SAS. + * Author: Neil Armstrong + * Author: Jerome Brunet + */ + +/dts-v1/; + +#include + +#include "meson-gxl-s905x.dtsi" + +/ { + compatible = "libretech,aml-s805x-ac", "amlogic,s805x", + "amlogic,meson-gxl"; + model = "Libre Computer Board AML-S805X-AC"; + + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + spi0 = &spifc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cvbs-connector { + /* + * The pads are present but no connector is soldered on + * 2J2, so keep this off by default. + */ + status = "disabled"; + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + dc_5v: regulator-dc_5v { + compatible = "regulator-fixed"; + regulator-name = "DC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; + + vcck: regulator-vcck { + compatible = "regulator-fixed"; + regulator-name = "VCCK"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_5v>; + + /* + * This is controlled by GPIOAO_9 we reserve this but + * claiming it as done below reset the board anyway + * Need to investigate this + * + * gpio = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; + * enable-active-high; + */ + regulator-always-on; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_5v>; + regulator-always-on; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; +}; + +&cec_AO { + status = "okay"; + pinctrl-0 = <&ao_cec_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +ðmac { + status = "okay"; +}; + +&internal_phy { + pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; + pinctrl-names = "default"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&gpio_ao { + gpio-line-names = "UART TX", + "UART RX", + "7J1 Header Pin31", + "", "", "", "", + "IR In", + "HDMI CEC", + "5V VCCK Regulator", + /* GPIO_TEST_N */ + ""; +}; + +&gpio { + gpio-line-names = /* Bank GPIOZ */ + "", "", "", "", "", "", "", + "", "", "", "", "", "", "", + "Eth Link LED", "Eth Activity LED", + /* Bank GPIOH */ + "HDMI HPD", "HDMI SDA", "HDMI SCL", + "", "7J1 Header Pin13", + "7J1 Header Pin15", + "7J1 Header Pin7", + "7J1 Header Pin12", + "7J1 Header Pin16", + "7J1 Header Pin18", + /* Bank BOOT */ + "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", + "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", + "eMMC Clk", "eMMC Reset", "eMMC CMD", + "SPI NOR MOSI", "SPI NOR MISO", "SPI NOR Clk", + "", "SPI NOR Chip Select", + /* Bank CARD */ + "", "", "", "", "", "", "", + /* Bank GPIODV */ + "", "", "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", + "7J1 Header Pin27", "7J1 Header Pin28", "", + "7J1 Header Pin29", + "VCCK Regulator", "VDDEE Regulator", + /* Bank GPIOX */ + "7J1 Header Pin22", "7J1 Header Pin26", + "7J1 Header Pin36", "7J1 Header Pin38", + "7J1 Header Pin40", "7J1 Header Pin37", + "7J1 Header Pin33", "7J1 Header Pin35", + "7J1 Header Pin19", "7J1 Header Pin21", + "7J1 Header Pin24", "7J1 Header Pin23", + "7J1 Header Pin8", "7J1 Header Pin10", + "", "", "7J1 Header Pin32", "", "", + /* Bank GPIOCLK */ + "", ""; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +&spifc { + status = "okay"; + pinctrl-0 = <&nor_pins>; + pinctrl-names = "default"; + + w25q32: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <3000000>; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb0 { + status = "okay"; +}; -- cgit From 146e99be22ee5ac50c89cfd68ef6617d097fb196 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:34:24 +0530 Subject: arm64: dts: amlogic: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Acked-by: Neil Armstrong Signed-off-by: Kevin Hilman --- .../boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 782e9edac805..3c3a667a8df8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -132,19 +132,15 @@ map1 { trip = <&cpu_alert1>; - cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>; - }; - - map2 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map3 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>, + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; -- cgit From 5e339a1d7e438b2cc9f46ec9f2682efb58ee2dd3 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Sun, 18 Nov 2018 14:50:24 +0100 Subject: arm64: dts: meson-gx: Add Internal Clock Measurer node The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal clock paths frequencies. This patch adds the node in the top-level meson-gx dtsi. Signed-off-by: Neil Armstrong Acked-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index f1e5cdbade5e..ed336c7a98a7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -262,6 +262,11 @@ status = "disabled"; }; + clock-measure@8758 { + compatible = "amlogic,meson-gx-clk-measure"; + reg = <0x0 0x8758 0x0 0x10>; + }; + i2c_B: i2c@87c0 { compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; reg = <0x0 0x087c0 0x0 0x20>; -- cgit From 634da3307b083ee83eb9b377081fdfd6416a148a Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Thu, 15 Nov 2018 10:18:08 -0700 Subject: arm64: dts: qcom: msm8998: correct xo clock name The root parent clock of most msm8998 clock is the "xo" clock. The DT node is incorrectly named "xo_board", which prevents Linux from correctly parsing the clock tree, resulting in most clocks being unparented and unable to be manipulated. The end result is that we can't turn on clocks for peripherals like SD, so init usually fails. Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Jeffrey Hugo Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 78227cce16db..a948d4ba57b0 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -53,7 +53,7 @@ }; clocks { - xo_board { + xo { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; -- cgit From 1cfce828dca847538f3ead447e52296202a2569c Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Thu, 15 Nov 2018 10:18:09 -0700 Subject: arm64: dts: qcom: msm8998: Add SDCC2 SDCC2 is typically used as the controller for an external SD card slot. Signed-off-by: Jeffrey Hugo Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index a948d4ba57b0..09deee0f7661 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -53,7 +53,7 @@ }; clocks { - xo { + xo: xo { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; @@ -605,6 +605,23 @@ #mbox-cells = <1>; }; + sdhc2: sdhci@c0a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clock-names = "iface", "core", "xo"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo>; + bus-width = <4>; + status = "disabled"; + }; + blsp2_uart1: serial@c1b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xc1b0000 0x1000>; -- cgit From 23bd4f785b53d96d45c0dc073ee219849b11e766 Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Thu, 15 Nov 2018 10:18:11 -0700 Subject: arm64: dts: qcom: msm8998-mtp: Add external SD The externally accessible SD card slot on the MTP is driven by SDCC2. Wire it up for use. Signed-off-by: Jeffrey Hugo Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/qcom/msm8998.dtsi | 1 + 2 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi index 11fd1fe8bdb5..50e9033aa7f6 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi @@ -245,3 +245,15 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; }; + +&sdhc2 { + status = "okay"; + cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 09deee0f7661..82f647238071 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -3,6 +3,7 @@ #include #include +#include / { interrupt-parent = <&intc>; -- cgit From 6da8016109fc0236cd465e06827804068fd00c7b Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Thu, 15 Nov 2018 10:18:10 -0700 Subject: arm64: dts: qcom: msm8998: Add SDC2 control pins The SDC2 control pins are typically used to manage sleep. Signed-off-by: Jeffrey Hugo Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998-pins.dtsi | 78 ++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 + 2 files changed, 80 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8998-pins.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi new file mode 100644 index 000000000000..6db70acd38ee --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ + +&tlmm { + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 mA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 mA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 mA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 mA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 mA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 mA */ + }; + }; + + sdc2_cd_on: sdc2_cd_on { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 mA */ + }; + }; + + sdc2_cd_off: sdc2_cd_off { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 mA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 82f647238071..8e7d788baac4 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -706,3 +706,5 @@ }; }; }; + +#include "msm8998-pins.dtsi" -- cgit From 77e65779ad3b7d1604e0e2800d0706463bb3623f Mon Sep 17 00:00:00 2001 From: Oskari Lemmela Date: Tue, 20 Nov 2018 19:52:05 +0200 Subject: ARM: dts: axp81x: add AC power supply subnode Add AC power supply subnode for AXP81X PMIC. Signed-off-by: Oskari Lemmela Reviewed-by: Quentin Schulz Reviewed-by: Chen-Yu Tsai Tested-by: Vasily Khoruzhick Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/axp81x.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi index 043c717dcef1..bd83962d3627 100644 --- a/arch/arm/boot/dts/axp81x.dtsi +++ b/arch/arm/boot/dts/axp81x.dtsi @@ -48,6 +48,11 @@ interrupt-controller; #interrupt-cells = <1>; + ac_power_supply: ac-power-supply { + compatible = "x-powers,axp813-ac-power-supply"; + status = "disabled"; + }; + axp_adc: adc { compatible = "x-powers,axp813-adc"; #io-channel-cells = <1>; -- cgit From 74221150240025841b8c76f0c7a82d3febbb2c20 Mon Sep 17 00:00:00 2001 From: Oskari Lemmela Date: Tue, 20 Nov 2018 19:52:06 +0200 Subject: arm64: dts: allwinner: axp803: add AC and battery power supplies Parts of the AXP803 are compatible with their counterparts on the AXP813. Add DT nodes ADC, GPIO, AC and battery power supplies. Signed-off-by: Oskari Lemmela Reviewed-by: Quentin Schulz Reviewed-by: Chen-Yu Tsai Tested-by: Vasily Khoruzhick Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/axp803.dtsi | 33 +++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi index e5eae8bafc42..c3a618e1279a 100644 --- a/arch/arm64/boot/dts/allwinner/axp803.dtsi +++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi @@ -49,6 +49,39 @@ interrupt-controller; #interrupt-cells = <1>; + ac_power_supply: ac-power-supply { + compatible = "x-powers,axp803-ac-power-supply", + "x-powers,axp813-ac-power-supply"; + status = "disabled"; + }; + + axp_adc: adc { + compatible = "x-powers,axp803-adc", "x-powers,axp813-adc"; + #io-channel-cells = <1>; + }; + + axp_gpio: gpio { + compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio"; + gpio-controller; + #gpio-cells = <2>; + + gpio0_ldo: gpio0-ldo { + pins = "GPIO0"; + function = "ldo"; + }; + + gpio1_ldo: gpio1-ldo { + pins = "GPIO1"; + function = "ldo"; + }; + }; + + battery_power_supply: battery-power-supply { + compatible = "x-powers,axp803-battery-power-supply", + "x-powers,axp813-battery-power-supply"; + status = "disabled"; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <3000>; -- cgit From 5e99c99aa8031ecaa5125ac41c210633e9f47b52 Mon Sep 17 00:00:00 2001 From: Oskari Lemmela Date: Tue, 20 Nov 2018 19:52:07 +0200 Subject: arm64: dts: allwinner: a64: sopine-baseboard: enable power supplies AXP803 ACIN pins are routed from SOM to the DC jack on the baseboard. AXP803 charger pins BATSENSE, LOADSENSE, N_BATDRV, LX_CHG, VIN_CHG and IPSOUT are connected via PMOS driver to SOM VBAT pins. VBAT and AXP803 TS pins are routed to the baseboard 3-pin battery connector. Signed-off-by: Oskari Lemmela Reviewed-by: Quentin Schulz Reviewed-by: Chen-Yu Tsai Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 2052319b9030..e6fb9683f213 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -80,6 +80,14 @@ }; }; +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + &codec { status = "okay"; }; -- cgit From 2c8d843d498d49c96cbab6911205a8a0dee44ba0 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Tue, 20 Nov 2018 19:52:08 +0200 Subject: arm64: dts: allwinner: a64: pinebook: enable power supplies Pinebook has ACIN connector and 10000 mAh battery. Signed-off-by: Vasily Khoruzhick Signed-off-by: Oskari Lemmela Reviewed-by: Chen-Yu Tsai Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 25018d032d51..d22736a62481 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -184,6 +184,14 @@ #include "axp803.dtsi" +&ac_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + ®_aldo1 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; -- cgit From d8c6557bc93be73ed1abe5b13fa1e46e59da028b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 29 Nov 2018 11:34:34 +0100 Subject: arm64: dts: renesas: r8a77965: Remove non-existent IPMMU-IR The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Aug 24, 2018) removed the IPMMU-IR IOMMU instance on R-Car M3-N, as this SoC does not have an Image Processing Unit (IMP-X5) nor the A3IR power domain. Fixes: 55697cbb44e4f7ea ("arm64: dts: renesas: r8a779{65,80,90}: Add IPMMU devices nodes") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 1c86e6f4dc71..6dc9b1fef830 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -795,14 +795,6 @@ #iommu-cells = <1>; }; - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A77965_PD_A3IR>; - #iommu-cells = <1>; - }; - ipmmu_mm: mmu@e67b0000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xe67b0000 0 0x1000>; -- cgit From 41e30b515a003a90e336b7a456c7c82d8c3aa6a7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 29 Nov 2018 11:34:35 +0100 Subject: arm64: dts: renesas: r8a7795-es1: Add missing power domains to IPMMU nodes While commit 3b7e7848f0e88b36 ("arm64: dts: renesas: r8a7795: Add IPMMU device nodes") for R-Car H3 ES2.0 did include power-domains properties, they were forgotten in the counterpart for older R-Car H3 ES1.x SoCs. Fixes: e4b9a493df45075b ("arm64: dts: renesas: r8a7795-es1: Add IPMMU device nodes") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index 0fb84c219b2f..40d10daca852 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -28,6 +28,7 @@ compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xec680000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 5>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -35,6 +36,7 @@ compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xe7730000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; #iommu-cells = <1>; }; -- cgit From 70827d9f6bc4f481fafe790dd6654ba568526768 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 29 Nov 2018 22:56:55 -0800 Subject: arm64: dts: qcom: msm8998: Fix compatible of scm node The scm binding and driver was updated to rely on the fallback to the default qcom,scm for any modern SoC and as such both are required. Add the default compatible to make the scm instance probe. Fixes: d850156a226a ("arm64: dts: qcom: msm8998: Add firmware node") Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 8e7d788baac4..49f0fee85e74 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -240,7 +240,7 @@ firmware { scm { - compatible = "qcom,scm-msm8998"; + compatible = "qcom,scm-msm8998", "qcom,scm"; }; }; -- cgit From b597a6f54280cdb20fb19c0224757f70cfb731c4 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Tue, 16 Oct 2018 13:50:52 +0300 Subject: arm64: dts: clearfog-gt-8k: fix USB regulator gpio polarity The fixed regulator driver ignores the gpio flags, so this change has no practical effect in the current implementation. Fix it anyway to correct the hardware description. Signed-off-by: Baruch Siach Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index 9473d40a292a..f03740d5ce62 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -42,7 +42,7 @@ v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { compatible = "regulator-fixed"; - gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; + gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&cp0_xhci_vbus_pins>; regulator-name = "v_5v0_usb3_hst_vbus"; -- cgit From babc5544c2933a5cbf9389679507dfa4911101ee Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Tue, 16 Oct 2018 13:50:53 +0300 Subject: arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal This reset signal controls the Marvell 1512 1G PHY. Note that current implementation queries the PHY over the MDIO bus (get_phy_device() call from of_mdiobus_register_phy()) before reset signal deassert. If the PHY reset signal is asserted at boot time, PHY registration fails. So current code relies on the bootloader to deassert the reset signal. Signed-off-by: Baruch Siach Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index f03740d5ce62..f2e5b98f0c32 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -333,6 +333,10 @@ */ marvell,reg-init = <3 16 0 0x1017>; reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_copper_eth_phy_reset>; + reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; }; switch0: switch0@4 { -- cgit From 235df2d80d3b196943043203bcb900325013a80a Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Fri, 19 Oct 2018 07:57:54 +0300 Subject: arm64: dts: clearfog-gt-8k: enable mini-PCIe CON2 USB Deassert the reset and wireless disable signals on the CON2 mini-PCIe socket. That allows the host to detect USB devices on the mini-PCIe socket. Signed-off-by: Baruch Siach Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index f2e5b98f0c32..dfb26661a88e 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -246,6 +246,18 @@ gpios = <1 GPIO_ACTIVE_HIGH>; output-high; }; + + lte_reset { + gpio-hog; + gpios = <2 GPIO_ACTIVE_LOW>; + output-low; + }; + + lte_disable { + gpio-hog; + gpios = <21 GPIO_ACTIVE_LOW>; + output-low; + }; }; &cp0_ethernet { -- cgit From eefe328439642101774f0f5c4ea0dc6ba1cfb687 Mon Sep 17 00:00:00 2001 From: Ding Tao Date: Fri, 26 Oct 2018 11:50:27 +0000 Subject: arm64: dts: marvell: armada37xx: Add emmc/sdio pinctrl definition Add emmc/sdio pinctrl definition for marvell armada37xx SoCs. Signed-off-by: Ding Tao Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 4472bcd8f9fb..e05594ea15fb 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -234,6 +234,11 @@ groups = "uart2"; function = "uart"; }; + + mmc_pins: mmc-pins { + groups = "emmc_nb"; + function = "emmc"; + }; }; nb_pm: syscon@14000 { @@ -266,6 +271,11 @@ function = "mii"; }; + sdio_pins: sdio-pins { + groups = "sdio_sb"; + function = "sdio"; + }; + }; eth0: ethernet@30000 { -- cgit From 03e96644d7a810916fc4997d572577e876908b18 Mon Sep 17 00:00:00 2001 From: René Kjellerup Date: Mon, 1 Oct 2018 15:07:16 -0700 Subject: ARM: dts: BCM5301X: Add basic DT for Linksys EA6500 V2 It is wireless home router based on BCM4708A0 with BCM4360 + BCM4331 wireless chipsets. The BCM4331 5GHz chip currently isn't supported only due to missing compatible firmware. Signed-off-by: Rene Kjellerup Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts | 45 +++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..93d44d63bc1f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -89,6 +89,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4708-asus-rt-ac68u.dtb \ bcm4708-buffalo-wzr-1750dhp.dtb \ bcm4708-linksys-ea6300-v1.dtb \ + bcm4708-linksys-ea6500-v2.dtb \ bcm4708-luxul-xap-1510.dtb \ bcm4708-luxul-xwc-1000.dtb \ bcm4708-netgear-r6250.dtb \ diff --git a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts new file mode 100644 index 000000000000..babcfec50dde --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2017 RafaÅ‚ MiÅ‚ecki + * Copyright (C) 2018 Rene Kjellerup + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "linksys,ea6500-v2", "brcm,bcm4708"; + model = "Linksys EA6500 V2"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb3_phy { + status = "okay"; +}; -- cgit From 9994241ac97cb84d1df98fdc172d3cc6b04b11bf Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Fri, 9 Nov 2018 09:56:49 +0100 Subject: ARM: dts: BCM5301X: Describe Northstar pins mux controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This describes hardware & will allow referencing pin functions. The first usage is UART1 which allows supporting devices using it. Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 44 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 7a5c188c2676..fd7af943fb0b 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -37,6 +37,8 @@ reg = <0x0400 0x100>; interrupts = ; clocks = <&iprocslow>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_uart1>; status = "disabled"; }; }; @@ -391,6 +393,48 @@ status = "disabled"; }; + dmu@1800c000 { + compatible = "simple-bus"; + ranges = <0 0x1800c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + cru@100 { + compatible = "simple-bus"; + reg = <0x100 0x1a4>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + pin-controller@1c0 { + compatible = "brcm,bcm4708-pinmux"; + reg = <0x1c0 0x24>; + reg-names = "cru_gpio_control"; + + spi-pins { + groups = "spi_grp"; + function = "spi"; + }; + + i2c { + groups = "i2c_grp"; + function = "i2c"; + }; + + pwm { + groups = "pwm0_grp", "pwm1_grp", + "pwm2_grp", "pwm3_grp"; + function = "pwm"; + }; + + pinmux_uart1: uart1 { + groups = "uart1_grp"; + function = "uart1"; + }; + }; + }; + }; + lcpll0: lcpll0@1800c100 { #clock-cells = <1>; compatible = "brcm,nsp-lcpll0"; -- cgit From ca40d2bd813efcee058760c63c9eae043d2939d9 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Wed, 28 Nov 2018 18:53:05 +0100 Subject: dt-bindings: mrvl,mmp-timer: add clock The timer needs the timer clock to be enabled, otherwise it stops ticking. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring Acked-by: Pavel Machek Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt b/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt index 9a6e251462e7..b8f02c663521 100644 --- a/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt +++ b/Documentation/devicetree/bindings/timer/mrvl,mmp-timer.txt @@ -5,9 +5,13 @@ Required properties: - reg : Address and length of the register set of timer controller. - interrupts : Should be the interrupt number. +Optional properties: +- clocks : Should contain a single entry describing the clock input. + Example: timer0: timer@d4014000 { compatible = "mrvl,mmp-timer"; reg = <0xd4014000 0x100>; interrupts = <13>; + clocks = <&coreclk 2>; }; -- cgit From 400583983f8a8e95ec02c9c9e2b50188753a87fb Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Wed, 28 Nov 2018 18:53:06 +0100 Subject: ARM: dts: mmp2: fix the gpio interrupt cell number gpio-pxa uses two cell to encode the interrupt source: the pin number and the trigger type. Adjust the device node accordingly. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek Signed-off-by: Olof Johansson --- arch/arm/boot/dts/mmp2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 766bbb8495b6..db15d1186cd0 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -180,7 +180,7 @@ clocks = <&soc_clocks MMP2_CLK_GPIO>; resets = <&soc_clocks MMP2_CLK_GPIO>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; ranges; gcb0: gpio@d4019000 { -- cgit From 5b3edb56bc6ef05a66c0902ea4315e3c35de93c5 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Wed, 28 Nov 2018 18:53:07 +0100 Subject: ARM: dts: mmp2: give gpio node a name This will be useful for boards that actually use GPIO pins. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek Signed-off-by: Olof Johansson --- arch/arm/boot/dts/mmp2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index db15d1186cd0..f2a18779de7c 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -168,7 +168,7 @@ status = "disabled"; }; - gpio@d4019000 { + gpio: gpio@d4019000 { compatible = "marvell,mmp2-gpio"; #address-cells = <1>; #size-cells = <1>; -- cgit From 1c22b9c10a61947f19d22cdd5d6e51415b59057b Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Wed, 28 Nov 2018 18:53:08 +0100 Subject: ARM: dts: mmp2: add clock to the timer The timer needs the timer clock to be enabled, otherwise it stops ticking. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek Signed-off-by: Olof Johansson --- arch/arm/boot/dts/mmp2.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index f2a18779de7c..4743a1288280 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -130,6 +130,7 @@ compatible = "mrvl,mmp-timer"; reg = <0xd4014000 0x100>; interrupts = <13>; + clocks = <&soc_clocks MMP2_CLK_TIMER>; }; uart1: uart@d4030000 { -- cgit From 03f64e17f57c0a8041c8fed35de9c0176a730aa5 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Wed, 28 Nov 2018 18:53:09 +0100 Subject: ARM: dts: mmp2: add MMC controllers There's apparently four of them on a MMP2. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek Signed-off-by: Olof Johansson --- arch/arm/boot/dts/mmp2.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 4743a1288280..1120fe6abbdc 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -117,6 +117,42 @@ reg-names = "mux status", "mux mask"; mrvl,intc-nr-irqs = <2>; }; + + mmc1: mmc@d4280000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4280000 0x120>; + clocks = <&soc_clocks MMP2_CLK_SDH0>; + clock-names = "io"; + interrupts = <39>; + status = "disabled"; + }; + + mmc2: mmc@d4280800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4280800 0x120>; + clocks = <&soc_clocks MMP2_CLK_SDH1>; + clock-names = "io"; + interrupts = <52>; + status = "disabled"; + }; + + mmc3: mmc@d4281000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4281000 0x120>; + clocks = <&soc_clocks MMP2_CLK_SDH2>; + clock-names = "io"; + interrupts = <53>; + status = "disabled"; + }; + + mmc4: mmc@d4281800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4281800 0x120>; + clocks = <&soc_clocks MMP2_CLK_SDH3>; + clock-names = "io"; + interrupts = <54>; + status = "disabled"; + }; }; apb@d4000000 { /* APB */ -- cgit From 1147e05ac9fc2ef86a3691e7ca5c2db7602d81dd Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Wed, 28 Nov 2018 18:53:10 +0100 Subject: ARM: dts: mmp2: fix TWSI2 Marvell keeps their MMP2 datasheet secret, but there are good clues that TWSI2 is not on 0xd4025000 on that platform, not does it use IRQ 58. In fact, the IRQ 58 on MMP2 seems to be a signal processor: arch/arm/mach-mmp/irqs.h:#define IRQ_MMP2_MSP 58 I'm taking a somewhat educated guess that is probably a copy & paste error from PXA168 or PXA910 and that the real controller in fact hides at address 0xd4031000 and uses an interrupt line multiplexed via IRQ 17. I'm also copying some properties from TWSI1 that were missing or incorrect. Tested on a OLPC XO 1.75 machine, where the RTC is on TWSI2. Signed-off-by: Lubomir Rintel Tested-by: Pavel Machek Signed-off-by: Olof Johansson --- arch/arm/boot/dts/mmp2.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 1120fe6abbdc..c5787eea57c7 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -257,12 +257,15 @@ status = "disabled"; }; - twsi2: i2c@d4025000 { + twsi2: i2c@d4031000 { compatible = "mrvl,mmp-twsi"; - reg = <0xd4025000 0x1000>; - interrupts = <58>; + reg = <0xd4031000 0x1000>; + interrupt-parent = <&intcmux17>; + interrupts = <0>; clocks = <&soc_clocks MMP2_CLK_TWSI1>; resets = <&soc_clocks MMP2_CLK_TWSI1>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; -- cgit From 8a22b194cedfee5347f198eec7796080696c5050 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Wed, 28 Nov 2018 18:53:11 +0100 Subject: ARM: dts: mmp2: add more TWSI controllers I've gotten the base addresses, clocks and interrupts from an rusty and old out-of-tree driver. I haven't actually checked against the datasheet, since that one is reserved for the Marvell inner circle. Tested with an accelerometer on TWSI6 on an OLPC XO 1.75 machine. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek Signed-off-by: Olof Johansson --- arch/arm/boot/dts/mmp2.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index c5787eea57c7..c48d17a38d6b 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -269,6 +269,55 @@ status = "disabled"; }; + twsi3: i2c@d4032000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4032000 0x1000>; + interrupt-parent = <&intcmux17>; + interrupts = <1>; + clocks = <&soc_clocks MMP2_CLK_TWSI2>; + resets = <&soc_clocks MMP2_CLK_TWSI2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + twsi4: i2c@d4033000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4033000 0x1000>; + interrupt-parent = <&intcmux17>; + interrupts = <2>; + clocks = <&soc_clocks MMP2_CLK_TWSI3>; + resets = <&soc_clocks MMP2_CLK_TWSI3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + + twsi5: i2c@d4033800 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4033800 0x1000>; + interrupt-parent = <&intcmux17>; + interrupts = <3>; + clocks = <&soc_clocks MMP2_CLK_TWSI4>; + resets = <&soc_clocks MMP2_CLK_TWSI4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + twsi6: i2c@d4034000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4034000 0x1000>; + interrupt-parent = <&intcmux17>; + interrupts = <4>; + clocks = <&soc_clocks MMP2_CLK_TWSI5>; + resets = <&soc_clocks MMP2_CLK_TWSI5>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; -- cgit From df606f41abede3c6db1c053153874b71db59df04 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Wed, 28 Nov 2018 18:53:12 +0100 Subject: ARM: dts: mmp2: add OTG PHY The USB OTG PHY chip. To be used by the OTG controller. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek Signed-off-by: Olof Johansson --- arch/arm/boot/dts/mmp2.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index c48d17a38d6b..57f6248f17cd 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -118,6 +118,13 @@ mrvl,intc-nr-irqs = <2>; }; + usb_otg_phy0: usb-otg-phy@d4207000 { + compatible = "marvell,mmp2-usb-phy"; + reg = <0xd4207000 0x40>; + #phy-cells = <0>; + status = "disabled"; + }; + mmc1: mmc@d4280000 { compatible = "mrvl,pxav3-mmc"; reg = <0xd4280000 0x120>; -- cgit From 3f3ad8ab3260ce0d370d2686ecdf75b0bbf73024 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Wed, 28 Nov 2018 18:53:13 +0100 Subject: ARM: dts: mmp2: add USB OTG host controller Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek Signed-off-by: Olof Johansson --- arch/arm/boot/dts/mmp2.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 57f6248f17cd..0c5a51b98c3f 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -125,6 +125,17 @@ status = "disabled"; }; + usb_otg0: usb-otg@d4208000 { + compatible = "marvell,pxau2o-ehci"; + reg = <0xd4208000 0x200>; + interrupts = <44>; + clocks = <&soc_clocks MMP2_CLK_USB>; + clock-names = "USBCLK"; + phys = <&usb_otg_phy0>; + phy-names = "usb"; + status = "disabled"; + }; + mmc1: mmc@d4280000 { compatible = "mrvl,pxav3-mmc"; reg = <0xd4280000 0x120>; -- cgit From d3e9d2ce7725d87afdf71f1056a4fa5f447832e7 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Wed, 28 Nov 2018 18:53:14 +0100 Subject: ARM: dts: mmp2: Add SSP controllers Despite Marvel keeps their base addresses secret there's a good chance they're actually correct. SSP1 and SSP3 bases were taken from OLPC 1.75: OpenFirmware and kernel respectively. SSP2 and SSP4 addresses are from James Cameron who actually has a copy of the data sheet. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek Signed-off-by: Olof Johansson --- arch/arm/boot/dts/mmp2.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 0c5a51b98c3f..ee03e0846740 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -346,6 +346,38 @@ resets = <&soc_clocks MMP2_CLK_RTC>; status = "disabled"; }; + + ssp1: ssp@d4035000 { + compatible = "marvell,mmp2-ssp"; + reg = <0xd4035000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP0>; + interrupts = <0>; + status = "disabled"; + }; + + ssp2: ssp@d4036000 { + compatible = "marvell,mmp2-ssp"; + reg = <0xd4036000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP1>; + interrupts = <1>; + status = "disabled"; + }; + + ssp3: ssp@d4037000 { + compatible = "marvell,mmp2-ssp"; + reg = <0xd4037000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP2>; + interrupts = <20>; + status = "disabled"; + }; + + ssp4: ssp@d4039000 { + compatible = "marvell,mmp2-ssp"; + reg = <0xd4039000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP3>; + interrupts = <21>; + status = "disabled"; + }; }; soc_clocks: clocks{ -- cgit From 7f4b001b7f6e0480b5bdab9cd8ce1711e43e5cb5 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 29 Nov 2018 19:05:47 -0600 Subject: ARM: dts: realview-pbx: Fix duplicate regulator nodes There's a bug in dtc in checking for duplicate node names when there's another section (e.g. "/ { };"). In this case, skeleton.dtsi provides another section. Upon removal of skeleton.dtsi, the dtb fails to build due to a duplicate node 'fixedregulator@0'. As both nodes were pretty much the same 3.3V fixed regulator, it hasn't really mattered. Fix this by renaming the nodes to something unique. In the process, drop the unit-address which shouldn't be present wtihout reg property. Cc: Linus Walleij Signed-off-by: Rob Herring Signed-off-by: Olof Johansson --- arch/arm/boot/dts/arm-realview-pbx.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi index a5676697ff3b..916a97734f84 100644 --- a/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi @@ -44,7 +44,7 @@ }; /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: fixedregulator@0 { + vmmc: regulator-vmmc { compatible = "regulator-fixed"; regulator-name = "vmmc"; regulator-min-microvolt = <3300000>; @@ -52,7 +52,7 @@ regulator-boot-on; }; - veth: fixedregulator@0 { + veth: regulator-veth { compatible = "regulator-fixed"; regulator-name = "veth"; regulator-min-microvolt = <3300000>; @@ -567,4 +567,3 @@ }; }; }; - -- cgit From 8ef86955fe59f7912a40d57ae4c6d511f0187b4d Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 29 Nov 2018 19:52:51 -0600 Subject: ARM: dts: aspeed: add missing memory unit-address The base aspeed-g5.dtsi already defines a '/memory@80000000' node, so '/memory' in the board files create a duplicate node. We're probably getting lucky that the bootloader fixes up the memory node that the kernel ends up using. Add the unit-address so it's merged with the base node. Found with DT json-schema checks. Cc: Joel Stanley Cc: Andrew Jeffery Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-aspeed@lists.ozlabs.org Signed-off-by: Rob Herring Signed-off-by: Olof Johansson --- arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts | 3 +-- arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts | 2 +- 4 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts index df1227613d48..c2ece0b91885 100644 --- a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts +++ b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts @@ -13,7 +13,7 @@ bootargs = "console=ttyS4,115200 earlyprintk"; }; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts index 7a291de02543..22dade6393d0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts +++ b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts @@ -13,7 +13,7 @@ bootargs = "earlyprintk"; }; - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts index d598b6391362..024e52a6cd0f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts @@ -14,7 +14,7 @@ bootargs = "console=ttyS4,115200 earlyprintk"; }; - memory { + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -322,4 +322,3 @@ &adc { status = "okay"; }; - diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts index 43ed13963d35..33d704541de6 100644 --- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts +++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts @@ -17,7 +17,7 @@ bootargs = "console=ttyS4,115200 earlyprintk"; }; - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; -- cgit From 452ad2f2f8b7f210ac3b6fc08a52a6f5e392059a Mon Sep 17 00:00:00 2001 From: PaweÅ‚ Chmiel Date: Fri, 30 Nov 2018 19:04:23 +0100 Subject: ARM: dts: s5pv210: Add s5p-jpeg codec node. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add node for s5p-jpeg codec, which is present in S5PV210 SoC. Signed-off-by: PaweÅ‚ Chmiel Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 75f454a210d6..12eac8930eac 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -627,6 +627,15 @@ samsung,lcd-wb; }; }; + + jpeg_codec: jpeg-codec@fb600000 { + compatible = "samsung,s5pv210-jpeg"; + reg = <0xfb600000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <8>; + clocks = <&clocks CLK_JPEG>; + clock-names = "jpeg"; + }; }; }; -- cgit From 40b217a04363a7325aa9df743b830888fb18e816 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Mon, 5 Nov 2018 20:18:27 +0100 Subject: ARM: dts: pxa3xx: add gcu node Add a device node for hardware graphic acceleration. Signed-off-by: Daniel Mack Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa3xx.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 3a8f0edc3af9..264f681bebd9 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -300,4 +300,12 @@ clocks = <&clks CLK_OSTIMER>; status = "okay"; }; + + gcu: display-controller@54000000 { + compatible = "marvell,pxa300-gcu"; + reg = <0x54000000 0x1000>; + interrupts = <39>; + clocks = <&clks CLK_PXA300_GCU>; + status = "disabled"; + }; }; -- cgit From a6da403dc9d5d5f4ec20a29896d1d1262888aa24 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 30 Nov 2018 18:55:37 +0100 Subject: ARM: dts: pxa2xx: drop #address-cells and #size-cells from /cpus PXA is single-core only, so this node will not have enumerable children. Drop the #address-cells and #size-cells properties to squelch a dtc warning. Signed-off-by: Daniel Mack Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa2xx.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index 080d5c5169b5..7d3dfa8259f8 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -43,8 +43,6 @@ }; cpus { - #address-cells = <0>; - #size-cells = <0>; cpu { compatible = "marvell,xscale"; device_type = "cpu"; -- cgit From 1b583921815cde6487f3f04b92730233d3ff7bd9 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 30 Nov 2018 18:55:38 +0100 Subject: ARM: dts: pxa3xx: drop #address-cells and #size-cells from pinctrl node The pinctrl node does not have any children, so the #address-cells and #size-cells properties are not needed. Signed-off-by: Daniel Mack Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa3xx.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 264f681bebd9..eb3223e85f9a 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -151,8 +151,6 @@ pinctrl: pinctrl@40e10000 { compatible = "pinconf-single"; reg = <0x40e10000 0xffff>; - #address-cells = <1>; - #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7>; -- cgit From 513057f110a7c3c53ab08499e29dec29c6852648 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 30 Nov 2018 18:55:39 +0100 Subject: ARM: dts: pxa2xx: fix hwuart memory range The memory range for the hwuart is at 0x41600000, not 0x41100000. This also solves a conflict with the MMC controller node. Signed-off-by: Daniel Mack Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa2xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index 7d3dfa8259f8..30e77ebbcc4d 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -117,9 +117,9 @@ status = "disabled"; }; - hwuart: serial@41100000 { + hwuart: serial@41600000 { compatible = "mrvl,pxa-uart"; - reg = <0x41100000 0x30>; + reg = <0x41600000 0x30>; interrupts = <7>; status = "disabled"; }; -- cgit From 64396bd286d36a3926f099db297f4d25b3156896 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 30 Nov 2018 18:55:41 +0100 Subject: ARM: dts: pxa3xx: order timer and gcu nodes under /pxabus These are devices on the PXA bus, so make the device tree structure reflect that. Signed-off-by: Daniel Mack Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa3xx.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index eb3223e85f9a..71c470a5d03f 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -273,6 +273,22 @@ clocks = <&clks CLK_SSP4>; status = "disabled"; }; + + timer@40a00000 { + compatible = "marvell,pxa-timer"; + reg = <0x40a00000 0x20>; + interrupts = <26>; + clocks = <&clks CLK_OSTIMER>; + status = "okay"; + }; + + gcu: display-controller@54000000 { + compatible = "marvell,pxa300-gcu"; + reg = <0x54000000 0x1000>; + interrupts = <39>; + clocks = <&clks CLK_PXA300_GCU>; + status = "disabled"; + }; }; clocks { @@ -290,20 +306,4 @@ status = "okay"; }; }; - - timer@40a00000 { - compatible = "marvell,pxa-timer"; - reg = <0x40a00000 0x20>; - interrupts = <26>; - clocks = <&clks CLK_OSTIMER>; - status = "okay"; - }; - - gcu: display-controller@54000000 { - compatible = "marvell,pxa300-gcu"; - reg = <0x54000000 0x1000>; - interrupts = <39>; - clocks = <&clks CLK_PXA300_GCU>; - status = "disabled"; - }; }; -- cgit From e9ae49f7b3cb7d71b156ae76cd540f8c1b84753a Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 30 Nov 2018 18:55:42 +0100 Subject: ARM: dts: pxa3xx: clean up pxa3xx clock controller node name The clock controller node does not need a unit slave designator as it does not have a reg property. Also, remove the underscore from the name. Signed-off-by: Daniel Mack Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa3xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 71c470a5d03f..d9f7c68479ab 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -300,7 +300,7 @@ #size-cells = <1>; ranges; - clks: pxa3xx_clks@41300004 { + clks: clocks { compatible = "marvell,pxa300-clocks"; #clock-cells = <1>; status = "okay"; -- cgit From c40ad24254f1dbd54f2df5f5f524130dc1862122 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Sat, 1 Dec 2018 14:54:51 +0100 Subject: ARM: dts: pxa: clean up USB controller nodes PXA25xx SoCs don't have a USB controller, so drop the node from the common pxa2xx.dtsi base file. Both pxa27x and pxa3xx have a dedicated node already anyway. While at it, unify the names for the nodes across all pxa platforms. Signed-off-by: Daniel Mack Reported-by: Sergey Yanovich Link: https://patchwork.kernel.org/patch/8375421/ Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa27x.dtsi | 2 +- arch/arm/boot/dts/pxa2xx.dtsi | 7 ------- arch/arm/boot/dts/pxa3xx.dtsi | 2 +- 3 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index 3228ad5fb725..ccbecad9c5c7 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -35,7 +35,7 @@ clocks = <&clks CLK_NONE>; }; - pxa27x_ohci: usb@4c000000 { + usb0: usb@4c000000 { compatible = "marvell,pxa-ohci"; reg = <0x4c000000 0x10000>; interrupts = <3>; diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index 30e77ebbcc4d..e83879d97aea 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -134,13 +134,6 @@ status = "disabled"; }; - usb0: ohci@4c000000 { - compatible = "marvell,pxa-ohci"; - reg = <0x4c000000 0x10000>; - interrupts = <3>; - status = "disabled"; - }; - mmc0: mmc@41100000 { compatible = "marvell,pxa-mmc"; reg = <0x41100000 0x1000>; diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index d9f7c68479ab..e1e607f53ce6 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -202,7 +202,7 @@ status = "disabled"; }; - pxa3xx_ohci: usb@4c000000 { + usb0: usb@4c000000 { compatible = "marvell,pxa-ohci"; reg = <0x4c000000 0x10000>; interrupts = <3>; -- cgit From d776dd52247c2b82e719403fab9a755cf22bd258 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 24 Jul 2018 14:24:03 +1000 Subject: ARM: dts: aspeed: Romulus system can use coprocessor for FSI This replaces the FSI compatible with the ColdFire FSI compatible. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 7d28c03a9e0b..cb14f14514d0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -30,6 +30,11 @@ no-map; reg = <0x98000000 0x04000000>; /* 64M */ }; + + coldfire_memory: codefire_memory@9ef00000 { + reg = <0x9ef00000 0x00100000>; + no-map; + }; }; leds { @@ -49,11 +54,15 @@ }; fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; + compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; #address-cells = <2>; #size-cells = <0>; no-gpio-delays; + memory-region = <&coldfire_memory>; + aspeed,sram = <&sram>; + aspeed,cvic = <&cvic>; + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; -- cgit From fad06e25b04b1090c21b2be4343cf7ee07f02ab5 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 24 Jul 2018 14:24:04 +1000 Subject: ARM: dts: aspeed: Palmetto system can use coprocessor for FSI This allows userspace to switch away from bitbanging to use kernel FSI with the coprocessor. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 28 ++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index c7084a819dc6..e6cfdf3c1a67 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -26,6 +26,11 @@ no-map; reg = <0x5f000000 0x01000000>; /* 16M */ }; + + coldfire_memory: codefire_memory@5ee00000 { + reg = <0x5ee00000 0x00200000>; + no-map; + }; }; leds { @@ -44,6 +49,22 @@ }; }; + fsi: gpio-fsi { + compatible = "aspeed,ast2400-cf-fsi-master", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + + memory-region = <&coldfire_memory>; + aspeed,sram = <&sram>; + aspeed,cvic = <&cvic>; + + clock-gpios = <&gpio ASPEED_GPIO(A, 4) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(A, 5) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>; + }; + gpio-keys { compatible = "gpio-keys"; @@ -303,13 +324,6 @@ line-name = "SYS_PWROK_BMC"; }; - pin_gpio_h6 { - gpio-hog; - gpios = ; - output-high; - line-name = "SCM1_FSI0_DATA_EN"; - }; - pin_gpio_h7 { gpio-hog; gpios = ; -- cgit From 39cc9f037ca5ed417db29a57445e61a454216f49 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 27 Aug 2018 16:15:19 -0700 Subject: ARM: dts: aspeed-palmetto: Add LPC control node This adds the required LPC node with phandles to the reserved memory region and the mtd device. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index e6cfdf3c1a67..9aa1d4467453 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -31,6 +31,11 @@ reg = <0x5ee00000 0x00200000>; no-map; }; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x01000000>; /* 16MB */ + }; }; leds { @@ -190,6 +195,12 @@ status = "okay"; }; +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi>; +}; + &gpio { pin_func_mode0 { gpio-hog; -- cgit From 89b32a47e36ec6cd0243c1e573f46bb8d09d2fcb Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 4 Jul 2018 16:25:41 +1000 Subject: ARM: dts: aspeed: Enable VHUB on Romulus The Romulus USB bus is connected to the Power9's PCIe USB controller. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index cb14f14514d0..1c6c8cc03ea0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -283,3 +283,7 @@ &ibt { status = "okay"; }; + +&vhub { + status = "okay"; +}; -- cgit From 163d88c4bf92721c297ce828c96f4d85367208d9 Mon Sep 17 00:00:00 2001 From: Lei YU Date: Wed, 22 Aug 2018 15:47:28 +0800 Subject: ARM: dts: aspeed: romulus: Enable iio-hwmon-battery Add iio-hwmon-battery using adc channel 12 and enable adc to make adc running. This channel is used to read RTC battery voltage. Note with Romulus hardware design, it requires GPIOR3 to be pulled high to read the voltage, otherwise the reading is 0. When GPIOR3 is high, it consumes battery and impacts the battery life. So it is left for user space to toggle the GPIO when trying to read the voltage. Signed-off-by: Lei YU Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 1c6c8cc03ea0..76fe994f2ba4 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -85,6 +85,11 @@ linux,code = ; }; }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; }; &fmc { @@ -287,3 +292,7 @@ &vhub { status = "okay"; }; + +&adc { + status = "okay"; +}; -- cgit From 6d2e46885f3dfc8b32560f88c5f10cb1c93a3996 Mon Sep 17 00:00:00 2001 From: Matt Spinler Date: Fri, 12 Oct 2018 10:29:15 -0500 Subject: ARM: dts: aspeed: wspoon: Enable iio-hwmon battery The BMC can read the RTC battery voltage via ADC channel 12. Signed-off-by: Matt Spinler Reviewed-by: Lei YU Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 656036106001..ad54117c075e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -56,6 +56,11 @@ }; }; + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; + gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -583,3 +588,7 @@ &ibt { status = "okay"; }; + +&adc { + status = "okay"; +}; -- cgit From b54a5b19926cfb36e758130de466e2abfc11b9e6 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Thu, 8 Nov 2018 16:50:34 -0800 Subject: ARM: dts: Add Facebook BMC flash layout This is the layout used by Facebook BMC systems. It describes the fixed flash layout of a 32MB mtd device. Signed-off-by: Tao Ren Signed-off-by: Joel Stanley --- arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi | 42 ++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi diff --git a/arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi b/arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi new file mode 100644 index 000000000000..87bb8b576250 --- /dev/null +++ b/arch/arm/boot/dts/facebook-bmc-flash-layout.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0x60000>; + label = "u-boot"; + }; + + u-boot-env@60000 { + reg = <0x60000 0x20000>; + label = "env"; + }; + + fit@80000 { + reg = <0x80000 0x1b80000>; + label = "fit"; + }; + + /* + * "data0" partition is used by several Facebook BMC platforms + * as persistent data store. + */ + data0@1c00000 { + reg = <0x1c00000 0x400000>; + label = "data0"; + }; + + /* + * Although the master partition can be created by enabling + * MTD_PARTITIONED_MASTER option, below "flash0" partition is + * explicitly created to avoid breaking legacy applications. + */ + flash0@0 { + reg = <0x0 0x2000000>; + label = "flash0"; + }; +}; -- cgit From 76d0bbd8a4ef1b1256d49e082a61a33eb0b004c7 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Thu, 8 Nov 2018 16:50:46 -0800 Subject: ARM: dts: aspeed: Add Facebook Backpack-CMM BMC Add initial version of device tree file for Facebook Backpack CMM (Chasis Management Module) ast2500 BMC. Signed-off-by: Tao Ren Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts | 368 ++++++++++++++++++++++++++ 2 files changed, 369 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..ffac701a1ee8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1212,6 +1212,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ aspeed-bmc-arm-centriq2400-rep.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ + aspeed-bmc-facebook-cmm.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-intel-s2600wf.dtb \ aspeed-bmc-opp-lanyang.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts new file mode 100644 index 000000000000..9f194b5eeba4 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + model = "Facebook Backpack CMM BMC"; + compatible = "facebook,cmm-bmc", "aspeed,ast2500"; + + aliases { + /* + * Override the default uart aliases to avoid breaking + * the legacy applications. + */ + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart3; + serial3 = &uart4; + + /* + * Hardcode the bus number of i2c switches' channels to + * avoid breaking the legacy applications. + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; + i2c36 = &imux36; + i2c37 = &imux37; + i2c38 = &imux38; + i2c39 = &imux39; + }; + + chosen { + stdout-path = &uart1; + bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +/* + * Update reset type to "system" (full chip) to fix warm reboot hang issue + * when reset type is set to default ("soc", gated by reset mask registers). + */ +&wdt1 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +/* + * wdt2 is not used by Backpack CMM. + */ +&wdt2 { + status = "disabled"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "facebook-bmc-flash-layout.dtsi" + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_ndsr1_default + &pinctrl_ndtr1_default + &pinctrl_nrts1_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default + &pinctrl_ncts3_default + &pinctrl_ndcd3_default + &pinctrl_nri3_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac1 { + status = "okay"; + no-hw-checksum; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +/* + * I2C bus reserved for communication with COM-E. + */ +&i2c0 { + status = "okay"; +}; + +/* + * I2C bus to Line Cards and Fabric Cards. + */ +&i2c1 { + status = "okay"; + + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +/* + * I2C bus to Power Distribution Board. + */ +&i2c2 { + status = "okay"; + + i2c-switch@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux28: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux29: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux30: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux31: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +/* + * I2c bus connected with temperature sensors on CMM. + */ +&i2c3 { + status = "okay"; +}; + +/* + * I2C bus reserved for communication with COM-E. + */ +&i2c4 { + status = "okay"; +}; + +/* + * I2c bus connected with ADM1278. + */ +&i2c5 { + status = "okay"; +}; + +/* + * I2c bus connected with I/O Expander. + */ +&i2c6 { + status = "okay"; +}; + +/* + * I2c bus connected with I/O Expander and EPROMs. + */ +&i2c7 { + status = "okay"; +}; + +/* + * I2C bus to Fan Control Board. + */ +&i2c8 { + status = "okay"; + + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + + imux32: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux33: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux34: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux35: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux36: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux37: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux38: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux39: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +/* + * I2C bus to CMM CPLD. + */ +&i2c13 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; -- cgit From 3db6d3ba0863f46350969e76c1fa0fdb06b10f9f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 23 Nov 2018 13:31:36 +0100 Subject: arm64: tegra: Add display support on Tegra194 Tegra194 contains a display architecture very similar to that found on the Tegra186. One notable exception is that DSI is no longer a supported output. Instead there are four display controllers and four SORs (with a DPAUX associated to each of them) that can drive HDMI or DP. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 335 +++++++++++++++++++++++++++++++ 1 file changed, 335 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c2091bb16546..0e6d89c557b1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra194"; @@ -418,6 +419,340 @@ <0x0c3a0000 0x10000>; reg-names = "pmc", "wake", "aotag", "scratch", "misc"; }; + + host1x@13e00000 { + compatible = "nvidia,tegra194-host1x", "simple-bus"; + reg = <0x13e00000 0x10000>, + <0x13e10000 0x10000>; + reg-names = "hypervisor", "vm"; + interrupts = , + ; + clocks = <&bpmp TEGRA194_CLK_HOST1X>; + clock-names = "host1x"; + resets = <&bpmp TEGRA194_RESET_HOST1X>; + reset-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x15000000 0x15000000 0x01000000>; + + display-hub@15200000 { + compatible = "nvidia,tegra194-display", "simple-bus"; + resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, + <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, + <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, + <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, + <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, + <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, + <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; + reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", + "wgrp3", "wgrp4", "wgrp5"; + clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, + <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; + clock-names = "disp", "hub"; + status = "disabled"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x15200000 0x15200000 0x40000>; + + display@15200000 { + compatible = "nvidia,tegra194-dc"; + reg = <0x15200000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; + clock-names = "dc"; + resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; + reset-names = "dc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + + nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; + nvidia,head = <0>; + }; + + display@15210000 { + compatible = "nvidia,tegra194-dc"; + reg = <0x15210000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; + clock-names = "dc"; + resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; + reset-names = "dc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; + + nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; + nvidia,head = <1>; + }; + + display@15220000 { + compatible = "nvidia,tegra194-dc"; + reg = <0x15220000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; + clock-names = "dc"; + resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; + reset-names = "dc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; + + nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; + nvidia,head = <2>; + }; + + display@15230000 { + compatible = "nvidia,tegra194-dc"; + reg = <0x15230000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; + clock-names = "dc"; + resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; + reset-names = "dc"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; + + nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; + nvidia,head = <3>; + }; + }; + + dpaux0: dpaux@155c0000 { + compatible = "nvidia,tegra194-dpaux"; + reg = <0x155c0000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_DPAUX>, + <&bpmp TEGRA194_CLK_PLLDP>; + clock-names = "dpaux", "parent"; + resets = <&bpmp TEGRA194_RESET_DPAUX>; + reset-names = "dpaux"; + status = "disabled"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + + state_dpaux0_aux: pinmux-aux { + groups = "dpaux-io"; + function = "aux"; + }; + + state_dpaux0_i2c: pinmux-i2c { + groups = "dpaux-io"; + function = "i2c"; + }; + + state_dpaux0_off: pinmux-off { + groups = "dpaux-io"; + function = "off"; + }; + + i2c-bus { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dpaux1: dpaux@155d0000 { + compatible = "nvidia,tegra194-dpaux"; + reg = <0x155d0000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_DPAUX1>, + <&bpmp TEGRA194_CLK_PLLDP>; + clock-names = "dpaux", "parent"; + resets = <&bpmp TEGRA194_RESET_DPAUX1>; + reset-names = "dpaux"; + status = "disabled"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + + state_dpaux1_aux: pinmux-aux { + groups = "dpaux-io"; + function = "aux"; + }; + + state_dpaux1_i2c: pinmux-i2c { + groups = "dpaux-io"; + function = "i2c"; + }; + + state_dpaux1_off: pinmux-off { + groups = "dpaux-io"; + function = "off"; + }; + + i2c-bus { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dpaux2: dpaux@155e0000 { + compatible = "nvidia,tegra194-dpaux"; + reg = <0x155e0000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_DPAUX2>, + <&bpmp TEGRA194_CLK_PLLDP>; + clock-names = "dpaux", "parent"; + resets = <&bpmp TEGRA194_RESET_DPAUX2>; + reset-names = "dpaux"; + status = "disabled"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + + state_dpaux2_aux: pinmux-aux { + groups = "dpaux-io"; + function = "aux"; + }; + + state_dpaux2_i2c: pinmux-i2c { + groups = "dpaux-io"; + function = "i2c"; + }; + + state_dpaux2_off: pinmux-off { + groups = "dpaux-io"; + function = "off"; + }; + + i2c-bus { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dpaux3: dpaux@155f0000 { + compatible = "nvidia,tegra194-dpaux"; + reg = <0x155f0000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_DPAUX3>, + <&bpmp TEGRA194_CLK_PLLDP>; + clock-names = "dpaux", "parent"; + resets = <&bpmp TEGRA194_RESET_DPAUX3>; + reset-names = "dpaux"; + status = "disabled"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + + state_dpaux3_aux: pinmux-aux { + groups = "dpaux-io"; + function = "aux"; + }; + + state_dpaux3_i2c: pinmux-i2c { + groups = "dpaux-io"; + function = "i2c"; + }; + + state_dpaux3_off: pinmux-off { + groups = "dpaux-io"; + function = "off"; + }; + + i2c-bus { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + sor0: sor@15b00000 { + compatible = "nvidia,tegra194-sor"; + reg = <0x15b00000 0x40000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, + <&bpmp TEGRA194_CLK_SOR0_OUT>, + <&bpmp TEGRA194_CLK_PLLD>, + <&bpmp TEGRA194_CLK_PLLDP>, + <&bpmp TEGRA194_CLK_SOR_SAFE>, + <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; + clock-names = "sor", "out", "parent", "dp", "safe", + "pad"; + resets = <&bpmp TEGRA194_RESET_SOR0>; + reset-names = "sor"; + pinctrl-0 = <&state_dpaux0_aux>; + pinctrl-1 = <&state_dpaux0_i2c>; + pinctrl-2 = <&state_dpaux0_off>; + pinctrl-names = "aux", "i2c", "off"; + status = "disabled"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + nvidia,interface = <0>; + }; + + sor1: sor@15b40000 { + compatible = "nvidia,tegra194-sor"; + reg = <0x155c0000 0x40000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, + <&bpmp TEGRA194_CLK_SOR1_OUT>, + <&bpmp TEGRA194_CLK_PLLD2>, + <&bpmp TEGRA194_CLK_PLLDP>, + <&bpmp TEGRA194_CLK_SOR_SAFE>, + <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; + clock-names = "sor", "out", "parent", "dp", "safe", + "pad"; + resets = <&bpmp TEGRA194_RESET_SOR1>; + reset-names = "sor"; + pinctrl-0 = <&state_dpaux1_aux>; + pinctrl-1 = <&state_dpaux1_i2c>; + pinctrl-2 = <&state_dpaux1_off>; + pinctrl-names = "aux", "i2c", "off"; + status = "disabled"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + nvidia,interface = <1>; + }; + + sor2: sor@15b80000 { + compatible = "nvidia,tegra194-sor"; + reg = <0x15b80000 0x40000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, + <&bpmp TEGRA194_CLK_SOR2_OUT>, + <&bpmp TEGRA194_CLK_PLLD3>, + <&bpmp TEGRA194_CLK_PLLDP>, + <&bpmp TEGRA194_CLK_SOR_SAFE>, + <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; + clock-names = "sor", "out", "parent", "dp", "safe", + "pad"; + resets = <&bpmp TEGRA194_RESET_SOR2>; + reset-names = "sor"; + pinctrl-0 = <&state_dpaux2_aux>; + pinctrl-1 = <&state_dpaux2_i2c>; + pinctrl-2 = <&state_dpaux2_off>; + pinctrl-names = "aux", "i2c", "off"; + status = "disabled"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + nvidia,interface = <2>; + }; + + sor3: sor@15bc0000 { + compatible = "nvidia,tegra194-sor"; + reg = <0x15bc0000 0x40000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, + <&bpmp TEGRA194_CLK_SOR3_OUT>, + <&bpmp TEGRA194_CLK_PLLD4>, + <&bpmp TEGRA194_CLK_PLLDP>, + <&bpmp TEGRA194_CLK_SOR_SAFE>, + <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; + clock-names = "sor", "out", "parent", "dp", "safe", + "pad"; + resets = <&bpmp TEGRA194_RESET_SOR3>; + reset-names = "sor"; + pinctrl-0 = <&state_dpaux3_aux>; + pinctrl-1 = <&state_dpaux3_i2c>; + pinctrl-2 = <&state_dpaux3_off>; + pinctrl-names = "aux", "i2c", "off"; + status = "disabled"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + nvidia,interface = <3>; + }; + }; }; sysram@40000000 { -- cgit From 8d424ec221d0b72f316be04d10beb59fda6868bd Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 23 Nov 2018 13:31:37 +0100 Subject: arm64: tegra: Add VIC support on Tegra194 Tegra194 has a version of VIC that is very similar to that on Tegra186. Add the device tree node for it that is enabled by default. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 0e6d89c557b1..0ce8efb65ba4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -521,6 +521,18 @@ }; }; + vic@15340000 { + compatible = "nvidia,tegra194-vic"; + reg = <0x15340000 0x00040000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_VIC>; + clock-names = "vic"; + resets = <&bpmp TEGRA194_RESET_VIC>; + reset-names = "vic"; + + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; + }; + dpaux0: dpaux@155c0000 { compatible = "nvidia,tegra194-dpaux"; reg = <0x155c0000 0x10000>; -- cgit From 33c038e4b5adf0c66877e757bdc081fc3f54d2ac Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 23 Nov 2018 13:31:38 +0100 Subject: arm64: tegra: Enable HDMI on P2972-0000 Add the 5V HDMI regulator and hook up the VDD_1V0 and VDD_1V8HS supplies from the PMIC to the display block. Also enable the display hub which is responsible for instantiating the display controllers. Finally, enable the third SOR that drives the TMDS signals to the HDMI connector. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 15 +++++++++++-- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 26 ++++++++++++++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 57d3f00464ce..204a207ff4bd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -163,7 +163,7 @@ in-ldo4-6-supply = <&vdd_5v0_sys>; in-ldo7-8-supply = <&vdd_1v8ls>; - sd0 { + vdd_1v0: sd0 { regulator-name = "VDD_1V0"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -171,7 +171,7 @@ regulator-boot-on; }; - sd1 { + vdd_1v8hs: sd1 { regulator-name = "VDD_1V8HS"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -262,5 +262,16 @@ regulator-always-on; regulator-boot-on; }; + + vdd_hdmi: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + + regulator-name = "VDD_5V0_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index d4cd241b7666..c781f28d1cc4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -13,9 +13,35 @@ status = "okay"; }; + ddc: i2c@31c0000 { + status = "okay"; + }; + pwm@c340000 { status = "okay"; }; + + host1x@13e00000 { + display-hub@15200000 { + status = "okay"; + }; + + dpaux@155e0000 { + status = "okay"; + }; + + sor@15b80000 { + status = "okay"; + + avdd-io-supply = <&vdd_1v0>; + vdd-pll-supply = <&vdd_1v8hs>; + hdmi-supply = <&vdd_hdmi>; + + nvidia,ddc-i2c-bus = <&ddc>; + nvidia,hpd-gpio = <&gpio TEGRA194_MAIN_GPIO(M, 2) + GPIO_ACTIVE_LOW>; + }; + }; }; fan { -- cgit From 686ba00900bb2bd1137bd19c8d22a6b0f95f0aba Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 23 Nov 2018 13:18:38 +0100 Subject: arm64: tegra: Add thermal zones on Tegra194 The NVIDIA Tegra194 SoC defines six thermal zones. Define all of them in device tree. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 39 ++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 0ce8efb65ba4..4c0067ced6c7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra194"; @@ -878,6 +879,44 @@ method = "smc"; }; + thermal-zones { + cpu { + thermal-sensors = <&{/bpmp/thermal} + TEGRA194_BPMP_THERMAL_ZONE_CPU>; + status = "disabled"; + }; + + gpu { + thermal-sensors = <&{/bpmp/thermal} + TEGRA194_BPMP_THERMAL_ZONE_GPU>; + status = "disabled"; + }; + + aux { + thermal-sensors = <&{/bpmp/thermal} + TEGRA194_BPMP_THERMAL_ZONE_AUX>; + status = "disabled"; + }; + + pllx { + thermal-sensors = <&{/bpmp/thermal} + TEGRA194_BPMP_THERMAL_ZONE_PLLX>; + status = "disabled"; + }; + + ao { + thermal-sensors = <&{/bpmp/thermal} + TEGRA194_BPMP_THERMAL_ZONE_AO>; + status = "disabled"; + }; + + tj { + thermal-sensors = <&{/bpmp/thermal} + TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; + status = "disabled"; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = Date: Fri, 23 Nov 2018 13:18:39 +0100 Subject: arm64: tegra: p2972: Enable the CPU, GPU and AUX thermal zones Enable these thermal zones to be able to monitor their temperatures and control the fan to cool down the system if necessary. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 91 +++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index c781f28d1cc4..2223b2b49b2d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -44,8 +44,97 @@ }; }; - fan { + fan: fan { compatible = "pwm-fan"; pwms = <&pwm4 0 45334>; + + cooling-levels = <0 64 128 255>; + cooling-min-state = <0>; + cooling-max-state = <3>; + #cooling-cells = <2>; + }; + + thermal-zones { + cpu { + polling-delay = <0>; + polling-delay-passive = <500>; + status = "okay"; + + trips { + cpu_trip_critical: critical { + temperature = <96500>; + hysteresis = <0>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <70000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active: active { + temperature = <50000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_passive: passive { + temperature = <30000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu-critical { + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_critical>; + }; + + cpu-hot { + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_hot>; + }; + + cpu-active { + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active>; + }; + + cpu-passive { + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; + }; + + gpu { + polling-delay = <0>; + polling-delay-passive = <500>; + status = "okay"; + + trips { + gpu_alert0: critical { + temperature = <99000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aux { + polling-delay = <0>; + polling-delay-passive = <500>; + status = "okay"; + + trips { + aux_alert0: critical { + temperature = <90000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; }; }; -- cgit From 6f13f10b3bbfed3b29c812f0f65bef802ce05e3c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 28 Nov 2018 17:47:25 +0100 Subject: arm64: tegra: Fix power key interrupt type on Jetson TX2 In order for the correct interrupt type to be configured, the event action for the power key needs to be "asserted". Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index bd5305a634b1..9fc577a1ec44 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -2,6 +2,7 @@ /dts-v1/; #include +#include #include "tegra186-p3310.dtsi" @@ -121,6 +122,7 @@ linux,input-type = ; linux,code = ; debounce-interval = <10>; + wakeup-event-action = ; wakeup-source; }; -- cgit From 32e66e46af0b343d892cb74020a7671508d90a61 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 28 Nov 2018 18:19:54 +0100 Subject: arm64: tegra: Enable PMC wake events on Tegra186 Wake events are a feature that allows the interrupt and GPIO controllers to be powered off as part of system sleep. The PMC which is always on is monitoring these wake events and can power up subsequent controllers as necessary to process them. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 2f3c8e29520d..6b7528a670b1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -407,7 +407,7 @@ #interrupt-cells = <2>; }; - pmc@c360000 { + pmc: pmc@c360000 { compatible = "nvidia,tegra186-pmc"; reg = <0 0x0c360000 0 0x10000>, <0 0x0c370000 0 0x10000>, @@ -415,6 +415,9 @@ <0 0x0c390000 0 0x10000>; reg-names = "pmc", "wake", "aotag", "scratch"; + #interrupt-cells = <2>; + interrupt-controller; + sdmmc1_3v3: sdmmc1-3v3 { pins = "sdmmc1-hv"; power-source = ; -- cgit From 9733a251728ee5cf290840d99fba84990b5aae4e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 28 Nov 2018 17:49:40 +0100 Subject: arm64: tegra: Add RTC support on Tegra186 The RTC on Tegra186 is very similar to the RTC on earlier generations. One notable exception is that the source clock is now the 32 kHz clock instead of a dedicated RTC clock and the RTC alarm is a wake event and can be used to wake the system from sleep. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 6b7528a670b1..4c79778d80db 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -395,6 +395,16 @@ status = "disabled"; }; + rtc: rtc@c2a0000 { + compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; + reg = <0 0x0c2a0000 0 0x10000>; + interrupt-parent = <&pmc>; + interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA186_CLK_CLK_32K>; + clock-names = "rtc"; + status = "disabled"; + }; + gpio_aon: gpio@c2f0000 { compatible = "nvidia,tegra186-gpio-aon"; reg-names = "security", "gpio"; -- cgit From 127d82670174f44644ede9dd940bc53ca50c7c65 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 28 Nov 2018 17:49:41 +0100 Subject: arm64: tegra: p3310: Enable on-die RTC The on-die RTC isn't hooked up to a backup battery, so it isn't useful to track time across reboots, but as long as power remains enabled, it keeps track of time accurately and can be used to wake the system from sleep, for example. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 13f57fff1477..b539561e7877 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -124,6 +124,10 @@ status = "okay"; }; + rtc@c2a0000 { + status = "okay"; + }; + pmc@c360000 { nvidia,invert-interrupt; }; -- cgit From 38ecf1e5f47167ae48ef31a1fd1fbbe9562eff2b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 28 Nov 2018 18:19:55 +0100 Subject: arm64: tegra: Enable PMC wake events on Tegra194 Wake events are a feature that allows the interrupt and GPIO controllers to be powered off as part of system sleep. The PMC which is always on is monitoring these wake events and can power up subsequent controllers as necessary to process them. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 4c0067ced6c7..a09ca098eb4d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -411,7 +411,7 @@ #pwm-cells = <2>; }; - pmc@c360000 { + pmc: pmc@c360000 { compatible = "nvidia,tegra194-pmc"; reg = <0x0c360000 0x10000>, <0x0c370000 0x10000>, @@ -419,6 +419,9 @@ <0x0c390000 0x10000>, <0x0c3a0000 0x10000>; reg-names = "pmc", "wake", "aotag", "scratch", "misc"; + + #interrupt-cells = <2>; + interrupt-controller; }; host1x@13e00000 { -- cgit From 37e5a31df5431cff64264f702c191e47a2ea419e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 28 Nov 2018 17:50:49 +0100 Subject: arm64: tegra: Add RTC support on Tegra194 The RTC on Tegra194 is very similar to the RTC on earlier generations. One notable exception is that the source clock is now the 32 kHz clock instead of a dedicated RTC clock and the RTC alarm is a wake event and can be used to wake the system from sleep. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index a09ca098eb4d..afb3597e05e4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -399,6 +399,16 @@ status = "disabled"; }; + rtc: rtc@c2a0000 { + compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; + reg = <0x0c2a0000 0x10000>; + interrupt-parent = <&pmc>; + interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA194_CLK_CLK_32K>; + clock-names = "rtc"; + status = "disabled"; + }; + pwm4: pwm@c340000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; -- cgit From 3ae50e8331dae745e5c91bc73df0aa63488f0d07 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 28 Nov 2018 17:50:50 +0100 Subject: arm64: tegra: p2888: Enable on-die RTC The on-die RTC isn't hooked up to a backup battery, so it isn't useful to track time across reboots, but as long as power remains enabled, it keeps track of time accurately and can be used to wake the system from sleep, for example. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 204a207ff4bd..de70b5ff7fe6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -66,6 +66,10 @@ vmmc-supply = <&vdd_emmc_3v3>; }; + rtc@c2a0000 { + status = "okay"; + }; + pmc@c360000 { nvidia,invert-interrupt; }; -- cgit From 4d286331bdee4bb08b66531989d7c86d8eb7f891 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 28 Nov 2018 18:19:56 +0100 Subject: arm64: tegra: Add AON GPIO controller on Tegra194 The AON GPIO controller is in an always-on power partition and typically provides pins for functions that need to always work, such as the power key for example. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index afb3597e05e4..2cc22ce8efca 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -409,6 +409,21 @@ status = "disabled"; }; + gpio_aon: gpio@c2f0000 { + compatible = "nvidia,tegra194-gpio-aon"; + reg-names = "security", "gpio"; + reg = <0xc2f0000 0x1000>, + <0xc2f1000 0x1000>; + interrupts = , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + pwm4: pwm@c340000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; -- cgit From e47ac50885f530717946a41dd3aa0d9c26c6f154 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 28 Nov 2018 18:19:57 +0100 Subject: arm64: tegra: Add gpio-keys on Jetson Xavier The power and force recovery buttons found on Jetson Xavier are hooked up to two Tegra GPIOs. The power button can also function as a wake-up source. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 2223b2b49b2d..274937042c4a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; +#include +#include + #include "tegra194-p2888.dtsi" / { @@ -54,6 +57,30 @@ #cooling-cells = <2>; }; + gpio-keys { + compatible = "gpio-keys"; + + force-recovery { + label = "Force Recovery"; + gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0) + GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + }; + + power { + label = "Power"; + gpios = <&gpio_aon TEGRA194_AON_GPIO(EE, 4) + GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + thermal-zones { cpu { polling-delay = <0>; -- cgit From 8b457812f54b2baa70c15b8e7c8902c4c07b6589 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 28 Nov 2018 18:26:34 +0100 Subject: arm64: tegra: Add temperature sensor on P2888 The P2888 processor module contains a TI TMP451 temperature sensor with two channels. These are used to measure the temperatures at different locations on the module. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index de70b5ff7fe6..22a1c267aed9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -248,6 +248,17 @@ }; }; }; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; }; }; -- cgit From c9cbfd623d8bcfbbe9a37be13b247fa0ce8e92e7 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Mon, 3 Dec 2018 15:31:15 +0100 Subject: ARM: dts: exynos: Add opp-suspend to DMC and leftbus devfreq OPPs on Exynos4 Mark as opp-suspend required devfreq Operating Performance Points to fix resuming issues on Exynos 4 boards. The patch is based on earlier work by Tobias Jakobi. Suggested-by: Tobias Jakobi Suggested-by: Chanwoo Choi Reviewed-by: Chanwoo Choi Signed-off-by: Lukasz Luba Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210.dtsi | 2 ++ arch/arm/boot/dts/exynos4412.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 32ccb5fa14f1..b491c345b2e8 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -298,6 +298,7 @@ opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-microvolt = <1150000>; + opp-suspend; }; }; @@ -367,6 +368,7 @@ }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; + opp-suspend; }; }; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index cd04bb4aea5f..26ad6ab3c6af 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -432,6 +432,7 @@ opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-microvolt = <1050000>; + opp-suspend; }; }; @@ -520,6 +521,7 @@ opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-microvolt = <1000000>; + opp-suspend; }; }; -- cgit From f491ac32c618057acc721de0db50df1aef552f33 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 2 Dec 2018 12:38:48 +0100 Subject: ARM: mmp2: DT: be compatible with mrvl,mmp2 There are more boards that can work with mmp2-dt than just Brownstone. The OLPC XO-1.75 device tree root is compatible with "mrvl,mmp2" only. The "mrvl,mmp2-brownstone" string is safe to remove: the Brownstone device tree contains the "mrvl,mmp2" compatible string too. Signed-off-by: Lubomir Rintel Signed-off-by: Olof Johansson --- arch/arm/mach-mmp/mmp2-dt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c index 0341359b24a4..81232ecf08be 100644 --- a/arch/arm/mach-mmp/mmp2-dt.c +++ b/arch/arm/mach-mmp/mmp2-dt.c @@ -31,7 +31,7 @@ static void __init mmp_init_time(void) } static const char *const mmp2_dt_board_compat[] __initconst = { - "mrvl,mmp2-brownstone", + "mrvl,mmp2", NULL, }; -- cgit From ad8044f87c0b53ee45f5d367584eefb222a06883 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 30 Nov 2018 18:55:43 +0100 Subject: ARM: dts: pxa3xx: Add Raumfeld DTS files This patch adds a set of DTS files that support all PXA3xx based Raumfeld audio hardware devices. Common nodes are factored out into 'common' and 'tuneable-clock' include files to keep the top-level DTS files smaller. Signed-off-by: Daniel Mack [Robert: Reordered Makefile in alphabetical order] Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/Makefile | 7 + arch/arm/boot/dts/pxa300-raumfeld-common.dtsi | 405 +++++++++++++++++++++ arch/arm/boot/dts/pxa300-raumfeld-connector.dts | 73 ++++ arch/arm/boot/dts/pxa300-raumfeld-controller.dts | 266 ++++++++++++++ arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts | 11 + arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts | 11 + arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts | 137 +++++++ arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts | 11 + .../boot/dts/pxa300-raumfeld-tuneable-clock.dtsi | 85 +++++ 9 files changed, 1006 insertions(+) create mode 100644 arch/arm/boot/dts/pxa300-raumfeld-common.dtsi create mode 100644 arch/arm/boot/dts/pxa300-raumfeld-connector.dts create mode 100644 arch/arm/boot/dts/pxa300-raumfeld-controller.dts create mode 100644 arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts create mode 100644 arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts create mode 100644 arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts create mode 100644 arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts create mode 100644 arch/arm/boot/dts/pxa300-raumfeld-tuneable-clock.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..3fc3412ea55d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -778,6 +778,13 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \ owl-s500-sparky.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb +dtb-$(CONFIG_ARCH_PXA) += \ + pxa300-raumfeld-connector.dtb \ + pxa300-raumfeld-controller.dtb \ + pxa300-raumfeld-speaker-l.dtb \ + pxa300-raumfeld-speaker-m.dtb \ + pxa300-raumfeld-speaker-one.dtb \ + pxa300-raumfeld-speaker-s.dtb dtb-$(CONFIG_ARCH_OXNAS) += \ ox810se-wd-mbwe.dtb \ ox820-cloudengines-pogoplug-series-3.dtb diff --git a/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi new file mode 100644 index 000000000000..8ac24e3c8513 --- /dev/null +++ b/arch/arm/boot/dts/pxa300-raumfeld-common.dtsi @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "pxa3xx.dtsi" +#include +#include +#include + +/ { + /* Will be overridden by bootloader */ + hw-revision = <0>; + + chosen { + bootargs = "root=ubi0:RootFS rootfstype=ubifs rw ubi.mtd=3"; + stdout-path = &ffuart; + }; + + memory { + device_type = "memory"; + reg = <0xa0000000 0x8000000>; /* 128 MB */ + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3-fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8-fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_va_5v0: regulator-va-5v0 { + compatible = "regulator-fixed"; + regulator-name = "va-5v0-fixed-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 124 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + ssp_dai0: ssp-dai0 { + compatible = "mrvl,pxa-ssp-dai"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp0_dai_pins>; + port = <&ssp1>; + #sound-dai-cells = <0>; + dmas = <&pdma 13 3 + &pdma 14 3>; + dma-names = "rx", "tx"; + clock-names = "extclk"; + }; + + ssp_dai1: ssp-dai1 { + compatible = "mrvl,pxa-ssp-dai"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp1_dai_pins>; + port = <&ssp2>; + #sound-dai-cells = <0>; + dmas = <&pdma 15 3 + &pdma 16 3>; + dma-names = "rx", "tx"; + clock-names = "extclk"; + }; + + spi: spi { + compatible = "spi-gpio"; + #address-cells = <0x1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>; + gpio-sck = <&gpio 95 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio 98 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio 97 GPIO_ACTIVE_HIGH>; + cs-gpios = < + &gpio 34 GPIO_ACTIVE_HIGH + &gpio 125 GPIO_ACTIVE_HIGH + &gpio 96 GPIO_ACTIVE_HIGH + >; + num-chipselects = <3>; + + dac: dac@2 { + compatible = "ti,dac7512"; + reg = <2>; + spi-max-frequency = <1000000>; + vcc-supply = <®_3v3>; + }; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + on-off { + label = "on_off button"; + gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + rescue-boot { + label = "rescue boot button"; + gpios = <&gpio 115 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + + setup { + label = "setup"; + gpios = <&gpio 119 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + rotary: rotary-encoder { + compatible = "rotary-encoder"; + gpios = < + &gpio 19 GPIO_ACTIVE_LOW + &gpio 20 GPIO_ACTIVE_HIGH + >; + linux,axis = ; + rotary-encoder,relative-axis; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_a &led_pins_b>; + + left { + label = "raumfeld:1"; + gpios = <&gpio 36 GPIO_ACTIVE_LOW>; + }; + + right { + label = "raumfeld:2"; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + }; + }; + + poweroff { + compatible = "gpio-poweroff"; + pinctrl-names = "default"; + pinctrl-0 = <&poweroff_pins>; + gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + }; + + mmc0_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pwrseq_pins>; + reset-gpios = < + &gpio 113 GPIO_ACTIVE_LOW /* W2W_RESET */ + &gpio 114 GPIO_ACTIVE_LOW /* W2W_PDN */ + >; + }; + + ethernet: ethernet@10000000 { + compatible = "smsc,lan9115"; + pinctrl-names = "default"; + pinctrl-0 = <&smsc_pins &smsc_bus_pins>; + reg = <0x10000000 0x100000>; + phy-mode = "mii"; + interrupt-parent = <&gpio>; + interrupts = <40 IRQ_TYPE_EDGE_FALLING>; + vdd33a-supply = <®_3v3>; + vddvario-supply = <®_1v8>; + reset-gpios = <&gpio 39 GPIO_ACTIVE_LOW>; + reg-io-width = <4>; + smsc,save-mac-address; + smsc,irq-push-pull; + }; +}; + +&ffuart { + status = "okay"; +}; + +&pwri2c { + status = "okay"; + + max8660: regulator@34 { + compatible = "maxim,max8660"; + reg = <0x34>; + + regulators { + regulator-v3 { + regulator-compatible= "V3(DCDC)"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1800000>; + }; + + regulator-v4 { + regulator-compatible= "V4(DCDC)"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1800000>; + }; + + regulator-v5 { + regulator-compatible= "V5(LDO)"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2000000>; + }; + + reg_vcc_sdio: regulator-v6 { + regulator-compatible= "V6(LDO)"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + regulator-v7 { + regulator-compatible= "V7(LDO)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&pxai2c1 { + status = "okay"; + mrvl,i2c-fast-mode; + pinctrl-names = "default"; + pinctrl-0 = <&pxai2c1_pins>; +}; + +&ssp1 { + status = "okay"; +}; + +&ssp2 { + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + nand-rb = <0>; + nand-ecc-mode = "hw"; + marvell,nand-keep-config; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Bootloader"; + reg = <0x0000000 0xa0000>; + read-only; + }; + + partition@a0000 { + label = "BootloaderEnvironment"; + reg = <0x0a0000 0x20000>; + }; + + partition@c0000 { + label = "BootloaderSplashScreen"; + reg = <0x0c0000 0x60000>; + }; + + partition@120000 { + label = "UBI"; + reg = <0x120000 0x7ee0000>; + }; + }; + }; +}; + +&usb0 { + status = "okay"; + marvell,enable-port1; + marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */ + pinctrl-names = "default"; + pinctrl-0 = <&pxa3xx_ohci_pins>; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + pxa-mmc,detect-delay-ms = <200>; + vmmc-supply = <®_vcc_sdio>; + mmc-pwrseq = <&mmc0_pwrseq>; + non-removable; + bus-width = <4>; +}; + +&pinctrl { + poweroff_pins: poweroff-pins { + pinctrl-single,pins = ; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; + + led_pins_a: led-pins-a { + pinctrl-single,pins = ; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + led_pins_b: led-pins-b { + pinctrl-single,pins = ; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_DRIVE_HIGH); + }; + + pxai2c1_pins: pxai2c1-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(21) MFP_AF1 /* I2C_SCL */ + MFP_PIN_PXA300(22) MFP_AF1 /* I2C_SDA */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_HIGH); + }; + + gpio_keys_pins: gpio-keys-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(14) MFP_AF0 /* SCK */ + MFP_PIN_PXA300(115) MFP_AF0 /* MOSI */ + MFP_PIN_PXA300(119) MFP_AF0 /* MISO */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; + + spi_pins: spi-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(95) MFP_AF0 /* SCK */ + MFP_PIN_PXA300(97) MFP_AF0 /* MOSI */ + MFP_PIN_PXA300(98) MFP_AF0 /* MISO */ + MFP_PIN_PXA300(34) MFP_AF0 /* CS#0 */ + MFP_PIN_PXA300(125) MFP_AF0 /* CS#1 */ + MFP_PIN_PXA300(96) MFP_AF0 /* CS#2 */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + pxa3xx_ohci_pins: pxa3xx-ohci-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300_2(0) MFP_AF1 /* USBHPEN */ + MFP_PIN_PXA300_2(1) MFP_AF1 /* USBHPWR */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + smsc_pins: smsc-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(39) MFP_AF0 /* RESET */ + MFP_PIN_PXA300(40) MFP_AF0 /* IRQ */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + smsc_bus_pins: smsc-bus-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(1) MFP_AF1 /* nCS2 */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; + + mmc0_pins: mmc0-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(3) MFP_AF4 /* MMC1_DAT0 */ + MFP_PIN_PXA300(4) MFP_AF4 /* MMC1_DAT1 */ + MFP_PIN_PXA300(5) MFP_AF4 /* MMC1_DAT2 */ + MFP_PIN_PXA300(6) MFP_AF4 /* MMC1_DAT3 */ + MFP_PIN_PXA300(7) MFP_AF4 /* MMC1_CLK */ + MFP_PIN_PXA300(8) MFP_AF4 /* MMC1_CMD */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_DRIVE_HIGH); + }; + + mmc0_pwrseq_pins: mmc0-pwrseq-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(113) MFP_AF0 /* W2W_RESET */ + MFP_PIN_PXA300(114) MFP_AF0 /* W2W_PDN */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; + + ssp0_dai_pins: ssp0-dai-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(85) MFP_AF1 /* SSP1_SCLK */ + MFP_PIN_PXA300(86) MFP_AF1 /* SSP1_FRM */ + MFP_PIN_PXA300(87) MFP_AF1 /* SSP1_TXD */ + MFP_PIN_PXA300(88) MFP_AF1 /* SSP1_RXD */ + MFP_PIN_PXA300(89) MFP_AF1 /* SSP1_EXTCLK */ + MFP_PIN_PXA300(90) MFP_AF1 /* SSP1_SYSCLK */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + ssp1_dai_pins: ssp1-dai-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(25) MFP_AF2 /* SSP2_SCLK */ + MFP_PIN_PXA300(26) MFP_AF2 /* SSP2_FRM */ + MFP_PIN_PXA300(27) MFP_AF2 /* SSP2_TXD */ + MFP_PIN_PXA300(29) MFP_AF2 /* SSP2_EXTCLK */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; +}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-connector.dts b/arch/arm/boot/dts/pxa300-raumfeld-connector.dts new file mode 100644 index 000000000000..3e9445419e39 --- /dev/null +++ b/arch/arm/boot/dts/pxa300-raumfeld-connector.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "pxa300-raumfeld-common.dtsi" +#include "pxa300-raumfeld-tuneable-clock.dtsi" + +/ { + model = "Raumfeld Connector (PXA3xx)"; + compatible = "raumfeld,raumfeld-connector-pxa303", "marvell,pxa300"; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Raumfeld Connector"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + format = "i2s"; + bitclock-master = <&dailink_master_analog>; + frame-master = <&dailink_master_analog>; + mclk-fs = <256>; + + dailink_master_analog: cpu { + sound-dai = <&ssp_dai0>; + }; + + codec { + sound-dai = <&cs4270>; + }; + }; + + simple-audio-card,dai-link@1 { + reg = <1>; + format = "i2s"; + bitclock-master = <&dailink_master_digital>; + frame-master = <&dailink_master_digital>; + mclk-fs = <256>; + + dailink_master_digital: cpu { + sound-dai = <&ssp_dai1>; + }; + + codec { + sound-dai = <&ak4104>; + }; + }; + }; +}; + +&ssp1 { + status = "okay"; +}; + +&ssp2 { + status = "okay"; +}; + +&spi { + ak4104: optical-transmitter@0 { + compatible = "asahi-kasei,ak4104"; + reg = <0>; + vdd-supply = <®_3v3>; + spi-max-frequency = <5000000>; + reset-gpios = <&gpio 38 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; +}; + +&rotary { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-controller.dts b/arch/arm/boot/dts/pxa300-raumfeld-controller.dts new file mode 100644 index 000000000000..65d825091f0d --- /dev/null +++ b/arch/arm/boot/dts/pxa300-raumfeld-controller.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "pxa300-raumfeld-common.dtsi" + +/ { + model = "Raumfeld Controller (PXA3xx)"; + compatible = "raumfeld,raumfeld-controller-pxa303", "marvell,pxa300"; + + reg_vbatt: regulator-vbatt { + compatible = "regulator-fixed"; + regulator-name = "vbatt-fixed-supply"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + lcd_supply: regulator-va-tft { + compatible = "regulator-fixed"; + regulator-name = "va-tft-fixed-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + onewire { + compatible = "w1-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&w1_pins>; + gpios = < + &gpio 126 GPIO_OPEN_DRAIN /* W1 I/O */ + &gpio 105 GPIO_ACTIVE_HIGH /* pullup */ + >; + + w1_ds2760: slave-ds2760 { + compatible = "maxim,ds2760"; + power-supplies = <&charger>; + }; + }; + + charger: charger { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio 101 GPIO_ACTIVE_LOW>; + }; + + /* + * One of the following two will be set to "okay" by the bootloader, + * depending on the hardware revision. + */ + backlight-controller-pwm { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; + pwms = <&pwm0 10000>; + power-supply = <®_vbatt>; + status = "disabled"; + + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <100>; + }; + + backlight-controller { + compatible = "lltc,lt3593"; + pinctrl-names = "default"; + pinctrl-0 = <<3593_pins>; + lltc,ctrl-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + led { + label = "backlight"; + default-state = "on"; + }; + }; +}; + +®_va_5v0 { + status = "disabled"; +}; + +ðernet { + status = "disabled"; +}; + +&leds { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&pwm0 { + status = "okay"; +}; + +&keys { + dock-detect { + label = "dock detect"; + gpios = <&gpio 116 GPIO_ACTIVE_HIGH>; + linux,code = ; + }; +}; + +&spi { + accelerometer@1 { + compatible = "st,lis302dl-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&lis302_pins>; + reg = <1>; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio>; + interrupts = <104 IRQ_TYPE_EDGE_FALLING>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <10>; + st,click-thresh-y = <10>; + st,click-thresh-z = <10>; + st,irq1-click; + st,irq2-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + }; +}; + +&lcdc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc_pins>; + lcd-supply = <&lcd_supply>; + + port { + lcdc_out: endpoint { + remote-endpoint = <&panel_in>; + bus-width = <16>; + }; + }; + + panel { + compatible = "sharp,lq043t3dx0-panel"; + display-timings { + native-mode = <&timing0>; + timing0: timing { + clock-frequency = <9009000>; + pixelclk-active = <0>; /* negative edge */ + hactive = <480>; + vactive = <272>; + hsync-len = <41>; + hback-porch = <2>; + hfront-porch = <1>; + vsync-len = <10>; + vback-porch = <3>; + vfront-porch = <1>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdc_out>; + }; + }; + }; +}; + +&gcu { + status = "okay"; +}; + +&pxai2c1 { + touchscreen@a { + compatible = "eeti,exc3000-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&eeti_ts_pins>; + reg = <0xa>; + interrupt-parent = <&gpio>; + interrupts = <32 IRQ_TYPE_EDGE_RISING>; + attn-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>; + touchscreen-inverted-y; + }; +}; + +&pinctrl { + lis302_pins: lis302-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(104) MFP_AF0 /* IRQ */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + eeti_ts_pins: eeti-ts-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(32) MFP_AF0 /* IRQ */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; + + lt3593_pins: lt3593-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(17) MFP_AF0 /* Backlight */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + pwm0_pins: pwm0-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(17) MFP_AF1 /* PWM */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + w1_pins: w1-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(126) MFP_AF0 /* PWM */ + MFP_PIN_PXA300(105) MFP_AF0 /* PWM */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; + + lcdc_pins: lcdc-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(54) MFP_AF1 /* LDD_0 */ + MFP_PIN_PXA300(55) MFP_AF1 /* LDD_1 */ + MFP_PIN_PXA300(56) MFP_AF1 /* LDD_2 */ + MFP_PIN_PXA300(57) MFP_AF1 /* LDD_3 */ + MFP_PIN_PXA300(58) MFP_AF1 /* LDD_4 */ + MFP_PIN_PXA300(59) MFP_AF1 /* LDD_5 */ + MFP_PIN_PXA300(60) MFP_AF1 /* LDD_6 */ + MFP_PIN_PXA300(61) MFP_AF1 /* LDD_7 */ + MFP_PIN_PXA300(62) MFP_AF1 /* LDD_8 */ + MFP_PIN_PXA300(63) MFP_AF1 /* LDD_9 */ + MFP_PIN_PXA300(64) MFP_AF1 /* LDD_10 */ + MFP_PIN_PXA300(65) MFP_AF1 /* LDD_11 */ + MFP_PIN_PXA300(66) MFP_AF1 /* LDD_12 */ + MFP_PIN_PXA300(67) MFP_AF1 /* LDD_13 */ + MFP_PIN_PXA300(68) MFP_AF1 /* LDD_14 */ + MFP_PIN_PXA300(69) MFP_AF1 /* LDD_15 */ + MFP_PIN_PXA300(70) MFP_AF1 /* LDD_16 */ + MFP_PIN_PXA300(71) MFP_AF1 /* LDD_17 */ + MFP_PIN_PXA300(72) MFP_AF1 /* LCD_FCLK */ + MFP_PIN_PXA300(73) MFP_AF1 /* LCD_LCLK */ + MFP_PIN_PXA300(74) MFP_AF1 /* LCD_PCLK */ + MFP_PIN_PXA300(75) MFP_AF1 /* LCD_BIAS */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; +}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts b/arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts new file mode 100644 index 000000000000..5a0f7f17856f --- /dev/null +++ b/arch/arm/boot/dts/pxa300-raumfeld-speaker-l.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "pxa300-raumfeld-common.dtsi" +#include "pxa300-raumfeld-tuneable-clock.dtsi" + +/ { + model = "Raumfeld Speaker L (PXA3xx)"; + compatible = "raumfeld,raumfeld-speaker-l-pxa303", "marvell,pxa300"; +}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts b/arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts new file mode 100644 index 000000000000..fa10d896282c --- /dev/null +++ b/arch/arm/boot/dts/pxa300-raumfeld-speaker-m.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "pxa300-raumfeld-common.dtsi" +#include "pxa300-raumfeld-tuneable-clock.dtsi" + +/ { + model = "Raumfeld Speaker M (PXA3xx)"; + compatible = "raumfeld,raumfeld-speaker-m-pxa303", "marvell,pxa300"; +}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts b/arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts new file mode 100644 index 000000000000..5f9e37585a28 --- /dev/null +++ b/arch/arm/boot/dts/pxa300-raumfeld-speaker-one.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "pxa300-raumfeld-common.dtsi" + +/ { + model = "Raumfeld Speaker One (PXA3xx)"; + compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300"; + + wm8782: wm8782 { + compatible = "wm8782"; + #sound-dai-cells = <0>; + Vdd-supply = <®_3v3>; + Vdda-supply = <®_va_5v0>; + }; + + xo_11mhz: oscillator-11mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + clock-accuracy = <100>; + }; + + xo_audio: clock-gate { + compatible = "gpio-gate-clock"; + pinctrlnames = "default"; + pinctrl-0 = <&xo_audio_pins>; + clocks = <&xo_11mhz>; + #clock-cells = <0>; + enable-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>; + }; + + reg_va_30v0: regulator-va-30v0 { + compatible = "regulator-fixed"; + regulator-name = "va-30v0-fixed-supply"; + regulator-min-microvolt = <30000000>; + regulator-max-microvolt = <30000000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Raumfeld Speaker"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + format = "i2s"; + bitclock-master = <&dailink_master_analog_out>; + frame-master = <&dailink_master_analog_out>; + mclk-fs = <256>; + + dailink_master_analog_out: cpu { + sound-dai = <&ssp_dai0>; + }; + + codec { + sound-dai = <&sta320>; + }; + }; + + simple-audio-card,dai-link@1 { + reg = <1>; + format = "i2s"; + bitclock-master = <&dailink_master_analog_in>; + frame-master = <&dailink_master_analog_in>; + mclk-fs = <256>; + + dailink_master_analog_in: cpu { + sound-dai = <&ssp_dai0>; + }; + + codec { + sound-dai = <&wm8782>; + }; + }; + }; +}; + +&ssp_dai0 { + clocks = <&xo_audio>; +}; + +&spi { + dac@2 { + compatible = "ti,dac7512"; + reg = <2>; + spi-max-frequency = <1000000>; + vcc-supply = <®_3v3>; + }; +}; + +&rotary { + status = "okay"; +}; + +&pxai2c1 { + sta320: codec@1a { + compatible = "st,sta32x"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&sta320_pins>; + clocks = <&xo_audio>; + clock-names = "xti"; + reset-gpios = <&gpio 120 GPIO_ACTIVE_HIGH>; + Vdda-supply = <®_3v3>; + Vdd3-supply = <®_3v3>; + Vcc-supply = <®_va_30v0>; + #sound-dai-cells = <0>; + st,thermal-warning-adjustment; + st,thermal-warning-recovery; + st,fault-detect-recovery; + st,drop-compensation-ns = <80>; + st,max-power-use-mpcc; + st,invalid-input-detect-mute; + /* 2 (half-bridge) and 1 (full-bridge) on-board power */ + st,output-conf = /bits/ 8 <0x1>; + st,needs_esd_watchdog; + }; +}; + +&pinctrl { + xo_audio_pins: xo-audio-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(111) MFP_AF0 /* ENABLE */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + sta320_pins: sta320-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(120) MFP_AF0 /* CODEC_RESET */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_FLOAT); + }; +}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts b/arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts new file mode 100644 index 000000000000..36e20cbf8704 --- /dev/null +++ b/arch/arm/boot/dts/pxa300-raumfeld-speaker-s.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "pxa300-raumfeld-common.dtsi" +#include "pxa300-raumfeld-tuneable-clock.dtsi" + +/ { + model = "Raumfeld Speaker S (PXA3xx)"; + compatible = "raumfeld,raumfeld-speaker-s-pxa303", "marvell,pxa300"; +}; diff --git a/arch/arm/boot/dts/pxa300-raumfeld-tuneable-clock.dtsi b/arch/arm/boot/dts/pxa300-raumfeld-tuneable-clock.dtsi new file mode 100644 index 000000000000..561483b93989 --- /dev/null +++ b/arch/arm/boot/dts/pxa300-raumfeld-tuneable-clock.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +/ { + xo_27mhz: oscillator-27mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-accuracy = <100>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Raumfeld Speaker"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + format = "i2s"; + bitclock-master = <&dailink_master_analog>; + frame-master = <&dailink_master_analog>; + mclk-fs = <256>; + + dailink_master_analog: cpu { + sound-dai = <&ssp_dai0>; + }; + + codec { + sound-dai = <&cs4270>; + }; + }; + }; +}; + +&ssp_dai0 { + clocks = <&max9485 MAX9485_CLKOUT1>; +}; + +&ssp_dai1 { + clocks = <&max9485 MAX9485_CLKOUT1>; +}; + +&pxai2c1 { + cs4270: codec@48 { + compatible = "cirrus,cs4270"; + pinctrl-names = "default"; + pinctrl-0 = <&cs4270_pins>; + reg = <0x48>; + va-supply = <®_va_5v0>; + vd-supply = <®_3v3>; + vlc-supply = <®_3v3>; + reset-gpios = <&gpio 120 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; + + max9485: clock-generator@63 { + compatible = "maxim,max9485"; + pinctrl-names = "default"; + pinctrl-0 = <&max9485_pins>; + reg = <0x63>; + vdd-supply = <®_3v3>; + clock-names = "xclk"; + clocks = <&xo_27mhz>; + reset-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>; + #clock-cells = <1>; + }; +}; + +&pinctrl { + cs4270_pins: cs4270-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(120) MFP_AF0 /* RESET */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; + + max9485_pins: max9485-pins { + pinctrl-single,pins = < + MFP_PIN_PXA300(111) MFP_AF0 /* RESET */ + >; + pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW); + }; +}; -- cgit From 40d9d791c97a9be2fa5b0a21b139c70980725e86 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:34:30 +0530 Subject: arm64: dts: msm8916: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 42e72a3164b9..47522362024a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -202,7 +202,10 @@ cooling-maps { map0 { trip = <&cpu_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -229,7 +232,10 @@ cooling-maps { map0 { trip = <&cpu_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; -- cgit From e7b6e5ccae5c7713eb63671914678e991d888130 Mon Sep 17 00:00:00 2001 From: Todor Tomov Date: Fri, 26 Oct 2018 18:37:15 +0300 Subject: arm64: dts: qcom: msm8916: Add IOMMU sub-node for VFE context bank Add IOMMU sub-node for VFE secure context bank. Signed-off-by: Todor Tomov Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 47522362024a..e34c7320e762 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -827,6 +827,13 @@ clock-names = "iface", "bus"; qcom,iommu-secure-id = <17>; + // vfe: + iommu-ctx@3000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + // mdp_0: iommu-ctx@4000 { compatible = "qcom,msm-iommu-v1-ns"; -- cgit From 58f479f90a7ca8675b5e3f60d8a9ea672484efc3 Mon Sep 17 00:00:00 2001 From: Todor Tomov Date: Fri, 26 Oct 2018 18:37:16 +0300 Subject: arm64: dts: qcom: msm8916: Add CAMSS support Add a node for the Camera Subsystem present on the Qualcomm MSM8916 SoC. Signed-off-by: Todor Tomov Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 80 +++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e34c7320e762..c5348c3da5a2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1445,6 +1445,86 @@ compatible = "venus-encoder"; }; }; + + camss: camss@1b00000 { + compatible = "qcom,msm8916-camss"; + reg = <0x1b0ac00 0x200>, + <0x1b00030 0x4>, + <0x1b0b000 0x200>, + <0x1b00038 0x4>, + <0x1b08000 0x100>, + <0x1b08400 0x100>, + <0x1b0a000 0x500>, + <0x1b00020 0x10>, + <0x1b10000 0x1000>; + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csid0", + "csid1", + "ispif", + "csi_clk_mux", + "vfe0"; + interrupts = , + , + , + , + , + ; + interrupt-names = "csiphy0", + "csiphy1", + "csid0", + "csid1", + "ispif", + "vfe0"; + power-domains = <&gcc VFE_GDSC>; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AHB_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>; + clock-names = "top_ahb", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe_ahb", + "vfe_axi"; + vdda-supply = <&pm8916_l2>; + iommus = <&apps_iommu 3>; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; smd { -- cgit From 1ab0fb75812628ada8001f76ba650277cd0534f3 Mon Sep 17 00:00:00 2001 From: Todor Tomov Date: Tue, 13 Nov 2018 11:19:12 +0200 Subject: arm64: dts: qcom: Add Camera Control Interface pinctrls Add pinctrls required for Camera Control Interface. Signed-off-by: Todor Tomov Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/qcom/msm8996-pins.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 390a2fa28514..990120cb3bf6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -689,4 +689,16 @@ bias-pull-up; }; }; + + cci0_default: cci0_default { + pinmux { + function = "cci_i2c"; + pins = "gpio29", "gpio30"; + }; + pinconf { + pins = "gpio29", "gpio30"; + drive-strength = <16>; + bias-disable; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index c5c42e94f387..d6a0a4aaaf22 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -495,4 +495,28 @@ bias-disable; }; }; + + cci0_default: cci0_default { + pinmux { + function = "cci_i2c"; + pins = "gpio17", "gpio18"; + }; + pinconf { + pins = "gpio17", "gpio18"; + drive-strength = <16>; + bias-disable; + }; + }; + + cci1_default: cci1_default { + pinmux { + function = "cci_i2c"; + pins = "gpio19", "gpio20"; + }; + pinconf { + pins = "gpio19", "gpio20"; + drive-strength = <16>; + bias-disable; + }; + }; }; -- cgit From acd48330e96fa2aa9ae4caecdee49d180a818f0f Mon Sep 17 00:00:00 2001 From: Todor Tomov Date: Tue, 13 Nov 2018 11:19:13 +0200 Subject: arm64: dts: qcom: Add pinctrls for camera sensors Add pinctrls required for camera sensors: - power down signal; - reset signal; - camera external clock. Signed-off-by: Todor Tomov Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 64 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/msm8996-pins.dtsi | 96 ++++++++++++++++++++++++++++++ 2 files changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 990120cb3bf6..aa9a0ffedfa9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -701,4 +701,68 @@ bias-disable; }; }; + + camera_front_default: camera_front_default { + pinmux_pwdn { + function = "gpio"; + pins = "gpio33"; + }; + pinconf_pwdn { + pins = "gpio33"; + drive-strength = <16>; + bias-disable; + }; + + pinmux_rst { + function = "gpio"; + pins = "gpio28"; + }; + pinconf_rst { + pins = "gpio28"; + drive-strength = <16>; + bias-disable; + }; + + pinmux_mclk1 { + function = "cam_mclk1"; + pins = "gpio27"; + }; + pinconf_mclk1 { + pins = "gpio27"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera_rear_default: camera_rear_default { + pinmux_pwdn { + function = "gpio"; + pins = "gpio34"; + }; + pinconf_pwdn { + pins = "gpio34"; + drive-strength = <16>; + bias-disable; + }; + + pinmux_rst { + function = "gpio"; + pins = "gpio35"; + }; + pinconf_rst { + pins = "gpio35"; + drive-strength = <16>; + bias-disable; + }; + + pinmux_mclk0 { + function = "cam_mclk0"; + pins = "gpio26"; + }; + pinconf_mclk0 { + pins = "gpio26"; + drive-strength = <16>; + bias-disable; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index d6a0a4aaaf22..8d5114d16d09 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -519,4 +519,100 @@ bias-disable; }; }; + + camera_board_default: camera_board_default { + mux_pwdn { + function = "gpio"; + pins = "gpio98"; + }; + config_pwdn { + pins = "gpio98"; + drive-strength = <16>; + bias-disable; + }; + + mux_rst { + function = "gpio"; + pins = "gpio104"; + }; + config_rst { + pins = "gpio104"; + drive-strength = <16>; + bias-disable; + }; + + mux_mclk1 { + function = "cam_mclk"; + pins = "gpio14"; + }; + config_mclk1 { + pins = "gpio14"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera_front_default: camera_front_default { + mux_pwdn { + function = "gpio"; + pins = "gpio133"; + }; + config_pwdn { + pins = "gpio133"; + drive-strength = <16>; + bias-disable; + }; + + mux_rst { + function = "gpio"; + pins = "gpio23"; + }; + config_rst { + pins = "gpio23"; + drive-strength = <16>; + bias-disable; + }; + + mux_mclk2 { + function = "cam_mclk"; + pins = "gpio15"; + }; + config_mclk2 { + pins = "gpio15"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera_rear_default: camera_rear_default { + mux_pwdn { + function = "gpio"; + pins = "gpio26"; + }; + config_pwdn { + pins = "gpio26"; + drive-strength = <16>; + bias-disable; + }; + + mux_rst { + function = "gpio"; + pins = "gpio25"; + }; + config_rst { + pins = "gpio25"; + drive-strength = <16>; + bias-disable; + }; + + mux_mclk0 { + function = "cam_mclk"; + pins = "gpio13"; + }; + config_mclk0 { + pins = "gpio13"; + drive-strength = <16>; + bias-disable; + }; + }; }; -- cgit From f3442ab972573b42d765491450c0394254deded7 Mon Sep 17 00:00:00 2001 From: Todor Tomov Date: Mon, 19 Nov 2018 11:25:36 +0200 Subject: arm64: dts: qcom: msm8996: Add VFE SMMU node Add VFE SMMU node. Signed-off-by: Todor Tomov Reviewed-by: Vivek Gautam Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 13bb96444df0..a4d087e5bfbd 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -950,6 +950,23 @@ }; }; + vfe_smmu: arm,smmu@da0000 { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0xda0000 0x10000>; + + #global-interrupts = <1>; + interrupts = , + , + ; + power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; + clocks = <&mmcc SMMU_VFE_AHB_CLK>, + <&mmcc SMMU_VFE_AXI_CLK>; + clock-names = "iface", + "bus"; + #iommu-cells = <1>; + status = "ok"; + }; + agnoc@0 { power-domains = <&gcc AGGRE0_NOC_GDSC>; compatible = "simple-pm-bus"; -- cgit From e0531312e78f06c43e0526209b3de530abc564b4 Mon Sep 17 00:00:00 2001 From: Todor Tomov Date: Mon, 19 Nov 2018 11:25:37 +0200 Subject: arm64: dts: qcom: msm8996: Add CAMSS support Add a node for the Camera Subsystem present on the Qualcomm MSM8996 SoC. Signed-off-by: Todor Tomov Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 135 ++++++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index a4d087e5bfbd..8585c61e32ef 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -967,6 +967,141 @@ status = "ok"; }; + camss: camss@a00000 { + compatible = "qcom,msm8996-camss"; + reg = <0xa34000 0x1000>, + <0xa00030 0x4>, + <0xa35000 0x1000>, + <0xa00038 0x4>, + <0xa36000 0x1000>, + <0xa00040 0x4>, + <0xa30000 0x100>, + <0xa30400 0x100>, + <0xa30800 0x100>, + <0xa30c00 0x100>, + <0xa31000 0x500>, + <0xa00020 0x10>, + <0xa10000 0x1000>, + <0xa14000 0x1000>; + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csiphy2", + "csiphy2_clk_mux", + "csid0", + "csid1", + "csid2", + "csid3", + "ispif", + "csi_clk_mux", + "vfe0", + "vfe1"; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csid0", + "csid1", + "csid2", + "csid3", + "ispif", + "vfe0", + "vfe1"; + power-domains = <&mmcc VFE0_GDSC>; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_ISPIF_AHB_CLK>, + <&mmcc CAMSS_CSI0PHYTIMER_CLK>, + <&mmcc CAMSS_CSI1PHYTIMER_CLK>, + <&mmcc CAMSS_CSI2PHYTIMER_CLK>, + <&mmcc CAMSS_CSI0_AHB_CLK>, + <&mmcc CAMSS_CSI0_CLK>, + <&mmcc CAMSS_CSI0PHY_CLK>, + <&mmcc CAMSS_CSI0PIX_CLK>, + <&mmcc CAMSS_CSI0RDI_CLK>, + <&mmcc CAMSS_CSI1_AHB_CLK>, + <&mmcc CAMSS_CSI1_CLK>, + <&mmcc CAMSS_CSI1PHY_CLK>, + <&mmcc CAMSS_CSI1PIX_CLK>, + <&mmcc CAMSS_CSI1RDI_CLK>, + <&mmcc CAMSS_CSI2_AHB_CLK>, + <&mmcc CAMSS_CSI2_CLK>, + <&mmcc CAMSS_CSI2PHY_CLK>, + <&mmcc CAMSS_CSI2PIX_CLK>, + <&mmcc CAMSS_CSI2RDI_CLK>, + <&mmcc CAMSS_CSI3_AHB_CLK>, + <&mmcc CAMSS_CSI3_CLK>, + <&mmcc CAMSS_CSI3PHY_CLK>, + <&mmcc CAMSS_CSI3PIX_CLK>, + <&mmcc CAMSS_CSI3RDI_CLK>, + <&mmcc CAMSS_AHB_CLK>, + <&mmcc CAMSS_VFE0_CLK>, + <&mmcc CAMSS_CSI_VFE0_CLK>, + <&mmcc CAMSS_VFE0_AHB_CLK>, + <&mmcc CAMSS_VFE0_STREAM_CLK>, + <&mmcc CAMSS_VFE1_CLK>, + <&mmcc CAMSS_CSI_VFE1_CLK>, + <&mmcc CAMSS_VFE1_AHB_CLK>, + <&mmcc CAMSS_VFE1_STREAM_CLK>, + <&mmcc CAMSS_VFE_AHB_CLK>, + <&mmcc CAMSS_VFE_AXI_CLK>; + clock-names = "top_ahb", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csiphy2_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "csi2_ahb", + "csi2", + "csi2_phy", + "csi2_pix", + "csi2_rdi", + "csi3_ahb", + "csi3", + "csi3_phy", + "csi3_pix", + "csi3_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe0_ahb", + "vfe0_stream", + "vfe1", + "csi_vfe1", + "vfe1_ahb", + "vfe1_stream", + "vfe_ahb", + "vfe_axi"; + vdda-supply = <&pm8994_l2>; + iommus = <&vfe_smmu 0>, + <&vfe_smmu 1>, + <&vfe_smmu 2>, + <&vfe_smmu 3>; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + agnoc@0 { power-domains = <&gcc AGGRE0_NOC_GDSC>; compatible = "simple-pm-bus"; -- cgit From 4ba16d17efdd3bae25863a3e95a4d9b5f52dc686 Mon Sep 17 00:00:00 2001 From: Mesih Kilinc Date: Sun, 2 Dec 2018 23:23:50 +0300 Subject: ARM: dts: suniv: add initial DTSI file for F1C100s F1C100s is one product with the suniv die, which has a 32MiB co-packaged DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a initial DTSI for it. Signed-off-by: Mesih Kilinc Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 147 +++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi new file mode 100644 index 000000000000..aff5f9022cd6 --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + * Copyright 2018 Mesih Kilinc + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + clocks { + osc24M: clk-24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: clk-32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + cpus { + cpu { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram-controller@1c00000 { + compatible = "allwinner,suniv-f1c100s-system-control", + "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_d: sram@10000 { + compatible = "mmio-sram"; + reg = <0x00010000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00010000 0x1000>; + + otg_sram: sram-section@0 { + compatible = "allwinner,suniv-f1c100s-sram-d", + "allwinner,sun4i-a10-sram-d"; + reg = <0x0000 0x1000>; + status = "disabled"; + }; + }; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,suniv-f1c100s-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + intc: interrupt-controller@1c20400 { + compatible = "allwinner,suniv-f1c100s-ic"; + reg = <0x01c20400 0x400>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,suniv-f1c100s-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <38>, <39>, <40>; + clocks = <&ccu 37>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + uart0_pe_pins: uart0-pe-pins { + pins = "PE0", "PE1"; + function = "uart0"; + }; + }; + + timer@1c20c00 { + compatible = "allwinner,suniv-f1c100s-timer"; + reg = <0x01c20c00 0x90>; + interrupts = <13>; + clocks = <&osc24M>; + }; + + wdt: watchdog@1c20ca0 { + compatible = "allwinner,suniv-f1c100s-wdt", + "allwinner,sun4i-a10-wdt"; + reg = <0x01c20ca0 0x20>; + }; + + uart0: serial@1c25000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25000 0x400>; + interrupts = <1>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu 38>; + resets = <&ccu 24>; + status = "disabled"; + }; + + uart1: serial@1c25400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25400 0x400>; + interrupts = <2>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu 39>; + resets = <&ccu 25>; + status = "disabled"; + }; + + uart2: serial@1c25800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c25800 0x400>; + interrupts = <3>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu 40>; + resets = <&ccu 26>; + status = "disabled"; + }; + }; +}; -- cgit From 324f4071a08046676a637521f211a34848f0cc0d Mon Sep 17 00:00:00 2001 From: Mesih Kilinc Date: Sun, 2 Dec 2018 23:23:51 +0300 Subject: ARM: dts: suniv: Add device tree for Lichee Pi Nano Lichee Pi Nano is a F1C100s board by Lichee Pi. Add initial device tree for it. Signed-off-by: Mesih Kilinc Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 2 ++ arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 26 +++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e1628224aada..1256f2194ae9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1067,6 +1067,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_MACH_SUNIV) += \ + suniv-f1c100s-licheepi-nano.dtb dtb-$(CONFIG_ARCH_TANGO) += \ tango4-vantage-1172.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts new file mode 100644 index 000000000000..a1154e6c7cb5 --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2018 Icenowy Zheng + */ + +/dts-v1/; +#include "suniv-f1c100s.dtsi" + +/ { + model = "Lichee Pi Nano"; + compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pe_pins>; + status = "okay"; +}; -- cgit From 6d2372fc77e45f23b1d20d9fe2844d2978ad9c93 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 3 Dec 2018 16:04:47 +0100 Subject: ARM: dts: r8a7743: Remove legacy "renesas,rcar-thermal" compatibility The thermal hardware description for the RZ/G1M SoC was added to its DTS after the introduction of support for thermal zones, and included a thermal-zones node from the beginning. Hence there is no need to claim compatibility with "renesas,rcar-thermal", which would be needed only for backwards compatibility with kernels predating thermal zone support. Fixes: 6c76b4f7d89e89f0 ("ARM: dts: r8a7743: Add thermal device to DT") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 24715f74ae08..3cc33f7ff7fe 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -348,8 +348,7 @@ thermal: thermal@e61f0000 { compatible = "renesas,thermal-r8a7743", - "renesas,rcar-gen2-thermal", - "renesas,rcar-thermal"; + "renesas,rcar-gen2-thermal"; reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; interrupts = ; clocks = <&cpg CPG_MOD 522>; -- cgit From 3c248aefe73b5586347dae74b0a8d40aea1018b3 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:15 +0000 Subject: ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM Add support for iWave RZ/G1N Qseven System On Module. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7744-iwg20m.dtsi diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi new file mode 100644 index 000000000000..6166ae053060 --- /dev/null +++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave RZ/G1N Qseven SOM + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include "r8a7744.dtsi" +#include + +/ { + compatible = "iwave,g20m", "renesas,r8a7744"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; -- cgit From d83010f87ab31861eacac1ffe1278f655a376268 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:16 +0000 Subject: ARM: dts: r8a7744: Initial SoC device tree Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders to avoid compilation error with the common platform code. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 369 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 369 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7744.dtsi diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi new file mode 100644 index 000000000000..f4d0abde3f56 --- /dev/null +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a7744 SoC + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7744"; + #address-cells = <2>; + #size-cells = <2>; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + power-domains = <&sysc R8A7744_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7744_PD_CA15_SCU>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + reg = <0 0xe6050000 0 0x50>; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + /* placeholder */ + }; + + gpio1: gpio@e6051000 { + reg = <0 0xe6051000 0 0x50>; + #gpio-cells = <2>; + /* placeholder */ + }; + + gpio2: gpio@e6052000 { + reg = <0 0xe6052000 0 0x50>; + #gpio-cells = <2>; + /* placeholder */ + }; + + gpio6: gpio@e6055400 { + reg = <0 0xe6055400 0 0x50>; + #gpio-cells = <2>; + /* placeholder */ + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7744"; + reg = <0 0xe6060000 0 0x250>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7744-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7744-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7744-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xe6530000 0 0x40>; + /* placeholder */ + }; + + i2c5: i2c@e6528000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xe6528000 0 0x40>; + /* placeholder */ + }; + + hsusb: usb@e6590000 { + reg = <0 0xe6590000 0 0x100>; + /* placeholder */ + }; + + usbphy: usb-phy@e6590100 { + reg = <0 0xe6590100 0 0x100>; + /* placeholder */ + }; + + avb: ethernet@e6800000 { + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + /* placeholder */ + }; + + scifb1: serial@e6c30000 { + reg = <0 0xe6c30000 0 0x100>; + /* placeholder */ + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + reg = <0 0xe6e68000 0 0x40>; + /* placeholder */ + }; + + hscif1: serial@e62c8000 { + reg = <0 0xe62c8000 0 0x60>; + /* placeholder */ + }; + + can0: can@e6e80000 { + reg = <0 0xe6e80000 0 0x1000>; + /* placeholder */ + }; + + can1: can@e6e88000 { + reg = <0 0xe6e88000 0 0x1000>; + /* placeholder */ + }; + + rcar_sound: sound@ec500000 { + reg = <0 0xec500000 0 0x1000>; + + rcar_sound,dvc { + dvc0: dvc-0 {}; + dvc1: dvc-1 {}; + }; + + rcar_sound,src { + src2: src-2 {}; + src3: src-3 {}; + }; + + rcar_sound,ssi { + ssi0: ssi-0 {}; + ssi1: ssi-1 {}; + }; + /* placeholder */ + }; + + pci0: pci@ee090000 { + reg = <0 0xee090000 0 0xc00>; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + /* placeholder */ + }; + + pci1: pci@ee0d0000 { + reg = <0 0xee0d0000 0 0xc00>; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + /* placeholder */ + }; + + sdhi1: sd@ee140000 { + reg = <0 0xee140000 0 0x100>; + /* placeholder */ + }; + + sdhi2: sd@ee160000 { + reg = <0 0xee160000 0 0x100>; + /* placeholder */ + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + du: display@feb00000 { + reg = <0 0xfeb00000 0 0x40000>, + <0 0xfeb90000 0 0x1c>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + }; + /* placeholder */ + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; -- cgit From 45c660ecdfd598eb93c46f5a95da6eb75008abb9 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:17 +0000 Subject: ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N Add support for iWave RainboW-G20D-Qseven board based on RZ/G1N. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7744-iwg20d-q7.dts | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..aba5a25b7eac 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -829,6 +829,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a7743-iwg20d-q7.dtb \ r8a7743-iwg20d-q7-dbcm-ca.dtb \ r8a7743-sk-rzg1m.dtb \ + r8a7744-iwg20d-q7.dtb \ r8a7745-iwg22d-sodimm.dtb \ r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ r8a7745-sk-rzg1e.dtb \ diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts new file mode 100644 index 000000000000..1fdac528f274 --- /dev/null +++ b/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1N Qseven board + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a7744-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" + +/ { + model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1N"; + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"; +}; -- cgit From 484775a5a9d9875ee3b3dde22b913286d91a0c44 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:18 +0000 Subject: ARM: dts: r8a7744: Add SYS-DMAC support Describe SYS-DMAC0/1 in the R8A7744 device tree. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index f4d0abde3f56..732c5d71191c 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -215,6 +215,72 @@ /* placeholder */ }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7744", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7744", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + avb: ethernet@e6800000 { reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; #address-cells = <1>; -- cgit From 78ce1559b2f1c741ceda6f511c80beee57b1b71e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:19 +0000 Subject: ARM: dts: r8a7744: Add GPIO support Describe GPIO blocks in the R8A7744 device tree. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 102 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 98 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 732c5d71191c..ea1a78288707 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -116,29 +116,123 @@ ranges; gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; reg = <0 0xe6050000 0 0x50>; + interrupts = ; #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - /* placeholder */ + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; reg = <0 0xe6051000 0 0x50>; + interrupts = ; #gpio-cells = <2>; - /* placeholder */ + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; reg = <0 0xe6052000 0 0x50>; + interrupts = ; #gpio-cells = <2>; - /* placeholder */ + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; reg = <0 0xe6055400 0 0x50>; + interrupts = ; #gpio-cells = <2>; - /* placeholder */ + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7744", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 904>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 904>; }; pfc: pin-controller@e6060000 { -- cgit From d94369fe69fd235e2109331c41f28dcfcfac28eb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:20 +0000 Subject: ARM: dts: r8a7744: Add Ethernet AVB support Add Ethernet AVB support for R8A7744 SoC. Signed-off-by: Biju Das Reviewed-by: Simon Horman Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index ea1a78288707..4d4ddbaba456 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -376,10 +376,16 @@ }; avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7744", + "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; - /* placeholder */ + status = "disabled"; }; scifb1: serial@e6c30000 { -- cgit From f1546da8a5c8862d1e66835affcfaf9a0c123abc Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:21 +0000 Subject: ARM: dts: r8a7744: Add SMP support Add DT node for the Advanced Power Management Unit (APMU), add the second CPU core, and use "renesas,apmu" as "enable-method". Also add cpu1 phandle node to the PMU interrupt-affinity property. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 38 ++++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 4d4ddbaba456..2cb6d8fa2fa0 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -49,6 +49,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -69,6 +70,25 @@ < 375000 1000000>; }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + power-domains = <&sysc R8A7744_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + L2_CA15: cache-controller-0 { compatible = "cache"; cache-unified; @@ -96,7 +116,7 @@ compatible = "arm,cortex-a15-pmu"; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>; + interrupt-affinity = <&cpu0>, <&cpu1>; }; /* External SCIF clock */ @@ -250,6 +270,12 @@ #reset-cells = <1>; }; + apmu@e6152000 { + compatible = "renesas,r8a7744-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + rst: reset-controller@e6160000 { compatible = "renesas,r8a7744-rst"; reg = <0 0xe6160000 0 0x100>; @@ -483,7 +509,7 @@ interrupt-controller; reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; @@ -520,10 +546,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clock - can be overridden by the board */ -- cgit From 28c0cf739819124573cb24d3ab23b213f3b0d011 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:22 +0000 Subject: ARM: dts: r8a7744: Add [H]SCIF{A|B} support Describe [H]SCIF{|A|B} ports in the R8A7744 device tree. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 257 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 254 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 2cb6d8fa2fa0..1fe694d0215b 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -414,9 +414,139 @@ status = "disabled"; }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1106>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 1106>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1107>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 1107>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7744", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 1108>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 1108>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7744", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7744", + "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7744", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; }; scif0: serial@e6e60000 { @@ -427,19 +557,140 @@ clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; resets = <&cpg 721>; status = "disabled"; }; scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e68000 0 0x40>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 719>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 718>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7744", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7744", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; }; hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7744", + "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 0x60>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7744", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 713>, + <&cpg CPG_CORE R8A7744_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; }; can0: can@e6e80000 { -- cgit From fb64de56dfd9e8efe05d12adca7e2885ce1b9e17 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:23 +0000 Subject: ARM: dts: r8a7744: Add I2C and IIC support Add the I2C[0-5] and IIC[0,1,3] devices nodes to the R8A7744 device tree. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 127 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 125 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 1fe694d0215b..57e0be34b989 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -310,19 +310,142 @@ reg = <0 0xe6300000 0 0x40000>; }; + /* The memory map in the User's Manual maps the cores to + * bus numbers + */ + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7744", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7744", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + i2c2: i2c@e6530000 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,i2c-r8a7744", + "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7744", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7744", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; }; i2c5: i2c@e6528000 { /* doesn't need pinmux */ #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,i2c-r8a7744", + "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7744", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7744", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + iic3: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7744"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; }; hsusb: usb@e6590000 { -- cgit From b591e323b271fdc2ffdc40eaf06e926a1e272994 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:24 +0000 Subject: ARM: dts: r8a7744: Add SDHI nodes Add SDHI nodes to the DT of the r8a7744 SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 57e0be34b989..97b417c1b5f9 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -866,14 +866,49 @@ /* placeholder */ }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7744", + "renesas,rcar-gen2-sdhi"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7744", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; }; sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7744", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; }; gic: interrupt-controller@f1001000 { -- cgit From d9e792206d2101de871ea99220b59fe2930ebbcc Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:25 +0000 Subject: ARM: dts: r8a7744: Add MMC node Add MMC node to the DT of the r8a7744 SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 97b417c1b5f9..3f7674b2aac5 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -911,6 +911,22 @@ status = "disabled"; }; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7744", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + max-frequency = <97500000>; + status = "disabled"; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit From 266d863eece3f0b1e333203f9efe8fa89e042b3b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:26 +0000 Subject: ARM: dts: r8a7744-iwg20m: Add eMMC support Add eMMC support for iWave RZ/G1N Qseven System On Module. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi index 6166ae053060..1e57b1f9baed 100644 --- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi @@ -29,3 +29,20 @@ &extal_clk { clock-frequency = <20000000>; }; + +&pfc { + mmcif0_pins: mmc { + groups = "mmc_data8_b", "mmc_ctrl"; + function = "mmc"; + }; +}; + +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; -- cgit From f9a3d5f23b6c8e4029a3474945971477d1f9365a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:27 +0000 Subject: ARM: dts: r8a7744-iwg20m: Enable SDHI0 controller Enable the SDHI0 controller on iWave RZ/G1N Qseven System On Module. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi index 1e57b1f9baed..503583e2c852 100644 --- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi @@ -35,6 +35,12 @@ groups = "mmc_data8_b", "mmc_ctrl"; function = "mmc"; }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; }; &mmcif0 { @@ -46,3 +52,13 @@ non-removable; status = "okay"; }; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; -- cgit From ce28396b7a8621e048cfb8d002bc869b428a905e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:28 +0000 Subject: ARM: dts: r8a7744: USB 2.0 host support Describe internal PCI bridge devices, USB phy device and link PCI USB devices to USB phy. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 77 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 72 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 3f7674b2aac5..1d4cb5e447cd 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -454,8 +454,25 @@ }; usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7744", + "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; - /* placeholder */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; }; dmac0: dma-controller@e6700000 { @@ -847,23 +864,73 @@ }; pci0: pci@ee090000 { - reg = <0 0xee090000 0 0xc00>; + compatible = "renesas,pci-r8a7744", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; bus-range = <0 0>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - /* placeholder */ + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; }; pci1: pci@ee0d0000 { - reg = <0 0xee0d0000 0 0xc00>; + compatible = "renesas,pci-r8a7744", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; bus-range = <1 1>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - /* placeholder */ + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; }; sdhi0: sd@ee100000 { -- cgit From a5d56930c703ddbdd8712553247c38ec6f406b74 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:29 +0000 Subject: ARM: dts: r8a7744: Add USB-DMAC and HSUSB device nodes Add usb dmac and hsusb device nodes on RZ/G1N SoC dtsi. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 42 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 1d4cb5e447cd..cf05ce05bba1 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -449,8 +449,20 @@ }; hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7744", + "renesas,rcar-gen2-usbhs"; reg = <0 0xe6590000 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 704>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; }; usbphy: usb-phy@e6590100 { @@ -475,6 +487,34 @@ }; }; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7744-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7744-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7744", "renesas,rcar-dmac"; -- cgit From 336a425ce67d151fe1e275389aeccd08d66d9833 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:30 +0000 Subject: ARM: dts: r8a7744: Add RWDT node Add a device node for the Watchdog Timer (RWDT) controller on the Renesas RZ/G1N (r8a7744) SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index cf05ce05bba1..fabc7f990952 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -135,6 +135,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7744-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7744", "renesas,rcar-gen2-gpio"; -- cgit From 5133bfed5e585cec75550cdc795d848fe70097a9 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:31 +0000 Subject: ARM: dts: r8a7744: Add audio support Add sound support for the RZ/G1N SoC (a.k.a. R8A7744). This work is based on similar work done on the R8A7743 SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 243 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 235 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index fabc7f990952..cb6dfb5af218 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -894,23 +894,250 @@ }; rcar_sound: sound@ec500000 { - reg = <0 0xec500000 0 0x1000>; + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7744", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7744_CLK_M2>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", "src.5", + "src.4", "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; + status = "disabled"; rcar_sound,dvc { - dvc0: dvc-0 {}; - dvc1: dvc-1 {}; + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; }; rcar_sound,src { - src2: src-2 {}; - src3: src-3 {}; + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; }; rcar_sound,ssi { - ssi0: ssi-0 {}; - ssi1: ssi-1 {}; + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; }; - /* placeholder */ + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7744", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7744", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <13>; }; pci0: pci@ee090000 { -- cgit From 56f1896093043c63c6ecd8a53080aa89d6b41070 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:32 +0000 Subject: ARM: dts: r8a7744: Add CAN support Add the definitions for can0 and can1 to the r8a7744 SoC dtsi. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index cb6dfb5af218..87187f266066 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -884,13 +884,31 @@ }; can0: can@e6e80000 { + compatible = "renesas,can-r8a7744", + "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7744_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; }; can1: can@e6e88000 { + compatible = "renesas,can-r8a7744", + "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7744_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; }; rcar_sound: sound@ec500000 { -- cgit From 154a05f0c870e6c49753cda689d2209c0915996e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:33 +0000 Subject: ARM: dts: r8a7744: Add IRQC support Describe the IRQC interrupt controller in the r8a7744 device tree. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 87187f266066..91096c36dcac 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -297,6 +297,26 @@ #power-domain-cells = <1>; }; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7744", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; -- cgit From ef9d757c06e9b0258b10fcb19c3be2d8cbbc0a30 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:34 +0000 Subject: ARM: dts: r8a7744: Add thermal device to DT This patch instantiates the thermal sensor module with thermal-zone support. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 91096c36dcac..937c800b2415 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -317,6 +317,17 @@ resets = <&cpg 407>; }; + thermal: thermal@e61f0000 { + compatible = "renesas,thermal-r8a7744", + "renesas,rcar-gen2-thermal"; + reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; @@ -1351,6 +1362,26 @@ }; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <95000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, -- cgit From 90bcf80c37df5d76d953673717cdd5082776d98e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 30 Nov 2018 15:26:35 +0000 Subject: ARM: dts: r8a7744: Add CMT SoC specific support Add CMT[01] support to SoC DT. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 937c800b2415..8f43fb41ec91 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1360,6 +1360,38 @@ compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; }; + + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7744-cmt0", + "renesas,rcar-gen2-cmt0"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7744-cmt1", + "renesas,rcar-gen2-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 329>; + status = "disabled"; + }; }; thermal-zones { -- cgit From 10fabcb817c5e37aeb8a1b79a95468c8df45898c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 28 Nov 2018 16:38:27 +0000 Subject: ARM: dts: r8a7744: add VIN dt support Add VIN[012] support to SoC dt. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 8f43fb41ec91..094e1c4107e9 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -942,6 +942,39 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7744", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7744", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7744", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required -- cgit From eddcbe813dd3c8247840859bf4d04b3423d35f8f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 28 Nov 2018 16:38:28 +0000 Subject: ARM: dts: r8a7744: Add VSP support Add VSP support to SoC DT. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 094e1c4107e9..be84400c08ad 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1367,6 +1367,33 @@ resets = <&cpg 408>; }; + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + du: display@feb00000 { reg = <0 0xfeb00000 0 0x40000>, <0 0xfeb90000 0 0x1c>; -- cgit From 350ae49b97c4612002e253a311f5070680509373 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 28 Nov 2018 16:38:29 +0000 Subject: ARM: dts: r8a7744: Add IPMMU DT nodes Add the six IPMMU instances found in the r8a7744 to DT with a disabled status. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 58 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index be84400c08ad..06952f5a1e9f 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -328,6 +328,64 @@ #thermal-sensor-cells = <0>; }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; -- cgit From cebc31e8b59445aaf84b8810ff76b2fcc246fea2 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 28 Nov 2018 16:38:30 +0000 Subject: ARM: dts: r8a7744: Add PWM SoC support Add the definitions for pwm[0123456] to the SoC dtsi. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 70 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 06952f5a1e9f..181aa0732ce1 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -972,6 +972,76 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + can0: can@e6e80000 { compatible = "renesas,can-r8a7744", "renesas,rcar-gen2-can"; -- cgit From eb83d144978e9f21aaa1372d75b50f3eec22ed48 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 28 Nov 2018 16:38:31 +0000 Subject: ARM: dts: r8a7744: Add TPU support Add TPU support to SoC DT. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 181aa0732ce1..bab78d43b5db 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -270,6 +270,16 @@ reg = <0 0xe6060000 0 0x250>; }; + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7744", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7744-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- cgit From 7fbbfe07b588cd81c1046a1846345a5cf614589a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 27 Nov 2018 11:56:25 +0000 Subject: ARM: dts: r8a7744-iwg20d-q7-dbcm-ca: Add device tree for camera DB This patch adds support for the camera daughter board which is connected to iWave's RZ/G1N Qseven carrier board. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index aba5a25b7eac..9cf6fdfd1f3a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -830,6 +830,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a7743-iwg20d-q7-dbcm-ca.dtb \ r8a7743-sk-rzg1m.dtb \ r8a7744-iwg20d-q7.dtb \ + r8a7744-iwg20d-q7-dbcm-ca.dtb \ r8a7745-iwg22d-sodimm.dtb \ r8a7745-iwg22d-sodimm-dbhd-ca.dtb \ r8a7745-sk-rzg1e.dtb \ diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts new file mode 100644 index 000000000000..3e58c2e92e03 --- /dev/null +++ b/arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave Systems RZ/G1N Qseven board development + * platform with camera daughter board + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a7744-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" +#include "iwg20d-q7-dbcm-ca.dtsi" + +/ { + model = "iWave Systems RZ/G1N Qseven development platform with camera add-on"; + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744"; +}; -- cgit From 0faadd5a410533d3a75601b607ee5a4110b754f4 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 27 Nov 2018 11:56:31 +0000 Subject: ARM: dts: r8a7744: Add QSPI support Add the DT node for the QSPI interface to the SoC dtsi. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index bab78d43b5db..28fea2aaa0cf 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -703,6 +703,22 @@ status = "disabled"; }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7744", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7744", "renesas,rcar-gen2-scifa", "renesas,scifa"; -- cgit From 491e70588805a8895bff6ac5a626c8bb481fea1c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 27 Nov 2018 11:56:33 +0000 Subject: ARM: dts: r8a7744: Add MSIOF[012] support Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 28fea2aaa0cf..992d622b5393 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1068,6 +1068,54 @@ status = "disabled"; }; + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7744", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7744", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7744", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + can0: can@e6e80000 { compatible = "renesas,can-r8a7744", "renesas,rcar-gen2-can"; -- cgit From 54234e80858cf3730917d71af80a13ac4b8f26dc Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 27 Nov 2018 11:56:34 +0000 Subject: ARM: dts: r8a7744: Add xhci support Add a device node for the xhci controller on the Renesas RZ/G1N (r8a7744) SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 992d622b5393..33e15c5f21c9 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1424,6 +1424,26 @@ dma-channels = <13>; }; + /* + * pci1 and xhci share the same phy, therefore only one of them + * can be active at any one time. If both of them are enabled, + * a race condition will determine who'll control the phy. + * A firmware file is needed by the xhci driver in order for + * USB 3.0 to work properly. + */ + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7744", + "renesas,rcar-gen2-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 328>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + pci0: pci@ee090000 { compatible = "renesas,pci-r8a7744", "renesas,pci-rcar-gen2"; -- cgit From 24035072999c5c175ac03ed2db2ef98cb339b319 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 27 Nov 2018 11:56:35 +0000 Subject: ARM: dts: r8a7744: Add PCIe Controller device node Add a device node for the PCIe controller on the Renesas RZ/G1N (r8a7744) SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 33e15c5f21c9..04148d608fc4 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1616,6 +1616,34 @@ resets = <&cpg 127>; }; + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7744", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 + 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + du: display@feb00000 { reg = <0 0xfeb00000 0 0x40000>, <0 0xfeb90000 0 0x1c>; -- cgit From 6f31ba17c83c184de658a78a8f84b8c843eb8e74 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Fri, 23 Nov 2018 14:45:41 +0000 Subject: arm64: dts: meson-axg: Enable watchdog on Meson AXG SoCs Add the watchdog node also on the AXG platforms. Signed-off-by: Carlo Caione Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 5f512c91471e..524f6ab85070 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1551,6 +1551,12 @@ status = "disabled"; }; + watchdog@f0d0 { + compatible = "amlogic,meson-gxbb-wdt"; + reg = <0x0 0xf0d0 0x0 0x10>; + clocks = <&xtal>; + }; + pwm_ab: pwm@1b000 { compatible = "amlogic,meson-axg-ee-pwm"; reg = <0x0 0x1b000 0x0 0x20>; -- cgit From ed85b3435e45a983dc24e388bfe0b1b337c6377f Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 29 Nov 2018 17:54:51 +0100 Subject: arm64: dts: meson-axg: remove alternate xtal There is actually no alternate xtal on any of the axg board I have seen so far. The 32k is actually generated internally, deriving from the 24MHz main xtal. Amlogic SoC also have the option to provide the 32k reference externally, through one of the AO pads, but no platform is using this ATM. Fixes: 5e395e146667 ("ARM64: dts: meson-axg: add an 32K alt aoclk") Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 524f6ab85070..cb6c222f9d0e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -53,13 +53,6 @@ status = "disabled"; }; - ao_alt_xtal: ao_alt_xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <32000000>; - clock-output-names = "ao_alt_xtal"; - #clock-cells = <0>; - }; - arm-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = , -- cgit From e8c276d953d800adced2c6174310320f90c5d432 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 23 Nov 2018 20:53:07 +0100 Subject: ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripherals The public Meson8b (S805) datasheet describes a memory region called "A9 Periph base" which starts at 0xC4300000 and ends at 0xC430FFFF. Add a simple-bus node and move all peripherals that are part of this memory region. This makes the .dts a bit easier to read. No functional changes. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 24 ++++++++++++++++-------- arch/arm/boot/dts/meson8.dtsi | 12 +++++++----- arch/arm/boot/dts/meson8b.dtsi | 12 +++++++----- 3 files changed, 30 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 0839da07a75c..e4645f612712 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -59,14 +59,6 @@ cache-level = <2>; }; - gic: interrupt-controller@c4301000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xc4301000 0x1000>, - <0xc4300100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; @@ -207,6 +199,22 @@ }; }; + periph: bus@c4300000 { + compatible = "simple-bus"; + reg = <0xc4300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc4300000 0x10000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x1000 0x1000>, + <0x100 0x100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; + aobus: aobus@c8100000 { compatible = "simple-bus"; reg = <0xc8100000 0x100000>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 3be5fbd07997..28b9f6779993 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -129,11 +129,6 @@ no-map; }; }; - - scu@c4300000 { - compatible = "arm,cortex-a9-scu"; - reg = <0xc4300000 0x100>; - }; }; /* end of / */ &aobus { @@ -362,6 +357,13 @@ arm,shared-override; }; +&periph { + scu@0 { + compatible = "arm,cortex-a9-scu"; + reg = <0x0 0x100>; + }; +}; + &pwm_ab { compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; }; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 587a855f872b..6b097ab8637f 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -112,11 +112,6 @@ no-map; }; }; - - scu@c4300000 { - compatible = "arm,cortex-a5-scu"; - reg = <0xc4300000 0x100>; - }; }; /* end of / */ &aobus { @@ -349,6 +344,13 @@ arm,shared-override; }; +&periph { + scu@0 { + compatible = "arm,cortex-a5-scu"; + reg = <0x0 0x100>; + }; +}; + &pwm_ab { compatible = "amlogic,meson8b-pwm"; }; -- cgit From 1124d790b431a97dc3c6f4333718bad0f6f3093b Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 23 Nov 2018 20:53:08 +0100 Subject: ARM: dts: meson8: add the ARM TWD timer The Meson8 and Meson8m2 SoC are using four ARM Cortex-A9 cores which come with a "TWD" (Timer-Watchdog) based timer. This adds support for the ARM TWD Timer on these two SoCs. Suggested-by: Carlo Caione [ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured" message during boot, use pre-processor macros to specify the IRQ, added the correct clock, dropped TWD watchdog node since there's no driver for it anymore ] Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 28b9f6779993..2b0b3edbd896 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -362,6 +362,13 @@ compatible = "arm,cortex-a9-scu"; reg = <0x0 0x100>; }; + + timer@600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x600 0x20>; + interrupts = ; + clocks = <&clkc CLKID_PERIPH>; + }; }; &pwm_ab { -- cgit From 2710e8d2131047c042b390c26d9a1ad9fe5765a1 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 23 Nov 2018 20:53:09 +0100 Subject: ARM: dts: meson8: add the Cortex-A9 global timer The Meson8 and Meson8m2 SoCs are using four Cortex-A9 cores. These come with an ARM global timer. This adds the Cortex-A9 global timer but keeps it disabled for now. The timer is clocked by the "PERIPH" clock whose rate can change during runtime (when changing the frequency of the CPU clock). Unfortunately the arm_global_timer driver does not handle changes to the clock rate yet. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 2b0b3edbd896..2575a5835567 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -363,6 +363,19 @@ reg = <0x0 0x100>; }; + timer@200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x200 0x20>; + interrupts = ; + clocks = <&clkc CLKID_PERIPH>; + + /* + * the arm_global_timer driver currently does not handle clock + * rate changes. Keep it disabled for now. + */ + status = "disabled"; + }; + timer@600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x600 0x20>; -- cgit From f5506e82f78873dcc502d96cb08d0ed05fb5c289 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 23 Nov 2018 20:53:10 +0100 Subject: ARM: dts: meson8b: add the ARM TWD timer The Meson8B SoC is using four ARM Cortex-A5 cores which come with a "TWD" (Timer-Watchdog) based timer. This adds support for the ARM TWD Timer on this SoC. Suggested-by: Carlo Caione [ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured" message during boot, use pre-processor macros to specify the IRQ, added the correct clock, dropped TWD watchdog node since there's no driver for it anymore ] Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 6b097ab8637f..a3a5649e32fa 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -349,6 +349,13 @@ compatible = "arm,cortex-a5-scu"; reg = <0x0 0x100>; }; + + timer@600 { + compatible = "arm,cortex-a5-twd-timer"; + reg = <0x600 0x20>; + interrupts = ; + clocks = <&clkc CLKID_PERIPH>; + }; }; &pwm_ab { -- cgit From da38636393cea70d39237eeda2f63ec21f93aa00 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 23 Nov 2018 20:53:11 +0100 Subject: ARM: dts: meson8b: add the Cortex-A5 global timer The Meson8b SoC is using four Cortex-A5 cores. These come with an ARM global timer. This adds the Cortex-A5 global timer but keeps it disabled for now. The timer is clocked by the "PERIPH" clock whose rate can change during runtime (when changing the frequency of the CPU clock). Unfortunately the arm_global_timer driver does not handle changes to the clock rate yet. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index a3a5649e32fa..a38d187d3d6e 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -350,6 +350,19 @@ reg = <0x0 0x100>; }; + timer@200 { + compatible = "arm,cortex-a5-global-timer"; + reg = <0x200 0x20>; + interrupts = ; + clocks = <&clkc CLKID_PERIPH>; + + /* + * the arm_global_timer driver currently does not handle clock + * rate changes. Keep it disabled for now. + */ + status = "disabled"; + }; + timer@600 { compatible = "arm,cortex-a5-twd-timer"; reg = <0x600 0x20>; -- cgit From 622b9827b24df2269581716b9795ebb181b11fd3 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 30 Nov 2018 00:00:43 +0100 Subject: ARM: dts: meson: meson8: add the CPU OPP table The values are taken from Amlogic's 3.10 kernel sources. Their sources have a "meson8m2_n200_2G.dtd" which defines a different voltage table: - 0.86V for 96MHz - (values in between omitted) - 1.14V for 1.992GHz The reason for this is simply the hardware design because the voltage regulator on this board is has a minimum output of 0.86V and a maximum output of 1.14V. The recommended settings are added with this patch instead of using the values that are only valid for one board. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 72 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 2575a5835567..e5cd325d7ea8 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -64,6 +64,8 @@ reg = <0x200>; enable-method = "amlogic,meson8-smp"; resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; }; cpu1: cpu@201 { @@ -73,6 +75,8 @@ reg = <0x201>; enable-method = "amlogic,meson8-smp"; resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; }; cpu2: cpu@202 { @@ -82,6 +86,8 @@ reg = <0x202>; enable-method = "amlogic,meson8-smp"; resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; }; cpu3: cpu@203 { @@ -91,6 +97,72 @@ reg = <0x203>; enable-method = "amlogic,meson8-smp"; resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-96000000 { + opp-hz = /bits/ 64 <96000000>; + opp-microvolt = <825000>; + }; + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + opp-microvolt = <825000>; + }; + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <825000>; + }; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <825000>; + }; + opp-504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <825000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <850000>; + }; + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <850000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <875000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <925000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <975000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1025000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1100000>; + }; + opp-1800000000 { + status = "disabled"; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1125000>; + }; + opp-1992000000 { + status = "disabled"; + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1150000>; }; }; -- cgit From c311552a8eadf1f9960e6126d23c4bf683ca9ae0 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 30 Nov 2018 00:00:44 +0100 Subject: ARM: dts: meson: meson8b: add the CPU OPP tables The values are taken from Amlogic's 3.10 kernel sources. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index a38d187d3d6e..22d775460767 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -62,6 +62,8 @@ reg = <0x200>; enable-method = "amlogic,meson8b-smp"; resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; }; cpu1: cpu@201 { @@ -71,6 +73,8 @@ reg = <0x201>; enable-method = "amlogic,meson8b-smp"; resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; }; cpu2: cpu@202 { @@ -80,6 +84,8 @@ reg = <0x202>; enable-method = "amlogic,meson8b-smp"; resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; }; cpu3: cpu@203 { @@ -89,6 +95,66 @@ reg = <0x203>; enable-method = "amlogic,meson8b-smp"; resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPUCLK>; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-96000000 { + opp-hz = /bits/ 64 <96000000>; + opp-microvolt = <860000>; + }; + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + opp-microvolt = <860000>; + }; + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <860000>; + }; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <860000>; + }; + opp-504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <860000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <860000>; + }; + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <860000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1140000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1140000>; + }; + opp-1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <1140000>; + }; + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + opp-microvolt = <1140000>; + }; + opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-microvolt = <1140000>; }; }; -- cgit From fa3abfb6943ef2976deda78d83788a1352963f47 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 3 Dec 2018 18:16:38 +0100 Subject: dt-bindings: clk: meson: add ao controller clock inputs Add the clock inputs of amlogic AO clock controller Signed-off-by: Jerome Brunet Reviewed-by: Stephen Boyd Signed-off-by: Kevin Hilman --- .../devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt index 3a880528030e..79511d7bb321 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt @@ -11,6 +11,13 @@ Required Properties: - GXM (S912) : "amlogic,meson-gxm-aoclkc" - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" followed by the common "amlogic,meson-gx-aoclkc" +- clocks: list of clock phandle, one for each entry clock-names. +- clock-names: should contain the following: + * "xtal" : the platform xtal + * "mpeg-clk" : the main clock controller mother clock (aka clk81) + * "ext-32k-0" : external 32kHz reference #0 if any (optional) + * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only) + * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only) - #clock-cells: should be 1. @@ -40,8 +47,9 @@ ao_sysctrl: sys-ctrl@0 { compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; -}; Example: UART controller node that consumes the clock and reset generated by the clock controller: -- cgit From b1d02a84b552fde1232dc11b3c8465433fa1339d Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 3 Dec 2018 18:16:39 +0100 Subject: dt-bindings: clk: meson: add main controller clock input Add the clock input of the main clock controller Signed-off-by: Jerome Brunet Reviewed-by: Stephen Boyd Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index e950599566a9..a6871953bf04 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -9,6 +9,9 @@ Required Properties: "amlogic,gxbb-clkc" for GXBB SoC, "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. +- clocks : list of clock phandle, one for each entry clock-names. +- clock-names : should contain the following: + * "xtal": the platform xtal - #clock-cells: should be 1. @@ -31,6 +34,8 @@ sysctrl: system-controller@0 { clkc: clock-controller { #clock-cells = <1>; compatible = "amlogic,gxbb-clkc"; + clocks = <&xtal>; + clock-names = "xtal"; }; }; -- cgit From 16361ff23e20d2f967456fab9971152331b65117 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 3 Dec 2018 18:16:40 +0100 Subject: arm64: dts: meson: add clock controller clock inputs Add the clock inputs of the clock controllers Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index cb6c222f9d0e..f077b2102b7e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1082,6 +1082,8 @@ clkc: clock-controller { compatible = "amlogic,axg-clkc"; #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; }; }; }; @@ -1327,6 +1329,8 @@ compatible = "amlogic,meson-axg-aoclkc"; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 6796d250985a..a7b883ced0a8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -299,6 +299,8 @@ &clkc_AO { compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; &efuse { @@ -334,6 +336,8 @@ clkc: clock-controller { compatible = "amlogic,gxbb-clkc"; #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index ed278097825b..d5c3d78aafeb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -260,6 +260,8 @@ &clkc_AO { compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; + clocks = <&xtal>, <&clkc CLKID_CLK81>; + clock-names = "xtal", "mpeg-clk"; }; &gpio_intc { @@ -284,6 +286,8 @@ clkc: clock-controller { compatible = "amlogic,gxl-clkc"; #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; }; }; -- cgit From 925c5afd78c40169c7e0e6adec52d5119ff43751 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 5 Dec 2018 10:24:30 +0100 Subject: ARM: dts: sun8i: h3: Fix the system-control register range Unlike in previous generations, the system-control register range is not limited to a size of 0x30 on the H3. In particular, the EMAC clock configuration register (accessed through syscon) is at offset 0x30 in that range. Extend the register size to its full range (0x1000) as a result. Signed-off-by: Paul Kocialkowski Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 3ecfabb10151..45242df7425b 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -136,7 +136,7 @@ soc { system-control@1c00000 { compatible = "allwinner,sun8i-h3-system-control"; - reg = <0x01c00000 0x30>; + reg = <0x01c00000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges; -- cgit From 973efbc6a061488f280ac1792200e48eb0b1ff5e Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 5 Dec 2018 10:24:36 +0100 Subject: arm64: dts: allwinner: h5: Add system-control node with SRAM C1 Add the H5-specific system control node description to its device-tree with support for the SRAM C1 section, that will be used by the video codec node later on. The CPU-side SRAM address was obtained empirically while the size was taken from the documentation. They may not be entirely accurate. Signed-off-by: Paul Kocialkowski Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index b41dc1aab67d..f184d8f55c8a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -94,6 +94,28 @@ }; soc { + system-control@1c00000 { + compatible = "allwinner,sun50i-h5-system-control"; + reg = <0x01c00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c1: sram@18000 { + compatible = "mmio-sram"; + reg = <0x00018000 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00018000 0x1c000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun50i-h5-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x1c000>; + }; + }; + }; + mali: gpu@1e80000 { compatible = "allwinner,sun50i-h5-mali", "arm,mali-450"; reg = <0x01e80000 0x30000>; -- cgit From 24a1be4e7e80fc7a19290be4715191b77fe80b41 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 5 Dec 2018 10:24:37 +0100 Subject: ARM/arm64: dts: allwinner: Move H3/H5 syscon label over to soc-specific nodes The EMAC driver requires a syscon node to access the EMAC clock configuration register (that is part of the system-control register range and controlled). For this purpose, a dummy syscon node was introduced to let the driver access the register freely. Recently, the EMAC driver was tuned to get access to the register when the SRAM driver is registered (as used on the A64). As a result, it is no longer necessary to have a dummy syscon node for that purpose. Now that we have a proper system-control node for both the H3 and H5, we can get rid of that dummy syscon node and have the EMAC driver use the node corresponding to the proper SRAM driver (by switching the syscon label over to each dtsi). This way, we no longer have two separate nodes for the same register space. Signed-off-by: Paul Kocialkowski Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3.dtsi | 2 +- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 6 ------ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 2 +- 3 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 45242df7425b..e93c4716512e 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -134,7 +134,7 @@ }; soc { - system-control@1c00000 { + syscon: system-control@1c00000 { compatible = "allwinner,sun8i-h3-system-control"; reg = <0x01c00000 0x1000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 0d9e9eac518c..ed5846982685 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -152,12 +152,6 @@ }; }; - syscon: syscon@1c00000 { - compatible = "allwinner,sun8i-h3-system-controller", - "syscon"; - reg = <0x01c00000 0x1000>; - }; - dma: dma-controller@1c02000 { compatible = "allwinner,sun8i-h3-dma"; reg = <0x01c02000 0x1000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index f184d8f55c8a..107607baaa42 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -94,7 +94,7 @@ }; soc { - system-control@1c00000 { + syscon: system-control@1c00000 { compatible = "allwinner,sun50i-h5-system-control"; reg = <0x01c00000 0x1000>; #address-cells = <1>; -- cgit From 8be5b161bb3d07bc5a119dfe0285ec05d28202c9 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 5 Dec 2018 10:24:43 +0100 Subject: arm64: dts: allwinner: h5: Add Video Engine node This adds the Video Engine node for the H5. Since it can map the whole DRAM range, there is no particular need for a reserved memory node (unlike platforms preceding the A33). Signed-off-by: Paul Kocialkowski Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index 107607baaa42..b45c449e6e75 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -116,6 +116,17 @@ }; }; + video-codec@1c0e000 { + compatible = "allwinner,sun50i-h5-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_VE>; + interrupts = ; + allwinner,sram = <&ve_sram 1>; + }; + mali: gpu@1e80000 { compatible = "allwinner,sun50i-h5-mali", "arm,mali-450"; reg = <0x01e80000 0x30000>; -- cgit From 7aed1e3a963877efc02a25f5dc6fb605e52ff441 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 5 Dec 2018 10:24:31 +0100 Subject: ARM: dts: sun8i: a33: Remove unnecessary reserved memory node While we believed that the memory for the video engine had to be kept in the first 256 MiBs of DRAM, this is no longer true starting with the A33 and any address can be mapped. As a result, remove the reserved memory node and let the kernel allocate the CMA pool wherever it sees fit. Signed-off-by: Paul Kocialkowski Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a33.dtsi | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index c2c10cd4a210..9ac4fae6c10d 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -186,21 +186,6 @@ }; }; - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ - default-pool { - compatible = "shared-dma-pool"; - size = <0x6000000>; - alloc-ranges = <0x4a000000 0x6000000>; - reusable; - linux,cma-default; - }; - }; - sound: sound { compatible = "simple-audio-card"; simple-audio-card,name = "sun8i-a33-audio"; -- cgit From 82992cdf4af7553319e3551a07e6dc1f4c32ab41 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 5 Dec 2018 10:24:32 +0100 Subject: ARM: dts: sun8i: h3: Remove unnecessary reserved memory node Just like on the A33, the video engine on the H3 can map any address in memory, so there is no particular need to have reserved memory at a fixed address. As a result, remove the reserved memory node and let the kernel allocate the CMA pool wherever it sees fit. Signed-off-by: Paul Kocialkowski Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3.dtsi | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index c2da3a3d373a..7e6031768401 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -119,20 +119,6 @@ ; }; - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - default-pool { - compatible = "shared-dma-pool"; - size = <0x6000000>; - alloc-ranges = <0x4a000000 0x6000000>; - reusable; - linux,cma-default; - }; - }; - soc { system-control@1c00000 { compatible = "allwinner,sun8i-h3-system-control"; -- cgit From 106deea8ba53b09005613d9a47072bc3a1e01637 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 5 Dec 2018 10:24:39 +0100 Subject: arm64: dts: allwinner: a64: Add support for the SRAM C1 section Add the description for the SRAM C1 section to the A64 device-tree. Since there is no entry for this section in the A64 manual, the base address and size were only verified to be consistent empirically. Signed-off-by: Paul Kocialkowski Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 384c417cb7a2..8557d52c7c99 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -301,6 +301,20 @@ reg = <0x0000 0x28000>; }; }; + + sram_c1: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0x40000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun50i-a64-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x40000>; + }; + }; }; dma: dma-controller@1c02000 { -- cgit From d60ce24740d2a416f6772f2c39e289d745688fa4 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Wed, 5 Dec 2018 10:24:44 +0100 Subject: arm64: dts: allwinner: a64: Add Video Engine node This adds the Video Engine node for the A64. Since it can map the whole DRAM range, there is no particular need for a reserved memory node (unlike platforms preceding the A33). Signed-off-by: Paul Kocialkowski Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 8557d52c7c99..8d024c10d7cb 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -397,6 +397,17 @@ }; }; + video-codec@1c0e000 { + compatible = "allwinner,sun50i-h5-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_VE>; + interrupts = ; + allwinner,sram = <&ve_sram 1>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun50i-a64-mmc"; reg = <0x01c0f000 0x1000>; -- cgit From 7ff33bd321b1a1092ccf4b80a1742528754ecc30 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 5 Dec 2018 18:11:52 +0800 Subject: ARM: dts: sun8i: a33: Drop audio codec oversampling rate to 128 fs The current oversampling rate of 512 means that for 48 kHz 16 bit stereo, the MCLK is running at the same rate as the module clock, so there is no head room to support higher sampling rates. The codec however supports up to 192 kHz for playback. This patch drops the oversampling rate from 512 to 128, so that 192 kHz audio can be played back directly without downsampling. Ideally we should be using different oversampling rates for different sampling rates, but that's not possible without a platform-specific machine driver. Fixes: 870f1bd1f5e9 ("ARM: dts: sun8i: Add audio codec, dai and card for A33") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a33.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 9ac4fae6c10d..626152c30f50 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -192,7 +192,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&link_codec>; simple-audio-card,bitclock-master = <&link_codec>; - simple-audio-card,mclk-fs = <512>; + simple-audio-card,mclk-fs = <128>; simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,routing = "Left DAC", "AIF1 Slot 0 Left", -- cgit From c2e66b8f7c37567e63859e04b3e69fa7027ebb86 Mon Sep 17 00:00:00 2001 From: Houlong Wei Date: Thu, 29 Nov 2018 11:37:08 +0800 Subject: arm64: dts: mt8173: Add GCE node This patch adds the device node of the GCE hardware for CMDQ module. Signed-off-by: Houlong Wei Signed-off-by: HS Liao Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index abd2f15a544b..412ffd4d426b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include #include "mt8173-pinfunc.h" / { @@ -521,6 +522,15 @@ status = "disabled"; }; + gce: mailbox@10212000 { + compatible = "mediatek,mt8173-gce"; + reg = <0 0x10212000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + #mbox-cells = <3>; + }; + mipi_tx0: mipi-dphy@10215000 { compatible = "mediatek,mt8173-mipi-tx"; reg = <0 0x10215000 0 0x1000>; -- cgit From bb2203d5f10bb8b2da16db1a1f357ff1178a5b9f Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 3 Oct 2018 17:24:09 -0700 Subject: arm64: dts: qcom: sdm845: Add UART nodes This adds nodes for all possible UARTs to sdm845.dtsi. By default only configure the RX/TX lines with pinctrl. Boards that use UARTs with flow control can overwrite the configuration in the .dtsi. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 270 +++++++++++++++++++++++++++++++++++ 1 file changed, 270 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1419b0098cb3..c27cbd3bcb0a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -402,6 +402,17 @@ status = "disabled"; }; + uart0: serial@880000 { + compatible = "qcom,geni-uart"; + reg = <0x880000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart0_default>; + interrupts = ; + status = "disabled"; + }; + i2c1: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0x884000 0x4000>; @@ -428,6 +439,17 @@ status = "disabled"; }; + uart1: serial@884000 { + compatible = "qcom,geni-uart"; + reg = <0x884000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart1_default>; + interrupts = ; + status = "disabled"; + }; + i2c2: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0x888000 0x4000>; @@ -454,6 +476,17 @@ status = "disabled"; }; + uart2: serial@888000 { + compatible = "qcom,geni-uart"; + reg = <0x888000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart2_default>; + interrupts = ; + status = "disabled"; + }; + i2c3: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0x88c000 0x4000>; @@ -480,6 +513,17 @@ status = "disabled"; }; + uart3: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0x88c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart3_default>; + interrupts = ; + status = "disabled"; + }; + i2c4: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0x890000 0x4000>; @@ -506,6 +550,17 @@ status = "disabled"; }; + uart4: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0x890000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart4_default>; + interrupts = ; + status = "disabled"; + }; + i2c5: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0x894000 0x4000>; @@ -532,6 +587,17 @@ status = "disabled"; }; + uart5: serial@894000 { + compatible = "qcom,geni-uart"; + reg = <0x894000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart5_default>; + interrupts = ; + status = "disabled"; + }; + i2c6: i2c@898000 { compatible = "qcom,geni-i2c"; reg = <0x898000 0x4000>; @@ -558,6 +624,17 @@ status = "disabled"; }; + uart6: serial@898000 { + compatible = "qcom,geni-uart"; + reg = <0x898000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart6_default>; + interrupts = ; + status = "disabled"; + }; + i2c7: i2c@89c000 { compatible = "qcom,geni-i2c"; reg = <0x89c000 0x4000>; @@ -583,6 +660,17 @@ #size-cells = <0>; status = "disabled"; }; + + uart7: serial@89c000 { + compatible = "qcom,geni-uart"; + reg = <0x89c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_default>; + interrupts = ; + status = "disabled"; + }; }; qupv3_id_1: geniqup@ac0000 { @@ -622,6 +710,17 @@ status = "disabled"; }; + uart8: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0xa80000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart8_default>; + interrupts = ; + status = "disabled"; + }; + i2c9: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0xa84000 0x4000>; @@ -685,6 +784,17 @@ status = "disabled"; }; + uart10: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0xa88000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart10_default>; + interrupts = ; + status = "disabled"; + }; + i2c11: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0xa8c000 0x4000>; @@ -711,6 +821,17 @@ status = "disabled"; }; + uart11: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0xa8c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart11_default>; + interrupts = ; + status = "disabled"; + }; + i2c12: i2c@a90000 { compatible = "qcom,geni-i2c"; reg = <0xa90000 0x4000>; @@ -737,6 +858,17 @@ status = "disabled"; }; + uart12: serial@a90000 { + compatible = "qcom,geni-uart"; + reg = <0xa90000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart12_default>; + interrupts = ; + status = "disabled"; + }; + i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0xa94000 0x4000>; @@ -763,6 +895,17 @@ status = "disabled"; }; + uart13: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0xa94000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart13_default>; + interrupts = ; + status = "disabled"; + }; + i2c14: i2c@a98000 { compatible = "qcom,geni-i2c"; reg = <0xa98000 0x4000>; @@ -789,6 +932,17 @@ status = "disabled"; }; + uart14: serial@a98000 { + compatible = "qcom,geni-uart"; + reg = <0xa98000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart14_default>; + interrupts = ; + status = "disabled"; + }; + i2c15: i2c@a9c000 { compatible = "qcom,geni-i2c"; reg = <0xa9c000 0x4000>; @@ -814,6 +968,17 @@ #size-cells = <0>; status = "disabled"; }; + + uart15: serial@a9c000 { + compatible = "qcom,geni-uart"; + reg = <0xa9c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart15_default>; + interrupts = ; + status = "disabled"; + }; }; tcsr_mutex_regs: syscon@1f40000 { @@ -1070,12 +1235,117 @@ }; }; + qup_uart0_default: qup-uart0-default { + pinmux { + pins = "gpio2", "gpio3"; + function = "qup0"; + }; + }; + + qup_uart1_default: qup-uart1-default { + pinmux { + pins = "gpio19", "gpio20"; + function = "qup1"; + }; + }; + + qup_uart2_default: qup-uart2-default { + pinmux { + pins = "gpio29", "gpio30"; + function = "qup2"; + }; + }; + + qup_uart3_default: qup-uart3-default { + pinmux { + pins = "gpio43", "gpio44"; + function = "qup3"; + }; + }; + + qup_uart4_default: qup-uart4-default { + pinmux { + pins = "gpio91", "gpio92"; + function = "qup4"; + }; + }; + + qup_uart5_default: qup-uart5-default { + pinmux { + pins = "gpio87", "gpio88"; + function = "qup5"; + }; + }; + + qup_uart6_default: qup-uart6-default { + pinmux { + pins = "gpio47", "gpio48"; + function = "qup6"; + }; + }; + + qup_uart7_default: qup-uart7-default { + pinmux { + pins = "gpio95", "gpio96"; + function = "qup7"; + }; + }; + + qup_uart8_default: qup-uart8-default { + pinmux { + pins = "gpio67", "gpio68"; + function = "qup8"; + }; + }; + qup_uart9_default: qup-uart9-default { pinmux { pins = "gpio4", "gpio5"; function = "qup9"; }; }; + + qup_uart10_default: qup-uart10-default { + pinmux { + pins = "gpio53", "gpio54"; + function = "qup10"; + }; + }; + + qup_uart11_default: qup-uart11-default { + pinmux { + pins = "gpio33", "gpio34"; + function = "qup11"; + }; + }; + + qup_uart12_default: qup-uart12-default { + pinmux { + pins = "gpio51", "gpio52"; + function = "qup12"; + }; + }; + + qup_uart13_default: qup-uart13-default { + pinmux { + pins = "gpio107", "gpio108"; + function = "qup13"; + }; + }; + + qup_uart14_default: qup-uart14-default { + pinmux { + pins = "gpio31", "gpio32"; + function = "qup14"; + }; + }; + + qup_uart15_default: qup-uart15-default { + pinmux { + pins = "gpio83", "gpio84"; + function = "qup15"; + }; + }; }; usb_1_hsphy: phy@88e2000 { -- cgit From b72ce26cb73afd042d65f737971f560a491e1275 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 5 Dec 2018 09:06:51 +0000 Subject: ARM: dts: iwg20d-q7-common: Move cmt/rwdt node out of RZ/G1M SOM The iWave RZ/G1N board is almost identical to RZ/G1M. cmt and rwdt modules are SoC specific and should be part of board dts rather than SoM dtsi. By moving these nodes to the common dtsi it allows cmt and rwdt to be enabled on both of these boards with less lines of code. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/iwg20d-q7-common.dtsi | 9 +++++++++ arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 9 --------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi index ca9154dd8052..e2b1ab9b56e5 100644 --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -116,6 +116,10 @@ status = "okay"; }; +&cmt0 { + status = "okay"; +}; + &hsusb { status = "okay"; pinctrl-0 = <&usb0_pins>; @@ -230,6 +234,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi index 0e2e033cc849..b3fee1d61c87 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi @@ -31,10 +31,6 @@ }; }; -&cmt0 { - status = "okay"; -}; - &extal_clk { clock-frequency = <20000000>; }; @@ -88,11 +84,6 @@ }; }; -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-names = "default"; -- cgit From 4fbd4158fe8967e9296516ebae2cfaf7a1c7a214 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 25 Nov 2018 16:40:30 +0200 Subject: arm64: dts: renesas: r8a77995: draak: Add backlight Add the backlight device for the LVDS1 output, in preparation for panel support. Signed-off-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 48bb1d77744f..52d044b9f3f2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -24,6 +24,17 @@ stdout-path = "serial0:115200n8"; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000>; + + brightness-levels = <256 128 64 16 8 4 0>; + default-brightness-level = <6>; + + power-supply = <®_12p0v>; + enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; + }; + composite-in { compatible = "composite-video-connector"; @@ -104,6 +115,15 @@ regulator-always-on; }; + reg_12p0v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "D12.0V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + vga { compatible = "vga-connector"; -- cgit From e259e04748e2798a747d9c363ded50514b15a7b9 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 5 Dec 2018 09:06:52 +0000 Subject: ARM: dts: r8a7744-iwg20m: Add SPI NOR support Add support for the SPI NOR device used to boot up the system to the iWave RZ/G1N Qseven System On Module DT. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi index 503583e2c852..82ee3c1140ef 100644 --- a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi @@ -36,6 +36,11 @@ function = "mmc"; }; + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; @@ -53,6 +58,27 @@ status = "okay"; }; +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-names = "default"; -- cgit From 1d596472429cdb223f074c1dd02e3f777d3c8936 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 5 Dec 2018 14:08:21 -0800 Subject: ARM: dts: Add missing ranges for am437x mcasp l3 ports We need to add mcasp l3 port ranges for mcasp to use a correct l3 data port address for dma. Fixes: d95adfd45853 ("ARM: dts: am437x: Move l4 child devices to probe them with ti-sysc") Reported-by: Peter Ujfalusi Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index ff2c11ed0877..ca0896f80248 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -613,7 +613,9 @@ ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ <0x00100000 0x48100000 0x100000>, /* segment 1 */ <0x00200000 0x48200000 0x100000>, /* segment 2 */ - <0x00300000 0x48300000 0x100000>; /* segment 3 */ + <0x00300000 0x48300000 0x100000>, /* segment 3 */ + <0x46000000 0x46000000 0x400000>, /* l3 data port */ + <0x46400000 0x46400000 0x400000>; /* l3 data port */ segment@0 { /* 0x48000000 */ compatible = "simple-bus"; @@ -664,7 +666,9 @@ <0x00034000 0x00034000 0x001000>, /* ap 80 */ <0x00035000 0x00035000 0x001000>, /* ap 81 */ <0x00036000 0x00036000 0x001000>, /* ap 84 */ - <0x00037000 0x00037000 0x001000>; /* ap 85 */ + <0x00037000 0x00037000 0x001000>, /* ap 85 */ + <0x46000000 0x46000000 0x400000>, /* l3 data port */ + <0x46400000 0x46400000 0x400000>; /* l3 data port */ target-module@8000 { /* 0x48008000, ap 6 10.0 */ compatible = "ti,sysc"; @@ -826,7 +830,8 @@ clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x38000 0x2000>; + ranges = <0x0 0x38000 0x2000>, + <0x46000000 0x46000000 0x400000>; mcasp0: mcasp@0 { compatible = "ti,am33xx-mcasp-audio"; @@ -857,7 +862,8 @@ clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x3c000 0x2000>; + ranges = <0x0 0x3c000 0x2000>, + <0x46400000 0x46400000 0x400000>; mcasp1: mcasp@0 { compatible = "ti,am33xx-mcasp-audio"; -- cgit From 772c3a452a1381c270d45f855bcee3a6f7953880 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 3 Dec 2018 22:58:21 +0800 Subject: ARM: dts: sunxi: h3/h5: Add clock accuracy for external oscillators The H3 datasheet specifies a tolerance range for the external oscillators used. Add them to the device tree as the clock accuracy. The internal oscillator is left unchanged, as it will be removed later. Acked-by: Maxime Ripard Tested-by: Corentin Labbe Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 4b1530ebe427..f63a5ef527be 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -86,6 +86,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; + clock-accuracy = <50000>; clock-output-names = "osc24M"; }; @@ -93,6 +94,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-accuracy = <50000>; clock-output-names = "osc32k"; }; -- cgit From 75d64e8bf5c1582853515adc7e6f734852d5d5c7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 3 Dec 2018 22:58:23 +0800 Subject: ARM: dts: sun8i: r40: Add clock accuracy for external oscillators The R40 datasheet specifies a tolerance range for the external oscillators used. Add them to the device tree as the clock accuracy. Acked-by: Maxime Ripard Tested-by: Corentin Labbe Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-r40.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 6f4c9ca5a3ee..a8917f8b1c80 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -61,6 +61,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; + clock-accuracy = <50000>; clock-output-names = "osc24M"; }; @@ -68,6 +69,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-accuracy = <20000>; clock-output-names = "osc32k"; }; }; -- cgit From 5cd4c31a1252ca63999f771796dcc09320e8e410 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 30 Nov 2018 14:34:32 -0300 Subject: arm64: dts: rockchip: add VPU device node for RK3399 Add the Video Processing Unit node for the RK3399 SoC. Also, fix the VPU IOMMU node, which was disabled and lacking its power domain property. Reviewed-by: Tomasz Figa Signed-off-by: Ezequiel Garcia Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 5bd735637b77..6cc1c9fa4ea6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1242,6 +1242,18 @@ status = "disabled"; }; + vpu: video-codec@ff650000 { + compatible = "rockchip,rk3399-vpu"; + reg = <0x0 0xff650000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3399_PD_VCODEC>; + }; + vpu_mmu: iommu@ff650800 { compatible = "rockchip,iommu"; reg = <0x0 0xff650800 0x0 0x40>; @@ -1250,7 +1262,7 @@ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3399_PD_VCODEC>; }; vdec_mmu: iommu@ff660480 { -- cgit From ad5399d12ca4f68fdb9e58e4b9a556eb997a9639 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 30 Nov 2018 14:34:31 -0300 Subject: ARM: dts: rockchip: add VPU device node for RK3288 Add the Video Processing Unit node for RK3288 SoC. Fix the VPU IOMMU node, which was disabled and lacking its power domain property. Reviewed-by: Tomasz Figa Signed-off-by: Ezequiel Garcia Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 1da86e82bb57..ca7d52daa8fb 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1232,6 +1232,18 @@ }; }; + vpu: video-codec@ff9a0000 { + compatible = "rockchip,rk3288-vpu"; + reg = <0x0 0xff9a0000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3288_PD_VIDEO>; + }; + vpu_mmu: iommu@ff9a0800 { compatible = "rockchip,iommu"; reg = <0x0 0xff9a0800 0x0 0x100>; @@ -1240,7 +1252,7 @@ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3288_PD_VIDEO>; }; hevc_mmu: iommu@ff9c0440 { -- cgit From f7cb866a96868771504bbb0d5e5ff79ab90b4abb Mon Sep 17 00:00:00 2001 From: Oskari Lemmela Date: Sat, 1 Dec 2018 12:08:17 +0200 Subject: arm64: dts: rockchip: enable hdmi output on rk3399-rockpro64 The rockpro64 does have hdmi support, so add the necessary devicetree node to enable it. Signed-off-by: Oskari Lemmela Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts index 1d35f5406b5e..f7025b9103ca 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts @@ -205,6 +205,13 @@ status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; -- cgit From 36ead91499160b459d66cd70949511cde829204f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 28 Aug 2018 08:45:54 +0200 Subject: ARM: dts: rockchip: add BQ Edison 2 QC devicetree The Edison 2 Quad-Core was a Tablet device released in 2013 by MundoReader using a rk3188 soc. Add a devicetree for it. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3188-bqedison2qc.dts | 711 +++++++++++++++++++++ 3 files changed, 716 insertions(+) create mode 100644 arch/arm/boot/dts/rk3188-bqedison2qc.dts diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 0cc71236d639..4e37938edbe9 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -33,6 +33,10 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; +- bq Edison 2 Quad-Core tablet: + Required root node properties: + - compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; + - ChipSPARK Rayeager PX2 board: Required root node properties: - compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..71d6c015f246 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -854,6 +854,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3066a-marsboard.dtb \ rk3066a-mk808.dtb \ rk3066a-rayeager.dtb \ + rk3188-bqedison2qc.dtb \ rk3188-px3-evb.dtb \ rk3188-radxarock.dtb \ rk3228-evb.dtb \ diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts new file mode 100644 index 000000000000..a7477a09fbe8 --- /dev/null +++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts @@ -0,0 +1,711 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 MundoReader S.L. + * Author: Heiko Stuebner + */ + +/dts-v1/; +#include +#include +#include "rk3188.dtsi" + +/ { + model = "BQ Edison2 Quad-Core"; + compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vsys>; + pwms = <&pwm1 0 25000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key &usb_int>; + + power { + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + debounce-interval = <100>; + wakeup-source; + }; + + wake_on_usb: wake-on-usb { + label = "Wake-on-USB"; + gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_hold>; + /* only drive the pin low until device is off */ + active-delay-ms = <3000>; + }; + + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_in_vop0: endpoint { + remote-endpoint = <&vop0_out_lvds>; + }; + }; + + port@1 { + reg = <1>; + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + + panel { + compatible = "innolux,ee101ia-01d", "panel-lvds"; + backlight = <&backlight>; + + /* pin LCD_CS, Nshtdn input of lvds-encoder */ + enable-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_cs>; + power-supply = <&vcc_lcd>; + + data-mapping = "vesa-24"; + height-mm = <163>; + width-mm = <261>; + + panel-timing { + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <160>; + hfront-porch = <16>; + hsync-len = <10>; + vback-porch = <23>; + vfront-porch = <12>; + vsync-len = <3>; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on>; + reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; + }; + + avdd_cif: cif-avdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "avdd-cif"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_avdd_en>; + startup-delay-us = <100000>; + vin-supply = <&vcc28_cif>; + }; + + vcc_5v: vcc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&v5_drv>; + vin-supply = <&vsys>; + }; + + vcc_lcd: lcd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-lcd"; + gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_en>; + startup-delay-us = <50000>; + vin-supply = <&vcc_io>; + }; + + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_drv>; + startup-delay-us = <100000>; + vin-supply = <&vcc_5v>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vccq_emmc: emmc-vccq-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccq-emmc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_io>; + }; + + /* supplied from the bq24196 */ + vsys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&cru { + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru ACLK_CPU>, + <&cru HCLK_CPU>, <&cru PCLK_CPU>, + <&cru ACLK_PERI>, <&cru HCLK_PERI>, + <&cru PCLK_PERI>; + assigned-clock-rates = <594000000>, <504000000>, + <300000000>, + <150000000>, <75000000>, + <300000000>, <150000000>, + <75000000>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vccq_emmc>; + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + lis3de: accelerometer@29 { + compatible = "st,lis3de"; + reg = <0x29>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int>; + rotation-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + vdd-supply = <&vcc_io>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + tmp108@48 { + compatible = "ti,tmp108"; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&tmp_alrt>; + #thermal-sensor-cells = <0>; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; + + bat: battery@55 { + compatible = "ti,bq27541"; + reg = <0x55>; + power-supplies = <&bq24196>; + }; + + act8846: pmic@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&dvs0_ctl &pmic_int>; + + vp1-supply = <&vsys>; + vp2-supply = <&vsys>; + vp3-supply = <&vsys>; + vp4-supply = <&vsys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vsys>; + inl3-supply = <&vsys>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_log: REG2 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_arm: REG3 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vcc_io: vcc_hdmi: REG4 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vdd_10: REG5 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_12: REG6 { + regulator-name = "VDD_12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc18_cif: REG7 { + regulator-name = "VCC18_CIF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcca_33: REG8 { + regulator-name = "VCCA_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_tp: REG9 { + regulator-name = "VCC_TP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccio_wl: REG10 { + regulator-name = "VCCIO_WL"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc28_cif: REG12 { + regulator-name = "VCC28_CIF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + }; + + bq24196: charger@6b { + compatible = "ti,bq24196"; + reg = <0x6b>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&charger_int &chg_ctl &otg_en>; + ti,system-minimum-microvolt = <3200000>; + monitored-battery = <&bat>; + omit-battery-class; + + usb_otg_vbus: usb-otg-vbus { }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + rt5616: codec@1b { + compatible = "realtek,rt5616"; + reg = <0x1b>; + clocks = <&cru SCLK_I2S0>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>; + vmmcq-supply = <&vccio_wl>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio3>; + interrupts = ; + interrupt-names = "host-wake"; + brcm,drive-strength = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + act8846 { + dvs0_ctl: dvs0-ctl { + rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + bq24196 { + charger_int: charger-int { + rockchip,pins = <0 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + /* pin hog to make it select usb profile */ + chg_ctl: chg-ctl { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + /* low: charging, high: complete, fault: blinking */ + chg_det: chg-det { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* charging enabled when pin low and register set */ + chg_en: chg-en { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; + }; + + /* bq29196 powergood (when low) signal */ + dc_det: dc-det { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* wire bq24196 otg pin to high, to enable 500mA charging */ + otg_en: otg-en { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + camera { + cif0_pdn: cif0-pdn { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cif1_pdn: cif1-pdn { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cif_avdd_en: cif-avdd-en { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + display { + lcd_cs: lcd-cs { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_en: lcd-en { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ft5606 { + tp_int: tp-int { + rockchip,pins = <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + tp_rst: tp-rst { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + hdmi_int: hdmi-int { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdmi_rst: hdmi-rst { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_hold: pwr-hold { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lis3de { + gsensor_int: gsensor-int { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tmp108 { + tmp_alrt: tmp-alrt { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + v5_drv: v5-drv { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_drv: otg-drv { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_int: usb-int { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rk903 { + bt_host_wake: bt-host-wake { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_reg_on: bt-reg-on { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* pin hog to pull the reset high */ + bt_rst: bt-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + bt_wake: bt-wake { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake: wifi-host-wake { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_reg_on: wifi-reg-on { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <2000000>; + device-wakeup-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_reg_on &bt_rst &bt_wake>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vop0 { + status = "okay"; +}; + +&vop0_out { + vop0_out_lvds: endpoint { + remote-endpoint = <&lvds_in_vop0>; + }; +}; + +&vop1 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdc1_dclk &lcdc1_den &lcdc1_hsync + &lcdc1_vsync &lcdc1_rgb24>; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; -- cgit From b066a31040b74ea71704211b52307c7e113992f4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Dec 2018 17:50:16 +0100 Subject: arm64: tegra: Add HDA controller on Tegra186 The HDA controller found on Tegra186 can be used for audio playback over HDMI. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 4c79778d80db..6cea54dc9d35 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -318,6 +318,22 @@ status = "disabled"; }; + hda@3510000 { + compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; + reg = <0x0 0x03510000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_HDA>, + <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, + <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; + resets = <&bpmp TEGRA186_RESET_HDA>, + <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, + <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; + status = "disabled"; + }; + fuse@3820000 { compatible = "nvidia,tegra186-efuse"; reg = <0x0 0x03820000 0x0 0x10000>; -- cgit From 7c3adf1243cc31327713c20bc162ee99cf0ed237 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Dec 2018 17:50:17 +0100 Subject: arm64: tegra: Enable HDA on Jetson TX2 Enable the HDA controller on Jetson TX2 so that it can be used for audio playback over HDMI. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 9fc577a1ec44..65487eee2ce6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -51,6 +51,10 @@ vmmc-supply = <&vdd_sd>; }; + hda@3510000 { + status = "okay"; + }; + pcie@10003000 { status = "okay"; -- cgit From 97cf683c123d49cfdb2d19ea5dca99b590f5650f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Dec 2018 17:50:18 +0100 Subject: arm64: tegra: Add CEC controller on Tegra186 The CEC controller found on Tegra186 can be used to control consumer devices using the HDMI CEC pin. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 6cea54dc9d35..19fb266c0895 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -352,6 +352,15 @@ interrupt-parent = <&gic>; }; + cec@3960000 { + compatible = "nvidia,tegra186-cec"; + reg = <0x0 0x03960000 0x0 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_CEC>; + clock-names = "cec"; + status = "disabled"; + }; + hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra186-hsp"; reg = <0x0 0x03c00000 0x0 0xa0000>; -- cgit From 4878cc0c9fab0c8bcf3501252139fd32689302bf Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Tue, 4 Dec 2018 17:44:22 +0530 Subject: arm64: tegra: Add HDA controller on Tegra194 The HDA controller found on Tegra194 can be used for audio playback over HDMI. Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 2cc22ce8efca..b89038555d42 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -328,6 +328,22 @@ status = "disabled"; }; + hda@3510000 { + compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; + reg = <0x3510000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_HDA>, + <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, + <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; + clock-names = "hda", "hda2codec_2x", "hda2hdmi"; + resets = <&bpmp TEGRA194_RESET_HDA>, + <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, + <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; + reset-names = "hda", "hda2codec_2x", "hda2hdmi"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; + status = "disabled"; + }; + gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit From 01e13ae3b5f5fce8a35e492535d1a77fe1e010ba Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Dec 2018 17:50:20 +0100 Subject: arm64: tegra: Enable HDA on Jetson Xavier Enable the HDA controller on Jetson Xavier so that it can be used for audio playback over HDMI. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 274937042c4a..adf351010ff5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -24,6 +24,10 @@ status = "okay"; }; + hda@3510000 { + status = "okay"; + }; + host1x@13e00000 { display-hub@15200000 { status = "okay"; -- cgit From badb80bed041362f8977fe2990f65a96c2c9b381 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Dec 2018 17:50:21 +0100 Subject: arm64: tegra: Add CEC controller on Tegra194 The CEC controller found on Tegra194 can be used to control consumer devices using the HDMI CEC pin. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index b89038555d42..b7665c4277aa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -357,6 +357,15 @@ interrupt-parent = <&gic>; }; + cec@3960000 { + compatible = "nvidia,tegra194-cec"; + reg = <0x03960000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_CEC>; + clock-names = "cec"; + status = "disabled"; + }; + hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra186-hsp"; reg = <0x03c00000 0xa0000>; -- cgit From caa7a8e3c312b20eb66fe4924900a951c45df52e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Dec 2018 17:50:22 +0100 Subject: arm64: tegra: Enable HDA controller on Jetson TX1 The HDA controller can be used for audio playback over HDMI. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 365726ddd418..a96e6ee70c21 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1330,6 +1330,10 @@ phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; }; + hda@70030000 { + status = "okay"; + }; + padctl@7009f000 { status = "okay"; -- cgit From 8589a649d5f9495a5ae8375c1a96c7281cfd1206 Mon Sep 17 00:00:00 2001 From: Krishna Reddy Date: Tue, 16 Oct 2018 19:06:48 -0700 Subject: arm64: dts: tegra186: Enable IOMMU for SDHCI Enable IOMMU for all SDHCI controllers in Tegra186. Signed-off-by: Krishna Reddy Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 19fb266c0895..176dc0c128d8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -237,6 +237,7 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA186_RESET_SDMMC1>; reset-names = "sdhci"; + iommus = <&smmu TEGRA186_SID_SDMMC1>; pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; pinctrl-0 = <&sdmmc1_3v3>; pinctrl-1 = <&sdmmc1_1v8>; @@ -262,6 +263,7 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA186_RESET_SDMMC2>; reset-names = "sdhci"; + iommus = <&smmu TEGRA186_SID_SDMMC2>; pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; pinctrl-0 = <&sdmmc2_3v3>; pinctrl-1 = <&sdmmc2_1v8>; @@ -282,6 +284,7 @@ clock-names = "sdhci"; resets = <&bpmp TEGRA186_RESET_SDMMC3>; reset-names = "sdhci"; + iommus = <&smmu TEGRA186_SID_SDMMC3>; pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; pinctrl-0 = <&sdmmc3_3v3>; pinctrl-1 = <&sdmmc3_1v8>; @@ -307,6 +310,7 @@ assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; resets = <&bpmp TEGRA186_RESET_SDMMC4>; reset-names = "sdhci"; + iommus = <&smmu TEGRA186_SID_SDMMC4>; nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; -- cgit From 57b13b8b34002ce8f1d822ea05f0a84e5bc3a64a Mon Sep 17 00:00:00 2001 From: Andrzej Hajda Date: Thu, 6 Dec 2018 15:16:35 +0100 Subject: ARM: dts: exynos: remove display-port node from Arndale Arndale boards have wires for DSI and eDP panels, but in-kernel support for eDP panels is broken for long time and breaks display support even on boards with DSI panels. Signed-off-by: Andrzej Hajda Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250-arndale.dts | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index e2e5b3f28686..2ca9319f48f2 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -181,31 +181,6 @@ }; }; -&dp { - status = "okay"; - samsung,color-space = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - - display-timings { - native-mode = <&timing0>; - - timing0: timing { - /* 2560x1600 DP panel */ - clock-frequency = <50000>; - hactive = <2560>; - vactive = <1600>; - hfront-porch = <48>; - hback-porch = <80>; - hsync-len = <32>; - vback-porch = <16>; - vfront-porch = <8>; - vsync-len = <6>; - }; - }; -}; - &fimd { status = "okay"; }; -- cgit From 1deb430d291270f9d0067061a5dc7409819dfcfb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 26 Sep 2018 09:21:44 +0100 Subject: dt-bindings: arm: renesas: Document iWave RZ/G1N SOM Document the iW-RainboW-G20M-RZ/G1N Qseven device tree bindings, listing it as a supported system on module. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index f5e0f82fd503..4cfb56787a90 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -101,6 +101,8 @@ Boards: compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) compatible = "iwave,g20m", "renesas,r8a7743" + - iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven) + compatible = "iwave,g20m", "renesas,r8a7744" - Kingfisher (SBEV-RCAR-KF-M03) compatible = "shimafuji,kingfisher" - Koelsch (RTP0RC7791SEB00010S) -- cgit From ea456bf918e31a0f755c5c02963b4e10513fa82c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 26 Sep 2018 11:44:46 +0100 Subject: dt-bindings: arm: renesas: Document iW-RainboW-G20D-Qseven-RZG1N board Document the iW-RainboW-G20D-Qseven-RZG1N device tree bindings, listing it as a supported board. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 4cfb56787a90..144f045a9f4b 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -101,6 +101,8 @@ Boards: compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) compatible = "iwave,g20m", "renesas,r8a7743" + - iWave Systems RZ/G1N Qseven Development Platform (iW-RainboW-G20D-Qseven) + compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744" - iWave Systems RZ/G1N Qseven System On Module (iW-RainboW-G20M-Qseven) compatible = "iwave,g20m", "renesas,r8a7744" - Kingfisher (SBEV-RCAR-KF-M03) -- cgit From 74791d15fd7c405511e3cc097c2f043171ecbdb0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 3 Dec 2018 15:32:14 -0600 Subject: dt-bindings: arm: renesas: Move 'renesas,prr' binding to its own doc In preparation to convert board-level bindings to json-schema, move various misc SoC bindings out to their own file. Signed-off-by: Rob Herring Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- .../devicetree/bindings/arm/renesas,prr.txt | 20 ++++++++++++++++++++ Documentation/devicetree/bindings/arm/shmobile.txt | 18 ------------------ 2 files changed, 20 insertions(+), 18 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.txt diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.txt b/Documentation/devicetree/bindings/arm/renesas,prr.txt new file mode 100644 index 000000000000..08e482e953ca --- /dev/null +++ b/Documentation/devicetree/bindings/arm/renesas,prr.txt @@ -0,0 +1,20 @@ +Renesas Product Register + +Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that +allows to retrieve SoC product and revision information. If present, a device +node for this register should be added. + +Required properties: + - compatible: Must be one of: + "renesas,prr" + "renesas,bsid" + - reg: Base address and length of the register block. + + +Examples +-------- + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 144f045a9f4b..92cda17870d3 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -153,21 +153,3 @@ Boards: compatible = "renesas,v3msk", "renesas,r8a77970" - Wheat (RTP0RC7792ASKB0000JE) compatible = "renesas,wheat", "renesas,r8a7792" - - -Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that -allows to retrieve SoC product and revision information. If present, a device -node for this register should be added. - -Required properties: - - compatible: Must be "renesas,prr" or "renesas,bsid" - - reg: Base address and length of the register block. - - -Examples --------- - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; -- cgit From f6f4422532ad9ec9380a9936ed16b30922066a50 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 3 Dec 2018 22:58:20 +0800 Subject: ARM: dts: sun8i: a23/a33: Fix up RTC device node The RTC module on the A23 was claimed to be the same as on the A31, when in fact it is not. The A31 does not have an RTC external clock output, and its internal RC oscillator's average clock rate is not in the same range. The A33's RTC is the same as the A23. This patch fixes the compatible string and clock properties to conform to the updated bindings. The register range is also fixed. Acked-by: Maxime Ripard Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index c2ff8975ac60..a9c123de5d2c 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -573,11 +573,11 @@ }; rtc: rtc@1f00000 { - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; + compatible = "allwinner,sun8i-a23-rtc"; + reg = <0x01f00000 0x400>; interrupts = , ; - clock-output-names = "osc32k"; + clock-output-names = "osc32k", "osc32k-out"; clocks = <&ext_osc32k>; #clock-cells = <1>; }; -- cgit From 507c6e89d6c4b2cd68a8e7ff69d1a00cf74b15dd Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 3 Dec 2018 22:58:22 +0800 Subject: ARM: dts: sunxi: h3/h5: Fix up RTC device node and clock references The RTC module on the H3 was claimed to be the same as on the A31, when in fact it is not. The A31 does not have an RTC external clock output, and its internal RC oscillator's average clock rate is not in the same range. The H5's RTC has some extra crypto-related registers compared to the H3. Their exact functions are not clear. Also the RTC-VIO regulator has different settings. This patch fixes the compatible string and clock properties to conform to the updated bindings. The device node for the internal oscillator is removed, as it is internalized into the RTC device. Clock references to the IOSC and LOSC are also fixed. Acked-by: Maxime Ripard Tested-by: Corentin Labbe Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 26 ++++++++++---------------- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ++++ 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 7e6031768401..d50dbd5a7ffa 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -227,3 +227,7 @@ &pio { compatible = "allwinner,sun8i-h3-pinctrl"; }; + +&rtc { + compatible = "allwinner,sun8i-h3-rtc"; +}; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index f63a5ef527be..464fe36c721d 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -95,15 +95,7 @@ compatible = "fixed-clock"; clock-frequency = <32768>; clock-accuracy = <50000>; - clock-output-names = "osc32k"; - }; - - iosc: internal-osc-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-accuracy = <300000000>; - clock-output-names = "iosc"; + clock-output-names = "ext_osc32k"; }; }; @@ -377,7 +369,7 @@ ccu: clock@1c20000 { /* compatible is in per SoC .dtsi file */ reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; + clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -388,7 +380,7 @@ reg = <0x01c20800 0x400>; interrupts = , ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -791,17 +783,19 @@ }; rtc: rtc@1f00000 { - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; + /* compatible is in per SoC .dtsi file */ + reg = <0x01f00000 0x400>; interrupts = , ; + clock-output-names = "osc32k", "osc32k-out", "iosc"; + clocks = <&osc32k>; + #clock-cells = <1>; }; r_ccu: clock@1f01400 { compatible = "allwinner,sun8i-h3-r-ccu"; reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&osc32k>, <&iosc>, - <&ccu 9>; + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 9>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; #reset-cells = <1>; @@ -839,7 +833,7 @@ compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = ; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index b41dc1aab67d..fe731b35f761 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -172,3 +172,7 @@ ; compatible = "allwinner,sun50i-h5-pinctrl"; }; + +&rtc { + compatible = "allwinner,sun50i-h5-rtc"; +}; -- cgit From 5f9e882825467105acafd208520b69bf95adb963 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 3 Dec 2018 22:58:24 +0800 Subject: ARM: dts: sun8i: r40: Add RTC device node The R40 has an RTC hardware block, which has additional registers that are not related to RTC or clock functions, and is otherwise compatible with the H3's RTC. Add a device node for it, and fix up any references to the LOSC. Acked-by: Maxime Ripard Tested-by: Corentin Labbe Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-r40.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index a8917f8b1c80..89762dbefe42 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -70,7 +70,7 @@ compatible = "fixed-clock"; clock-frequency = <32768>; clock-accuracy = <20000>; - clock-output-names = "osc32k"; + clock-output-names = "ext-osc32k"; }; }; @@ -315,17 +315,27 @@ ccu: clock@1c20000 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; + clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; }; + rtc: rtc@1c20400 { + compatible = "allwinner,sun8i-r40-rtc", + "allwinner,sun8i-h3-rtc"; + reg = <0x01c20400 0x400>; + interrupts = ; + clock-output-names = "osc32k", "osc32k-out"; + clocks = <&osc32k>; + #clock-cells = <1>; + }; + pio: pinctrl@1c20800 { compatible = "allwinner,sun8i-r40-pinctrl"; reg = <0x01c20800 0x400>; interrupts = ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; -- cgit From 44ff3cafcd7f413e7710a58ac40cfdc3a9380097 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 3 Dec 2018 22:58:25 +0800 Subject: arm64: dts: allwinner: a64: Fix up RTC device node and clock references The RTC module on the A64 was claimed to be the same as on the A31, when in fact it is not. It is actually compatible to the H3's RTC. The A64's RTC has some extra crypto-related registers which the H3's does not, but the exact function of these is not clear. This patch fixes the compatible string and clock properties to conform to the updated bindings. The device node for the internal oscillator is removed, as it is internalized into the RTC device. Clock references to the IOSC and LOSC are also fixed. Acked-by: Maxime Ripard Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 22 +++++++--------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 8d024c10d7cb..837a03dee875 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -139,15 +139,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - iosc: internal-osc-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-accuracy = <300000000>; - clock-output-names = "iosc"; + clock-output-names = "ext-osc32k"; }; psci { @@ -539,7 +531,7 @@ ccu: clock@1c20000 { compatible = "allwinner,sun50i-a64-ccu"; reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; + clocks = <&osc24M>, <&rtc 0>; clock-names = "hosc", "losc"; #clock-cells = <1>; #reset-cells = <1>; @@ -969,11 +961,12 @@ }; rtc: rtc@1f00000 { - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; + compatible = "allwinner,sun50i-a64-rtc", + "allwinner,sun8i-h3-rtc"; + reg = <0x01f00000 0x400>; interrupts = , ; - clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; + clock-output-names = "osc32k", "osc32k-out", "iosc"; clocks = <&osc32k>; #clock-cells = <1>; }; @@ -990,8 +983,7 @@ r_ccu: clock@1f01400 { compatible = "allwinner,sun50i-a64-r-ccu"; reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&osc32k>, <&iosc>, - <&ccu 11>; + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; #reset-cells = <1>; -- cgit From ffa1ad89ddf2c17d777dc2abc4aa81832030df8e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Dec 2018 19:00:16 +0100 Subject: arm64: tegra: Set reg property for display-hub on Tegra186 Technically the display-hub driver could access registers via the specified region, though it practice it will do so via the display controllers' register regions. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 176dc0c128d8..22815db4a3ed 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -702,6 +702,7 @@ display-hub@15200000 { compatible = "nvidia,tegra186-display", "simple-bus"; + reg = <0x15200000 0x00040000>; resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, -- cgit From 611a1c69f8ca85fc656f09d0cd56f5934e2af5fb Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Dec 2018 19:00:17 +0100 Subject: arm64: tegra: Set reg property for display-hub on Tegra194 Technically the display-hub driver could access registers via the specified region, though it practice it will do so via the display controllers' register regions. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index b7665c4277aa..6dfa1ca0b851 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -493,6 +493,7 @@ display-hub@15200000 { compatible = "nvidia,tegra194-display", "simple-bus"; + reg = <0x15200000 0x00040000>; resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, -- cgit From 5719ac19fc32d892434939c1756c2f9a8322e6ef Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 6 Dec 2018 13:11:42 -0600 Subject: ARM: dts: sunxi: Fix PMU compatible strings "arm,cortex-a15-pmu" is not a valid fallback compatible string for an Cortex-A7 PMU, so drop it. Cc: Maxime Ripard Cc: Chen-Yu Tsai Signed-off-by: Rob Herring Acked-by: Will Deacon Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 2ca4f255adbe..353d90f99b40 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -200,7 +200,7 @@ }; pmu { - compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; + compatible = "arm,cortex-a7-pmu"; interrupts = , , , diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 86158528ed93..641a8fa6d428 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -195,7 +195,7 @@ }; pmu { - compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; + compatible = "arm,cortex-a7-pmu"; interrupts = , ; }; -- cgit From f2fb18c7cc697c3d313e4d86ceb7d5c81c1c388d Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 5 Dec 2018 14:08:37 -0800 Subject: ARM: dts: Add am335x mcasp with l3 data port ranges Earlier attempt to move am335x mcasp to probe with ti-sysc interconnect target module caused audio to stop working and and the dts changes were reverted by commit 5d2632a577ba ("ARM: dts: Revert am335x mcasp ti-sysc changes"). Turns out we were missing the l3 data port ranges for mcasp. This caused mcasp dma to attempt to use wrong port address. So let's try again essentially reverting the earlier revert and adding the missing l3 data port ranges. Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 42 ++++++++++++++++++++++++++++++++++------ arch/arm/boot/dts/am33xx.dtsi | 29 --------------------------- 2 files changed, 36 insertions(+), 35 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index fd99e2390541..bbfdd6ba039d 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -824,7 +824,9 @@ ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ <0x00100000 0x48100000 0x100000>, /* segment 1 */ <0x00200000 0x48200000 0x100000>, /* segment 2 */ - <0x00300000 0x48300000 0x100000>; /* segment 3 */ + <0x00300000 0x48300000 0x100000>, /* segment 3 */ + <0x46000000 0x46000000 0x400000>, /* l3 data port */ + <0x46400000 0x46400000 0x400000>; /* l3 data port */ segment@0 { /* 0x48000000 */ compatible = "simple-bus"; @@ -881,7 +883,9 @@ <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ - <0x000cb000 0x000cb000 0x001000>; /* ap 92 */ + <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ + <0x46000000 0x46000000 0x400000>, /* l3 data port */ + <0x46400000 0x46400000 0x400000>; /* l3 data port */ target-module@8000 { /* 0x48008000, ap 6 10.0 */ compatible = "ti,sysc"; @@ -1055,8 +1059,21 @@ clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x38000 0x2000>; - status = "disabled"; + ranges = <0x0 0x38000 0x2000>, + <0x46000000 0x46000000 0x400000>; + + mcasp0: mcasp@0 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x2000>, + <0x46000000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <80>, <81>; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 8 2>, + <&edma 9 2>; + dma-names = "tx", "rx"; + }; }; target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ @@ -1073,8 +1090,21 @@ clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x3c000 0x2000>; - status = "disabled"; + ranges = <0x0 0x3c000 0x2000>, + <0x46400000 0x46400000 0x400000>; + + mcasp1: mcasp@0 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x0 0x2000>, + <0x46400000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <82>, <83>; + interrupt-names = "tx", "rx"; + status = "disabled"; + dmas = <&edma 10 2>, + <&edma 11 2>; + dma-names = "tx", "rx"; + }; }; target-module@40000 { /* 0x48040000, ap 22 1e.0 */ diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index fc07d2d6112e..e5c2f71a7c77 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -440,36 +440,7 @@ <&edma 5 0>; dma-names = "tx", "rx"; }; - - mcasp0: mcasp@48038000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp0"; - reg = <0x48038000 0x2000>, - <0x46000000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <80>, <81>; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 8 2>, - <&edma 9 2>; - dma-names = "tx", "rx"; - }; - - mcasp1: mcasp@4803c000 { - compatible = "ti,am33xx-mcasp-audio"; - ti,hwmods = "mcasp1"; - reg = <0x4803C000 0x2000>, - <0x46400000 0x400000>; - reg-names = "mpu", "dat"; - interrupts = <82>, <83>; - interrupt-names = "tx", "rx"; - status = "disabled"; - dmas = <&edma 10 2>, - <&edma 11 2>; - dma-names = "tx", "rx"; - }; }; - }; #include "am33xx-l4.dtsi" -- cgit From 818046ebe2a7b9d5517588e08df7eaeb858decb7 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Fri, 7 Dec 2018 12:27:48 -0600 Subject: arm64: dts: qcom: msm8998: Fixup clock to use xo_board This patch sets the msm8998 xo clock name back to xo_board. Recent clock tree changes fixed the clock tree and the change to the xo name is causing issues where msm8998 boards do not boot properly. Let's change it back and leave the xo label on it. Fixes: 634da3307b08 (arm64: dts: qcom: msm8998: correct xo clock name) Signed-off-by: Andy Gross Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Reviewed-by: Jeffrey Hugo --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 49f0fee85e74..8d41b69ec2da 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -54,10 +54,11 @@ }; clocks { - xo: xo { + xo: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; + clock-output-names = "xo_board"; }; sleep_clk { -- cgit From 1504b91c819359b574b55c269c850352260b8d19 Mon Sep 17 00:00:00 2001 From: Manu Gautam Date: Thu, 31 May 2018 16:17:10 +0530 Subject: arm64: dts: msm8996: Use dwc3-qcom glue driver for USB Move from dwc3-of-simple to dwc3-qcom glue driver to support peripheral mode which requires qscratch wrapper programming on VBUS event. Fixes: a4333c3a6ba9 ("usb: dwc3: Add Qualcomm DWC3 glue driver") Signed-off-by: Manu Gautam Tested-by: Vivek Gautam Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 6 ++++-- arch/arm64/boot/dts/qcom/msm8996.dtsi | 10 ++++++---- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index bf20c55a6bc4..6d50449fbcdf 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -385,8 +385,9 @@ status = "okay"; }; - usb@6a00000 { + usb@6af8800 { status = "okay"; + extcon = <&usb3_id>; dwc3@6a00000 { extcon = <&usb3_id>; @@ -401,8 +402,9 @@ pinctrl-0 = <&usb3_vbus_det_gpio>; }; - usb@7600000 { + usb@76f8800 { status = "okay"; + extcon = <&usb2_id>; dwc3@7600000 { extcon = <&usb2_id>; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8585c61e32ef..99b7495455a6 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -893,8 +893,9 @@ status = "disabled"; }; - usb2: usb@7600000 { - compatible = "qcom,dwc3"; + usb2: usb@76f8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0x76f8800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -921,8 +922,9 @@ }; }; - usb3: usb@6a00000 { - compatible = "qcom,dwc3"; + usb3: usb@6af8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0x6af8800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges; -- cgit From de7c2fa5fc9f74a2777b3bc6397a227be755f203 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 5 Dec 2018 15:52:07 +0000 Subject: arm64: dts: meson-axg: s400: Enable PHY interrupt Now that the GPIO controller has been enabled also on AXG we can hook up the GPIO interrupt for the PHY. Tested-by: Jerome Brunet Signed-off-by: Carlo Caione Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 7759fda3ddfd..824eba98db2c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -357,6 +357,8 @@ eth_phy0: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ reg = <0>; + interrupt-parent = <&gpio_intc>; + interrupts = <98 IRQ_TYPE_LEVEL_LOW>; eee-broken-1000t; }; }; -- cgit From cbddb02e37b8bad058e1c552d4db87aa4d7c9582 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Sat, 1 Dec 2018 16:43:01 +0000 Subject: arm64: dts: meson-axg: Enable GPIO interrupt controller Enable the GPIO interrupt controller for the AXG SoCs. Signed-off-by: Carlo Caione Reviewed-by: Jerome Brunet Tested-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index f077b2102b7e..b160bd1084de 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1540,12 +1540,12 @@ }; gpio_intc: interrupt-controller@f080 { - compatible = "amlogic,meson-gpio-intc"; + compatible = "amlogic,meson-axg-gpio-intc", + "amlogic,meson-gpio-intc"; reg = <0x0 0xf080 0x0 0x10>; interrupt-controller; #interrupt-cells = <2>; amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - status = "disabled"; }; watchdog@f0d0 { -- cgit From 8b3e6f8999f8d704fccce225b9455b3fa639d1c9 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Fri, 7 Dec 2018 10:52:30 +0000 Subject: arm64: dts: meson: Fix IRQ trigger type for macirq A long running stress test on a custom board shipping an AXG SoCs and a Realtek RTL8211F PHY revealed that after a few hours the connection speed would drop drastically, from ~1000Mbps to ~3Mbps. At the same time the 'macirq' (eth0) IRQ would stop being triggered at all and as consequence the GMAC IRQs never ACKed. After a painful investigation the problem seemed to be due to a wrong defined IRQ type for the GMAC IRQ that should be LEVEL_HIGH instead of EDGE_RISING. The change in the macirq IRQ type also solved another long standing issue affecting this SoC/PHY where EEE was causing the network connection to die after stressing it with iperf3 (even though much sooner). It's now possible to remove the 'eee-broken-1000t' quirk as well. Fixes: feb3cbea0946 ("ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage") Fixes: 6d28d577510f ("ARM64: dts: meson-axg: fix ethernet stability issue") Reviewed-by: Jerome Brunet Tested-by: Jerome Brunet Acked-by: Neil Armstrong Signed-off-by: Carlo Caione Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 1 - 4 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index b160bd1084de..fffd55787981 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -166,7 +166,7 @@ compatible = "amlogic,meson-axg-dwmac", "snps,dwmac"; reg = <0x0 0xff3f0000 0x0 0x10000 0x0 0xff634540 0x0 0x8>; - interrupts = ; + interrupts = ; interrupt-names = "macirq"; clocks = <&clkc CLKID_ETH>, <&clkc CLKID_FCLK_DIV2>, diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index ed336c7a98a7..44c5c51ff1fa 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -467,7 +467,7 @@ compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; reg = <0x0 0xc9410000 0x0 0x10000 0x0 0xc8834540 0x0 0x4>; - interrupts = ; + interrupts = ; interrupt-names = "macirq"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 00f7be6d83f7..2e1cd5e3a246 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -143,7 +143,6 @@ interrupt-parent = <&gpio_intc>; /* MAC_INTR on GPIOZ_15 */ interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - eee-broken-1000t; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index 70325b273bd2..ec09bb5792b7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -142,7 +142,6 @@ eth_phy0: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ reg = <0>; - eee-broken-1000t; }; }; }; -- cgit From 26a06c6e290e0a577d82f1dd3ecdee4a838aee80 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Tue, 16 Oct 2018 07:40:29 +0000 Subject: arm64: dts: ls1012a: Add FRWY-LS1012A board support LS1012A-FRWY is an ls1012a based SoC board. Key features of this board are Micro SD, USB 3.0, upto 1GB DDR, UART Signed-off-by: Pramod Kumar Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts | 25 ++++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 46b1479b7a6b..9a88530c5f38 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts new file mode 100644 index 000000000000..8749634c55ee --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Freescale LS1012A FRWY Board. + * + * Copyright 2018 NXP + * + * Pramod Kumar + * + */ +/dts-v1/; + +#include "fsl-ls1012a.dtsi" + +/ { + model = "LS1012A FRWY Board"; + compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; +}; + +&duart0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; -- cgit From aa2aa88847154010157aa5957951ae826118d28c Mon Sep 17 00:00:00 2001 From: Bao Xiaowei Date: Mon, 5 Nov 2018 16:46:48 +0800 Subject: arm64: dts: fsl: Add the status property disable PCIe Add the status property disable the PCIe, the property will be enable by bootloader. Signed-off-by: Bao Xiaowei Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 3 +++ arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 4 ++++ 5 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 5da732f82fa0..21f2b3ba6b58 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -496,6 +496,7 @@ <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 3fed504b5381..760d510d78de 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -683,6 +683,7 @@ <0000 0 0 2 &gic 0 111 0x4>, <0000 0 0 3 &gic 0 112 0x4>, <0000 0 0 4 &gic 0 113 0x4>; + status = "disabled"; }; pcie@3500000 { @@ -708,6 +709,7 @@ <0000 0 0 2 &gic 0 121 0x4>, <0000 0 0 3 &gic 0 122 0x4>, <0000 0 0 4 &gic 0 123 0x4>; + status = "disabled"; }; pcie@3600000 { @@ -733,6 +735,7 @@ <0000 0 0 2 &gic 0 155 0x4>, <0000 0 0 3 &gic 0 156 0x4>, <0000 0 0 4 &gic 0 157 0x4>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 51cbd50012d6..64d334c6b0b4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -652,6 +652,7 @@ <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; pcie@3500000 { @@ -677,6 +678,7 @@ <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; pcie@3600000 { @@ -702,6 +704,7 @@ <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index a07f612ab56b..9deb9cb83046 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -533,6 +533,7 @@ <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; pcie@3500000 { @@ -557,6 +558,7 @@ <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; pcie@3600000 { @@ -581,6 +583,7 @@ <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; }; cluster1_core0_watchdog: wdt@c000000 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index d188774a36e8..5732e3b48be7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -648,6 +648,7 @@ <0000 0 0 2 &gic 0 0 0 110 4>, <0000 0 0 3 &gic 0 0 0 111 4>, <0000 0 0 4 &gic 0 0 0 112 4>; + status = "disabled"; }; pcie2: pcie@3500000 { @@ -669,6 +670,7 @@ <0000 0 0 2 &gic 0 0 0 115 4>, <0000 0 0 3 &gic 0 0 0 116 4>, <0000 0 0 4 &gic 0 0 0 117 4>; + status = "disabled"; }; pcie3: pcie@3600000 { @@ -690,6 +692,7 @@ <0000 0 0 2 &gic 0 0 0 120 4>, <0000 0 0 3 &gic 0 0 0 121 4>, <0000 0 0 4 &gic 0 0 0 122 4>; + status = "disabled"; }; pcie4: pcie@3700000 { @@ -711,6 +714,7 @@ <0000 0 0 2 &gic 0 0 0 125 4>, <0000 0 0 3 &gic 0 0 0 126 4>, <0000 0 0 4 &gic 0 0 0 127 4>; + status = "disabled"; }; sata0: sata@3200000 { -- cgit From 1fa35bc09d48de9dbbadf11e667adced9e461131 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 7 Nov 2018 05:35:32 +0000 Subject: arm64: dts: layerscape: removed compatible string "snps,dw-pcie" Removed the wrong compatible string "snps,dw-pcie", in case match incorrect driver. Signed-off-by: Hou Zhiqiang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 8 ++++---- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 12 ++++-------- 6 files changed, 18 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 21f2b3ba6b58..816f3a4537e3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -475,7 +475,7 @@ }; pcie@3400000 { - compatible = "fsl,ls1012a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1012a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 760d510d78de..3364a7fe18e0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -661,7 +661,7 @@ }; pcie@3400000 { - compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1043a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; @@ -687,7 +687,7 @@ }; pcie@3500000 { - compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1043a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; @@ -713,7 +713,7 @@ }; pcie@3600000 { - compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1043a-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 64d334c6b0b4..54a3827788ba 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -630,7 +630,7 @@ }; pcie@3400000 { - compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1046a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; @@ -656,7 +656,7 @@ }; pcie@3500000 { - compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1046a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; @@ -682,7 +682,7 @@ }; pcie@3600000 { - compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1046a-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 9deb9cb83046..b8b710015e15 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -512,7 +512,7 @@ }; pcie@3400000 { - compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; @@ -537,7 +537,7 @@ }; pcie@3500000 { - compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; @@ -562,7 +562,7 @@ }; pcie@3600000 { - compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index 7c882da3f6b0..a5f668d786b8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -119,7 +119,7 @@ }; &pcie1 { - compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls2088a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -128,7 +128,7 @@ }; &pcie2 { - compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls2088a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -137,7 +137,7 @@ }; &pcie3 { - compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls2088a-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ @@ -146,7 +146,7 @@ }; &pcie4 { - compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls2088a-pcie"; reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 5732e3b48be7..f3591966c347 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -630,8 +630,7 @@ }; pcie1: pcie@3400000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", - "snps,dw-pcie"; + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; interrupts = <0 108 0x4>; /* Level high type */ interrupt-names = "intr"; @@ -652,8 +651,7 @@ }; pcie2: pcie@3500000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", - "snps,dw-pcie"; + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; interrupts = <0 113 0x4>; /* Level high type */ interrupt-names = "intr"; @@ -674,8 +672,7 @@ }; pcie3: pcie@3600000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", - "snps,dw-pcie"; + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; interrupts = <0 118 0x4>; /* Level high type */ interrupt-names = "intr"; @@ -696,8 +693,7 @@ }; pcie4: pcie@3700000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", - "snps,dw-pcie"; + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; reg-names = "regs", "config"; interrupts = <0 123 0x4>; /* Level high type */ interrupt-names = "intr"; -- cgit From 8897f3255c9c411b86482e09ccbc3e75a8a201e7 Mon Sep 17 00:00:00 2001 From: Bhaskar Upadhaya Date: Wed, 14 Nov 2018 05:30:52 +0000 Subject: arm64: dts: Add support for NXP LS1028A SoC LS1028A contains two ARM v8 CortexA72 processor cores with 32 KB L1-D cache and 48 KB L1-I cache Features summary Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs - Arranged as single clusters of two cores sharing a 1 MB L2 cache - Speed Up to 1.3 GHz - Support for cluster power-gating. Cache coherent interconnect (CCI-400) - Hardware-managed data coherency - Up to 400 MHz 32-bit DDR4 SDRAM memory controller with ECC Two PCIe 3.0 controllers One serial ATA (SATA 3.0) controller Two high-speed USB 3.0 controllers with integrated PHY Following levels of DTSI/DTS files have been created for the LS1028A SoC family: - fsl-ls1028a.dtsi: DTS-Include file for NXP LS1028A SoC. - fsl-ls1028a-qds.dts: DTS file for NXP LS1028A QDS board. - fsl-ls1028a-rdb.dts: DTS file for NXP LS1028A RDB board Signed-off-by: Sudhanshu Gupta Signed-off-by: Rai Harninder Signed-off-by: Bhaskar Upadhaya Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 93 ++++++ arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 73 +++++ arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 339 ++++++++++++++++++++++ 4 files changed, 507 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 9a88530c5f38..7748e6dfc3c9 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -3,6 +3,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts new file mode 100644 index 000000000000..14c79f4691ea --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for NXP LS1028A QDS Board. + * + * Copyright 2018 NXP + * + * Harninder Rai + * + */ + +/dts-v1/; + +#include "fsl-ls1028a.dtsi" + +/ { + model = "LS1028A QDS Board"; + compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + serial0 = &duart0; + serial1 = &duart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x00000000>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + i2c-mux@77 { + compatible = "nxp,pca9847"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + current-monitor@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + current-monitor@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; + + eeprom@56 { + compatible = "atmel,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "atmel,24c512"; + reg = <0x57>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts new file mode 100644 index 000000000000..fdeb4176fc33 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for NXP LS1028A RDB Board. + * + * Copyright 2018 NXP + * + * Harninder Rai + * + */ + +/dts-v1/; +#include "fsl-ls1028a.dtsi" + +/ { + model = "LS1028A RDB Board"; + compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; + + aliases { + serial0 = &duart0; + serial1 = &duart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0000000>; + }; +}; + +&i2c0 { + status = "okay"; + + i2c-mux@77 { + compatible = "nxp,pca9847"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02>; + + current-monitor@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <500>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; + }; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi new file mode 100644 index 000000000000..a8cf92af05fb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for NXP Layerscape-1028A family SoC. + * + * Copyright 2018 NXP + * + * Harninder Rai + * + */ + +#include +#include + +/ { + compatible = "fsl,ls1028a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0>; + enable-method = "psci"; + clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PH20>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x1>; + enable-method = "psci"; + clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PH20>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + idle-states { + /* + * PSCI node is not added default, U-boot will add missing + * parts if it determines to use PSCI. + */ + entry-method = "arm,psci"; + + CPU_PH20: cpu-ph20 { + compatible = "arm,idle-state"; + idle-state-name = "PH20"; + arm,psci-suspend-param = <0x00010000>; + entry-latency-us = <1000>; + exit-latency-us = <1000>; + min-residency-us = <3000>; + }; + }; + + sysclk: clock-sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + reboot { + compatible ="syscon-reboot"; + regmap = <&dcfg>; + offset = <0xb0>; + mask = <0x02>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + gic: interrupt-controller@6000000 { + compatible= "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ + #interrupt-cells= <3>; + interrupt-controller; + interrupts = ; + its: gic-its@6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ddr: memory-controller@1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = ; + big-endian; + }; + + dcfg: syscon@1e00000 { + compatible = "fsl,ls1028a-dcfg", "syscon"; + reg = <0x0 0x1e00000 0x0 0x10000>; + big-endian; + }; + + scfg: syscon@1fc0000 { + compatible = "fsl,ls1028a-scfg", "syscon"; + reg = <0x0 0x1fc0000 0x0 0x10000>; + big-endian; + }; + + clockgen: clock-controller@1300000 { + compatible = "fsl,ls1028a-clockgen"; + reg = <0x0 0x1300000 0x0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + i2c4: i2c@2040000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2040000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + i2c5: i2c@2050000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2050000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + i2c6: i2c@2060000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2060000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + i2c7: i2c@2070000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2070000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + duart0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0500 0x0 0x100>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + duart1: serial@21c0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0600 0x0 0x100>; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + gpio1: gpio@2300000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2310000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2320000 { + compatible = "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wdog0: watchdog@23c0000 { + compatible = "fsl,ls1028a-wdt", "fsl,imx21-wdt"; + reg = <0x0 0x23c0000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + sata: sata@3200000 { + compatible = "fsl,ls1028a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>, + <0x0 0x20140520 0x0 0x4>; + reg-names = "ahci", "sata-ecc"; + interrupts = ; + clocks = <&clockgen 4 1>; + status = "disabled"; + }; + + smmu: iommu@5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #global-interrupts = <8>; + #iommu-cells = <1>; + stream-match-mask = <0x7c00>; + /* global secure fault */ + interrupts = , + /* combined secure interrupt */ + , + /* global non-secure fault */ + , + /* combined non-secure interrupt */ + , + /* performance counter interrupts 0-7 */ + , , + , , + /* per context interrupt, 64 interrupts */ + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; + }; + }; +}; -- cgit From c9a1f24304cbf6d576a0e0c379ae85e7329cd0ba Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:34:26 +0530 Subject: arm64: dts: fsl: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 ++++-- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++-- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 17 ++++++++-------- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 28 ++++++++------------------ 4 files changed, 24 insertions(+), 33 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 3364a7fe18e0..712cc27755cc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -171,8 +171,10 @@ map0 { trip = <&cpu_alert>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 54a3827788ba..8cfc84826023 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -140,8 +140,10 @@ map0 { trip = <&cpu_alert>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index b8b710015e15..42a935bac07d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -152,15 +152,14 @@ map0 { trip = <&cpu_alert>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_alert>; - cooling-device = - <&cpu4 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index f3591966c347..6d6ca166f86b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -101,26 +101,14 @@ map0 { trip = <&cpu_alert>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert>; - cooling-device = - <&cpu2 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - map2 { - trip = <&cpu_alert>; - cooling-device = - <&cpu4 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - map3 { - trip = <&cpu_alert>; - cooling-device = - <&cpu6 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; -- cgit From a2468676cc826be36d8f2ab3d593eea80f639c44 Mon Sep 17 00:00:00 2001 From: Ioana Ciocoi Radulescu Date: Tue, 4 Dec 2018 16:33:06 +0000 Subject: arm64: dts: ls1088a: Move fsl-mc node The fsl-mc node should sit under the soc node, so move it to its proper location. Fixes: ac7c9ff741fb ("arm64: dts: ls1088a: add fsl-mc hardware resource manager node") Signed-off-by: Ioana Radulescu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 142 ++++++++++++------------- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 42a935bac07d..f3ab53bb6f20 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -173,77 +173,6 @@ <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ }; - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - msi-parent = <&its>; - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - dpmacs { - #address-cells = <1>; - #size-cells = <0>; - - dpmac1: dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <1>; - }; - - dpmac2: dpmac@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <2>; - }; - - dpmac3: dpmac@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <3>; - }; - - dpmac4: dpmac@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <4>; - }; - - dpmac5: dpmac@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <5>; - }; - - dpmac6: dpmac@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <6>; - }; - - dpmac7: dpmac@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <7>; - }; - - dpmac8: dpmac@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <8>; - }; - - dpmac9: dpmac@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <9>; - }; - - dpmac10: dpmac@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; - }; - }; - }; - psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -640,6 +569,77 @@ clocks = <&clockgen 4 3>, <&clockgen 4 3>; clock-names = "apb_pclk", "wdog_clk"; }; + + fsl_mc: fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc"; + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + msi-parent = <&its>; + #address-cells = <3>; + #size-cells = <1>; + + /* + * Region type 0x0 - MC portals + * Region type 0x1 - QBMAN portals + */ + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; + + dpmacs { + #address-cells = <1>; + #size-cells = <0>; + + dpmac1: dpmac@1 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <1>; + }; + + dpmac2: dpmac@2 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <2>; + }; + + dpmac3: dpmac@3 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <3>; + }; + + dpmac4: dpmac@4 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <4>; + }; + + dpmac5: dpmac@5 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <5>; + }; + + dpmac6: dpmac@6 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <6>; + }; + + dpmac7: dpmac@7 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <7>; + }; + + dpmac8: dpmac@8 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <8>; + }; + + dpmac9: dpmac@9 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <9>; + }; + + dpmac10: dpmac@a { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xa>; + }; + }; + }; }; firmware { -- cgit From d9a71ef086e89e411ca508a69361b38beb0aafdf Mon Sep 17 00:00:00 2001 From: Ioana Ciocoi Radulescu Date: Tue, 4 Dec 2018 16:33:07 +0000 Subject: arm64: dts: ls1088a: Add missing dma-ranges property LS1088A has a 48-bit address size so make sure that the dma-ranges property reflects this. Signed-off-by: Ioana Radulescu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index f3ab53bb6f20..de93b42b1f51 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -190,6 +190,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; clockgen: clocking@1300000 { compatible = "fsl,ls1088a-clockgen"; -- cgit From 29813f669d89a1a9ae2e3e2d2cf55e12ed54853f Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Thu, 6 Dec 2018 19:18:22 +0800 Subject: arm64: dts: ls1043a: add qdma device tree nodes add the qDMA device tree nodes for LS1043A devices. Signed-off-by: Wen He Signed-off-by: Peng Ma Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 712cc27755cc..70057b4e46e8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -739,6 +739,28 @@ <0000 0 0 4 &gic 0 157 0x4>; status = "disabled"; }; + + qdma: dma-controller@8380000 { + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma"; + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ + <0x0 0x8390000 0x0 0x10000>, /* Status regs */ + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ + interrupts = , + , + , + , + ; + interrupt-names = "qdma-error", "qdma-queue0", + "qdma-queue1", "qdma-queue2", "qdma-queue3"; + dma-channels = <8>; + block-number = <1>; + block-offset = <0x10000>; + fsl,dma-queues = <2>; + status-sizes = <64>; + queue-sizes = <64 64>; + big-endian; + }; + }; firmware { -- cgit From 58f5fa68372505c8c6e57754a370f0e7e6004513 Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Thu, 6 Dec 2018 19:18:23 +0800 Subject: arm64: dts: ls1046a: add qdma device tree nodes add the qDMA device tree nodes for LS1046A devices. Signed-off-by: Wen He Signed-off-by: Peng Ma Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 8cfc84826023..9a2106e60e19 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -709,6 +709,27 @@ status = "disabled"; }; + qdma: dma-controller@8380000 { + compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ + <0x0 0x8390000 0x0 0x10000>, /* Status regs */ + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ + interrupts = , + , + , + , + ; + interrupt-names = "qdma-error", "qdma-queue0", + "qdma-queue1", "qdma-queue2", "qdma-queue3"; + dma-channels = <8>; + block-number = <1>; + block-offset = <0x10000>; + fsl,dma-queues = <2>; + status-sizes = <64>; + queue-sizes = <64 64>; + big-endian; + }; + }; reserved-memory { -- cgit From 43ebc7c1b3ed8198b9acf3019eca16e722f7331c Mon Sep 17 00:00:00 2001 From: Ding Tao Date: Fri, 26 Oct 2018 11:50:28 +0000 Subject: arm64: dts: marvell: armada-37xx: Enable emmc on espressobin The ESPRESSObin board has a emmc interface available on U11: declare it and let the bootloader enable it if the emmc is present. [gregory.clement@bootlin.com: disable the emmc by default] Signed-off-by: Ding Tao Signed-off-by: Gregory CLEMENT --- .../boot/dts/marvell/armada-3720-espressobin.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index 3ab25ad402b9..846003bb480c 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -60,9 +60,31 @@ cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; marvell,pad-type = "sd"; vqmmc-supply = <&vcc_sd_reg1>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pins>; status = "okay"; }; +/* U11 */ +&sdhci0 { + non-removable; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + marvell,xenon-emmc; + marvell,xenon-tun-count = <9>; + marvell,pad-type = "fixed-1-8v"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins>; +/* + * This eMMC is not populated on all boards, so disable it by + * default and let the bootloader enable it, if it is present + */ + status = "disabled"; +}; + &spi0 { status = "okay"; -- cgit From b1f0bbe2700051886b954192b6c1751233fe0f52 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 5 Nov 2018 17:25:41 +0000 Subject: arm64: dts: add support for Macchiatobin Single Shot board Add DT support for the Macchiatobin Single Shot board from SolidRun, which is similar to the Double Shot board, but does not have the 10G 3310 PHYs - the two ethernet ports are instead connected directly to the SFP+ cages. Signed-off-by: Russell King Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../dts/marvell/armada-8040-mcbin-singleshot.dts | 29 ++ arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 333 +------------------- arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 346 +++++++++++++++++++++ 4 files changed, 380 insertions(+), 329 deletions(-) create mode 100644 arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts create mode 100644 arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index eca8bac6303a..2eff1f927471 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -6,4 +6,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts new file mode 100644 index 000000000000..c3e18fd5bc27 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for MACCHIATOBin Armada 8040 community board platform + */ + +#include "armada-8040-mcbin.dtsi" + +/ { + model = "Marvell 8040 MACCHIATOBin Single-shot"; + compatible = "marvell,armada8040-mcbin-singleshot", + "marvell,armada8040-mcbin", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; +}; + +&cp0_eth0 { + status = "okay"; + phy-mode = "10gbase-kr"; + managed = "in-band-status"; + sfp = <&sfp_eth0>; +}; + +&cp1_eth0 { + status = "okay"; + phy-mode = "10gbase-kr"; + managed = "in-band-status"; + sfp = <&sfp_eth1>; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts index 56fa44860909..d06f5ab7ddab 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts @@ -5,226 +5,13 @@ * Device Tree file for MACCHIATOBin Armada 8040 community board platform */ -#include "armada-8040.dtsi" - -#include +#include "armada-8040-mcbin.dtsi" / { - model = "Marvell 8040 MACCHIATOBin"; - compatible = "marvell,armada8040-mcbin", "marvell,armada8040", + model = "Marvell 8040 MACCHIATOBin Double-shot"; + compatible = "marvell,armada8040-mcbin-doubleshot", + "marvell,armada8040-mcbin", "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 = &cp0_eth0; - ethernet1 = &cp1_eth0; - ethernet2 = &cp1_eth1; - ethernet3 = &cp1_eth2; - }; - - /* Regulator labels correspond with schematics */ - v_3_3: regulator-3-3v { - compatible = "regulator-fixed"; - regulator-name = "v_3_3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - status = "okay"; - }; - - v_vddo_h: regulator-1-8v { - compatible = "regulator-fixed"; - regulator-name = "v_vddo_h"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - status = "okay"; - }; - - v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_xhci_vbus_pins>; - regulator-name = "v_5v0_usb3_hst_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - status = "okay"; - }; - - usb3h0_phy: usb3_phy0 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&v_5v0_usb3_hst_vbus>; - }; - - sfp_eth0: sfp-eth0 { - /* CON15,16 - CPM lane 4 */ - compatible = "sff,sfp"; - i2c-bus = <&sfpp0_i2c>; - los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_sfpp0_pins>; - }; - - sfp_eth1: sfp-eth1 { - /* CON17,18 - CPS lane 4 */ - compatible = "sff,sfp"; - i2c-bus = <&sfpp1_i2c>; - los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>; - }; - - sfp_eth3: sfp-eth3 { - /* CON13,14 - CPS lane 5 */ - compatible = "sff,sfp"; - i2c-bus = <&sfp_1g_i2c>; - los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&ap_sdhci0 { - bus-width = <8>; - /* - * Not stable in HS modes - phy needs "more calibration", so add - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. - */ - marvell,xenon-phy-slow-mode; - no-1-8-v; - no-sd; - no-sdio; - non-removable; - status = "okay"; - vqmmc-supply = <&v_vddo_h>; -}; - -&cp0_i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c0_pins>; - status = "okay"; -}; - -&cp0_i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c1_pins>; - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - sfpp0_i2c: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - sfpp1_i2c: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - sfp_1g_i2c: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - }; -}; - -/* J25 UART header */ -&cp0_uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_uart1_pins>; - status = "okay"; -}; - -&cp0_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_ge_mdio_pins>; - status = "okay"; - - ge_phy: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cp0_pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_pcie_pins>; - num-lanes = <4>; - num-viewport = <8>; - reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&cp0_pinctrl { - cp0_ge_mdio_pins: ge-mdio-pins { - marvell,pins = "mpp32", "mpp34"; - marvell,function = "ge"; - }; - cp0_i2c1_pins: i2c1-pins { - marvell,pins = "mpp35", "mpp36"; - marvell,function = "i2c1"; - }; - cp0_i2c0_pins: i2c0-pins { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp0_uart1_pins: uart1-pins { - marvell,pins = "mpp40", "mpp41"; - marvell,function = "uart1"; - }; - cp0_xhci_vbus_pins: xhci0-vbus-pins { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - cp0_sfp_1g_pins: sfp-1g-pins { - marvell,pins = "mpp51", "mpp53", "mpp54"; - marvell,function = "gpio"; - }; - cp0_pcie_pins: pcie-pins { - marvell,pins = "mpp52"; - marvell,function = "gpio"; - }; - cp0_sdhci_pins: sdhci-pins { - marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", - "mpp60", "mpp61"; - marvell,function = "sdio"; - }; - cp0_sfpp1_pins: sfpp1-pins { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; }; &cp0_xmdio { @@ -243,46 +30,11 @@ }; }; -&cp0_ethernet { - status = "okay"; -}; - &cp0_eth0 { status = "okay"; /* Network PHY */ phy = <&phy0>; phy-mode = "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy4 0>; -}; - -&cp0_sata0 { - /* CPM Lane 0 - U29 */ - status = "okay"; -}; - -&cp0_sdhci0 { - /* U6 */ - broken-cd; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sdhci_pins>; - status = "okay"; - vqmmc-supply = <&v_3_3>; -}; - -&cp0_usb3_0 { - /* J38? - USB2.0 only */ - status = "okay"; -}; - -&cp0_usb3_1 { - /* J38? - USB2.0 only */ - status = "okay"; -}; - -&cp1_ethernet { - status = "okay"; }; &cp1_eth0 { @@ -290,81 +42,4 @@ /* Network PHY */ phy = <&phy8>; phy-mode = "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy4 0>; -}; - -&cp1_eth1 { - /* CPS Lane 0 - J5 (Gigabit RJ45) */ - status = "okay"; - /* Network PHY */ - phy = <&ge_phy>; - phy-mode = "sgmii"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy0 1>; -}; - -&cp1_eth2 { - /* CPS Lane 5 */ - status = "okay"; - /* Network PHY */ - phy-mode = "2500base-x"; - managed = "in-band-status"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy5 2>; - sfp = <&sfp_eth3>; -}; - -&cp1_pinctrl { - cp1_sfpp1_pins: sfpp1-pins { - marvell,pins = "mpp8", "mpp10", "mpp11"; - marvell,function = "gpio"; - }; - cp1_spi1_pins: spi1-pins { - marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - cp1_uart0_pins: uart0-pins { - marvell,pins = "mpp6", "mpp7"; - marvell,function = "uart0"; - }; - cp1_sfp_1g_pins: sfp-1g-pins { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - cp1_sfpp0_pins: sfpp0-pins { - marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29"; - marvell,function = "gpio"; - }; -}; - -/* J27 UART header */ -&cp1_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&cp1_uart0_pins>; - status = "okay"; -}; - -&cp1_sata0 { - /* CPS Lane 1 - U32 */ - /* CPS Lane 3 - U31 */ - status = "okay"; -}; - -&cp1_spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&cp1_spi1_pins>; - status = "okay"; - - spi-flash@0 { - compatible = "st,w25q32"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&cp1_usb3_0 { - /* CPS Lane 2 - CON7 */ - usb-phy = <&usb3h0_phy>; - status = "okay"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi new file mode 100644 index 000000000000..29ea7e81ec4c --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * + * Device Tree file for MACCHIATOBin Armada 8040 community board platform + */ + +#include "armada-8040.dtsi" + +#include + +/ { + model = "Marvell 8040 MACCHIATOBin"; + compatible = "marvell,armada8040-mcbin", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + aliases { + ethernet0 = &cp0_eth0; + ethernet1 = &cp1_eth0; + ethernet2 = &cp1_eth1; + ethernet3 = &cp1_eth2; + }; + + /* Regulator labels correspond with schematics */ + v_3_3: regulator-3-3v { + compatible = "regulator-fixed"; + regulator-name = "v_3_3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + status = "okay"; + }; + + v_vddo_h: regulator-1-8v { + compatible = "regulator-fixed"; + regulator-name = "v_vddo_h"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + status = "okay"; + }; + + v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_xhci_vbus_pins>; + regulator-name = "v_5v0_usb3_hst_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "okay"; + }; + + usb3h0_phy: usb3_phy0 { + compatible = "usb-nop-xceiv"; + vcc-supply = <&v_5v0_usb3_hst_vbus>; + }; + + sfp_eth0: sfp-eth0 { + /* CON15,16 - CPM lane 4 */ + compatible = "sff,sfp"; + i2c-bus = <&sfpp0_i2c>; + los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_sfpp0_pins>; + }; + + sfp_eth1: sfp-eth1 { + /* CON17,18 - CPS lane 4 */ + compatible = "sff,sfp"; + i2c-bus = <&sfpp1_i2c>; + los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>; + }; + + sfp_eth3: sfp-eth3 { + /* CON13,14 - CPS lane 5 */ + compatible = "sff,sfp"; + i2c-bus = <&sfp_1g_i2c>; + los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&ap_sdhci0 { + bus-width = <8>; + /* + * Not stable in HS modes - phy needs "more calibration", so add + * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. + */ + marvell,xenon-phy-slow-mode; + no-1-8-v; + no-sd; + no-sdio; + non-removable; + status = "okay"; + vqmmc-supply = <&v_vddo_h>; +}; + +&cp0_i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c0_pins>; + status = "okay"; +}; + +&cp0_i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c1_pins>; + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + sfpp0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + sfpp1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + sfp_1g_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + }; +}; + +/* J25 UART header */ +&cp0_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_uart1_pins>; + status = "okay"; +}; + +&cp0_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_ge_mdio_pins>; + status = "okay"; + + ge_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cp0_pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_pcie_pins>; + num-lanes = <4>; + num-viewport = <8>; + reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&cp0_pinctrl { + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins = "mpp32", "mpp34"; + marvell,function = "ge"; + }; + cp0_i2c1_pins: i2c1-pins { + marvell,pins = "mpp35", "mpp36"; + marvell,function = "i2c1"; + }; + cp0_i2c0_pins: i2c0-pins { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "i2c0"; + }; + cp0_uart1_pins: uart1-pins { + marvell,pins = "mpp40", "mpp41"; + marvell,function = "uart1"; + }; + cp0_xhci_vbus_pins: xhci0-vbus-pins { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + cp0_sfp_1g_pins: sfp-1g-pins { + marvell,pins = "mpp51", "mpp53", "mpp54"; + marvell,function = "gpio"; + }; + cp0_pcie_pins: pcie-pins { + marvell,pins = "mpp52"; + marvell,function = "gpio"; + }; + cp0_sdhci_pins: sdhci-pins { + marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", + "mpp60", "mpp61"; + marvell,function = "sdio"; + }; + cp0_sfpp1_pins: sfpp1-pins { + marvell,pins = "mpp62"; + marvell,function = "gpio"; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth0 { + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy4 0>; +}; + +&cp0_sata0 { + /* CPM Lane 0 - U29 */ + status = "okay"; +}; + +&cp0_sdhci0 { + /* U6 */ + broken-cd; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_sdhci_pins>; + status = "okay"; + vqmmc-supply = <&v_3_3>; +}; + +&cp0_usb3_0 { + /* J38? - USB2.0 only */ + status = "okay"; +}; + +&cp0_usb3_1 { + /* J38? - USB2.0 only */ + status = "okay"; +}; + +&cp1_ethernet { + status = "okay"; +}; + +&cp1_eth0 { + /* Generic PHY, providing serdes lanes */ + phys = <&cp1_comphy4 0>; +}; + +&cp1_eth1 { + /* CPS Lane 0 - J5 (Gigabit RJ45) */ + status = "okay"; + /* Network PHY */ + phy = <&ge_phy>; + phy-mode = "sgmii"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp1_comphy0 1>; +}; + +&cp1_eth2 { + /* CPS Lane 5 */ + status = "okay"; + /* Network PHY */ + phy-mode = "2500base-x"; + managed = "in-band-status"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp1_comphy5 2>; + sfp = <&sfp_eth3>; +}; + +&cp1_pinctrl { + cp1_sfpp1_pins: sfpp1-pins { + marvell,pins = "mpp8", "mpp10", "mpp11"; + marvell,function = "gpio"; + }; + cp1_spi1_pins: spi1-pins { + marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; + marvell,function = "spi1"; + }; + cp1_uart0_pins: uart0-pins { + marvell,pins = "mpp6", "mpp7"; + marvell,function = "uart0"; + }; + cp1_sfp_1g_pins: sfp-1g-pins { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + cp1_sfpp0_pins: sfpp0-pins { + marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29"; + marvell,function = "gpio"; + }; +}; + +/* J27 UART header */ +&cp1_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp1_uart0_pins>; + status = "okay"; +}; + +&cp1_sata0 { + /* CPS Lane 1 - U32 */ + /* CPS Lane 3 - U31 */ + status = "okay"; +}; + +&cp1_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp1_spi1_pins>; + status = "okay"; + + spi-flash@0 { + compatible = "st,w25q32"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&cp1_usb3_0 { + /* CPS Lane 2 - CON7 */ + usb-phy = <&usb3h0_phy>; + status = "okay"; +}; -- cgit From dfc1259a3f7a116b96e23e3467607c713c38a383 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 6 Dec 2018 13:19:09 +0200 Subject: arm64: dts: clearfog-gt-8k: describe mini-PCIe CON2 USB Enable the USB3 peripheral that is wired to CON2 on the Clearfog GT-8K board. Signed-off-by: Baruch Siach Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index dfb26661a88e..5b4a9609e31f 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -282,6 +282,10 @@ vqmmc-supply = <&v_3_3>; }; +&cp0_usb3_1 { + status = "okay"; +}; + &cp1_pinctrl { /* * MPP Bus: -- cgit From 738a05e673435afb986b53da43befd83ad87ec3b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 17 May 2018 17:00:10 +0200 Subject: ARM: dts: Fix up the D-Link DIR-685 MTD partition info The vendor firmware was analyzed to get the right idea about this flash layout. /proc/mtd contains: dev: size erasesize name mtd0: 01e7ff40 00020000 "rootfs" mtd1: 01f40000 00020000 "upgrade" mtd2: 00040000 00020000 "rgdb" mtd3: 00020000 00020000 "nvram" mtd4: 00040000 00020000 "RedBoot" mtd5: 00020000 00020000 "LangPack" mtd6: 02000000 00020000 "flash" Here "flash" is obviously the whole device and we know "rootfs" is a bogus hack to point to a squashfs rootfs inside of the main "upgrade partition". We know "RedBoot" is the first 0x40000 of the flash and the "upgrade" partition follows from 0x40000 to 0x1f8000. So we have mtd0, 1, 4 and 6 covered. Remains: mtd2: 00040000 00020000 "rgdb" mtd3: 00020000 00020000 "nvram" mtd5: 00020000 00020000 "LangPack" Inspecting the flash at 0x1f8000 and 0x1fa000 reveals each of these starting with "RGCFG1" so we assume 0x1f8000-1fbfff is "rgdb" of 0x40000. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-dlink-dir-685.dts | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index 6f258b50eb44..502a361d1fe9 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -274,20 +274,16 @@ read-only; }; /* - * Between the boot loader and the rootfs is the kernel - * in a custom Storlink format flashed from the boot - * menu. The rootfs is in squashfs format. + * This firmware image contains the kernel catenated + * with the squashfs root filesystem. For some reason + * this is called "upgrade" on the vendor system. */ - partition@1800c0 { - label = "rootfs"; - reg = <0x001800c0 0x01dbff40>; - read-only; - }; - partition@1f40000 { + partition@40000 { label = "upgrade"; - reg = <0x01f40000 0x00040000>; + reg = <0x00040000 0x01f40000>; read-only; }; + /* RGDB, Residental Gateway Database? */ partition@1f80000 { label = "rgdb"; reg = <0x01f80000 0x00040000>; -- cgit From 137cd7100ec6fa36d610e106df00acb4d8af99df Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 11 Oct 2018 20:06:23 +0200 Subject: ARM: dts: Enable Gemini flash access Some Gemini platforms have a parallel NOR flash which conflicts with use cases reusing some of the flash lines (such as CE1) for GPIO. Fix this on the D-Link DIR-685 and Itian SQ201 by creating "enabled" and "disabled" states for the flash pin control handle, and rely on the flash handling code to switch this in and out when accessed so these lines can be used for GPIO when flash is not accessed, and enable flash access. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-dlink-dir-685.dts | 35 ++++++++++++++++++++---------- arch/arm/boot/dts/gemini-sq201.dts | 31 ++++++++++++++------------ 2 files changed, 41 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index 502a361d1fe9..318e9b2ba7dc 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -64,7 +64,6 @@ gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>; gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>; gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>; - /* Collides with pflash CE1, not so cool */ cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; @@ -253,15 +252,18 @@ soc { flash@30000000 { /* - * Flash access is by default disabled, because it - * collides with the Chip Enable signal for the display - * panel, that reuse the parallel flash Chip Select 1 - * (CS1). Enabling flash makes graphics stop working. - * - * We might be able to hack around this by letting - * GPIO poke around in the flash controller registers. + * Flash access collides with the Chip Enable signal for + * the display panel, that reuse the parallel flash Chip + * Select 1 (CS1). We switch the pin control state so we + * enable these pins for flash access only when we need + * then, and when disabled they can be used for GPIO which + * is what the display panel needs. */ - /* status = "okay"; */ + status = "okay"; + pinctrl-names = "enabled", "disabled"; + pinctrl-0 = <&pflash_default_pins>; + pinctrl-1 = <&pflash_disabled_pins>; + /* 32MB of flash */ reg = <0x30000000 0x02000000>; @@ -327,7 +329,6 @@ "gpio0cgrp", "gpio0egrp", "gpio0fgrp", - "gpio0ggrp", "gpio0hgrp"; }; }; @@ -342,6 +343,18 @@ groups = "gpio1bgrp"; }; }; + /* + * These GPIO groups will be mapped in over some + * of the flash pins when the flash is not in + * active use. + */ + pflash_disabled_pins: pinctrl-pflash-disabled { + mux { + function = "gpio0"; + groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", + "gpio0kgrp"; + }; + }; pinctrl-gmii { mux { function = "gmii"; @@ -430,7 +443,7 @@ }; display-controller@6a000000 { - status = "okay"; + status = "disabled"; port@0 { reg = <0>; diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index 3787cf3763c4..af4be6ecb02c 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -41,14 +41,12 @@ compatible = "gpio-leds"; led-green-info { label = "sq201:green:info"; - /* Conflict with parallel flash */ gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; default-state = "on"; linux,default-trigger = "heartbeat"; }; led-green-usb { label = "sq201:green:usb"; - /* Conflict with parallel and NAND flash */ gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "usb-host"; @@ -126,15 +124,10 @@ soc { flash@30000000 { - /* - * Flash access can be enabled, with the side effect - * of disabling access to GPIO LED on GPIO0[20] which - * reuse one of the parallel flash chip select lines. - * Also the default firmware on the machine has the - * problem that since it uses the flash, the two LEDS - * on the right become numb. - */ - /* status = "okay"; */ + status = "okay"; + pinctrl-names = "enabled", "disabled"; + pinctrl-0 = <&pflash_default_pins>; + pinctrl-1 = <&pflash_disabled_pins>; /* 16MB of flash */ reg = <0x30000000 0x01000000>; @@ -184,9 +177,7 @@ mux { function = "gpio0"; groups = "gpio0fgrp", - "gpio0ggrp", - "gpio0hgrp", - "gpio0kgrp"; + "gpio0hgrp"; }; }; /* @@ -199,6 +190,18 @@ groups = "gpio1dgrp"; }; }; + /* + * These GPIO groups will be mapped in over some + * of the flash pins when the flash is not in + * active use. + */ + pflash_disabled_pins: pinctrl-pflash-disabled { + mux { + function = "gpio0"; + groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp", + "gpio0kgrp"; + }; + }; pinctrl-gmii { mux { function = "gmii"; -- cgit From d88b11ef91b15d0af9c0676cbf4f441a0dff0c56 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 19 Oct 2018 09:00:51 +0200 Subject: ARM: dts: Fix up SQ201 flash access This sets the partition information on the SQ201 to be read out from the RedBoot partition table, removes the static partition table and sets our boot options to mount root from /dev/mtdblock2 where the squashfs+JFFS2 resides. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-sq201.dts | 37 +++++-------------------------------- 1 file changed, 5 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index af4be6ecb02c..c5bb24102b75 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "console=ttyS0,115200n8"; + bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; stdout-path = &uart0; }; @@ -131,37 +131,10 @@ /* 16MB of flash */ reg = <0x30000000 0x01000000>; - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00120000>; - read-only; - }; - partition@120000 { - label = "Kernel"; - reg = <0x00120000 0x00200000>; - }; - partition@320000 { - label = "Ramdisk"; - reg = <0x00320000 0x00600000>; - }; - partition@920000 { - label = "Application"; - reg = <0x00920000 0x00600000>; - }; - partition@f20000 { - label = "VCTL"; - reg = <0x00f20000 0x00020000>; - read-only; - }; - partition@f40000 { - label = "CurConf"; - reg = <0x00f40000 0x000a0000>; - read-only; - }; - partition@fe0000 { - label = "FIS directory"; - reg = <0x00fe0000 0x00020000>; - read-only; + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0xfe0000 */ + fis-index-block = <0x1fc>; }; }; -- cgit From d6d0cef55e5b6362bd7e4fe81ea3ac1e5a48b3f4 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 21 Apr 2017 20:50:22 +0200 Subject: ARM: dts: Add the FOTG210 USB host to Gemini boards This adds the FOTG210 USB host controller to the Gemini device trees. In the main SoC DTSI it is flagged as disabled and then it is selectively enabled on the devices that utilize it. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-dlink-dir-685.dts | 8 ++++++++ arch/arm/boot/dts/gemini-nas4220b.dts | 8 ++++++++ arch/arm/boot/dts/gemini-rut1xx.dts | 20 +++++++++++++++++++ arch/arm/boot/dts/gemini-sl93512r.dts | 8 ++++++++ arch/arm/boot/dts/gemini-sq201.dts | 8 ++++++++ arch/arm/boot/dts/gemini-wbd111.dts | 8 ++++++++ arch/arm/boot/dts/gemini-wbd222.dts | 8 ++++++++ arch/arm/boot/dts/gemini.dtsi | 32 ++++++++++++++++++++++++++++++ 8 files changed, 100 insertions(+) diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index 318e9b2ba7dc..5e8e96458903 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -452,5 +452,13 @@ }; }; }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts index 963ea890c87f..53b65ebe8454 100644 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini-nas4220b.dts @@ -204,5 +204,13 @@ ata@63400000 { status = "okay"; }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts index eb4f0bf074da..b2354c215a84 100644 --- a/arch/arm/boot/dts/gemini-rut1xx.dts +++ b/arch/arm/boot/dts/gemini-rut1xx.dts @@ -124,5 +124,25 @@ /* Not used in this platform */ }; }; + + ethernet@60000000 { + status = "okay"; + + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + /* Not used in this platform */ + }; + }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini-sl93512r.dts index ebefb7297379..2bb953440793 100644 --- a/arch/arm/boot/dts/gemini-sl93512r.dts +++ b/arch/arm/boot/dts/gemini-sl93512r.dts @@ -324,5 +324,13 @@ ata@63400000 { status = "okay"; }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index c5bb24102b75..ecbc27d93b2d 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -292,5 +292,13 @@ ata@63000000 { status = "okay"; }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts index 29af86cd10f7..6831d2aed17a 100644 --- a/arch/arm/boot/dts/gemini-wbd111.dts +++ b/arch/arm/boot/dts/gemini-wbd111.dts @@ -171,5 +171,13 @@ /* Not used in this platform */ }; }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts index 24e6ae3616f7..ed38d48ef5f6 100644 --- a/arch/arm/boot/dts/gemini-wbd222.dts +++ b/arch/arm/boot/dts/gemini-wbd222.dts @@ -183,5 +183,13 @@ phy-handle = <&phy1>; }; }; + + usb@68000000 { + status = "okay"; + }; + + usb@69000000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index eb752e9495de..8cf67b11751f 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -409,5 +409,37 @@ #size-cells = <0>; status = "disabled"; }; + + usb@68000000 { + compatible = "cortina,gemini-usb", "faraday,fotg210"; + reg = <0x68000000 0x1000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_USB0>; + clocks = <&syscon GEMINI_CLK_GATE_USB0>; + clock-names = "PCLK"; + /* + * This will claim pins for USB0 and USB1 at the same + * time as they are using some common pins. If you for + * some reason have a system using USB1 at 96000000 but + * NOT using USB0 at 68000000 you wll have to add the + * usb_default_pins to the USB controller at 96000000 + * in your .dts for the board. + */ + pinctrl-names = "default"; + pinctrl-0 = <&usb_default_pins>; + syscon = <&syscon>; + status = "disabled"; + }; + + usb@69000000 { + compatible = "cortina,gemini-usb", "faraday,fotg210"; + reg = <0x69000000 0x1000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_USB1>; + clocks = <&syscon GEMINI_CLK_GATE_USB1>; + clock-names = "PCLK"; + syscon = <&syscon>; + status = "disabled"; + }; }; }; -- cgit From f18fd0f560eb3b798f9835fbd09fad1a27235e13 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 26 Aug 2018 12:45:05 +0200 Subject: ARM: dts: Bump Gemini platforms to use 100ms debounce The 50ms debounce is too low and give ghost bounces on some platforms. Bump it to 100ms to make it stable. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/gemini-dlink-dir-685.dts | 4 ++-- arch/arm/boot/dts/gemini-dlink-dns-313.dts | 2 +- arch/arm/boot/dts/gemini-nas4220b.dts | 4 ++-- arch/arm/boot/dts/gemini-rut1xx.dts | 2 +- arch/arm/boot/dts/gemini-sq201.dts | 2 +- arch/arm/boot/dts/gemini-wbd111.dts | 2 +- arch/arm/boot/dts/gemini-wbd222.dts | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts index 5e8e96458903..cc0c3cf89eaa 100644 --- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts +++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts @@ -28,7 +28,7 @@ compatible = "gpio-keys"; button-esc { - debounce-interval = <50>; + debounce-interval = <100>; wakeup-source; linux,code = ; label = "reset"; @@ -36,7 +36,7 @@ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; }; button-eject { - debounce-interval = <50>; + debounce-interval = <100>; wakeup-source; linux,code = ; label = "unmount"; diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts index d1329322b968..b12504e10f0b 100644 --- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts +++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts @@ -34,7 +34,7 @@ compatible = "gpio-keys"; button-esc { - debounce-interval = <50>; + debounce-interval = <100>; wakeup-source; linux,code = ; label = "reset"; diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts index 53b65ebe8454..f4535d635f3b 100644 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini-nas4220b.dts @@ -28,7 +28,7 @@ compatible = "gpio-keys"; button-setup { - debounce-interval = <50>; + debounce-interval = <100>; wakeup-source; linux,code = ; label = "Backup button"; @@ -36,7 +36,7 @@ gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; }; button-restart { - debounce-interval = <50>; + debounce-interval = <100>; wakeup-source; linux,code = ; label = "Softreset button"; diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts index b2354c215a84..9611ddf06792 100644 --- a/arch/arm/boot/dts/gemini-rut1xx.dts +++ b/arch/arm/boot/dts/gemini-rut1xx.dts @@ -28,7 +28,7 @@ compatible = "gpio-keys"; button-setup { - debounce-interval = <50>; + debounce-interval = <100>; wakeup-source; linux,code = ; label = "Reset to defaults"; diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts index ecbc27d93b2d..239dfacaae4d 100644 --- a/arch/arm/boot/dts/gemini-sq201.dts +++ b/arch/arm/boot/dts/gemini-sq201.dts @@ -28,7 +28,7 @@ compatible = "gpio-keys"; button-setup { - debounce-interval = <50>; + debounce-interval = <100>; wakeup-source; linux,code = ; label = "factory reset"; diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts index 6831d2aed17a..3a2761dd460f 100644 --- a/arch/arm/boot/dts/gemini-wbd111.dts +++ b/arch/arm/boot/dts/gemini-wbd111.dts @@ -29,7 +29,7 @@ compatible = "gpio-keys"; button-setup { - debounce-interval = <50>; + debounce-interval = <100>; wakeup-source; linux,code = ; label = "reset"; diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts index ed38d48ef5f6..52b4dbc0c072 100644 --- a/arch/arm/boot/dts/gemini-wbd222.dts +++ b/arch/arm/boot/dts/gemini-wbd222.dts @@ -28,7 +28,7 @@ compatible = "gpio-keys"; button-setup { - debounce-interval = <50>; + debounce-interval = <100>; wakeup-source; linux,code = ; label = "reset"; -- cgit From 6a9681168b83c62abfa457c709f2f4b126bd6b92 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 5 Nov 2018 19:14:45 -0200 Subject: ARM: dts: imx51: Fix memory node duplication Boards based on imx51 have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx51.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-apf51.dts | 1 + arch/arm/boot/dts/imx51-babbage.dts | 1 + arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 1 + arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi | 1 + arch/arm/boot/dts/imx51-ts4800.dts | 1 + arch/arm/boot/dts/imx51-zii-rdu1.dts | 1 + arch/arm/boot/dts/imx51-zii-scu2-mezz.dts | 1 + arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 1 + arch/arm/boot/dts/imx51.dtsi | 2 -- 9 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts index 79d80036f74d..1eddf2908b3f 100644 --- a/arch/arm/boot/dts/imx51-apf51.dts +++ b/arch/arm/boot/dts/imx51-apf51.dts @@ -22,6 +22,7 @@ compatible = "armadeus,imx51-apf51", "fsl,imx51"; memory@90000000 { + device_type = "memory"; reg = <0x90000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 35ee1b4247c3..ed6a3ce874b2 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -15,6 +15,7 @@ }; memory@90000000 { + device_type = "memory"; reg = <0x90000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 5761a66e8a0d..82d8df097ef1 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -17,6 +17,7 @@ compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51"; memory@90000000 { + device_type = "memory"; reg = <0x90000000 0x08000000>; }; }; diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi index f8902a338e49..2e3125391bc4 100644 --- a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi +++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi @@ -23,6 +23,7 @@ compatible = "eukrea,cpuimx51", "fsl,imx51"; memory@90000000 { + device_type = "memory"; reg = <0x90000000 0x10000000>; /* 256M */ }; }; diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts index 39eb067904c3..4344632f7940 100644 --- a/arch/arm/boot/dts/imx51-ts4800.dts +++ b/arch/arm/boot/dts/imx51-ts4800.dts @@ -18,6 +18,7 @@ }; memory@90000000 { + device_type = "memory"; reg = <0x90000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index e45a15ceb94b..3ca4f9b750b0 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -53,6 +53,7 @@ /* Will be filled by the bootloader */ memory@90000000 { + device_type = "memory"; reg = <0x90000000 0>; }; diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts index 243d1c8cab0a..aa91e5dde4b8 100644 --- a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts +++ b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts @@ -18,6 +18,7 @@ /* Will be filled by the bootloader */ memory@90000000 { + device_type = "memory"; reg = <0x90000000 0>; }; diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index 14b207778114..875b10a7d674 100644 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -18,6 +18,7 @@ /* Will be filled by the bootloader */ memory@90000000 { + device_type = "memory"; reg = <0x90000000 0>; }; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 67d462715048..7651bedabdfb 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -16,10 +16,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { ethernet0 = &fec; -- cgit From e8fd17b900a4a1e3a8bef7b44727cbad35db05a7 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 5 Nov 2018 19:14:46 -0200 Subject: ARM: dts: imx53: Fix memory node duplication Boards based on imx53 have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx53.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-ard.dts | 1 + arch/arm/boot/dts/imx53-cx9020.dts | 1 + arch/arm/boot/dts/imx53-m53.dtsi | 1 + arch/arm/boot/dts/imx53-qsb-common.dtsi | 1 + arch/arm/boot/dts/imx53-smd.dts | 1 + arch/arm/boot/dts/imx53-tqma53.dtsi | 1 + arch/arm/boot/dts/imx53-tx53.dtsi | 1 + arch/arm/boot/dts/imx53-usbarmory.dts | 1 + arch/arm/boot/dts/imx53.dtsi | 2 -- 9 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts index 117bd002dd1d..7d5a48250f86 100644 --- a/arch/arm/boot/dts/imx53-ard.dts +++ b/arch/arm/boot/dts/imx53-ard.dts @@ -19,6 +19,7 @@ compatible = "fsl,imx53-ard", "fsl,imx53"; memory@70000000 { + device_type = "memory"; reg = <0x70000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts index cf70ebc4399a..c875e23ee45f 100644 --- a/arch/arm/boot/dts/imx53-cx9020.dts +++ b/arch/arm/boot/dts/imx53-cx9020.dts @@ -22,6 +22,7 @@ }; memory@70000000 { + device_type = "memory"; reg = <0x70000000 0x20000000>, <0xb0000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi index ce45f08e3051..db2e5bce9b6a 100644 --- a/arch/arm/boot/dts/imx53-m53.dtsi +++ b/arch/arm/boot/dts/imx53-m53.dtsi @@ -16,6 +16,7 @@ compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53"; memory@70000000 { + device_type = "memory"; reg = <0x70000000 0x20000000>, <0xb0000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index 50dde84b72ed..f00dda334976 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -11,6 +11,7 @@ }; memory@70000000 { + device_type = "memory"; reg = <0x70000000 0x20000000>, <0xb0000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 462071c9ddd7..09071ca11c6c 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -12,6 +12,7 @@ compatible = "fsl,imx53-smd", "fsl,imx53"; memory@70000000 { + device_type = "memory"; reg = <0x70000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi index a72b8981fc3b..c77d58f06c94 100644 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi @@ -17,6 +17,7 @@ compatible = "tq,tqma53", "fsl,imx53"; memory@70000000 { + device_type = "memory"; reg = <0x70000000 0x40000000>; /* Up to 1GiB */ }; diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index 54cf3e67069a..4ab135906949 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -51,6 +51,7 @@ /* Will be filled by the bootloader */ memory@70000000 { + device_type = "memory"; reg = <0x70000000 0>; }; diff --git a/arch/arm/boot/dts/imx53-usbarmory.dts b/arch/arm/boot/dts/imx53-usbarmory.dts index f6268d0ded29..ee6263d1c2d3 100644 --- a/arch/arm/boot/dts/imx53-usbarmory.dts +++ b/arch/arm/boot/dts/imx53-usbarmory.dts @@ -58,6 +58,7 @@ }; memory@70000000 { + device_type = "memory"; reg = <0x70000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 207eb557c90e..930e2e14d339 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -23,10 +23,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { ethernet0 = &fec; -- cgit From 48dd72f82acaa10dddb3cddc64e6c41ae57defa3 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 6 Nov 2018 09:19:36 +0000 Subject: ARM: dts: imx6sll: remove unused property in gpc node The "fsl,mf-mix-wakeup-irq" is ONLY used as a temporary solution in NXP's internal tree for Mega/Fast Mix off feature after suspend, upstream kernel does NOT need it, remove it. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index e462f76a1c01..1292d9f0c04b 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -593,7 +593,6 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; - fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; }; iomuxc: pinctrl@20e0000 { -- cgit From 6ff9ec2fea5ff2054520029cc717bca8a93b53a7 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 6 Nov 2018 09:19:41 +0000 Subject: ARM: dts: imx6sl: vddpu is NOT an always-on regulator Remove "regulator-always-on" property for vddpu regulator since it can be OFF when GPU power domain is OFF. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 9bbc5b0adf85..557d3fda1db9 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -588,7 +588,6 @@ regulator-name = "vddpu"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; - regulator-always-on; anatop-reg-offset = <0x140>; anatop-vol-bit-shift = <9>; anatop-vol-bit-width = <5>; -- cgit From d2cf9fd301538267015fdb6a5494da0cc8979868 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 6 Nov 2018 10:03:42 -0200 Subject: ARM: dts: imx6sx: Complete the PXP support According to Documentation/devicetree/bindings/media/fsl-pxp.txt, only one PXP clock needs to be described and it should be named "axi". Also pass the compatible string as suggested in the bindings doc. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 84b7687b2d31..b79b6c452964 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -1194,11 +1194,11 @@ }; pxp: pxp@2218000 { + compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; reg = <0x02218000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_PXP_AXI>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pxp-axi", "disp-axi"; + clocks = <&clks IMX6SX_CLK_PXP_AXI>; + clock-names = "axi"; status = "disabled"; }; -- cgit From 013d37e4707e24c7b9bc3fc55aeda55ce9c2b262 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 6 Nov 2018 13:40:45 -0200 Subject: ARM: dts: imx31: Fix memory node duplication Boards based on imx31 have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx31.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Reviewed-by: Vladimir Zapolskiy Tested-by: Vladimir Zapolskiy Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx31-bug.dts | 1 + arch/arm/boot/dts/imx31-lite.dts | 1 + arch/arm/boot/dts/imx31.dtsi | 2 -- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts index 6ee4ff8e4e8f..9eb960cc02cc 100644 --- a/arch/arm/boot/dts/imx31-bug.dts +++ b/arch/arm/boot/dts/imx31-bug.dts @@ -17,6 +17,7 @@ compatible = "buglabs,imx31-bug", "fsl,imx31"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128M */ }; }; diff --git a/arch/arm/boot/dts/imx31-lite.dts b/arch/arm/boot/dts/imx31-lite.dts index db52ddccabc3..d17abdfb6330 100644 --- a/arch/arm/boot/dts/imx31-lite.dts +++ b/arch/arm/boot/dts/imx31-lite.dts @@ -18,6 +18,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index af7afccf5f2f..d7f6fb764997 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -10,10 +10,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { gpio0 = &gpio1; -- cgit From 8721610a6c2b8c42fc57819d8c3bfbb9166f95a3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 6 Nov 2018 13:40:46 -0200 Subject: ARM: dts: imx35: Fix memory node duplication Boards based on imx35 have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx35.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi | 1 + arch/arm/boot/dts/imx35-pdk.dts | 1 + arch/arm/boot/dts/imx35.dtsi | 2 -- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi index ba39d938f289..5f8a47a9fcd4 100644 --- a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi +++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi @@ -18,6 +18,7 @@ compatible = "eukrea,cpuimx35", "fsl,imx35"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128M */ }; }; diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts index df613e88fd2c..ddce0a844758 100644 --- a/arch/arm/boot/dts/imx35-pdk.dts +++ b/arch/arm/boot/dts/imx35-pdk.dts @@ -11,6 +11,7 @@ compatible = "fsl,imx35-pdk", "fsl,imx35"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x8000000>, <0x90000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index a1c3d28e8771..59cadeee23ed 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -13,10 +13,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { ethernet0 = &fec; -- cgit From 29988e867cb17de7119e971f9acfad2c3fccdb47 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 6 Nov 2018 13:40:47 -0200 Subject: ARM: dts: imx7: Fix memory node duplication Boards based on imx7 have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx7s.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 3 ++- arch/arm/boot/dts/imx7d-colibri-emmc.dtsi | 1 + arch/arm/boot/dts/imx7d-colibri.dtsi | 1 + arch/arm/boot/dts/imx7d-nitrogen7.dts | 1 + arch/arm/boot/dts/imx7d-pico.dtsi | 1 + arch/arm/boot/dts/imx7d-sdb.dts | 1 + arch/arm/boot/dts/imx7s-colibri.dtsi | 1 + arch/arm/boot/dts/imx7s-warp.dts | 1 + arch/arm/boot/dts/imx7s.dtsi | 2 -- 9 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts index 8bf365d28cac..e61567437d73 100644 --- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts +++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts @@ -19,6 +19,7 @@ compatible = "compulab,cl-som-imx7", "fsl,imx7d"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */ }; @@ -284,4 +285,4 @@ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */ >; }; -}; \ No newline at end of file +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi index 04d24ee17b14..898f4b8d7421 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi +++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi @@ -8,6 +8,7 @@ / { memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi index d9f8fb69511b..e2e327f437e3 100644 --- a/arch/arm/boot/dts/imx7d-colibri.dtsi +++ b/arch/arm/boot/dts/imx7d-colibri.dtsi @@ -45,6 +45,7 @@ / { memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; }; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index d8aac4a2d02a..4fb7e84610c7 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -12,6 +12,7 @@ compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi index 21973eb55671..4846df0783c1 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -49,6 +49,7 @@ compatible = "technexion,imx7d-pico", "fsl,imx7d"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index f1bafdaa7e1a..b1b613bb817d 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -15,6 +15,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi index fe8344cee864..1fb1ec5d3d70 100644 --- a/arch/arm/boot/dts/imx7s-colibri.dtsi +++ b/arch/arm/boot/dts/imx7s-colibri.dtsi @@ -45,6 +45,7 @@ / { memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x10000000>; }; }; diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index f7ba2c0a24ad..23431faecaf4 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -14,6 +14,7 @@ compatible = "warp,imx7s-warp", "fsl,imx7s"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index aa8df7d93b2e..477901c2061c 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -17,10 +17,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { gpio0 = &gpio1; -- cgit From 8ff7754ae1f57c50a977aab7565ab84376ed6af6 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 7 Nov 2018 05:35:17 +0000 Subject: dt-bindings: pci: layerscape-pci: add compatible strings "fsl,ls1043a-pcie" The PCIe compatible string for LS1043A was lost, so add it. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 66df1e81e0b8..5eb1c202932f 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -18,6 +18,7 @@ Required properties: "fsl,ls2088a-pcie" "fsl,ls1088a-pcie" "fsl,ls1046a-pcie" + "fsl,ls1043a-pcie" "fsl,ls1012a-pcie" - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an -- cgit From ac8ed2824e8d7655bbf4eb6d22ee08ca3f1f63d4 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 7 Nov 2018 05:35:22 +0000 Subject: dt-bindings: pci: layerscape-pci: removed compatible string "snps,dw-pcie" Removed the compatible string "snps,dw-pcie", it is for the reference platform driver for PCI RC IP Protoyping Kits based on the ARC SDP, so it is not suitable for all platform with designware PCIe controller, and platform vendors have themselves' drivers. The compatible string "snsp,dw-pcie" was added by mistake and it's not matched that time, but it is matched because PCIe drivers has been collected recently. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 5eb1c202932f..9b2b8d66d1f4 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -13,8 +13,8 @@ information. Required properties: - compatible: should contain the platform identifier such as: - "fsl,ls1021a-pcie", "snps,dw-pcie" - "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" + "fsl,ls1021a-pcie" + "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" "fsl,ls2088a-pcie" "fsl,ls1088a-pcie" "fsl,ls1046a-pcie" @@ -36,7 +36,7 @@ Required properties: Example: pcie@3400000 { - compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1021a-pcie"; reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; -- cgit From 4246bd46ee99248301297b6adf251a680059899f Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Wed, 7 Nov 2018 05:35:27 +0000 Subject: ARM: dts: ls1021a: removed compatible string "snps,dw-pcie" Removed the wrong compatible string "snps,dw-pcie", in case match incorrect driver. Signed-off-by: Hou Zhiqiang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index b769e0e40553..fc9831b90267 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -716,7 +716,7 @@ }; pcie@3400000 { - compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1021a-pcie"; reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; @@ -740,7 +740,7 @@ }; pcie@3500000 { - compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; + compatible = "fsl,ls1021a-pcie"; reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; -- cgit From 7cd1abb3ae6b84391d68edcb9acd342398ee29c2 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 7 Nov 2018 08:51:07 +0000 Subject: ARM: dts: imx6sx: specify proper clock for nodes with dummy clock From i.MX6SX reference manual CCM chapter, KPP and WDOGn use IPG clock as their clock, specify IPG clock for KPP and WDOGn instead of DUMMY clock. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index b79b6c452964..7f3022892bc1 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -558,7 +558,7 @@ compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_DUMMY>; + clocks = <&clks IMX6SX_CLK_IPG>; status = "disabled"; }; @@ -566,14 +566,14 @@ compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_DUMMY>; + clocks = <&clks IMX6SX_CLK_IPG>; }; wdog2: wdog@20c0000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_DUMMY>; + clocks = <&clks IMX6SX_CLK_IPG>; status = "disabled"; }; @@ -1270,7 +1270,7 @@ compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x02288000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_DUMMY>; + clocks = <&clks IMX6SX_CLK_IPG>; status = "disabled"; }; -- cgit From 4ca7dbdb06c1eda3ba68846c78ebbaefd70c55c0 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Thu, 18 Oct 2018 09:45:04 +0200 Subject: ARM: dts: imx: Add dummy PHYs for HSIC-only USB controllers Some SOCs in the i.MX6 family have a USB host controller that is only capable of the HSIC interface and has no on-board PHY. To be able to use these controllers, we need to add "usb-nop-xceiv" dummy PHYs. Signed-off-by: Frieder Schrempf Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/imx6sl.dtsi | 7 +++++++ arch/arm/boot/dts/imx6sx.dtsi | 6 ++++++ 3 files changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index ae94113d037e..6d827b69ead0 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -140,6 +140,16 @@ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; }; + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -984,6 +994,8 @@ reg = <0x02184400 0x200>; interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBOH3>; + fsl,usbphy = <&usbphynop1>; + phy_type = "hsic"; fsl,usbmisc = <&usbmisc 2>; dr_mode = "host"; ahb-burst-config = <0x0>; @@ -997,6 +1009,8 @@ reg = <0x02184600 0x200>; interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBOH3>; + fsl,usbphy = <&usbphynop2>; + phy_type = "hsic"; fsl,usbmisc = <&usbmisc 3>; dr_mode = "host"; ahb-burst-config = <0x0>; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 557d3fda1db9..97e49aa7b033 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -110,6 +110,11 @@ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; }; + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -814,6 +819,8 @@ reg = <0x02184400 0x200>; interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBOH3>; + fsl,usbphy = <&usbphynop1>; + phy_type = "hsic"; fsl,usbmisc = <&usbmisc 2>; dr_mode = "host"; ahb-burst-config = <0x0>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 7f3022892bc1..54262671b053 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -159,6 +159,11 @@ interrupts = ; }; + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -877,6 +882,7 @@ reg = <0x02184400 0x200>; interrupts = ; clocks = <&clks IMX6SX_CLK_USBOH3>; + fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc 2>; phy_type = "hsic"; fsl,anatop = <&anatop>; -- cgit From fd12087d4882e32f061cabf168b4dafd69d41773 Mon Sep 17 00:00:00 2001 From: Jan Tuerk Date: Tue, 27 Nov 2018 16:04:01 +0100 Subject: ARM: dts: imx: Add an cpu0 label for imx6dl devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adding the label cpu0 allows the adjustment of cpu-parameters by reference in overlaying dtsi files in the same way as it is possible for imx6q devices. Signed-off-by: Jan Tuerk Reviewed-by: Andreas Färber Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index f0607eb41df4..2ed10310a7b7 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -15,7 +15,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; -- cgit From d87cf8ce52820256dcff3a52871d67e3994e39e0 Mon Sep 17 00:00:00 2001 From: Jan Tuerk Date: Tue, 27 Nov 2018 16:04:02 +0100 Subject: dt-bindings: arm: Document emtrion emCON-MX6 bindings Document the compatible strings for emtrion emCON-MX6 SoM's. Signed-off-by: Jan Tuerk Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/emtrion.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt new file mode 100644 index 000000000000..83329aefc483 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/emtrion.txt @@ -0,0 +1,12 @@ +Emtrion Devicetree Bindings +=========================== + +emCON Series: +------------- + +Required root node properties + - compatible: + - "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base + - "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM + - "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base -- cgit From 63e71fedc07c4ece748cb0d35642df1e42ebba79 Mon Sep 17 00:00:00 2001 From: Jan Tuerk Date: Tue, 27 Nov 2018 16:04:03 +0100 Subject: ARM: dts: Add support for emtrion emCON-MX6 series This patch adds support for the emtrion GmbH emCON-MX6 modules. They are available with imx.6 Solo, Dual-Lite, Dual and Quad equipped with Memory from 512MB to 2GB (configured by U-Boot). Our default developer-Kit ships with the Avari baseboard and the EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari). The devicetree is split into the common part providing all module components and the basic support for all SoC versions (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. Finally the support for the avari baseboard in the developer-kit configuration is provided by the emcon-avari dts files. Signed-off-by: Jan Tuerk Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-emcon-avari.dts | 14 + arch/arm/boot/dts/imx6q-emcon-avari.dts | 14 + arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi | 177 ++++++ arch/arm/boot/dts/imx6qdl-emcon.dtsi | 832 +++++++++++++++++++++++++++++ 5 files changed, 1039 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts create mode 100644 arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ef9ffa44d705..db95cf7c57ae 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -396,6 +396,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ imx6dl-dfi-fs700-m60.dtb \ + imx6dl-emcon-avari.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \ @@ -460,6 +461,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-dms-ba16.dtb \ + imx6q-emcon-avari.dtb \ imx6q-evi.dtb \ imx6q-gk802.dtb \ imx6q-gw51xx.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts new file mode 100644 index 000000000000..407ad8d43c84 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (C) 2018 emtrion GmbH +// + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6qdl-emcon-avari.dtsi" + +/ { + model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts new file mode 100644 index 000000000000..0f582a9d4c0e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (C) 2018 emtrion GmbH +// + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-emcon.dtsi" +#include "imx6qdl-emcon-avari.dtsi" + +/ { + model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi b/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi new file mode 100644 index 000000000000..828cf3e39784 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon-avari.dtsi @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (C) 2018 emtrion GmbH +// + +/ { + aliases { + boardid = &boardid; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + mmc3 = &usdhc4; + }; + + reg_wall_5p0: reg-wall5p0 { + compatible = "regulator-fixed"; + regulator-name = "Main-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_base3p3: reg-base3p3 { + compatible = "regulator-fixed"; + vin-supply = <®_wall_5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_base1p5: reg-base1p5 { + compatible = "regulator-fixed"; + vin-supply = <®_base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: reg-otgvbus { + compatible = "regulator-fixed"; + vin-supply = <®_wall_5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + clk_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "emCON-avari-sgtl5000"; + ssi-controller = <&ssi2>; + audio-codec = <&sgtl5000>; + audio-routing = + "Headphone Jack", "HP_OUT"; + mux-int-port = <2>; + mux-ext-port = <3>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&ecspi2 { + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_codec>; + VDDA-supply = <®_base3p3>; + VDDIO-supply = <®_base3p3>; + }; + + captouch: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + boardid: gpio@3a { + compatible = "nxp,pca8574"; + reg = <0x3a>; + gpio-controller; + #gpio-cells = <1>; + }; +}; + +&pcie { + status = "okay"; +}; + +&rgb_encoder { + status = "okay"; +}; + +&rgb_panel { + compatible = "edt,etm0700g0bdh6"; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + uart-has-rtscts; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi new file mode 100644 index 000000000000..bfd5f373921e --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -0,0 +1,832 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (C) 2018 emtrion GmbH +// + +#include +#include +#include + +/ { + + model = "emtrion SoM emCON-MX6"; + compatible = "emtrion,emcon-mx6"; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + mmc2 = &usdhc1; + rtc0 = &ds1307; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@10000000 { + reg = <0x10000000 0x40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emcon_wake>; + + wake { + label = "Wake"; + linux,code = ; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + som_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_som_leds>; + + green { + label = "som:green"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + red { + label = "som:red"; + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + }; + + lvds_backlight: lvds-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_bl>; + enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 50000>; + brightness-levels = < + 0 4 8 16 32 64 80 96 112 + 128 144 160 176 250 + >; + default-brightness-level = <13>; + status = "okay"; + }; + + pwm_fan: pwm-fan { + compatible = "pwm-fan"; + cooling-min-state = <0>; + cooling-max-state = <4>; + #cooling-cells = <2>; + pwms = <&pwm4 0 50000>; + cooling-levels = <0 64 127 191 255>; + status = "disabled"; + }; + + + rgb_encoder: display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb24_display>; + status = "disabled"; + + port@0 { + reg = <0>; + + rgb_encoder_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + rgb_encoder_out: endpoint { + remote-endpoint = <&rgb_panel_in>; + }; + }; + }; + + rgb_panel: lcd { + backlight = <&rgb_backlight>; + power-supply = <®_parallel_disp>; + + port { + rgb_panel_in: endpoint { + remote-endpoint = <&rgb_encoder_out>; + }; + }; + }; + + reg_parallel_disp: reg-parallel-display { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl_en>; + regulator-name = "LCD-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds_disp: reg-lvds-display { + compatible = "regulator-fixed"; + regulator-name = "LVDS-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + rgb_backlight: rgb-backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgb_bl>; + enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + pwms = <&pwm3 0 5000000>; + brightness-levels = < + 250 176 160 144 128 112 + 96 80 64 48 32 16 8 1 + >; + default-brightness-level = <13>; + status = "okay"; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, + <&gpio2 27 GPIO_ACTIVE_HIGH>; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nor_flash>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + phy-reset-duration = <50>; + phy-supply = <&vdd_1V8_reg>; + phy-handle = <&ksz9031>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ksz9031: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + rxdv-skew-ps = <480>; + txen-skew-ps = <480>; + rxd0-skew-ps = <480>; + rxd1-skew-ps = <480>; + rxd2-skew-ps = <480>; + rxd3-skew-ps = <480>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <360>; + txd3-skew-ps = <360>; + txc-skew-ps = <1020>; + rxc-skew-ps = <960>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + da9063: pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + onkey { + compatible = "dlg,da9063-onkey"; + wakeup-source; + }; + + watchdog { + compatible = "dlg,da9063-watchdog"; + timeout-sec = <0>; + }; + + regulators { + vddcore_reg: bcore1 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <2>; + regulator-name = "DA9063_CORE"; + regulator-always-on; + }; + + vddsoc_reg: bcore2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <2>; + regulator-name = "DA9063_SOC"; + regulator-always-on; + }; + + vdd_ddr3_reg: bpro { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <2>; + regulator-always-on; + }; + + vdd_3v3_reg: bperi { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <2>; + regulator-always-on; + }; + + vdd_sata_reg: ldo3 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + vdd_mipi_reg: ldo4 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_mx6_snvs_reg: ldo5 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_hdmi_reg: ldo6 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pcie_reg: ldo7 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vdd_1V8_reg: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3V3_sdc_reg: ldo9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_1V2_reg: ldo10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + }; + }; + + ds1307: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&iomuxc { + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 + >; + }; + + pinctrl_cpi1: csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 + >; + }; + + /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 + >; + }; + + pinctrl_emcon_gpio1: emcongpio1 { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio2: emcongpio2 { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio3: emcongpio3 { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio4: emcongpio4 { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio5: emcongpio5 { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio6: emcongpio6 { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio7: emcongpio7 { + fsl,pins = < + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 + >; + }; + + pinctrl_emcon_gpio8: emcongpio8 { + fsl,pins = < + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_a: emconirqa { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_b: emconirqb { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_c: emconirqc { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 + >; + }; + + pinctrl_emcon_irq_pwr: emconirqpwr { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 + >; + }; + + pinctrl_emcon_wake: emconwake { + fsl,pins = < + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 + >; + }; + + pinctrl_irq_touch1: irqtouch1 { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 + >; + }; + + pinctrl_irq_touch2: irqtouch2 { + fsl,pins = < + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 + >; + }; + + pinctrl_lvds_bl: lvdsbacklightgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 + >; + }; + + pinctrl_lvds_reg: lvdsreggrp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 + >; + }; + + + pinctrl_nor_flash: norflashgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 + >; + }; + + pinctrl_pcie_ctrl: pciegrp { + fsl,pins = < + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 + >; + }; + + pinctrl_pwm_fan: pwmfan { + fsl,pins = < + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 + >; + }; + + pinctrl_rgb_bl: rgbbacklightgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 + >; + }; + + pinctrl_rgb_bl_en: rgbenable { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 + >; + }; + + pinctrl_rgb24_display: rgbgrp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_secure: securegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 + >; + }; + + pinctrl_som_leds: somledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 + >; + }; + + pinctrl_spdif_in: spdifin { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_out: spdifout { + fsl,pins = < + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usb_host1: usbhgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 + >; + }; + + pinctrl_usb_otg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 + MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 + MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&rgb_encoder_in>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_ctrl>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_host1>; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg>; + vbus-supply = <®_usb_otg>; + dr_mode = "peripheral"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + fsl,wp-controller; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + fsl,wp-controller; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + bus-width = <8>; + status = "okay"; +}; + +/******device power Management*********/ + +&cpu0 { + voltage-tolerance = <2>; +}; + +®_arm { + vin-supply = <&vddcore_reg>; +}; + +®_soc { + vin-supply = <&vddsoc_reg>; +}; + +®_pu { + vin-supply = <&vddsoc_reg>; +}; + +/*******Disabled HW following***********/ + +&snvs_rtc { + status = "disabled"; +}; -- cgit From 4d8aa0097dcc5285c4cbc2d709188dc19e967599 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:31:11 +0530 Subject: ARM: dts: ls1021a: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index fc9831b90267..29baacbccb3f 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -324,6 +324,8 @@ trip = <&cpu_alert>; cooling-device = <&cpu0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; -- cgit From 3f343ec3eabcded338b62c04eadc8173955ec64e Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 20 Nov 2018 01:35:34 +0000 Subject: ARM: dts: imx7d-sdb: add rev-a board support Current imx7d-sdb.dts has some incorrect settings about Rev-A and Rev-B boards, some of the settings are based on Rev-A board but some are based on Rev-B board, clean up it by adding i.MX7D SDB Rev-A board support, make default imx7d-sdb.dts for Rev-B board as usual, and introduce imx7d-sdb-reva.dts for Rev-A board. Below are the affected differences of Rev-A and Rev-B board: Rev-A Rev-B USB_OTG2_PWR: UART3_CTS_B GPIO1_IO07 ENET_EN_B: None GPIO1_IO04 TP_INT_B: EPDC_DATA13 EPDC_BDR1 Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx7d-sdb-reva.dts | 40 ++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx7d-sdb.dts | 28 +++++++++++++++++++++++-- 3 files changed, 67 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/imx7d-sdb-reva.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index db95cf7c57ae..fbdabfbc5213 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -574,6 +574,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-pico-pi.dtb \ imx7d-sbc-imx7.dtb \ imx7d-sdb.dtb \ + imx7d-sdb-reva.dtb \ imx7d-sdb-sht11.dtb \ imx7s-colibri-eval-v3.dtb \ imx7s-warp.dtb diff --git a/arch/arm/boot/dts/imx7d-sdb-reva.dts b/arch/arm/boot/dts/imx7d-sdb-reva.dts new file mode 100644 index 000000000000..7ce9d8c91985 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-sdb-reva.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +/dts-v1/; + +#include "imx7d-sdb.dts" + +/ { + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg_reva>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&fec2 { + /delete-property/phy-supply; +}; + +&iomuxc { + imx7d-sdb { + pinctrl_tsc2046_pendown: tsc2046_pendown { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ + >; + }; + + pinctrl_usb_otg2_vbus_reg_reva: usbotg2vbusregrevagrp { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index b1b613bb817d..202922ed3754 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -72,9 +72,11 @@ reg_usb_otg2_vbus: regulator-usb-otg2-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg2_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -115,6 +117,16 @@ gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; }; + reg_fec2_3v3: regulator-fec2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fec2-3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000 0>; @@ -211,6 +223,7 @@ assigned-clock-rates = <0>, <100000000>; phy-mode = "rgmii"; phy-handle = <ðphy1>; + phy-supply = <®_fec2_3v3>; fsl,magic-packet; status = "okay"; }; @@ -492,6 +505,12 @@ >; }; + pinctrl_enet2_reg: enet2reggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 + >; + }; + pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 @@ -514,7 +533,6 @@ pinctrl_hog: hoggrp { fsl,pins = < - MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ >; }; @@ -736,4 +754,10 @@ MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 >; }; + + pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; }; -- cgit From 76368cca639e95b1c15d3a3abcc3b72e1afdbb5a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 20 Nov 2018 13:59:42 -0200 Subject: ARM: dts: imx6ul-ccimx6ulsom: Add memory node to board dts Add memory node to board dts. This is done in preparation of removing the memory node from imx6ul.dtsi. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi index c41ecee68ad9..b5781c3656d1 100644 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi @@ -7,6 +7,11 @@ */ / { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; /* will be filled by U-Boot */ + }; + reserved-memory { #address-cells = <1>; #size-cells = <1>; -- cgit From 750d8df6e7b269b828f66631a1d39ea027afc92a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 20 Nov 2018 13:59:43 -0200 Subject: ARM: dts: imx6ul: Fix memory node duplication Boards based on imx6ul have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx6ul.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 1 + arch/arm/boot/dts/imx6ul-geam.dts | 1 + arch/arm/boot/dts/imx6ul-isiot.dtsi | 1 + arch/arm/boot/dts/imx6ul-litesom.dtsi | 1 + arch/arm/boot/dts/imx6ul-opos6ul.dtsi | 1 + arch/arm/boot/dts/imx6ul-pico-hobbit.dts | 1 + arch/arm/boot/dts/imx6ul-tx6ul.dtsi | 1 + arch/arm/boot/dts/imx6ul.dtsi | 2 -- arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 1 + arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 1 + 10 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index 32a07232c034..818021126559 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -12,6 +12,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts index e22ec5be2b78..bc77f26a2f1d 100644 --- a/arch/arm/boot/dts/imx6ul-geam.dts +++ b/arch/arm/boot/dts/imx6ul-geam.dts @@ -15,6 +15,7 @@ compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi index b1fa3f0a684d..213e802bf35c 100644 --- a/arch/arm/boot/dts/imx6ul-isiot.dtsi +++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi @@ -10,6 +10,7 @@ / { memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx6ul-litesom.dtsi b/arch/arm/boot/dts/imx6ul-litesom.dtsi index 8f775f6974d1..8d6893210842 100644 --- a/arch/arm/boot/dts/imx6ul-litesom.dtsi +++ b/arch/arm/boot/dts/imx6ul-litesom.dtsi @@ -48,6 +48,7 @@ compatible = "grinn,imx6ul-litesom", "fsl,imx6ul"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; }; diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi index a031bee311df..cf7faf4b9c47 100644 --- a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi @@ -49,6 +49,7 @@ / { memory@80000000 { + device_type = "memory"; reg = <0x80000000 0>; /* will be filled by U-Boot */ }; diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 0c09420f9951..797262d2f27f 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -53,6 +53,7 @@ /* Will be filled by the bootloader */ memory@80000000 { + device_type = "memory"; reg = <0x80000000 0>; }; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index 02b5ba42cd59..bb6dbfd5546b 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -71,6 +71,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0>; /* will be filled by U-Boot */ }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index c71d2d648c2e..99c366303d73 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -15,10 +15,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { ethernet0 = &fec1; diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi index 10ab4697950f..fb213bec4654 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi @@ -7,6 +7,7 @@ / { memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x10000000>; }; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi index 183193e8580d..038d8c90f6df 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi @@ -7,6 +7,7 @@ / { memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; -- cgit From 216f35fedd8688c8b654ebfbad18c6e64713fad7 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 20 Nov 2018 13:59:44 -0200 Subject: ARM: dts: imx6sx: Fix memory node duplication Boards based on imx6sx have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx6sx.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 1 + arch/arm/boot/dts/imx6sx-sabreauto.dts | 1 + arch/arm/boot/dts/imx6sx-sdb.dtsi | 1 + arch/arm/boot/dts/imx6sx-softing-vining-2000.dts | 1 + arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts | 1 + arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts | 1 + arch/arm/boot/dts/imx6sx-udoo-neo-full.dts | 1 + arch/arm/boot/dts/imx6sx.dtsi | 2 -- 8 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index adb5cc7d8ce2..832b5c5d7441 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -12,6 +12,7 @@ compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts index 841a27f3198f..48aede543612 100644 --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts @@ -11,6 +11,7 @@ compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index 53b3408b5fab..59b377436065 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -21,6 +21,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts index 252175b59247..2bc51623a806 100644 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -21,6 +21,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts index 40ccdf43dffc..db0feb9b9f5d 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts +++ b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts @@ -49,6 +49,7 @@ compatible = "udoo,neobasic", "fsl,imx6sx"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; }; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts index 42bfc8f8f7f6..5c7a2bb9141c 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts +++ b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts @@ -49,6 +49,7 @@ compatible = "udoo,neoextended", "fsl,imx6sx"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts index c84c877f09d4..13dfe2afaba5 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts +++ b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts @@ -49,6 +49,7 @@ compatible = "udoo,neofull", "fsl,imx6sx"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 54262671b053..6c8d2bb09025 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -15,10 +15,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { can0 = &flexcan1; -- cgit From 7fa8ab65ee15e386558ac5e971004712da91e2dd Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 20 Nov 2018 13:59:45 -0200 Subject: ARM: dts: imx6sl: Fix memory node duplication Boards based on imx6sl have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx6sl.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-evk.dts | 1 + arch/arm/boot/dts/imx6sl-warp.dts | 1 + arch/arm/boot/dts/imx6sl.dtsi | 2 -- arch/arm/boot/dts/imx6sll-evk.dts | 1 + 4 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 679b4482ab13..f7a48e4622e1 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -17,6 +17,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts index 404e602e6781..408da704c459 100644 --- a/arch/arm/boot/dts/imx6sl-warp.dts +++ b/arch/arm/boot/dts/imx6sl-warp.dts @@ -55,6 +55,7 @@ compatible = "warp,imx6sl-warp", "fsl,imx6sl"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 97e49aa7b033..e7524e73efb4 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -13,10 +13,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { ethernet0 = &fec; diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index c8e115564ba2..0c2406ac8a63 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -20,6 +20,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x80000000>; }; -- cgit From 4f6de45f1eee524d0230e49ca1c1c26865b33a31 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Tue, 20 Nov 2018 18:57:06 +0000 Subject: ARM: dts: imx6qdl-sabreauto: Enable pcie The imx6qdl-sabreauto boards have a pcie slot so let's enable it. Tested on imx6dl-sabreauto with an atk9k wifi card; scanning works. There are unhandled differences for imx6qp but imx6qp-sabreauto.dts already contains a snippet explicitly disabling the &pcie node so that can be dealt with later. Signed-off-by: Leonard Crestez Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index a10f0ad0bfb1..38f94a1dddac 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -749,6 +749,10 @@ status = "okay"; }; +&pcie { + status = "okay"; +}; + &spdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spdif>; -- cgit From 366a209c928a80c68f4a608f2f172b06ba9f9f9e Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 21 Nov 2018 07:03:44 +0000 Subject: ARM: dts: imx6sll-evk: add debug LED support On i.MX6SLL EVK board, there is a debug LED controlled by MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 pin, add support for it. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 0c2406ac8a63..da6c5ea67d03 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -32,6 +32,18 @@ status = "okay"; }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user { + label = "debug"; + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + reg_usb_otg1_vbus: regulator-otg1-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -456,6 +468,12 @@ >; }; + pinctrl_led: ledgrp { + fsl,pins = < + MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059 + >; + }; + pinctrl_pwm1: pmw1grp { fsl,pins = < MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 -- cgit From 88d22f13a66cd9a767ae83c0cf8859ade1dd621d Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 22 Nov 2018 02:55:45 +0000 Subject: ARM: dts: imx6sll-evk: use WDOG_B pin reset i.MX6SLL EVK board has WDOG_B pin connected to the PMIC; Add the WDOG_B pinctrl entry and 'fsl,ext-reset-output' property to wdog node to let watchdog trigger a system POR reset via the PMIC. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index da6c5ea67d03..d8163705363e 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -314,6 +314,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; +}; + &iomuxc { pinctrl_reg_sd3_vmmc: sd3vmmcgrp { fsl,pins = < @@ -479,4 +485,10 @@ MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 >; }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX6SLL_PAD_WDOG_B__WDOG1_B 0x170b0 + >; + }; }; -- cgit From aab5e3ea95b958cf22a24e756a84e635bdb081c1 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 23 Nov 2018 11:25:19 -0200 Subject: ARM: dts: imx50: Fix memory node duplication imx50-evk has duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx50.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50-evk.dts | 1 + arch/arm/boot/dts/imx50.dtsi | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts index 682a99783ee6..a25da415cb02 100644 --- a/arch/arm/boot/dts/imx50-evk.dts +++ b/arch/arm/boot/dts/imx50-evk.dts @@ -12,6 +12,7 @@ compatible = "fsl,imx50-evk", "fsl,imx50"; memory@70000000 { + device_type = "memory"; reg = <0x70000000 0x80000000>; }; }; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 95b7fba58300..8be4ff4ca4f8 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -22,10 +22,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { ethernet0 = &fec; -- cgit From d9359f5807971add9eb10063837b003b193b7b88 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 25 Nov 2018 18:02:44 -0200 Subject: ARM: dts: imx6qdl-wandboard: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Most of the wandboard dts files have already been converted, so switch the remaining ones. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi | 15 +++++---------- arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi | 15 +++++---------- arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi | 15 +++++---------- 3 files changed, 15 insertions(+), 30 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi index 855dc6f9df75..e781a45785ed 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi @@ -1,13 +1,8 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2013 Freescale Semiconductor, Inc. +// +// Author: Fabio Estevam #include "imx6qdl-wandboard.dtsi" diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi index 49a0a557e62e..3874e74703f0 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi @@ -1,13 +1,8 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2013 Freescale Semiconductor, Inc. +// +// Author: Fabio Estevam #include "imx6qdl-wandboard.dtsi" diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi index 69d9c8661439..93909796885a 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard-revd1.dtsi @@ -1,13 +1,8 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2013 Freescale Semiconductor, Inc. +// +// Author: Fabio Estevam #include "imx6qdl-wandboard.dtsi" -- cgit From 07a4b4600974c5473131dc3a48a532128ee094d3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 25 Nov 2018 18:02:45 -0200 Subject: ARM: dts: imx6: Switch NXP board dts to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Most of the i.MX NXP reference board dts files have already been converted, so switch the remaining ones. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sdb-reva.dts | 10 +++----- arch/arm/boot/dts/imx6sx-sdb-sai.dts | 43 +++------------------------------ arch/arm/boot/dts/imx6sx-sdb.dts | 10 +++----- arch/arm/boot/dts/imx6sx-sdb.dtsi | 10 +++----- arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 10 +++----- arch/arm/boot/dts/imx6ull-14x14-evk.dts | 43 +++------------------------------ 6 files changed, 18 insertions(+), 108 deletions(-) diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index 9cc6ff206aea..9db930694c0e 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. #include "imx6sx-sdb.dtsi" diff --git a/arch/arm/boot/dts/imx6sx-sdb-sai.dts b/arch/arm/boot/dts/imx6sx-sdb-sai.dts index 2ac865b7c364..1c4eacd68e1b 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-sai.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-sai.dts @@ -1,43 +1,6 @@ -/* - * Copyright (C) 2016 NXP Semiconductors - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2016 Freescale Semiconductor, Inc. #include "imx6sx-sdb.dts" diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 6dd9bebfe027..96bd6375c5aa 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. #include "imx6sx-sdb.dtsi" diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index 59b377436065..e156ea11d042 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. /dts-v1/; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index 818021126559..095568b30d30 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. / { chosen { diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts index 0ba64546c13b..74aaa8a56a3d 100644 --- a/arch/arm/boot/dts/imx6ull-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ull-14x14-evk.dts @@ -1,43 +1,6 @@ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2016 Freescale Semiconductor, Inc. /dts-v1/; -- cgit From b629e83520fafe6f4c2f3e8c88c78a496fc4987c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 26 Nov 2018 10:08:55 -0200 Subject: ARM: dts: imx23: Fix memory node duplication Boards based on imx23 have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx23.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx23-evk.dts | 1 + arch/arm/boot/dts/imx23-olinuxino.dts | 1 + arch/arm/boot/dts/imx23-sansa.dts | 1 + arch/arm/boot/dts/imx23-stmp378x_devb.dts | 1 + arch/arm/boot/dts/imx23-xfi3.dts | 1 + arch/arm/boot/dts/imx23.dtsi | 2 -- 6 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 98efe1aeb26a..0b2701ca2921 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -10,6 +10,7 @@ compatible = "fsl,imx23-evk", "fsl,imx23"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts index 31b1e3581ac0..e2bac4d8f507 100644 --- a/arch/arm/boot/dts/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -20,6 +20,7 @@ compatible = "olimex,imx23-olinuxino", "fsl,imx23"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/imx23-sansa.dts index faf701b2adb2..46057d9bf555 100644 --- a/arch/arm/boot/dts/imx23-sansa.dts +++ b/arch/arm/boot/dts/imx23-sansa.dts @@ -50,6 +50,7 @@ compatible = "sandisk,sansa_fuze_plus", "fsl,imx23"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts index 2ff6cdf71a55..df2a9e6486a4 100644 --- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts +++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts @@ -17,6 +17,7 @@ compatible = "fsl,stmp378x-devb", "fsl,imx23"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/imx23-xfi3.dts index db53089fb7fb..a6213c590f94 100644 --- a/arch/arm/boot/dts/imx23-xfi3.dts +++ b/arch/arm/boot/dts/imx23-xfi3.dts @@ -49,6 +49,7 @@ compatible = "creative,x-fi3", "fsl,imx23"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index ea259927eef6..8257630f7a49 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -13,10 +13,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { gpio0 = &gpio0; -- cgit From 32018d1525c6b8bcdb0fd99bf61f4e56c3d25963 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 26 Nov 2018 10:08:56 -0200 Subject: ARM: dts: imx28: Fix memory node duplication Boards based on imx28 have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx28.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-apf28.dts | 1 + arch/arm/boot/dts/imx28-apx4devkit.dts | 1 + arch/arm/boot/dts/imx28-cfa10036.dts | 1 + arch/arm/boot/dts/imx28-duckbill-2-485.dts | 1 + arch/arm/boot/dts/imx28-duckbill-2-enocean.dts | 1 + arch/arm/boot/dts/imx28-duckbill-2-spi.dts | 1 + arch/arm/boot/dts/imx28-duckbill-2.dts | 1 + arch/arm/boot/dts/imx28-duckbill.dts | 1 + arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts | 1 + arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts | 1 + arch/arm/boot/dts/imx28-evk.dts | 1 + arch/arm/boot/dts/imx28-m28.dtsi | 1 + arch/arm/boot/dts/imx28-m28cu3.dts | 1 + arch/arm/boot/dts/imx28-m28evk.dts | 1 + arch/arm/boot/dts/imx28-sps1.dts | 1 + arch/arm/boot/dts/imx28-ts4600.dts | 1 + arch/arm/boot/dts/imx28-tx28.dts | 1 + arch/arm/boot/dts/imx28.dtsi | 2 -- 18 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts index bab78346fa9f..b6976fbec983 100644 --- a/arch/arm/boot/dts/imx28-apf28.dts +++ b/arch/arm/boot/dts/imx28-apf28.dts @@ -17,6 +17,7 @@ compatible = "armadeus,imx28-apf28", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index 6c9b498305c0..3a184d13887b 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -7,6 +7,7 @@ compatible = "bluegiga,apx4devkit", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index 8337ca21e281..d3e3622979c5 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -17,6 +17,7 @@ compatible = "crystalfontz,cfa10036", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/imx28-duckbill-2-485.dts index f4f2b3d16c8e..19957c2406e8 100644 --- a/arch/arm/boot/dts/imx28-duckbill-2-485.dts +++ b/arch/arm/boot/dts/imx28-duckbill-2-485.dts @@ -20,6 +20,7 @@ compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts index 71d0fcbc2d8c..498213137385 100644 --- a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts +++ b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts @@ -21,6 +21,7 @@ compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts index 6580ec6e26ba..d38d35b2a93d 100644 --- a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts +++ b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts @@ -24,6 +24,7 @@ }; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/imx28-duckbill-2.dts index 693634edae99..38160fbd44b6 100644 --- a/arch/arm/boot/dts/imx28-duckbill-2.dts +++ b/arch/arm/boot/dts/imx28-duckbill-2.dts @@ -20,6 +20,7 @@ compatible = "i2se,duckbill-2", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts index 16f524428ed7..7139c07ae19b 100644 --- a/arch/arm/boot/dts/imx28-duckbill.dts +++ b/arch/arm/boot/dts/imx28-duckbill.dts @@ -19,6 +19,7 @@ compatible = "i2se,duckbill", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts index b70f3349c350..28dab6d3a97c 100644 --- a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts +++ b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts @@ -24,6 +24,7 @@ compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x04000000>; }; }; diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts index 65efb78ac040..7c3d55277312 100644 --- a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts +++ b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts @@ -23,6 +23,7 @@ compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; }; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 5778300f44e8..96c1d106bc64 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -10,6 +10,7 @@ compatible = "fsl,imx28-evk", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi index 0ec415e1ff58..298ad28caceb 100644 --- a/arch/arm/boot/dts/imx28-m28.dtsi +++ b/arch/arm/boot/dts/imx28-m28.dtsi @@ -16,6 +16,7 @@ compatible = "aries,m28", "denx,m28", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts index 8883d36a51b5..ece33103a517 100644 --- a/arch/arm/boot/dts/imx28-m28cu3.dts +++ b/arch/arm/boot/dts/imx28-m28cu3.dts @@ -17,6 +17,7 @@ compatible = "msr,m28cu3", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 893886d17b2d..7d64301529c7 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -1,4 +1,5 @@ /* + * Copyright (C) 2012 Marek Vasut * * The code contained herein is licensed under the GNU General Public diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts index ea9212f6ecda..42c88a67912b 100644 --- a/arch/arm/boot/dts/imx28-sps1.dts +++ b/arch/arm/boot/dts/imx28-sps1.dts @@ -17,6 +17,7 @@ compatible = "schulercontrol,imx28-sps1", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts index dccdd6bcd0b2..e3fd4112e642 100644 --- a/arch/arm/boot/dts/imx28-ts4600.dts +++ b/arch/arm/boot/dts/imx28-ts4600.dts @@ -20,6 +20,7 @@ compatible = "technologic,imx28-ts4600", "fsl,imx28"; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0x10000000>; /* 256MB */ }; diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index b8f46432e2a2..164254c28f8e 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -66,6 +66,7 @@ }; memory@40000000 { + device_type = "memory"; reg = <0x40000000 0>; /* will be filled in by U-Boot */ }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 2b7efb659fc0..e14d8ef0158b 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -14,10 +14,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { ethernet0 = &mac0; -- cgit From 62864d5665c4fc636d3021f829b3ac00fa058e30 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 26 Nov 2018 10:40:52 -0200 Subject: ARM: dts: imx1: Fix memory node duplication Boards based on imx1 have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx1.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx1-ads.dts | 1 + arch/arm/boot/dts/imx1-apf9328.dts | 1 + arch/arm/boot/dts/imx1.dtsi | 2 -- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts index a1d81badb5c8..119b19ba53b6 100644 --- a/arch/arm/boot/dts/imx1-ads.dts +++ b/arch/arm/boot/dts/imx1-ads.dts @@ -21,6 +21,7 @@ }; memory@8000000 { + device_type = "memory"; reg = <0x08000000 0x04000000>; }; }; diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts index 11515c0cb195..ee4b1b106b1a 100644 --- a/arch/arm/boot/dts/imx1-apf9328.dts +++ b/arch/arm/boot/dts/imx1-apf9328.dts @@ -21,6 +21,7 @@ }; memory@8000000 { + device_type = "memory"; reg = <0x08000000 0x00800000>; }; }; diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi index b00ece16b853..b30448cde582 100644 --- a/arch/arm/boot/dts/imx1.dtsi +++ b/arch/arm/boot/dts/imx1.dtsi @@ -15,10 +15,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { gpio0 = &gpio1; -- cgit From 38715dcd49b4430ac5b6bc1293278d91a4d32bd5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 26 Nov 2018 10:40:53 -0200 Subject: ARM: dts: imx27: Fix memory node duplication Boards based on imx27 have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx27.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-apf27.dts | 1 + arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi | 1 + arch/arm/boot/dts/imx27-pdk.dts | 1 + arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi | 1 + arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 1 + arch/arm/boot/dts/imx27.dtsi | 2 -- 6 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts index 3eddd805a793..f635d5c5029c 100644 --- a/arch/arm/boot/dts/imx27-apf27.dts +++ b/arch/arm/boot/dts/imx27-apf27.dts @@ -20,6 +20,7 @@ compatible = "armadeus,imx27-apf27", "fsl,imx27"; memory@a0000000 { + device_type = "memory"; reg = <0xa0000000 0x04000000>; }; }; diff --git a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi index 9c455dcbe6eb..c85f9d01768a 100644 --- a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi +++ b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi @@ -17,6 +17,7 @@ compatible = "eukrea,cpuimx27", "fsl,imx27"; memory@a0000000 { + device_type = "memory"; reg = <0xa0000000 0x04000000>; }; diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index f9a882d99132..35123b7cb6b3 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -10,6 +10,7 @@ compatible = "fsl,imx27-pdk", "fsl,imx27"; memory@a0000000 { + device_type = "memory"; reg = <0xa0000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi index cbad7c88c58c..b0b4f7c00246 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi @@ -18,6 +18,7 @@ compatible = "phytec,imx27-pca100", "fsl,imx27"; memory@a0000000 { + device_type = "memory"; reg = <0xa0000000 0x08000000>; /* 128MB */ }; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index ec466b4bfd41..0935e1400e5d 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -17,6 +17,7 @@ compatible = "phytec,imx27-pcm038", "fsl,imx27"; memory@a0000000 { + device_type = "memory"; reg = <0xa0000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 151b0eb17dda..26ff5d419bfc 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -16,10 +16,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { ethernet0 = &fec; -- cgit From 59d8bb363f563e4a147a291037bf979cb8ff9a59 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 26 Nov 2018 10:40:54 -0200 Subject: ARM: dts: imx25: Fix memory node duplication Boards based on imx25 have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the imx25.dtsi file. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi | 1 + arch/arm/boot/dts/imx25-karo-tx25.dts | 1 + arch/arm/boot/dts/imx25-pdk.dts | 1 + arch/arm/boot/dts/imx25.dtsi | 2 -- 4 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi index e316fe08837a..e4d7da267532 100644 --- a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi +++ b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi @@ -18,6 +18,7 @@ compatible = "eukrea,cpuimx25", "fsl,imx25"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x4000000>; /* 64M */ }; }; diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts index 5cb6967866c0..f37e9a75a3ca 100644 --- a/arch/arm/boot/dts/imx25-karo-tx25.dts +++ b/arch/arm/boot/dts/imx25-karo-tx25.dts @@ -37,6 +37,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x02000000 0x90000000 0x02000000>; }; }; diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index a5626b46ac4e..f8544a9e4633 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -12,6 +12,7 @@ compatible = "fsl,imx25-pdk", "fsl,imx25"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index e80101847aff..9a097ef014af 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -12,10 +12,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { ethernet0 = &fec; -- cgit From 429c4580287c4a73c7a0065210a08871f7a928bd Mon Sep 17 00:00:00 2001 From: Alex Gonzalez Date: Thu, 25 Oct 2018 17:09:31 +0200 Subject: ARM: dts: ccimx6ulsbcpro: Enable AUO G101EVN010 lcdif panel This change adds support for the AUO G101EVN010 lcdif panel for the mxsfb DRM driver. Signed-off-by: Alex Gonzalez Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts index 11966d12af76..f6e6b2cf780b 100644 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts @@ -24,6 +24,18 @@ status = "okay"; }; + panel { + compatible = "auo,g101evn010", "simple-panel"; + power-supply = <&ldo4_ext>; + backlight = <&lcd_backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + reg_usb_otg1_vbus: regulator-usb-otg1 { compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; @@ -112,6 +124,12 @@ &pinctrl_lcdif_hvsync>; lcd-supply = <&ldo4_ext>; /* BU90T82 LVDS bridge power */ status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; }; &ldo4_ext { -- cgit From 7ccdc892104eb897abb5c5ce24f99e7d15ac069e Mon Sep 17 00:00:00 2001 From: Alex Gonzalez Date: Thu, 25 Oct 2018 17:09:33 +0200 Subject: ARM: dts: ccimx6ulsbcpro: Add support for Goodix touch controller The ConnectCore 6UL SBC Pro has an AUO/Goodix LCD accessory kit that is connected on the LVDS interface through an on-board LVDS transceiver. This change adds support for the touch interface. Signed-off-by: Alex Gonzalez Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts index f6e6b2cf780b..3749fdda3611 100644 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts @@ -117,6 +117,19 @@ }; }; +&i2c1 { + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_goodix_touch>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + irq-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat0_17 @@ -290,6 +303,12 @@ >; }; + pinctrl_goodix_touch: goodixgrp{ + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1020 + >; + }; + pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 { fsl,pins = < MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 -- cgit From f820ca29bfde05be286c346fdea69bd2a7b592c3 Mon Sep 17 00:00:00 2001 From: Patrick Havelange Date: Tue, 27 Nov 2018 15:09:44 +0100 Subject: ARM: dts: ls1021a: add nodes for PWMs The LS1021A has 8 possible PWMs, so adding them (disabled by default) Signed-off-by: Patrick Havelange Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 96 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 29baacbccb3f..82abf0abeb28 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -527,6 +527,102 @@ status = "disabled"; }; + pwm0: pwm@29d0000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x29d0000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm1: pwm@29e0000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x29e0000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm2: pwm@29f0000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x29f0000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm3: pwm@2a00000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a00000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm4: pwm@2a10000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a10000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm5: pwm@2a20000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a20000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm6: pwm@2a30000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a30000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + + pwm7: pwm@2a40000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x0 0x2a40000 0x0 0x10000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + status = "disabled"; + }; + wdog0: watchdog@2ad0000 { compatible = "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; -- cgit From 88dddae62eefb309391e2b442c3dd077a12aa35a Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Wed, 28 Nov 2018 11:03:48 +0000 Subject: ARM: dts: imx6sx-sdb: add flexcan support CAN transceiver is different on RevA and RevB board. It's active high on RevA while active low on Rev B. Signed-off-by: Aisheng Dong Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sdb-reva.dts | 12 ++++++++++ arch/arm/boot/dts/imx6sx-sdb.dts | 5 +++++ arch/arm/boot/dts/imx6sx-sdb.dtsi | 42 +++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index 9db930694c0e..53241ae09ee9 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -138,3 +138,15 @@ spi-max-frequency = <66000000>; }; }; + +®_can_en { + /* Transceiver EN/STBY is active high on RevA board */ + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +®_can_stby { + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 96bd6375c5aa..b1b33ad001d9 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -132,3 +132,8 @@ ®_soc { vin-supply = <&sw1a_reg>; }; + +®_can_stby { + /* Transceiver EN/STBY is active low on RevB board */ + gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index e156ea11d042..a146f8694fc7 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -135,6 +135,20 @@ regulator-max-microvolt = <5000000>; }; + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + sound { compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; @@ -201,6 +215,20 @@ status = "okay"; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + &i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -396,6 +424,20 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + pinctrl_gpio_keys: gpio_keysgrp { fsl,pins = < MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 -- cgit From 57ab56fa0b94c6e08e029fdf508db79511c81da4 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Wed, 28 Nov 2018 11:03:52 +0000 Subject: ARM: dts: imx6sx-sabreauto: add flexcan support The CAN transceiver on MX6SX Sabreauto board seems in sleep mode by default after power up the board. User has to press the wakeup key on ARD baseboard before using the transceiver, or it may not work properly when power up the board at the first time(warm reset does not have such issue). This patch operates the wake pin too besides stby/en pins by chaining them together in regulator mode. Signed-off-by: Aisheng Dong Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sabreauto.dts | 57 ++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts index 48aede543612..b0ee324afe58 100644 --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts @@ -37,6 +37,35 @@ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_can_wake: regulator-can-wake { + compatible = "regulator-fixed"; + regulator-name = "can-wake"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_wake>; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; }; &anaclk2 { @@ -76,6 +105,20 @@ status = "okay"; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -150,6 +193,20 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 -- cgit From 577f0104e3fc7fd6120432a85d7a4ed41f60e28d Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Wed, 28 Nov 2018 11:03:56 +0000 Subject: ARM: dts: imx6qdl-sabreauto: add flexcan support The flexcan1 is pin conflict with fec. User would make flexcan1 enabled with fec disabled to use CAN. Signed-off-by: Aisheng Dong Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 47 ++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 38f94a1dddac..a031023a8c52 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -101,6 +101,25 @@ enable-active-high; }; + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + sound-cs42888 { compatible = "fsl,imx6-sabreauto-cs42888", "fsl,imx-audio-cs42888"; @@ -279,6 +298,20 @@ status = "okay"; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "disabled"; /* pin conflict with fec */ +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; @@ -494,6 +527,20 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059 + >; + }; + pinctrl_gpio_keys: gpiokeysgrp { fsl,pins = < MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 -- cgit From 9a79142655a420d4ad567d459755c09a90aba003 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 29 Nov 2018 09:18:13 -0200 Subject: ARM: dts: imx50: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 8be4ff4ca4f8..ee1e3e8bf4ec 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -1,15 +1,8 @@ -/* - * Copyright 2013 Greg Ungerer - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2013 Greg Ungerer +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. #include "imx50-pinfunc.h" #include -- cgit From f46af111c6948a842708d68d16564666ea2d1c68 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 29 Nov 2018 09:18:14 -0200 Subject: ARM: dts: imx53: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 930e2e14d339..a9804c08e6a8 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -1,14 +1,7 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2011 Freescale Semiconductor, Inc. +// Copyright 2011 Linaro Ltd. #include "imx53-pinfunc.h" #include -- cgit From 0c29339d53bf7cf3b96847081ad7f64e835de4d4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 3 Dec 2018 15:40:19 -0200 Subject: ARM: dts: imx6ul: Correct mask for GIC PPI interrupts The GIC_CPU_MASK_SIMPLE() macro should take as its argument the actual number of CPU cores the interrupt controller is wired to. i.MX6UL contains a single Cortex-A7, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(1)". Tested on a imx6ul-evk. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 99c366303d73..0efc85f1bb95 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -94,7 +94,7 @@ intc: interrupt-controller@a01000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; - interrupts = ; + interrupts = ; #interrupt-cells = <3>; interrupt-controller; interrupt-parent = <&intc>; @@ -106,10 +106,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-parent = <&intc>; status = "disabled"; }; -- cgit From d7f3894f0e46802ea55af4b859b9606d3a6bb107 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 3 Dec 2018 15:40:20 -0200 Subject: ARM: dts: imx7: Correct mask for GIC PPI interrupts The GIC_CPU_MASK_SIMPLE() macro should take as its argument the actual number of CPU cores the interrupt controller is wired to. i.MX7S contains a single Cortex-A7, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(1)". Likewise, i.MX7D contains two Cortex-A7 cores, so it should use "GIC_CPU_MASK_SIMPLE(2)" instead. Tested on a imx7s-warp. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/imx7s.dtsi | 10 +++++----- 2 files changed, 26 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 826224bf7f4f..6b298e388f4b 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -24,6 +24,15 @@ }; }; + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + }; + cpu0_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared; @@ -72,6 +81,18 @@ }; }; }; + + intc: interrupt-controller@31001000 { + compatible = "arm,cortex-a7-gic"; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + reg = <0x31001000 0x1000>, + <0x31002000 0x2000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; + }; }; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 477901c2061c..098d2cc1d2c5 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -160,10 +160,10 @@ timer { compatible = "arm,armv7-timer"; interrupt-parent = <&intc>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; soc { @@ -305,7 +305,7 @@ intc: interrupt-controller@31001000 { compatible = "arm,cortex-a7-gic"; - interrupts = ; + interrupts = ; #interrupt-cells = <3>; interrupt-controller; interrupt-parent = <&intc>; -- cgit From f535d100985548e8458cf28027198b71709a1ebe Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 30 Nov 2018 22:44:52 -0200 Subject: ARM: dts: vf: Fix memory node duplication Boards based on vf500/vf600 have duplicate memory nodes: - One coming from the board dts file: memory@ - One coming from the vf500.dtsi/vf610m4.dtsi files. Fix the duplication by removing the memory node from the dtsi file and by adding 'device_type = "memory";' in the board dts. Reported-by: Rob Herring Signed-off-by: Fabio Estevam Reviewed-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf500-colibri.dtsi | 1 + arch/arm/boot/dts/vf500.dtsi | 1 - arch/arm/boot/dts/vf610-bk4.dts | 1 + arch/arm/boot/dts/vf610-colibri.dtsi | 1 + arch/arm/boot/dts/vf610-cosmic.dts | 1 + arch/arm/boot/dts/vf610-twr.dts | 1 + arch/arm/boot/dts/vf610-zii-cfu1.dts | 1 + arch/arm/boot/dts/vf610-zii-dev.dtsi | 1 + arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 1 + arch/arm/boot/dts/vf610m4-colibri.dts | 1 + arch/arm/boot/dts/vf610m4.dtsi | 1 - 11 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi index 2e7e3cebba1c..237b0246fa84 100644 --- a/arch/arm/boot/dts/vf500-colibri.dtsi +++ b/arch/arm/boot/dts/vf500-colibri.dtsi @@ -47,6 +47,7 @@ compatible = "toradex,vf610-colibri_vf50", "fsl,vf500"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi index 76a0949df4a8..b0ec475017ad 100644 --- a/arch/arm/boot/dts/vf500.dtsi +++ b/arch/arm/boot/dts/vf500.dtsi @@ -10,7 +10,6 @@ #size-cells = <1>; chosen { }; aliases { }; - memory { device_type = "memory"; }; cpus { #address-cells = <1>; diff --git a/arch/arm/boot/dts/vf610-bk4.dts b/arch/arm/boot/dts/vf610-bk4.dts index cab95714c058..689c8930dce3 100644 --- a/arch/arm/boot/dts/vf610-bk4.dts +++ b/arch/arm/boot/dts/vf610-bk4.dts @@ -16,6 +16,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi index aeaf99f1f0fc..05c9a39509b8 100644 --- a/arch/arm/boot/dts/vf610-colibri.dtsi +++ b/arch/arm/boot/dts/vf610-colibri.dtsi @@ -47,6 +47,7 @@ compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x10000000>; }; }; diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts index a3014e8d97a9..ea1b996a6bca 100644 --- a/arch/arm/boot/dts/vf610-cosmic.dts +++ b/arch/arm/boot/dts/vf610-cosmic.dts @@ -20,6 +20,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index 59fceea8805d..dbb5ffcdcec4 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -14,6 +14,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index b76c3d0413df..7cdcc5fe8282 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -16,6 +16,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi index 5ae5abfe1d55..19eb4a849efb 100644 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi @@ -50,6 +50,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index fe357668865b..757af56e8ee7 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -24,6 +24,7 @@ }; memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/vf610m4-colibri.dts b/arch/arm/boot/dts/vf610m4-colibri.dts index 41ec66a96990..607c60267364 100644 --- a/arch/arm/boot/dts/vf610m4-colibri.dts +++ b/arch/arm/boot/dts/vf610m4-colibri.dts @@ -55,6 +55,7 @@ }; memory@8c000000 { + device_type = "memory"; reg = <0x8c000000 0x3000000>; }; }; diff --git a/arch/arm/boot/dts/vf610m4.dtsi b/arch/arm/boot/dts/vf610m4.dtsi index 8293276b55a6..76bbfd5e32b6 100644 --- a/arch/arm/boot/dts/vf610m4.dtsi +++ b/arch/arm/boot/dts/vf610m4.dtsi @@ -50,7 +50,6 @@ #size-cells = <1>; chosen { }; aliases { }; - memory { device_type = "memory"; }; }; &mscm_ir { -- cgit From 1b9c329e1d02a0175f8bb77729ff13ba832d9752 Mon Sep 17 00:00:00 2001 From: Peng Ma Date: Tue, 30 Oct 2018 10:36:01 +0800 Subject: ARM: dts: ls1021a: add qdma device tree nodes add the qDMA device tree nodes for LS1021A devices. Signed-off-by: Wen He Signed-off-by: Peng Ma Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 82abf0abeb28..ed0941292172 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -912,5 +912,25 @@ #size-cells = <1>; ranges = <0x0 0x0 0x10010000 0x10000>; }; + + qdma: dma-controller@8390000 { + compatible = "fsl,ls1021a-qdma"; + reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ + <0x0 0x8389000 0x0 0x1000>, /* Status regs */ + <0x0 0x838a000 0x0 0x2000>; /* Block regs */ + interrupts = , + , + ; + interrupt-names = "qdma-error", + "qdma-queue0", "qdma-queue1"; + dma-channels = <8>; + block-number = <1>; + block-offset = <0x1000>; + fsl,dma-queues = <2>; + status-sizes = <64>; + queue-sizes = <64 64>; + big-endian; + }; + }; }; -- cgit From dda0553cc270ee7e0b07674ab615be1d2700bda8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 2 Dec 2018 19:18:05 -0200 Subject: ARM: dts: imx6ul-pico-hobbit: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-pico-hobbit.dts | 52 +++++--------------------------- 1 file changed, 7 insertions(+), 45 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 797262d2f27f..1bc4fb4b4841 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -1,48 +1,10 @@ -/* - * Copyright 2015 Technexion Ltd. - * - * Author: Wig Cheng - * Richard Hu - * Tapani Utriainen - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen /dts-v1/; #include "imx6ul.dtsi" -- cgit From 093f911dba8c882225af0340fdedaf4a6118f4f6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 2 Dec 2018 19:18:06 -0200 Subject: ARM: dts: imx6ul-pico-hobbit: Move SoM related part to imx6ul-pico.dtsi imx6ul-pico-hobbit board contains: - One SoM board (imx6ul pico) - One base board (hobbit). In order to make it easier for adding support for other board variants, move the commom SoM part to the imx6ul-pico.dtsi file. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-pico-hobbit.dts | 479 ++---------------------------- arch/arm/boot/dts/imx6ul-pico.dtsi | 493 +++++++++++++++++++++++++++++++ 2 files changed, 511 insertions(+), 461 deletions(-) create mode 100644 arch/arm/boot/dts/imx6ul-pico.dtsi diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 1bc4fb4b4841..3cc04dd6f341 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -7,80 +7,25 @@ // Tapani Utriainen /dts-v1/; -#include "imx6ul.dtsi" - +#include "imx6ul-pico.dtsi" / { - model = "Technexion Pico i.MX6UL Board"; + model = "TechNexion PICO-IMX6UL and HOBBIT baseboard"; compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; - /* Will be filled by the bootloader */ - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0>; - }; - - chosen { - stdout-path = &uart6; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 6 0>; - }; + leds { + compatible = "gpio-leds"; - reg_brcm: regulator-brcm { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; - regulator-name = "brcm_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <200000>; + hobbitled { + label = "hobbitled"; + gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + }; }; sound { compatible = "fsl,imx-audio-sgtl5000"; model = "imx6ul-sgtl5000"; audio-cpu = <&sai1>; - audio-codec = <&codec>; + audio-codec = <&sgtl5000>; audio-routing = "LINE_IN", "Line In Jack", "MIC_IN", "Mic Jack", @@ -93,92 +38,6 @@ #clock-cells = <0>; clock-frequency = <24576000>; }; - - leds { - compatible = "gpio-leds"; - - hobbitled { - label = "hobbitled"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - phy-reset-duration = <1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - max-speed = <100>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze3000@8 { - compatible = "fsl,pfuze3000"; - reg = <0x08>; - - regulators { - /* VDD_ARM_SOC_IN*/ - sw1b_reg: sw1b { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1475000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - /* DRAM */ - sw3a_reg: sw3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - regulator-always-on; - }; - - /* DRAM */ - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - }; - }; }; &i2c2 { @@ -187,7 +46,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - codec: sgtl5000@a { + sgtl5000: codec@a { reg = <0x0a>; compatible = "fsl,sgtl5000"; clocks = <&sys_mclk>; @@ -197,317 +56,15 @@ }; &i2c3 { - clock_frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <33200000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <210>; - hback-porch = <46>; - hsync-len = <1>; - vback-porch = <22>; - vfront-porch = <23>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm7 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm7>; status = "okay"; -}; - -&pwm8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - dr_mode = "otg"; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - status = "okay"; -}; - -&usdhc2 { /* Wifi SDIO */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_brcm>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; -}; - -&iomuxc { - pinctrl_brcm_reg: brcmreggrp { - fsl,pins = < - MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */ - MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */ - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0 - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800 - MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 - MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0 - MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - /* LCD reset */ - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0 - >; - }; - - pinctrl_pwm7: pwm7grp { - fsl,pins = < - MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 - MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 - MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 - MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1 - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 - >; - }; - - pinctrl_uart6: uart6grp { - fsl,pins = < - MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 - MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usb_otg1: usbotg1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 - MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 - MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 - MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 - MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 - >; + polytouch: touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; }; }; diff --git a/arch/arm/boot/dts/imx6ul-pico.dtsi b/arch/arm/boot/dts/imx6ul-pico.dtsi new file mode 100644 index 000000000000..89269955440b --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-pico.dtsi @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen +/dts-v1/; + +#include "imx6ul.dtsi" + +/ { + /* Will be filled by the bootloader */ + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; + }; + + chosen { + stdout-path = &uart6; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 6 0>; + }; + + reg_brcm: regulator-brcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6ul-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&codec>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + max-speed = <100>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + /* VDD_ARM_SOC_IN*/ + sw1b_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* DRAM */ + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + /* DRAM */ + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <33200000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <210>; + hback-porch = <46>; + hsync-len = <1>; + vback-porch = <22>; + vfront-porch = <23>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc2 { /* Wifi SDIO */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_brcm>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_brcm_reg: brcmreggrp { + fsl,pins = < + MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */ + MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */ + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800 + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0 + MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* LCD reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; -- cgit From 4a20c26023f379ac41edd1479aec01d6de30e02b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 2 Dec 2018 19:18:07 -0200 Subject: ARM: dts: imx6ul-pico-hobbit: Make the child led nodes standard Use the same child led node and label name as used in the imx7d-pico-hobbit board. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-pico-hobbit.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 3cc04dd6f341..8656ccbb5a06 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -15,8 +15,8 @@ leds { compatible = "gpio-leds"; - hobbitled { - label = "hobbitled"; + led { + label = "gpio-led"; gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; }; }; -- cgit From cb430d971a568b4de940ef3aebd6e75e413283fd Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 2 Dec 2018 19:18:08 -0200 Subject: ARM: dts: imx6ul-pico-hobbit: Extend peripherals support This adds following peripherals support: - ADC - GPIO LED - GPIOs Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-pico-hobbit.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 8656ccbb5a06..39eeeddac39e 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -14,6 +14,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; led { label = "gpio-led"; @@ -67,4 +69,32 @@ touchscreen-size-x = <800>; touchscreen-size-y = <480>; }; + + adc081c: adc@50 { + compatible = "ti,adc081c"; + reg = <0x50>; + vref-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0 + >; + }; }; -- cgit From 0aa49c61995fdffd1b9bb7d222ca8f105f3e7c36 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 2 Dec 2018 19:18:09 -0200 Subject: ARM: dts: imx6ul-pico: Add the imx6ul-pico-pi variant The imx6ul-pico-pi contains a imx6ul-pico SoM and a pi baseboard: https://www.technexion.com/products/pico-baseboards/detail/PICO-PI Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6ul-pico-pi.dts | 97 ++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6ul-pico.dtsi | 32 ------------ 3 files changed, 98 insertions(+), 32 deletions(-) create mode 100644 arch/arm/boot/dts/imx6ul-pico-pi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index fbdabfbc5213..1d6d916c2195 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -559,6 +559,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-liteboard.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-pico-hobbit.dtb \ + imx6ul-pico-pi.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-pico-pi.dts b/arch/arm/boot/dts/imx6ul-pico-pi.dts new file mode 100644 index 000000000000..de07357b27fc --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-pico-pi.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2015 Technexion Ltd. +// +// Author: Wig Cheng +// Richard Hu +// Tapani Utriainen +/dts-v1/; + +#include "imx6ul-pico.dtsi" +/ { + model = "TechNexion PICO-IMX6UL and PI baseboard"; + compatible = "technexion,imx6ul-pico-pi", "fsl,imx6ul"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6ul-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&sgtl5000>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + sgtl5000: codec@a { + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&sys_mclk>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c3 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + polytouch: touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x10b0 + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x10b0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-pico.dtsi b/arch/arm/boot/dts/imx6ul-pico.dtsi index 89269955440b..de9f83189ba8 100644 --- a/arch/arm/boot/dts/imx6ul-pico.dtsi +++ b/arch/arm/boot/dts/imx6ul-pico.dtsi @@ -72,24 +72,6 @@ regulator-max-microvolt = <3300000>; startup-delay-us = <200000>; }; - - sound { - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6ul-sgtl5000"; - audio-cpu = <&sai1>; - audio-codec = <&codec>; - audio-routing = - "LINE_IN", "Line In Jack", - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - }; - - sys_mclk: clock-sys-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; }; &can1 { @@ -169,20 +151,6 @@ }; }; -&i2c2 { - clock_frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock_frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; -- cgit From 807d043c1226fe9f807fcebe498b51f96c822207 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Mon, 3 Dec 2018 05:20:19 +0000 Subject: ARM: dts: imx6sx: Add flexcan stop mode wakeup support Add stop-mode property which is required by stop mode wakeup feature. Signed-off-by: Aisheng Dong Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 6c8d2bb09025..272ff6133ec1 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -451,6 +451,7 @@ clocks = <&clks IMX6SX_CLK_CAN1_IPG>, <&clks IMX6SX_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; @@ -461,6 +462,7 @@ clocks = <&clks IMX6SX_CLK_CAN2_IPG>, <&clks IMX6SX_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; -- cgit From d2463e8631ce5d4f7e7c294cac6ee6bbfbbd01c7 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Mon, 3 Dec 2018 05:20:23 +0000 Subject: ARM: dts: imx6qdl: Add flexcan stop mode wakeup support Add stop-mode property which is required by stop mode wakeup feature. Signed-off-by: Aisheng Dong Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 6d827b69ead0..7fb8be1c9cef 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -561,6 +561,7 @@ clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, <&clks IMX6QDL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x34 28 0x10 17>; status = "disabled"; }; @@ -571,6 +572,7 @@ clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, <&clks IMX6QDL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x34 29 0x10 18>; status = "disabled"; }; -- cgit From f049557e478b96d654e7d7e29d1855bf031ca293 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Mon, 3 Dec 2018 05:20:27 +0000 Subject: ARM: dts: imx6ul: Add flexcan stop mode wakeup support Add stop-mode property which is required by stop mode wakeup feature. Signed-off-by: Aisheng Dong Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 0efc85f1bb95..4d034556a417 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -406,6 +406,7 @@ clocks = <&clks IMX6UL_CLK_CAN1_IPG>, <&clks IMX6UL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; @@ -416,6 +417,7 @@ clocks = <&clks IMX6UL_CLK_CAN2_IPG>, <&clks IMX6UL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; -- cgit From cf1bb82b0bd5ac64b8a19674283558a79968305f Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Mon, 3 Dec 2018 05:20:31 +0000 Subject: ARM: dts: imx7s: Add flexcan stop mode wakeup support Add stop-mode property which is required by stop mode wakeup feature. Signed-off-by: Aisheng Dong Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 098d2cc1d2c5..e88f53a4c7f4 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -873,6 +873,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN1_ROOT_CLK>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; @@ -883,6 +884,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN2_ROOT_CLK>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; -- cgit From c9a8cf0f1d6960911aa7303f95aef8a49a7e1f1f Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 5 Dec 2018 01:14:25 +0000 Subject: ARM: dts: imx6qdl-sabresd: add egalax touch screen support on i2c2 bus Add egalax touch screen support on i2c2 bus, it is connected to LVDS0, while the existing one on i2c3 bus is connected to LVDS1. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 6e46a195b399..d7389b58ef2e 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -272,6 +272,16 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + touchscreen@4 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + }; + ov5640: camera@3c { compatible = "ovti,ov5640"; pinctrl-names = "default"; @@ -498,6 +508,12 @@ >; }; + pinctrl_i2c2_egalax_int: i2c2egalaxintgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 -- cgit From 3e03b4ac50454ea2dfacc135f2a5e2e935937ae6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Dec 2018 09:19:35 -0200 Subject: ARM: dts: vf610-zii-scu4-aib: Add HI8435 support On the vf610-zii-scu4-aib board there is a hi8435 (32-channel discrete-to-digital SPI sensor device) in the DSPI0 bus. Add support for it. Signed-off-by: Fabio Estevam Reviewed-by: Chris Healy Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-scu4-aib.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts index 52bac1403f70..de6dfa57bec5 100644 --- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts +++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts @@ -397,6 +397,20 @@ }; }; +&dspi0 { + pinctrl-0 = <&pinctrl_dspi0>; + pinctrl-names = "default"; + bus-num = <0>; + status = "okay"; + + adc@5 { + compatible = "holt,hi8435"; + reg = <5>; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <1000000>; + }; +}; + &dspi1 { bus-num = <1>; pinctrl-names = "default"; -- cgit From 998a84c27a7f3f9133d32af64e19c05cec161a1a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Dec 2018 16:10:01 -0200 Subject: ARM: dts: imx53-voipac-dmm-668: Fix memory node duplication imx53-voipac-dmm-668 has two memory nodes, but the correct representation would be to use a single one with two reg entries - one for each RAM chip select, so fix it accordingly. Reported-by: Marco Franchi Signed-off-by: Fabio Estevam Signed-off-by: Marco Franchi Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi index f83a8c62ea53..d595034f3f1b 100644 --- a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi +++ b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi @@ -17,12 +17,8 @@ memory@70000000 { device_type = "memory"; - reg = <0x70000000 0x20000000>; - }; - - memory@b0000000 { - device_type = "memory"; - reg = <0xb0000000 0x20000000>; + reg = <0x70000000 0x20000000>, + <0xb0000000 0x20000000>; }; regulators { -- cgit From 69bf2fec500b59e2011bbf528e39c4a8f1b25020 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Dec 2018 16:10:02 -0200 Subject: ARM: dts: imx6dl-mamoj: Add a memory node Add a memory node, with an empty memory size, which will be filled by the bootloader. This is done in preparation for removing the memory node from imx6qdl.dtsi. Reported-by: Marco Franchi Signed-off-by: Fabio Estevam Signed-off-by: Marco Franchi Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-mamoj.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/imx6dl-mamoj.dts index df8607fe4142..385ce7b0029e 100644 --- a/arch/arm/boot/dts/imx6dl-mamoj.dts +++ b/arch/arm/boot/dts/imx6dl-mamoj.dts @@ -13,6 +13,12 @@ model = "BTicino i.MX6DL Mamoj board"; compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl"; + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */ -- cgit From 404c0c9314f4f204ad82ef059424ff7e0b20fcd0 Mon Sep 17 00:00:00 2001 From: Marco Franchi Date: Wed, 5 Dec 2018 16:10:03 -0200 Subject: ARM: dts: imx6qdl: Fix memory node duplication Boards based on imx6qdl have duplicate memory nodes: - One coming from the board device tree file: memory@ - One coming from the imx6qdl.dtsi file. Fix the duplication by removing the memory node from the imx6qdl.dtsi file and by adding 'device_type = "memory";' in the board Device Tree. Converted using the following command: perl -p0777i -e 's/memory\@10000000 \{\n/memory\@10000000 \{\n\t\tdevice_type = \"memory\";\n/m' `find ./arch/arm/boot/dts -name "imx6*"`` Reported-by: Rob Herring Signed-off-by: Marco Franchi Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-apf6dev.dts | 1 + arch/arm/boot/dts/imx6dl-aristainetos2_4.dts | 1 + arch/arm/boot/dts/imx6dl-aristainetos2_7.dts | 1 + arch/arm/boot/dts/imx6dl-aristainetos_4.dts | 1 + arch/arm/boot/dts/imx6dl-aristainetos_7.dts | 1 + arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 1 + arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts | 1 + arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi | 1 + arch/arm/boot/dts/imx6dl-rex-basic.dts | 1 + arch/arm/boot/dts/imx6dl-riotboard.dts | 1 + arch/arm/boot/dts/imx6dl-ts4900.dts | 1 + arch/arm/boot/dts/imx6dl-ts7970.dts | 1 + arch/arm/boot/dts/imx6dl-wandboard-revb1.dts | 1 + arch/arm/boot/dts/imx6dl-wandboard-revd1.dts | 1 + arch/arm/boot/dts/imx6dl-wandboard.dts | 1 + arch/arm/boot/dts/imx6q-apf6dev.dts | 1 + arch/arm/boot/dts/imx6q-arm2.dts | 1 + arch/arm/boot/dts/imx6q-ba16.dtsi | 1 + arch/arm/boot/dts/imx6q-cm-fx6.dts | 1 + arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts | 1 + arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 1 + arch/arm/boot/dts/imx6q-display5.dtsi | 1 + arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 1 + arch/arm/boot/dts/imx6q-evi.dts | 1 + arch/arm/boot/dts/imx6q-gk802.dts | 1 + arch/arm/boot/dts/imx6q-gw5400-a.dts | 1 + arch/arm/boot/dts/imx6q-h100.dts | 1 + arch/arm/boot/dts/imx6q-kp-tpc.dts | 1 + arch/arm/boot/dts/imx6q-marsboard.dts | 1 + arch/arm/boot/dts/imx6q-mccmon6.dts | 1 + arch/arm/boot/dts/imx6q-novena.dts | 1 + arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | 1 + arch/arm/boot/dts/imx6q-pistachio.dts | 1 + arch/arm/boot/dts/imx6q-rex-pro.dts | 1 + arch/arm/boot/dts/imx6q-sbc6x.dts | 1 + arch/arm/boot/dts/imx6q-tbs2910.dts | 1 + arch/arm/boot/dts/imx6q-ts4900.dts | 1 + arch/arm/boot/dts/imx6q-ts7970.dts | 1 + arch/arm/boot/dts/imx6q-wandboard-revb1.dts | 1 + arch/arm/boot/dts/imx6q-wandboard-revd1.dts | 1 + arch/arm/boot/dts/imx6q-wandboard.dts | 1 + arch/arm/boot/dts/imx6q-zii-rdu2.dts | 1 + arch/arm/boot/dts/imx6qdl-apalis.dtsi | 1 + arch/arm/boot/dts/imx6qdl-cubox-i.dtsi | 1 + arch/arm/boot/dts/imx6qdl-emcon.dtsi | 1 + arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 1 + arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 1 + arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 1 + arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 1 + arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 1 + arch/arm/boot/dts/imx6qdl-gw552x.dtsi | 1 + arch/arm/boot/dts/imx6qdl-gw553x.dtsi | 1 + arch/arm/boot/dts/imx6qdl-gw560x.dtsi | 1 + arch/arm/boot/dts/imx6qdl-gw5903.dtsi | 1 + arch/arm/boot/dts/imx6qdl-gw5904.dtsi | 1 + arch/arm/boot/dts/imx6qdl-hummingboard.dtsi | 1 + arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi | 1 + arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 1 + arch/arm/boot/dts/imx6qdl-icore.dtsi | 1 + arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 1 + arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 1 + arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 1 + arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 1 + arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 1 + arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 1 + arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 1 + arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 + arch/arm/boot/dts/imx6qdl-tx6.dtsi | 1 + arch/arm/boot/dts/imx6qdl-udoo.dtsi | 1 + arch/arm/boot/dts/imx6qdl-var-dart.dtsi | 1 + arch/arm/boot/dts/imx6qdl.dtsi | 2 -- arch/arm/boot/dts/imx6qp-wandboard-revd1.dts | 1 + arch/arm/boot/dts/imx6qp-zii-rdu2.dts | 1 + 73 files changed, 72 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-apf6dev.dts b/arch/arm/boot/dts/imx6dl-apf6dev.dts index 4a7f86de6c39..6632e99fbb68 100644 --- a/arch/arm/boot/dts/imx6dl-apf6dev.dts +++ b/arch/arm/boot/dts/imx6dl-apf6dev.dts @@ -55,6 +55,7 @@ compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x20000000>; }; }; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts index 29940ba215a8..b16603f27dce 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts @@ -49,6 +49,7 @@ compatible = "fsl,imx6dl"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts index 240f3661469f..abb2a1b9ce08 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts @@ -49,6 +49,7 @@ compatible = "fsl,imx6dl"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts index ad7733662fe5..b87a85cd44ac 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts @@ -28,6 +28,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts index 64ed84e3c512..e71ad9062fd1 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts @@ -17,6 +17,7 @@ compatible = "fsl,imx6dl"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index d08e0402793b..d5f7a1703aae 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -55,6 +55,7 @@ /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; diff --git a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts index 89384cb618f6..588286adee67 100644 --- a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts +++ b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts @@ -23,6 +23,7 @@ /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; }; diff --git a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi index 7d9888937f12..d7e72993eaf8 100644 --- a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi @@ -17,6 +17,7 @@ compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x20000000>; }; }; diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/imx6dl-rex-basic.dts index 3fb7f4ee2496..853e58defa9c 100644 --- a/arch/arm/boot/dts/imx6dl-rex-basic.dts +++ b/arch/arm/boot/dts/imx6dl-rex-basic.dts @@ -17,6 +17,7 @@ compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x20000000>; }; }; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 8e51491e68cf..65c184bb8fb0 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -16,6 +16,7 @@ compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6dl-ts4900.dts b/arch/arm/boot/dts/imx6dl-ts4900.dts index cc01a7a22e30..3d60cc725d9e 100644 --- a/arch/arm/boot/dts/imx6dl-ts4900.dts +++ b/arch/arm/boot/dts/imx6dl-ts4900.dts @@ -49,6 +49,7 @@ /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; }; diff --git a/arch/arm/boot/dts/imx6dl-ts7970.dts b/arch/arm/boot/dts/imx6dl-ts7970.dts index 82435d5bf33f..5da6feba2e66 100644 --- a/arch/arm/boot/dts/imx6dl-ts7970.dts +++ b/arch/arm/boot/dts/imx6dl-ts7970.dts @@ -50,6 +50,7 @@ /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; }; diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts index 738db4fc7702..c2946fbaa0dd 100644 --- a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts +++ b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts @@ -13,6 +13,7 @@ compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts index 51de6b4bd7d8..6d1d863c2e3a 100644 --- a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts +++ b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts @@ -13,6 +13,7 @@ compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts index b43454deaa1a..4a08d5a99452 100644 --- a/arch/arm/boot/dts/imx6dl-wandboard.dts +++ b/arch/arm/boot/dts/imx6dl-wandboard.dts @@ -13,6 +13,7 @@ compatible = "wand,imx6dl-wandboard", "fsl,imx6dl"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/imx6q-apf6dev.dts b/arch/arm/boot/dts/imx6q-apf6dev.dts index 5e72f81cdf8b..07a36bb8075b 100644 --- a/arch/arm/boot/dts/imx6q-apf6dev.dts +++ b/arch/arm/boot/dts/imx6q-apf6dev.dts @@ -55,6 +55,7 @@ compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index 953a5b5a8ea4..baadcb7fe011 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -19,6 +19,7 @@ compatible = "fsl,imx6q-arm2", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi index e903c488287b..adc9455e42c7 100644 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi @@ -47,6 +47,7 @@ / { memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 18ae4f3be6e3..cab9e92531c7 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -51,6 +51,7 @@ compatible = "compulab,cm-fx6", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts index ad12d76bbb89..e13acbbcdff4 100644 --- a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts +++ b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts @@ -23,6 +23,7 @@ /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; }; diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index bbba0671f0f4..387801dde02e 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -19,6 +19,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi index 85232c7c36a0..83524bb99eb3 100644 --- a/arch/arm/boot/dts/imx6q-display5.dtsi +++ b/arch/arm/boot/dts/imx6q-display5.dtsi @@ -48,6 +48,7 @@ compatible = "lwn,display5", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index b3c6a4a7897d..ee8c38eee03b 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -30,6 +30,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index fcd257bc5ac3..c63f371ede8b 100644 --- a/arch/arm/boot/dts/imx6q-evi.dts +++ b/arch/arm/boot/dts/imx6q-evi.dts @@ -51,6 +51,7 @@ compatible = "uniwest,imx6q-evi", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts index 84d3540b3a97..ccc2487d47ca 100644 --- a/arch/arm/boot/dts/imx6q-gk802.dts +++ b/arch/arm/boot/dts/imx6q-gk802.dts @@ -20,6 +20,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index a8f70b4266ef..4038170369fc 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -61,6 +61,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts index 714e09e04dcb..b8feadbff967 100644 --- a/arch/arm/boot/dts/imx6q-h100.dts +++ b/arch/arm/boot/dts/imx6q-h100.dts @@ -51,6 +51,7 @@ /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; diff --git a/arch/arm/boot/dts/imx6q-kp-tpc.dts b/arch/arm/boot/dts/imx6q-kp-tpc.dts index 302d8d06e4cc..50fbf46d17c2 100644 --- a/arch/arm/boot/dts/imx6q-kp-tpc.dts +++ b/arch/arm/boot/dts/imx6q-kp-tpc.dts @@ -13,6 +13,7 @@ compatible = "kiebackpeter,imx6q-tpc", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; }; diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts index dd763f205819..d8ccb533b6b7 100644 --- a/arch/arm/boot/dts/imx6q-marsboard.dts +++ b/arch/arm/boot/dts/imx6q-marsboard.dts @@ -48,6 +48,7 @@ compatible = "embest,imx6q-marsboard", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts index b7e9f38cec72..74d9824e920b 100644 --- a/arch/arm/boot/dts/imx6q-mccmon6.dts +++ b/arch/arm/boot/dts/imx6q-mccmon6.dts @@ -20,6 +20,7 @@ compatible = "lwn,mccmon6", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index fcd824dc485b..61347a545d6c 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -57,6 +57,7 @@ /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi index fad858c30fe9..097f2c56c20b 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi @@ -17,6 +17,7 @@ compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; }; diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts index a31e83cd07a3..5edf858c8b86 100644 --- a/arch/arm/boot/dts/imx6q-pistachio.dts +++ b/arch/arm/boot/dts/imx6q-pistachio.dts @@ -57,6 +57,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/imx6q-rex-pro.dts index d6cae73b1927..aa3004eab06c 100644 --- a/arch/arm/boot/dts/imx6q-rex-pro.dts +++ b/arch/arm/boot/dts/imx6q-rex-pro.dts @@ -17,6 +17,7 @@ compatible = "rex,imx6q-rex-pro", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; }; diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts index b7aa2f0b9f53..3129f727750f 100644 --- a/arch/arm/boot/dts/imx6q-sbc6x.dts +++ b/arch/arm/boot/dts/imx6q-sbc6x.dts @@ -13,6 +13,7 @@ compatible = "microsys,sbc6x", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; }; diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index 505cba776a2d..279b15e9ae2e 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -60,6 +60,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6q-ts4900.dts b/arch/arm/boot/dts/imx6q-ts4900.dts index e655107edc56..dce1e8671ebe 100644 --- a/arch/arm/boot/dts/imx6q-ts4900.dts +++ b/arch/arm/boot/dts/imx6q-ts4900.dts @@ -49,6 +49,7 @@ /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; }; diff --git a/arch/arm/boot/dts/imx6q-ts7970.dts b/arch/arm/boot/dts/imx6q-ts7970.dts index c615ac4feede..570bd3c309a6 100644 --- a/arch/arm/boot/dts/imx6q-ts7970.dts +++ b/arch/arm/boot/dts/imx6q-ts7970.dts @@ -50,6 +50,7 @@ /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; }; diff --git a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts index be85b980bdfe..f6ccbecff92c 100644 --- a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts +++ b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts @@ -13,6 +13,7 @@ compatible = "wand,imx6q-wandboard", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; }; diff --git a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts index fcfba28764d4..55331021d80c 100644 --- a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts +++ b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts @@ -13,6 +13,7 @@ compatible = "wand,imx6q-wandboard", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; }; diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts index fa36fe183fc0..0be548beef86 100644 --- a/arch/arm/boot/dts/imx6q-wandboard.dts +++ b/arch/arm/boot/dts/imx6q-wandboard.dts @@ -13,6 +13,7 @@ compatible = "wand,imx6q-wandboard", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; }; diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/imx6q-zii-rdu2.dts index 7da6dde9c857..0f0743db2779 100644 --- a/arch/arm/boot/dts/imx6q-zii-rdu2.dts +++ b/arch/arm/boot/dts/imx6q-zii-rdu2.dts @@ -50,6 +50,7 @@ /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 3dc99dd8dde1..8380f1b26826 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -49,6 +49,7 @@ /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi index 9332a31e6c8b..e3be453d8a4a 100644 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi @@ -44,6 +44,7 @@ / { /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi index bfd5f373921e..397e205551c4 100644 --- a/arch/arm/boot/dts/imx6qdl-emcon.dtsi +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -24,6 +24,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 17a7b9c083d0..d3609966b846 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -45,6 +45,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index b8044681006c..2ff377d0df7e 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -60,6 +60,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 629908fbaa32..68ab54351109 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -60,6 +60,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index a1a6fb5541e1..81b2fcf6eedf 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -60,6 +60,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index 4e21b3849394..8e46a80f57a4 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -75,6 +75,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index 81dae5b5bc87..dacc2a14d0e7 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -52,6 +52,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi index c5d95e8d2e09..a1066897be18 100644 --- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi @@ -81,6 +81,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi index b5986efe1090..e8e36dfd0a6b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi @@ -114,6 +114,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi index 368132274a91..9cb9a7439121 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi @@ -84,6 +84,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi index 3c52bdb453f3..6d21cc6a9d4b 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi @@ -94,6 +94,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi index 0e64016e765f..2ffb21dd89f2 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi @@ -43,6 +43,7 @@ / { /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi index c413f9c3540f..e4231331f04e 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi @@ -43,6 +43,7 @@ / { /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi index ba93026ecee8..1d1b4bd0670f 100644 --- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi @@ -10,6 +10,7 @@ / { memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi index aaed37c73c29..7814f1ef0804 100644 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -10,6 +10,7 @@ / { memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index 29baf25ae5d0..7a85116ef1d2 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -11,6 +11,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index 39200e5dc896..c3415aa348a2 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -11,6 +11,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0xF0000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index 572abd7499b1..ed53f07c6b7b 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -11,6 +11,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 98384a6c5d12..8b0e432099b5 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -13,6 +13,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index ed1aafd56973..1b50b01e9bac 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -16,6 +16,7 @@ compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index a031023a8c52..1280de50a984 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -12,6 +12,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 654cf2c9b073..8468216dae9b 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -50,6 +50,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index d7389b58ef2e..173aa2bd9ccb 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -13,6 +13,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index a98fb2564c63..c68cb90fd801 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -62,6 +62,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; /* will be filled by U-Boot */ }; diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi index 40d1b0d9faff..776bfc77f89d 100644 --- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi @@ -32,6 +32,7 @@ }; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi index 38080c1dfaec..8752a4961c47 100644 --- a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi +++ b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi @@ -11,6 +11,7 @@ / { memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 7fb8be1c9cef..fe17a3405edc 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -13,10 +13,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { ethernet0 = &fec; diff --git a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts index bcca5ac5fa51..08d8b78a2096 100644 --- a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts +++ b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts @@ -13,6 +13,7 @@ compatible = "wand,imx6qp-wandboard", "fsl,imx6qp"; memory@10000000 { + device_type = "memory"; reg = <0x10000000 0x80000000>; }; }; diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts index 8c293e9f36a7..98bf7a6b2850 100644 --- a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts +++ b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts @@ -50,6 +50,7 @@ /* Will be filled by the bootloader */ memory@10000000 { + device_type = "memory"; reg = <0x10000000 0>; }; }; -- cgit From 75ad7ff1797f62b011c7dde68981b10a089cfef9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 6 Dec 2018 01:42:30 +0000 Subject: ARM: dts: imx6qdl-sabresd: Move regulators outside of "simple-bus" It is not recommended to place regulators inside "simple-bus", so move them out to make it cleaner the addition of new regulators. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 82 +++++++++++++++------------------- 1 file changed, 36 insertions(+), 46 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 173aa2bd9ccb..d3877a529a85 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -17,52 +17,42 @@ reg = <0x10000000 0x40000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_usb_h1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 29 0>; - enable-active-high; - vin-supply = <&swbst_reg>; - }; - - reg_audio: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "wm8962-supply"; - gpio = <&gpio4 10 0>; - enable-active-high; - }; - - reg_pcie: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 19 0>; - enable-active-high; - }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 29 0>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply"; + gpio = <&gpio4 10 0>; + enable-active-high; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 19 0>; + enable-active-high; }; gpio-keys { -- cgit From ab43e984049008ecfca7cba7a9d7666da4916d2e Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 6 Dec 2018 01:42:34 +0000 Subject: ARM: dts: imx6qdl-sabresd: add light sensor support Add isl29023 light sensor support on i2c3 bus, the light sensor's power is controlled by a fixed regulator, since the isl29023 driver and most of other sensors on same board like mag3110 and mma8451 do NOT support regulator operation currently, they are all controlled by this regulator, so this patch also adds the fixed regulator support and make it always on. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index d3877a529a85..2e071b20b1fc 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -55,6 +55,18 @@ enable-active-high; }; + reg_sensors: regulator-sensors { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sensors_reg>; + regulator-name = "sensors-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -411,6 +423,15 @@ interrupts = <7 2>; wakeup-gpios = <&gpio6 7 0>; }; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_isl29023_int>; + interrupt-parent = <&gpio3>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + }; }; &iomuxc { @@ -512,6 +533,12 @@ >; }; + pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 + >; + }; + pinctrl_ipu1_csi0: ipu1csi0grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 @@ -560,6 +587,12 @@ >; }; + pinctrl_sensors_reg: sensorsreggrp { + fsl,pins = < + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 -- cgit From 9e6a7c47c3c4b5478c0ba0e42b271930038b1765 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 6 Dec 2018 01:42:38 +0000 Subject: ARM: dts: imx6qdl-sabresd: add magnetometer sensor support Add magnetometer sensor mag3110 support on i2c3 bus. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 2e071b20b1fc..366fa8fbae4d 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -424,6 +424,15 @@ wakeup-gpios = <&gpio6 7 0>; }; + magnetometer@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_mag3110_int>; + interrupt-parent = <&gpio3>; + interrupts = <16 IRQ_TYPE_EDGE_RISING>; + }; + light-sensor@44 { compatible = "isil,isl29023"; reg = <0x44>; @@ -539,6 +548,12 @@ >; }; + pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0xb0b1 + >; + }; + pinctrl_ipu1_csi0: ipu1csi0grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 -- cgit From 47853f18b63557740ef730cb212035fae8d13c88 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 6 Dec 2018 01:42:42 +0000 Subject: ARM: dts: imx6qdl-sabresd: add accelerometer sensor support Add accelerometer sensor mma8451 support on i2c1 bus. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 366fa8fbae4d..187548d58a92 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -243,6 +243,15 @@ >; }; + accelerometer@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_mma8451_int>; + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + }; + ov5642: camera@3c { compatible = "ovti,ov5642"; pinctrl-names = "default"; @@ -522,6 +531,12 @@ >; }; + pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -- cgit From 006303d6ba8edda0bbb2c2a271c2faa2968f18c8 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 4 Dec 2018 10:17:00 -0500 Subject: ARM: dts: imx5: add gpu nodes This adds the gpu nodes for the adreno 200 GPU on iMX51 and iMX53, now supported by the freedreno driver. The compatible for the iMX51 uses a patchid of 1, which is used by drm/msm driver to identify the smaller 128KiB GMEM size. Signed-off-by: Jonathan Marek Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 10 ++++++++++ arch/arm/boot/dts/imx53.dtsi | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 7651bedabdfb..a5ee25cedc10 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -121,6 +121,16 @@ reg = <0x1ffe0000 0x20000>; }; + gpu: gpu@30000000 { + compatible = "amd,imageon-200.1", "amd,imageon"; + reg = <0x30000000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <12>; + interrupt-names = "kgsl_3d0_irq"; + clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; + clock-names = "core_clk", "mem_iface_clk"; + }; + ipu: ipu@40000000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index a9804c08e6a8..b3300300aabe 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -200,6 +200,16 @@ }; }; + gpu: gpu@30000000 { + compatible = "amd,imageon-200.0", "amd,imageon"; + reg = <0x30000000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <12>; + interrupt-names = "kgsl_3d0_irq"; + clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; + clock-names = "core_clk", "mem_iface_clk"; + }; + aips@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; -- cgit From ca5c36ba42c1ad65f874c5e41edbd72866e47f83 Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Thu, 6 Dec 2018 03:51:27 +0000 Subject: ARM: dts: imx6ul: add flexcan support Add flexcan support for i.MX6UL board. Change the place of CAN node delete due to i.MX6ULZ include i.MX6UL dts but not support flexcan. Signed-off-by: Dong Aisheng Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 53 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6ulz-14x14-evk.dts | 2 ++ arch/arm/boot/dts/imx6ulz.dtsi | 2 -- 3 files changed, 55 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index 095568b30d30..5223ada4fe31 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -30,6 +30,14 @@ enable-active-high; }; + reg_can_3v3: regulator-can-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "mx6ul-wm8960"; @@ -64,6 +72,28 @@ }; }; + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + }; + }; + panel { compatible = "innolux,at043tn24"; backlight = <&backlight_display>; @@ -130,6 +160,20 @@ }; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -415,6 +459,15 @@ >; }; + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + pinctrl_tsc: tscgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 diff --git a/arch/arm/boot/dts/imx6ulz-14x14-evk.dts b/arch/arm/boot/dts/imx6ulz-14x14-evk.dts index 6f1af240e0ce..483d9732c002 100644 --- a/arch/arm/boot/dts/imx6ulz-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ulz-14x14-evk.dts @@ -9,6 +9,8 @@ /delete-node/ &fec1; /delete-node/ &fec2; +/delete-node/ &can1; +/delete-node/ &can2; /delete-node/ &lcdif; /delete-node/ &tsc; diff --git a/arch/arm/boot/dts/imx6ulz.dtsi b/arch/arm/boot/dts/imx6ulz.dtsi index ae6d7e593769..0b5f1a763567 100644 --- a/arch/arm/boot/dts/imx6ulz.dtsi +++ b/arch/arm/boot/dts/imx6ulz.dtsi @@ -20,8 +20,6 @@ }; /delete-node/ &adc1; -/delete-node/ &can1; -/delete-node/ &can2; /delete-node/ &ecspi3; /delete-node/ &ecspi4; /delete-node/ &epit2; -- cgit From 5649dbd31ef7c74acbf14c2f18c779572f75485e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 6 Dec 2018 08:36:41 -0200 Subject: ARM: dts: imx6qdl-sabresd: Use GPIO_ACTIVE_HIGH for regulators Passing GPIO_ACTIVE_HIGH as GPIO flags for the GPIO controlled regulator improves the readability, so use it instead of the hardcoded number. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 187548d58a92..8930aec6464c 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -22,7 +22,7 @@ regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&swbst_reg>; }; @@ -32,7 +32,7 @@ regulator-name = "usb_h1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio1 29 0>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&swbst_reg>; }; @@ -40,7 +40,7 @@ reg_audio: regulator-audio { compatible = "regulator-fixed"; regulator-name = "wm8962-supply"; - gpio = <&gpio4 10 0>; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -51,7 +51,7 @@ regulator-name = "MPCIE_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio3 19 0>; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; -- cgit From 81c0039b13c11bf77bbca700350d4f25d5cb2ec8 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Thu, 6 Dec 2018 19:22:16 +0000 Subject: ARM: dts: imx6ul: Remove extra space between node name and brace Fixes: 7d1cd2978664 ("ARM: dts: imx6ul: add gpmi support") Signed-off-by: Leonard Crestez Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 4d034556a417..62ed30c781ed 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -183,7 +183,7 @@ clocks = <&clks IMX6UL_CLK_APBHDMA>; }; - gpmi: gpmi-nand@1806000 { + gpmi: gpmi-nand@1806000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; -- cgit From 79da07dec740a42c70963ebacbd2bf8866af9e20 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 6 Dec 2018 21:41:17 -0200 Subject: ARM: dts: imx51-zii-rdu1: Do not specify "power-gpio" for hpa1 TPA6130A2 SD pin on RDU1 is not really controlled by SoC and instead is only meant to notify the system that audio was "muted" by external actors. To accommodate that, drop "power-gpio" property of hpa1 node as well as specify a name for that GPIO so that userspace can access it. Signed-off-by: Andrey Smirnov Signed-off-by: Fabio Estevam Tested-by: Chris Healy Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index 3ca4f9b750b0..9235fd45a824 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -478,6 +478,15 @@ }; &gpio1 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "hp-amp-shutdown-b", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + unused-sd3-wp-gpio { /* * See pinctrl_esdhc1 below for more details on this @@ -502,9 +511,6 @@ hpa1: amp@60 { compatible = "ti,tpa6130a2"; reg = <0x60>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ampgpio>; - power-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; Vdd-supply = <®_3p3v>; }; @@ -678,7 +684,10 @@ }; &iomuxc { - pinctrl_ampgpio: ampgpiogrp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { fsl,pins = < MX51_PAD_GPIO1_9__GPIO1_9 0x5e >; -- cgit From 50536c661194dcb43faeba8aaae85e3f34145ee4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 6 Dec 2018 08:08:57 -0200 Subject: ARM: dts: imx7d-pico: Do not harcode the memory size Currently the memory size described in dts is 2GB, which is incorrect. There are 512MB and 1GB versions of imx7d-pico boards, so remove the hardcoded memory size and let the bootloader pass the correct value to the kernel. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-pico.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi index 934a019f341e..0df68e53e9fa 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -48,9 +48,10 @@ model = "Technexion Pico i.MX7D Board"; compatible = "technexion,imx7d-pico", "fsl,imx7d"; + /* Will be filled by the bootloader */ memory@80000000 { device_type = "memory"; - reg = <0x80000000 0x80000000>; + reg = <0x80000000 0>; }; reg_ap6212: regulator-ap6212 { -- cgit From a26aec533ec065cd54949d6958f97e0fd79c3bfb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 6 Dec 2018 08:08:58 -0200 Subject: ARM: dts: imx7d-pico: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-pico-pi.dts | 44 +++---------------------------------- arch/arm/boot/dts/imx7d-pico.dtsi | 44 +++---------------------------------- 2 files changed, 6 insertions(+), 82 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-pico-pi.dts b/arch/arm/boot/dts/imx7d-pico-pi.dts index ee02d931cf49..33951f4c7f41 100644 --- a/arch/arm/boot/dts/imx7d-pico-pi.dts +++ b/arch/arm/boot/dts/imx7d-pico-pi.dts @@ -1,44 +1,6 @@ -/* - * Copyright 2017 NXP - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright 2017 NXP #include "imx7d-pico.dtsi" diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi index 0df68e53e9fa..d957454ce16b 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -1,44 +1,6 @@ -/* - * Copyright 2017 NXP - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright 2017 NXP /dts-v1/; -- cgit From 4edbe6aa46d15c8ac632b2b9f15c27414f940051 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 6 Dec 2018 08:08:59 -0200 Subject: ARM: dts: imx7d-pico-pi: Move SoM related part to imx7d-pico.dtsi imx7d-pico-pi board contains: - One SoM board (imx7d pico) - One base board (pi). In order to make it easier for adding support for other board variants, move the commom SoM part to the imx7d-pico.dtsi file. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-pico-pi.dts | 116 ++---------------------------------- arch/arm/boot/dts/imx7d-pico.dtsi | 111 +++++++++++++++++++++++++++++++++- 2 files changed, 113 insertions(+), 114 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-pico-pi.dts b/arch/arm/boot/dts/imx7d-pico-pi.dts index 33951f4c7f41..039c17066fe0 100644 --- a/arch/arm/boot/dts/imx7d-pico-pi.dts +++ b/arch/arm/boot/dts/imx7d-pico-pi.dts @@ -5,6 +5,9 @@ #include "imx7d-pico.dtsi" / { + model = "TechNexion PICO-IMX7D Board and PI baseboard"; + compatible = "technexion,imx7d-pico-pi", "fsl,imx7d"; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "imx7-sgtl5000"; @@ -16,43 +19,14 @@ }; dailink_master: simple-audio-card,codec { - sound-dai = <&codec>; + sound-dai = <&sgtl5000>; clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; }; }; }; -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - status = "okay"; - }; - }; -}; - &i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: sgtl5000@a { + sgtl5000: codec@a { #sound-dai-cells = <0>; reg = <0x0a>; compatible = "fsl,sgtl5000"; @@ -61,83 +35,3 @@ VDDIO-supply = <®_vref_1v8>; }; }; - - -&sai1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, - <&clks IMX7D_SAI1_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; - assigned-clock-rates = <0>, <24576000>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; - dr_mode = "host"; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 - MX7D_PAD_SD2_WP__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f - MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f - MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f - MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 - MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79 - MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79 - >; - }; - - pinctrl_usbotg1_pwr: usbotg_pwr { - fsl,pins = < - MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi index d957454ce16b..7319e2ecec5c 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -7,9 +7,6 @@ #include "imx7d.dtsi" / { - model = "Technexion Pico i.MX7D Board"; - compatible = "technexion,imx7d-pico", "fsl,imx7d"; - /* Will be filled by the bootloader */ memory@80000000 { device_type = "memory"; @@ -79,6 +76,37 @@ assigned-clock-rates = <0>, <32768>; }; +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + status = "okay"; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; @@ -174,6 +202,35 @@ }; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <24576000>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + &usdhc2 { /* Wifi SDIO */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>; @@ -208,6 +265,32 @@ }; &iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f + MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 + MX7D_PAD_SD2_WP__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f @@ -221,6 +304,28 @@ >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79 + MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79 + >; + }; + + pinctrl_usbotg1_pwr: usbotg_pwr { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x59 -- cgit From ce48443443303904032686bf50587c2cf08a83e7 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 6 Dec 2018 08:09:00 -0200 Subject: ARM: dts: imx7d-pico: Pass the USBOTG1_PWR pinctrl Pass the USBOTG1_PWR pinctrl description in the USBOTG GPIO controlled regulator. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-pico.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi index 7319e2ecec5c..cb30bded1e4a 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -41,6 +41,8 @@ }; reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_pwr>; compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; regulator-min-microvolt = <5000000>; -- cgit From 26255a529769e93736d1a9f955ec379513f71e27 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 6 Dec 2018 08:09:01 -0200 Subject: ARM: dts: imx7d-pico: Pass the Ethernet PHY reset GPIO Pass the "phy-reset-gpios" property in order to describe the GPIO that performs the Ethernet PHY reset. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-pico.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi index cb30bded1e4a..35791a1adabf 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -88,6 +88,7 @@ phy-mode = "rgmii"; phy-handle = <ðphy0>; fsl,magic-packet; + phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; status = "okay"; mdio { @@ -290,6 +291,7 @@ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */ >; }; -- cgit From bb1ff7ed6c1abfa1d4a376dd8750a0f7c731709f Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Thu, 6 Dec 2018 08:09:02 -0200 Subject: ARM: dts: imx7d-pico: Improve WiFi regulator name There are different models of WiFi being used in the SoM and the handle name was too restrictive. This reworks it to a more generic and meaningful name. Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-pico.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi index 35791a1adabf..417f034fb354 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -13,11 +13,11 @@ reg = <0x80000000 0>; }; - reg_ap6212: regulator-ap6212 { + reg_wlreg_on: regulator-wlreg_on { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_ap6212>; - regulator-name = "AP6212"; + pinctrl-0 = <&pinctrl_reg_wlreg_on>; + regulator-name = "wlreg_on"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; @@ -241,7 +241,7 @@ non-removable; keep-power-in-suspend; wakeup-source; - vmmc-supply = <®_ap6212>; + vmmc-supply = <®_wlreg_on>; mmc-pwrseq = <&usdhc2_pwrseq>; status = "okay"; }; @@ -302,7 +302,7 @@ >; }; - pinctrl_reg_ap6212: regap6212grp { + pinctrl_reg_wlreg_on: regregongrp { fsl,pins = < MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 >; -- cgit From f13f571ac8a18c45f4c21bceda7cff3ad4e7ba03 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 6 Dec 2018 08:09:03 -0200 Subject: ARM: dts: imx7d-pico: Extend peripherals support This extends the peripherals supported by the imx7d-pico.dtsi. It adds: - I2C2 - Flexcan (flexcan1 and flexcan2 ports) - USDHC1 - UART (6 and 7 ports) - PWM (4 ports) - eCSPI3 Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-pico.dtsi | 183 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi index 417f034fb354..3fd595a71202 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -78,6 +78,13 @@ assigned-clock-rates = <0>, <32768>; }; +&ecspi3 { + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -103,6 +110,18 @@ }; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -110,6 +129,12 @@ status = "okay"; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; @@ -215,6 +240,29 @@ status = "okay"; }; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { /* Backlight */ + status = "okay"; +}; + &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; @@ -223,6 +271,24 @@ status = "okay"; }; +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&uart7 { /* Bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; status = "okay"; @@ -234,6 +300,21 @@ status = "okay"; }; +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + bus-width = <4>; + tuning-step = <2>; + vmmc-supply = <®_3p3v>; + wakeup-source; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + &usdhc2 { /* Wifi SDIO */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>; @@ -268,6 +349,15 @@ }; &iomuxc { + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 + MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2 + MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2 + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f @@ -275,6 +365,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f + MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 @@ -295,6 +392,20 @@ >; }; + pinctrl_can1: can1frp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59 + MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59 + >; + }; + + pinctrl_can2: can2frp { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59 + MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f @@ -302,6 +413,24 @@ >; }; + pinctrl_pwm1: pwm1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f + >; + }; + + pinctrl_pwm2: pwm2 { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f + >; + }; + + pinctrl_pwm3: pwm3 { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f + >; + }; + pinctrl_reg_wlreg_on: regregongrp { fsl,pins = < MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 @@ -324,12 +453,66 @@ >; }; + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79 + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79 + MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79 + MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79 + MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79 + MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79 + MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79 + >; + }; + pinctrl_usbotg1_pwr: usbotg_pwr { fsl,pins = < MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14 >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x59 -- cgit From 9c77ba961ff2bca9ad0b158d0e23a76773c3eaf1 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 6 Dec 2018 08:09:04 -0200 Subject: ARM: dts: imx7d-pico-pi: Extend peripherals support This adds following peripherals for the imx7d-pico-pi as: - LED - Touchscreen - GPIO Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-pico-pi.dts | 56 +++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-pico-pi.dts b/arch/arm/boot/dts/imx7d-pico-pi.dts index 039c17066fe0..70bea95c06d8 100644 --- a/arch/arm/boot/dts/imx7d-pico-pi.dts +++ b/arch/arm/boot/dts/imx7d-pico-pi.dts @@ -8,6 +8,17 @@ model = "TechNexion PICO-IMX7D Board and PI baseboard"; compatible = "technexion,imx7d-pico-pi", "fsl,imx7d"; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + }; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "imx7-sgtl5000"; @@ -35,3 +46,48 @@ VDDIO-supply = <®_vref_1v8>; }; }; + +&i2c4 { + polytouch: touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupt-parent = <&gpio2>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 + >; + }; + +}; -- cgit From 7f68ffe0617b44fe189271701f6443beb23907ad Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 6 Dec 2018 08:09:05 -0200 Subject: ARM: dts: imx7d-pico: Add the imx7d-pico-hobbit variant The imx7d-pico-hobbit contains a imx7d-pico SoM and a hobbit baseboard. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx7d-pico-hobbit.dts | 105 ++++++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-pico-hobbit.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1d6d916c2195..5c7dc0b4aaa8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -572,6 +572,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \ imx7d-nitrogen7.dtb \ + imx7d-pico-hobbit.dtb \ imx7d-pico-pi.dtb \ imx7d-sbc-imx7.dtb \ imx7d-sdb.dtb \ diff --git a/arch/arm/boot/dts/imx7d-pico-hobbit.dts b/arch/arm/boot/dts/imx7d-pico-hobbit.dts new file mode 100644 index 000000000000..7b2198a9372c --- /dev/null +++ b/arch/arm/boot/dts/imx7d-pico-hobbit.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright 2017 NXP + +#include "imx7d-pico.dtsi" + +/ { + model = "TechNexion PICO-IMX7D Board using Hobbit baseboard"; + compatible = "technexion,imx7d-pico-hobbit", "fsl,imx7d"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led { + label = "gpio-led"; + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx7-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + }; + }; +}; + +&i2c1 { + sgtl5000: codec@a { + #sound-dai-cells = <0>; + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_vref_1v8>; + }; +}; + +&i2c4 { + status = "okay"; + + adc081c: adc@50 { + compatible = "ti,adc081c"; + reg = <0x50>; + vref-supply = <®_3p3v>; + }; +}; + +&ecspi3 { + ads7846@0 { + reg = <0>; + compatible = "ti,ads7846"; + interrupt-parent = <&gpio2>; + interrupts = <7 0>; + spi-max-frequency = <1000000>; + pendown-gpio = <&gpio2 7 0>; + vcc-supply = <®_3p3v>; + ti,x-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <4095>; + ti,y-min = /bits/ 16 <0>; + ti,y-max = /bits/ 16 <4095>; + ti,pressure-max = /bits/ 16 <1024>; + ti,x-plate-ohms = /bits/ 16 <90>; + ti,y-plate-ohms = /bits/ 16 <90>; + ti,debounce-max = /bits/ 16 <70>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <2>; + ti,settle-delay-usec = /bits/ 16 <150>; + wakeup-source; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 + >; + }; +}; -- cgit From 2bf5751726e8face217a39f2132df643b995d8bc Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Sat, 10 Nov 2018 15:12:56 +0000 Subject: dt-bindings: fsl: add compatible for imx7ulp evk Add compatible string for imx7ulp evk board. Cc: devicetree@vger.kernel.org Cc: Shawn Guo Acked-by: Rob Herring Signed-off-by: Dong Aisheng Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index 5074aeecd327..7fbc42484001 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -101,6 +101,10 @@ i.MX7 SabreSD Board Required root node properties: - compatible = "fsl,imx7d-sdb", "fsl,imx7d"; +i.MX7ULP Evaluation Kit +Required root node properties: + - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; + Generic i.MX boards ------------------- @@ -123,6 +127,10 @@ i.MX6q generic board Required root node properties: - compatible = "fsl,imx6q"; +i.MX7ULP generic board +Required root node properties: + - compatible = "fsl,imx7ulp"; + Freescale Vybrid Platform Device Tree Bindings ---------------------------------------------- -- cgit From 61ccb001534b7d555e01d013ecb7f94bbf3d1bbe Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Sat, 10 Nov 2018 15:13:00 +0000 Subject: dt-bindings: fsl: add imx7ulp pm related components bindings Add imx7ulp pm related components bindings. Cc: Shawn Guo Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- .../bindings/arm/freescale/fsl,imx7ulp-pm.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt new file mode 100644 index 000000000000..75195bee116f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt @@ -0,0 +1,23 @@ +Freescale i.MX7ULP Power Management Components +---------------------------------------------- + +The Multi-System Mode Controller (MSMC) is responsible for sequencing +the MCU into and out of all stop and run power modes. Specifically, it +monitors events to trigger transitions between power modes while +controlling the power, clocks, and memories of the MCU to achieve the +power consumption and functionality of that mode. + +The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or +Standby modes for either Cortex family. Run, Wait, and Stop are the +common terms used for the primary operating modes of Kinetis +microcontrollers. + +Required properties: +- compatible: Should be "fsl,imx7ulp-smc1". +- reg: Specifies base physical address and size of the register sets. + +Example: +smc1: smc1@40410000 { + compatible = "fsl,imx7ulp-smc1"; + reg = <0x40410000 0x1000>; +}; -- cgit From 20434dc92c058898cc394e352e9c1f83f503dcfe Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Sat, 10 Nov 2018 15:13:08 +0000 Subject: ARM: dts: imx: add common imx7ulp dtsi support The i.MX 7ULP family of processors features NXP's advanced implementation of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics Processing Units (GPUs). This patch aims to add the initial support including: 1) CLK 2) GPIO PTC, PTD, PTE, PTF 3) uSDHC 1/2 4) LPUART 4/5/6/7 5) LPI2C 6/7 Cc: Rob Herring Cc: Shawn Guo Cc: devicetree@vger.kernel.org Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7ulp.dtsi | 346 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 346 insertions(+) create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi new file mode 100644 index 000000000000..931b2754b099 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Dong Aisheng + */ + +#include +#include +#include + +#include "imx7ulp-pinfunc.h" + +/ { + interrupt-parent = <&intc>; + + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio_ptc; + gpio1 = &gpio_ptd; + gpio2 = &gpio_pte; + gpio3 = &gpio_ptf; + i2c0 = &lpi2c6; + i2c1 = &lpi2c7; + mmc0 = &usdhc0; + mmc1 = &usdhc1; + serial0 = &lpuart4; + serial1 = &lpuart5; + serial2 = &lpuart6; + serial3 = &lpuart7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + }; + + intc: interrupt-controller@40021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x40021000 0x1000>, + <0x40022000 0x1000>; + }; + + rosc: clock-rosc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "rosc"; + #clock-cells = <0>; + }; + + sosc: clock-sosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "sosc"; + #clock-cells = <0>; + }; + + sirc: clock-sirc { + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-output-names = "sirc"; + #clock-cells = <0>; + }; + + firc: clock-firc { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + clock-output-names = "firc"; + #clock-cells = <0>; + }; + + upll: clock-upll { + compatible = "fixed-clock"; + clock-frequency = <480000000>; + clock-output-names = "upll"; + #clock-cells = <0>; + }; + + mpll: clock-mpll { + compatible = "fixed-clock"; + clock-frequency = <480000000>; + clock-output-names = "mpll"; + #clock-cells = <0>; + }; + + ahbbridge0: bus@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x800000>; + ranges; + + lpuart4: serial@402d0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402d0000 0x1000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; + clock-names = "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + assigned-clock-rates = <24000000>; + status = "disabled"; + }; + + lpuart5: serial@402e0000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x402e0000 0x1000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; + clock-names = "ipg"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + tpm5: tpm@40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&pcc2 IMX7ULP_CLK_LPTPM5>; + clock-names = "ipg", "per"; + }; + + usdhc0: mmc@40370000 { + compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x40370000 0x10000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&pcc2 IMX7ULP_CLK_USDHC0>; + clock-names ="ipg", "ahb", "per"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc1: mmc@40380000 { + compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x40380000 0x10000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&pcc2 IMX7ULP_CLK_USDHC1>; + clock-names ="ipg", "ahb", "per"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + scg1: clock-controller@403e0000 { + compatible = "fsl,imx7ulp-scg1"; + reg = <0x403e0000 0x10000>; + clocks = <&rosc>, <&sosc>, <&sirc>, + <&firc>, <&upll>, <&mpll>; + clock-names = "rosc", "sosc", "sirc", + "firc", "upll", "mpll"; + #clock-cells = <1>; + }; + + pcc2: clock-controller@403f0000 { + compatible = "fsl,imx7ulp-pcc2"; + reg = <0x403f0000 0x10000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&scg1 IMX7ULP_CLK_DDR_DIV>, + <&scg1 IMX7ULP_CLK_APLL_PFD2>, + <&scg1 IMX7ULP_CLK_APLL_PFD1>, + <&scg1 IMX7ULP_CLK_APLL_PFD0>, + <&scg1 IMX7ULP_CLK_UPLL>, + <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_MIPI_PLL>, + <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_ROSC>, + <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; + clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", + "apll_pfd2", "apll_pfd1", "apll_pfd0", + "upll", "sosc_bus_clk", "mpll", + "firc_bus_clk", "rosc", "spll_bus_clk"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + }; + + smc1: smc1@40410000 { + compatible = "fsl,imx7ulp-smc1"; + reg = <0x40410000 0x1000>; + }; + + pcc3: clock-controller@40b30000 { + compatible = "fsl,imx7ulp-pcc3"; + reg = <0x40b30000 0x10000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&scg1 IMX7ULP_CLK_DDR_DIV>, + <&scg1 IMX7ULP_CLK_APLL_PFD2>, + <&scg1 IMX7ULP_CLK_APLL_PFD1>, + <&scg1 IMX7ULP_CLK_APLL_PFD0>, + <&scg1 IMX7ULP_CLK_UPLL>, + <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_MIPI_PLL>, + <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_ROSC>, + <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; + clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", + "apll_pfd2", "apll_pfd1", "apll_pfd0", + "upll", "sosc_bus_clk", "mpll", + "firc_bus_clk", "rosc", "spll_bus_clk"; + }; + }; + + ahbbridge1: bus@40800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40800000 0x800000>; + ranges; + + lpi2c6: i2c@40a40000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x40a40000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; + clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpi2c7: i2c@40a50000 { + compatible = "fsl,imx7ulp-lpi2c"; + reg = <0x40a50000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; + clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart6: serial@40a60000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40a60000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; + clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + lpuart7: serial@40a70000 { + compatible = "fsl,imx7ulp-lpuart"; + reg = <0x40a70000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; + clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; + status = "disabled"; + }; + + iomuxc1: pinctrl@40ac0000 { + compatible = "fsl,imx7ulp-iomuxc1"; + reg = <0x40ac0000 0x1000>; + }; + + gpio_ptc: gpio@40ae0000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x40ae0000 0x1000 0x400f0000 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLC>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 0 32>; + }; + + gpio_ptd: gpio@40af0000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x40af0000 0x1000 0x400f0040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLD>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 32 32>; + }; + + gpio_pte: gpio@40b00000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x40b00000 0x1000 0x400f0080 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 64 32>; + }; + + gpio_ptf: gpio@40b10000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x40b10000 0x1000 0x400f00c0 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLF>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 96 32>; + }; + }; +}; -- cgit From a73900b826ce6faded48ee3e41aa890fbeba4068 Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Sat, 10 Nov 2018 15:13:12 +0000 Subject: ARM: dts: imx: add imx7ulp evk support The NXP i.MX 7ULP Evaluation Kit (EVK) provides a platform for rapid evaluation of the i.MX 7ULP, which features NXP's advanced implementation of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics Processing Units (GPUs). The EVK enables HDMI output for simple out-of-the-box to bring up but allows reconfiguration for MIPI displays. The EVK is designed as a System-On-Module(SOM) board that connects to an associated baseboard. The SOM provides 1 GB LPDDR3, 8 MB Quad SPI flash, Micro SD 3.0 card socket, WiFi/ Bluetooth capability, USB 2.0 OTG with Type C connector and an NXP PF1550 power management IC (PMIC). The baseboard provides additional capabilities including a full SD/MMC 3.0 card socket, audio codec, multiple sensors, an HDMI connector, and an alternate MIPI display connector. Additionally, the EVK facilitates software development with the ultimate goal of faster time to market through the support of both Linux OS and AndroidTM rich operating systems, as well as FreeRTOS. This patch aims to support the preliminary booting up features as follows: GPIO LPUART FEC SD/MMC See more board details: https://www.nxp.com/products/processors-and-microcontrollers/ arm-based-processors-and-mcus/i.mx-applications-processors/ i.mx-7-processors/evaluation-kit-for-the-i.mx-7ulp-applications -processor:MCIMX7ULP-EVK Cc: Rob Herring Cc: Shawn Guo Cc: devicetree@vger.kernel.org Cc: Sascha Hauer Reviewed-by: Fabio Estevam Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx7ulp-evk.dts | 77 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+) create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b0e966d625b9..fb21bf51af80 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -575,6 +575,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb-sht11.dtb \ imx7s-colibri-eval-v3.dtb \ imx7s-warp.dtb +dtb-$(CONFIG_SOC_IMX7ULP) += \ + imx7ulp-evk.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts new file mode 100644 index 000000000000..a09026a6d22e --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Dong Aisheng + */ + +/dts-v1/; + +#include "imx7ulp.dtsi" + +/ { + model = "NXP i.MX7ULP EVK"; + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; + + chosen { + stdout-path = &lpuart4; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + reg_vsd_3v3: regulator-vsd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0_rst>; + gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&lpuart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&usdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0>; + cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_vsd_3v3>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 + >; + bias-pull-up; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 + IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */ + >; + }; + + pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp { + fsl,pins = < + IMX7ULP_PAD_PTD0__PTD0 0x3 + >; + }; +}; -- cgit From e9e685480b74aef3f3d0967dadb52eea3ff625d2 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 5 Dec 2018 14:48:51 -0800 Subject: ARM: dts: Fix hsi gdd range for omap4 While reviewing the missing mcasp ranges I noticed omap4 hsi range for gdd is wrong so let's fix it. I'm not aware of any omap4 devices in mainline kernel though that use hsi though. Fixes: 84badc5ec5fc ("ARM: dts: omap4: Move l4 child devices to probe them with ti-sysc") Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index 6eb26b837446..5059ecac4478 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -196,12 +196,12 @@ clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x58000 0x4000>; + ranges = <0x0 0x58000 0x5000>; hsi: hsi@0 { compatible = "ti,omap4-hsi"; reg = <0x0 0x4000>, - <0x4a05c000 0x1000>; + <0x5000 0x1000>; reg-names = "sys", "gdd"; clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>; -- cgit From 072ae88ad2f60cbe95bec147892046df3f195d79 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 16 Nov 2018 15:34:33 +0530 Subject: arm64: dts: uniphier: Add all CPUs in cooling maps Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index d7e2d8969601..4a0c46cb11cd 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -206,13 +206,10 @@ cooling-maps { map0 { trip = <&cpu_alert>; - cooling-device = <&cpu0 - THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert>; - cooling-device = <&cpu2 - THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; -- cgit From 5fd98eb7e8ce0f7d7e4f3c138e5b46fc98389804 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 28 Nov 2018 11:42:30 +0900 Subject: ARM: dts: uniphier: add MIO DMAC nodes Add MIO-DMAC (Media IO DMA Controller) nodes, and use them as the DMA engine of SD/eMMC controllers. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-ld4.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/uniphier-pro4.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/uniphier-sld8.dtsi | 14 ++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index b73d594b6dcd..c2706cef0b8a 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -235,6 +235,16 @@ }; }; + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + sd: sdhc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; @@ -246,6 +256,8 @@ clocks = <&mio_clk 0>; reset-names = "host", "bridge"; resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; bus-width = <4>; cap-sd-highspeed; sd-uhs-sdr12; @@ -263,6 +275,8 @@ clocks = <&mio_clk 1>; reset-names = "host", "bridge", "hw"; resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; bus-width = <8>; cap-mmc-highspeed; cap-mmc-hw-reset; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 0beb606cf3c8..97d051ef4968 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -269,6 +269,16 @@ }; }; + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + sd: sdhc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; @@ -280,6 +290,8 @@ clocks = <&mio_clk 0>; reset-names = "host", "bridge"; resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; bus-width = <4>; cap-sd-highspeed; sd-uhs-sdr12; @@ -297,6 +309,8 @@ clocks = <&mio_clk 1>; reset-names = "host", "bridge", "hw"; resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 5>; bus-width = <8>; cap-mmc-highspeed; cap-mmc-hw-reset; @@ -313,6 +327,8 @@ clocks = <&mio_clk 2>; reset-names = "host", "bridge"; resets = <&mio_rst 2>, <&mio_rst 5>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; bus-width = <4>; cap-sd-highspeed; }; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index f7fcf6b45995..efce02768b6f 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -239,6 +239,16 @@ }; }; + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + sd: sdhc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; @@ -250,6 +260,8 @@ clocks = <&mio_clk 0>; reset-names = "host", "bridge"; resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; bus-width = <4>; cap-sd-highspeed; sd-uhs-sdr12; @@ -267,6 +279,8 @@ clocks = <&mio_clk 1>; reset-names = "host", "bridge", "hw"; resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; bus-width = <8>; cap-mmc-highspeed; cap-mmc-hw-reset; -- cgit From f4ef6fd0789da20b32d303859b8f9f8a11396c09 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 10 Dec 2018 13:43:11 -0800 Subject: ARM: dts: Fix ranges for am335x epwmss Looks like I missed the ranges for am335x epwmss. Let's set it up the same way as for am437x and dra7. Fixes: 87fc89ced3a7 ("ARM: dts: am335x: Move l4 child devices to probe them with ti-sysc") Tested-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-cm-t335.dts | 2 +- arch/arm/boot/dts/am335x-evm.dts | 2 +- arch/arm/boot/dts/am335x-evmsk.dts | 2 +- arch/arm/boot/dts/am335x-shc.dts | 2 +- arch/arm/boot/dts/am33xx-l4.dtsi | 36 +++++++++++++++--------------------- 5 files changed, 19 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index c4d3e1f1a95e..2c724bb60417 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -393,7 +393,7 @@ status = "okay"; &epwmss0 { status = "okay"; - ecap0: ecap@48300100 { + ecap0: ecap@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index b7343fab899b..b67f5fee1469 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -519,7 +519,7 @@ &epwmss0 { status = "okay"; - ecap0: ecap@48300100 { + ecap0: ecap@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins>; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 88b41f8d08ae..172c0224e7f6 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -540,7 +540,7 @@ &epwmss2 { status = "okay"; - ecap2: ecap@48304100 { + ecap2: ecap@100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap2_pins>; diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index c9e07584549d..d0fd68873689 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -138,7 +138,7 @@ &epwmss1 { status = "okay"; - ehrpwm1: pwm@48302200 { + ehrpwm1: pwm@200 { pinctrl-names = "default"; pinctrl-0 = <&ehrpwm1_pins>; status = "okay"; diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index bbfdd6ba039d..7b818d9d2eab 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -1899,15 +1899,13 @@ #address-cells = <1>; #size-cells = <1>; status = "disabled"; - ranges = <0x48300100 0x48300100 0x80 /* ECAP */ - 0x48300180 0x48300180 0x80 /* EQEP */ - 0x48300200 0x48300200 0x80>; /* EHRPWM */ + ranges = <0 0 0x1000>; - ecap0: ecap@48300100 { + ecap0: ecap@100 { compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; - reg = <0x48300100 0x80>; + reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; interrupts = <31>; @@ -1915,11 +1913,11 @@ status = "disabled"; }; - ehrpwm0: pwm@48300200 { + ehrpwm0: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; - reg = <0x48300200 0x80>; + reg = <0x200 0x80>; clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -1954,15 +1952,13 @@ #address-cells = <1>; #size-cells = <1>; status = "disabled"; - ranges = <0x48302100 0x48302100 0x80 /* ECAP */ - 0x48302180 0x48302180 0x80 /* EQEP */ - 0x48302200 0x48302200 0x80>; /* EHRPWM */ + ranges = <0 0 0x1000>; - ecap1: ecap@48302100 { + ecap1: ecap@100 { compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; - reg = <0x48302100 0x80>; + reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; interrupts = <47>; @@ -1970,11 +1966,11 @@ status = "disabled"; }; - ehrpwm1: pwm@48302200 { + ehrpwm1: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; - reg = <0x48302200 0x80>; + reg = <0x200 0x80>; clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; @@ -2009,15 +2005,13 @@ #address-cells = <1>; #size-cells = <1>; status = "disabled"; - ranges = <0x48304100 0x48304100 0x80 /* ECAP */ - 0x48304180 0x48304180 0x80 /* EQEP */ - 0x48304200 0x48304200 0x80>; /* EHRPWM */ + ranges = <0 0 0x1000>; - ecap2: ecap@48304100 { + ecap2: ecap@100 { compatible = "ti,am3352-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; - reg = <0x48304100 0x80>; + reg = <0x100 0x80>; clocks = <&l4ls_gclk>; clock-names = "fck"; interrupts = <61>; @@ -2025,11 +2019,11 @@ status = "disabled"; }; - ehrpwm2: pwm@48304200 { + ehrpwm2: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; - reg = <0x48304200 0x80>; + reg = <0x200 0x80>; clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; clock-names = "tbclk", "fck"; status = "disabled"; -- cgit From 5241ccbf2819426e0b55c784105eee7f1c57c9b2 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 7 Dec 2018 16:52:46 -0800 Subject: ARM: dts: Add missing ranges for dra7 mcasp l3 ports We need to add mcasp l3 port ranges for mcasp to use a correct l3 data port address for dma. And we're also missing the optional clocks that we have tagged with HWMOD_OPT_CLKS_NEEDED in omap_hwmod_7xx_data.c. Note that for reading the module revision register HWMOD_OPT_CLKS_NEEDED do not seem to be needed. So they could be probably directly managed only by the mcasp driver, and then we could leave them out for the interconnect target module. Fixes: 4ed0dfe3cf39 ("ARM: dts: dra7: Move l4 child devices to probe them with ti-sysc") Reported-by: Peter Ujfalusi Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-l4.dtsi | 92 ++++++++++++++++++++++++++++++------------ 1 file changed, 66 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 6c01ada9197a..bb45cb7fc3b6 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -2296,7 +2296,15 @@ reg-names = "ap", "la", "ia0", "ia1", "ia2"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x00000000 0x48400000 0x400000>; /* segment 0 */ + ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */ + <0x45800000 0x45800000 0x400000>, /* L3 data port */ + <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ + <0x46000000 0x46000000 0x400000>, /* L3 data port */ + <0x48436000 0x48436000 0x400000>, /* L3 data port */ + <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ + <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ + <0x48450000 0x48450000 0x400000>, /* L3 data port */ + <0x48454000 0x48454000 0x400000>; /* L3 data port */ segment@0 { /* 0x48400000 */ compatible = "simple-bus"; @@ -2364,7 +2372,15 @@ <0x0005b000 0x0005b000 0x001000>, /* ap 59 */ <0x0005c000 0x0005c000 0x001000>, /* ap 60 */ <0x0005d000 0x0005d000 0x001000>, /* ap 61 */ - <0x0005e000 0x0005e000 0x001000>; /* ap 62 */ + <0x0005e000 0x0005e000 0x001000>, /* ap 62 */ + <0x45800000 0x45800000 0x400000>, /* L3 data port */ + <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ + <0x46000000 0x46000000 0x400000>, /* L3 data port */ + <0x48436000 0x48436000 0x400000>, /* L3 data port */ + <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ + <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ + <0x48450000 0x48450000 0x400000>, /* L3 data port */ + <0x48454000 0x48454000 0x400000>; /* L3 data port */ target-module@20000 { /* 0x48420000, ap 47 02.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; @@ -2727,11 +2743,14 @@ , ; /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ - clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x60000 0x2000>; + ranges = <0x0 0x60000 0x2000>, + <0x45800000 0x45800000 0x400000>; mcasp1: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; @@ -2761,11 +2780,14 @@ , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x64000 0x2000>; + ranges = <0x0 0x64000 0x2000>, + <0x45c00000 0x45c00000 0x400000>; mcasp2: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; @@ -2795,11 +2817,14 @@ , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x68000 0x2000>; + ranges = <0x0 0x68000 0x2000>, + <0x46000000 0x46000000 0x400000>; mcasp3: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; @@ -2828,11 +2853,14 @@ , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x6c000 0x2000>; + ranges = <0x0 0x6c000 0x2000>, + <0x48436000 0x48436000 0x400000>; mcasp4: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; @@ -2861,11 +2889,14 @@ , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x70000 0x2000>; + ranges = <0x0 0x70000 0x2000>, + <0x4843a000 0x4843a000 0x400000>; mcasp5: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; @@ -2894,11 +2925,14 @@ , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x74000 0x2000>; + ranges = <0x0 0x74000 0x2000>, + <0x4844c000 0x4844c000 0x400000>; mcasp6: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; @@ -2927,11 +2961,14 @@ , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x78000 0x2000>; + ranges = <0x0 0x78000 0x2000>, + <0x48450000 0x48450000 0x400000>; mcasp7: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; @@ -2960,11 +2997,14 @@ , ; /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ - clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>, + <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>; + clock-names = "fck", "ahclkx", "ahclkr"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x7c000 0x2000>; + ranges = <0x0 0x7c000 0x2000>, + <0x48454000 0x48454000 0x400000>; mcasp8: mcasp@0 { compatible = "ti,dra7-mcasp-audio"; -- cgit From ba0abee70a9825b321f9b3499329b781d1d32f1c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 29 Oct 2018 15:12:39 +0530 Subject: arm64: dts: rockchip: Add on-board LED support on rk3399-ficus Add on-board LED support for Ficus board based on the following standard used by other 96Boards: red:user1 default-trigger: heartbeat red:user2 default-trigger: mmc0/disk-activity (onboard-storage) red:user3 default-trigger: mmc1 (SD-card) red:user4 default-trigger: none, panic-indicator red:wlan default-trigger: phy0tx red:bt default-trigger: hci0-power Signed-off-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 78 +++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts index cce266da28cd..027d428917b8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts @@ -23,6 +23,52 @@ clock-output-names = "clkin_gmac"; #clock-cells = <0>; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>, + <&user_led4>, <&wlan_led>, <&bt_led>; + + user_led1 { + label = "red:user1"; + gpios = <&gpio4 25 0>; + linux,default-trigger = "heartbeat"; + }; + + user_led2 { + label = "red:user2"; + gpios = <&gpio4 26 0>; + linux,default-trigger = "mmc0"; + }; + + user_led3 { + label = "red:user3"; + gpios = <&gpio4 30 0>; + linux,default-trigger = "mmc1"; + }; + + user_led4 { + label = "red:user4"; + gpios = <&gpio1 0 0>; + panic-indicator; + linux,default-trigger = "none"; + }; + + wlan_active_led { + label = "red:wlan"; + gpios = <&gpio1 1 0>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt_active_led { + label = "red:bt"; + gpios = <&gpio1 4 0>; + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; }; &gmac { @@ -66,6 +112,38 @@ <4 27 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + leds { + user_led1: user_led1 { + rockchip,pins = + <4 25 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led2: user_led2 { + rockchip,pins = + <4 26 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led3: user_led3 { + rockchip,pins = + <4 30 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led4: user_led4 { + rockchip,pins = + <1 0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_led: wlan_led { + rockchip,pins = + <1 1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_led: bt_led { + rockchip,pins = + <1 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &usbdrd_dwc3_0 { -- cgit From 953d9f3903659fb1e21f6453ef5221a7652ec908 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 29 Oct 2018 15:12:40 +0530 Subject: arm64: dts: rockchip: Add on-board LED support on rk3399-rock960 Add on-board LED support for Rock960 board based on the following standard used by rest of the 96Boards: green:user1 default-trigger: heartbeat green:user2 default-trigger: mmc0/disk-activity(onboard-storage) green:user3 default-trigger: mmc1 (SD-card) green:user4 default-trigger: none, panic-indicator yellow:wlan default-trigger: phy0tx blue:bt default-trigger: hci0-power Signed-off-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 79 +++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts index 3c3308daec98..12285c51cceb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts @@ -13,6 +13,53 @@ chosen { stdout-path = "serial2:1500000n8"; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>, + <&user_led4>, <&wlan_led>, <&bt_led>; + + user_led1 { + label = "green:user1"; + gpios = <&gpio4 RK_PC2 0>; + linux,default-trigger = "heartbeat"; + }; + + user_led2 { + label = "green:user2"; + gpios = <&gpio4 RK_PC6 0>; + linux,default-trigger = "mmc0"; + }; + + user_led3 { + label = "green:user3"; + gpios = <&gpio4 RK_PD0 0>; + linux,default-trigger = "mmc1"; + }; + + user_led4 { + label = "green:user4"; + gpios = <&gpio4 RK_PD4 0>; + panic-indicator; + linux,default-trigger = "none"; + }; + + wlan_active_led { + label = "yellow:wlan"; + gpios = <&gpio4 RK_PD5 0>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt_active_led { + label = "blue:bt"; + gpios = <&gpio4 RK_PD6 0>; + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; + }; &pcie0 { @@ -20,6 +67,38 @@ }; &pinctrl { + leds { + user_led1: user_led1 { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led2: user_led2 { + rockchip,pins = + <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led3: user_led3 { + rockchip,pins = + <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led4: user_led4 { + rockchip,pins = + <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_led: wlan_led { + rockchip,pins = + <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_led: bt_led { + rockchip,pins = + <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie { pcie_drv: pcie-drv { rockchip,pins = -- cgit From 7841b88a8fdddc0e7f3377fc42efe4cb3be1ed8b Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Mon, 26 Nov 2018 15:35:06 -0200 Subject: ARM: dts: rockchip: Add internal timer support for rv1108 Add support for the internal timer peripheral on RV1108. Signed-off-by: Otavio Salvador Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt | 1 + arch/arm/boot/dts/rv1108.dtsi | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt index 16a5f4577a61..d65fdce7c7f0 100644 --- a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt +++ b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt @@ -2,6 +2,7 @@ Rockchip rk timer Required properties: - compatible: should be: + "rockchip,rv1108-timer", "rockchip,rk3288-timer": for Rockchip RV1108 "rockchip,rk3036-timer", "rockchip,rk3288-timer": for Rockchip RK3036 "rockchip,rk3066-timer", "rockchip,rk3288-timer": for Rockchip RK3066 "rockchip,rk3188-timer", "rockchip,rk3288-timer": for Rockchip RK3188 diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 17dbcf2571fd..d31370ff28f4 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -293,6 +293,14 @@ }; }; + timer: timer@10350000 { + compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer"; + reg = <0x10350000 0x20>; + interrupts = ; + clocks = <&xin24m>, <&cru PCLK_TIMER>; + clock-names = "timer", "pclk"; + }; + watchdog: wdt@10360000 { compatible = "snps,dw-wdt"; reg = <0x10360000 0x100>; -- cgit From a323a513c7128e1597e59f6d3db38c426d229cb9 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Dec 2018 09:50:11 +0100 Subject: dt-bindings: arm: Convert Rockchip board/soc bindings to json-schema Convert Rockchip SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Heiko Stuebner Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Rob Herring [move to per-board entries after confirming with Rob and added recently added boards] Signed-off-by: Heiko Stuebner Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/arm/rockchip.txt | 278 -------------- .../devicetree/bindings/arm/rockchip.yaml | 423 +++++++++++++++++++++ 2 files changed, 423 insertions(+), 278 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/rockchip.txt create mode 100644 Documentation/devicetree/bindings/arm/rockchip.yaml diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt deleted file mode 100644 index 6445dbc25c29..000000000000 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ /dev/null @@ -1,278 +0,0 @@ -Rockchip platforms device tree bindings ---------------------------------------- - -- 96boards RK3399 Ficus (ROCK960 Enterprise Edition) - Required root node properties: - - compatible = "vamrs,ficus", "rockchip,rk3399"; - -- 96boards RK3399 Rock960 (ROCK960 Consumer Edition) - Required root node properties: - - compatible = "vamrs,rock960", "rockchip,rk3399"; - -- Amarula Vyasa RK3288 board - Required root node properties: - - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288"; - -- Asus Tinker board - Required root node properties: - - compatible = "asus,rk3288-tinker", "rockchip,rk3288"; - -- Asus Tinker board S - Required root node properties: - - compatible = "asus,rk3288-tinker-s", "rockchip,rk3288"; - -- Kylin RK3036 board: - Required root node properties: - - compatible = "rockchip,kylin-rk3036", "rockchip,rk3036"; - -- MarsBoard RK3066 board: - Required root node properties: - - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; - -- bq Curie 2 tablet: - Required root node properties: - - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; - -- bq Edison 2 Quad-Core tablet: - Required root node properties: - - compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188"; - -- ChipSPARK Rayeager PX2 board: - Required root node properties: - - compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; - -- Radxa Rock board: - Required root node properties: - - compatible = "radxa,rock", "rockchip,rk3188"; - -- Radxa Rock2 Square board: - Required root node properties: - - compatible = "radxa,rock2-square", "rockchip,rk3288"; - -- Rikomagic MK808 v1 board: - Required root node properties: - - compatible = "rikomagic,mk808", "rockchip,rk3066a"; - -- Firefly Firefly-RK3288 board: - Required root node properties: - - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; - or - - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; - -- Firefly Firefly-RK3288 Reload board: - Required root node properties: - - compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; - -- Firefly Firefly-RK3399 board: - Required root node properties: - - compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; - -- Firefly roc-rk3328-cc board: - Required root node properties: - - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; - -- Firefly ROC-RK3399-PC board: - Required root node properties: - - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; - -- ChipSPARK PopMetal-RK3288 board: - Required root node properties: - - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; - -- Netxeon R89 board: - Required root node properties: - - compatible = "netxeon,r89", "rockchip,rk3288"; - -- GeekBuying GeekBox: - Required root node properties: - - compatible = "geekbuying,geekbox", "rockchip,rk3368"; - -- Google Bob (Asus Chromebook Flip C101PA): - Required root node properties: - compatible = "google,bob-rev13", "google,bob-rev12", - "google,bob-rev11", "google,bob-rev10", - "google,bob-rev9", "google,bob-rev8", - "google,bob-rev7", "google,bob-rev6", - "google,bob-rev5", "google,bob-rev4", - "google,bob", "google,gru", "rockchip,rk3399"; - -- Google Brain (dev-board): - Required root node properties: - - compatible = "google,veyron-brain-rev0", "google,veyron-brain", - "google,veyron", "rockchip,rk3288"; - -- Google Gru (dev-board): - Required root node properties: - - compatible = "google,gru-rev15", "google,gru-rev14", - "google,gru-rev13", "google,gru-rev12", - "google,gru-rev11", "google,gru-rev10", - "google,gru-rev9", "google,gru-rev8", - "google,gru-rev7", "google,gru-rev6", - "google,gru-rev5", "google,gru-rev4", - "google,gru-rev3", "google,gru-rev2", - "google,gru", "rockchip,rk3399"; - -- Google Jaq (Haier Chromebook 11 and more): - Required root node properties: - - compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4", - "google,veyron-jaq-rev3", "google,veyron-jaq-rev2", - "google,veyron-jaq-rev1", "google,veyron-jaq", - "google,veyron", "rockchip,rk3288"; - -- Google Jerry (Hisense Chromebook C11 and more): - Required root node properties: - - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", - "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", - "google,veyron-jerry-rev3", "google,veyron-jerry", - "google,veyron", "rockchip,rk3288"; - -- Google Kevin (Samsung Chromebook Plus): - Required root node properties: - - compatible = "google,kevin-rev15", "google,kevin-rev14", - "google,kevin-rev13", "google,kevin-rev12", - "google,kevin-rev11", "google,kevin-rev10", - "google,kevin-rev9", "google,kevin-rev8", - "google,kevin-rev7", "google,kevin-rev6", - "google,kevin", "google,gru", "rockchip,rk3399"; - -- Google Mickey (Asus Chromebit CS10): - Required root node properties: - - compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7", - "google,veyron-mickey-rev6", "google,veyron-mickey-rev5", - "google,veyron-mickey-rev4", "google,veyron-mickey-rev3", - "google,veyron-mickey-rev2", "google,veyron-mickey-rev1", - "google,veyron-mickey-rev0", "google,veyron-mickey", - "google,veyron", "rockchip,rk3288"; - -- Google Minnie (Asus Chromebook Flip C100P): - Required root node properties: - - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", - "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", - "google,veyron-minnie-rev0", "google,veyron-minnie", - "google,veyron", "rockchip,rk3288"; - -- Google Pinky (dev-board): - Required root node properties: - - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky", - "google,veyron", "rockchip,rk3288"; - -- Google Scarlet - with display from Kingdisplay - Required root node properties: - - compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15", - "google,scarlet-rev14-sku7", "google,scarlet-rev14", - "google,scarlet-rev13-sku7", "google,scarlet-rev13", - "google,scarlet-rev12-sku7", "google,scarlet-rev12", - "google,scarlet-rev11-sku7", "google,scarlet-rev11", - "google,scarlet-rev10-sku7", "google,scarlet-rev10", - "google,scarlet-rev9-sku7", "google,scarlet-rev9", - "google,scarlet-rev8-sku7", "google,scarlet-rev8", - "google,scarlet-rev7-sku7", "google,scarlet-rev7", - "google,scarlet-rev6-sku7", "google,scarlet-rev6", - "google,scarlet-rev5-sku7", "google,scarlet-rev5", - "google,scarlet-rev4-sku7", "google,scarlet-rev4", - "google,scarlet-rev3-sku7", "google,scarlet-rev3", - "google,scarlet", "google,gru", "rockchip,rk3399"; - -- Google Scarlet - with display from Innolux - Required root node properties: - - compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", - "google,scarlet-rev14-sku6", "google,scarlet-rev14", - "google,scarlet-rev13-sku6", "google,scarlet-rev13", - "google,scarlet-rev12-sku6", "google,scarlet-rev12", - "google,scarlet-rev11-sku6", "google,scarlet-rev11", - "google,scarlet-rev10-sku6", "google,scarlet-rev10", - "google,scarlet-rev9-sku6", "google,scarlet-rev9", - "google,scarlet-rev8-sku6", "google,scarlet-rev8", - "google,scarlet-rev7-sku6", "google,scarlet-rev7", - "google,scarlet-rev6-sku6", "google,scarlet-rev6", - "google,scarlet-rev5-sku6", "google,scarlet-rev5", - "google,scarlet-rev4-sku6", "google,scarlet-rev4", - "google,scarlet", "google,gru", "rockchip,rk3399"; - - -- Google Speedy (Asus C201 Chromebook): - Required root node properties: - - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", - "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", - "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", - "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", - "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; - -- mqmaker MiQi: - Required root node properties: - - compatible = "mqmaker,miqi", "rockchip,rk3288"; - -- Phytec phyCORE-RK3288: Rapid Development Kit - Required root node properties: - - compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; - -- Pine64 Rock64 board: - Required root node properties: - - compatible = "pine64,rock64", "rockchip,rk3328"; - -- Pine64 RockPro64 board: - Required root node properties: - - compatible = "pine64,rockpro64", "rockchip,rk3399"; - -- Rockchip PX3 Evaluation board: - Required root node properties: - - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188"; - -- Rockchip PX5 Evaluation board: - Required root node properties: - - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; - -- Rockchip PX30 Evaluation board: - Required root node properties: - - compatible = "rockchip,px30-evb", "rockchip,px30"; - -- Rockchip RV1108 Evaluation board - Required root node properties: - - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - -- Rockchip RK3368 evb: - Required root node properties: - - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; - -- Rockchip R88 board: - Required root node properties: - - compatible = "rockchip,r88", "rockchip,rk3368"; - -- Rockchip RK3228 Evaluation board: - Required root node properties: - - compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; - -- Rockchip RK3229 Evaluation board: - - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - -- Rockchip RK3288 Fennec board: - Required root node properties: - - compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; - -- Rockchip RK3328 evb: - Required root node properties: - - compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; - -- Rockchip RK3399 evb: - Required root node properties: - - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; - -- Rockchip RK3399 Sapphire board standalone: - Required root node properties: - - compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; - -- Rockchip RK3399 Sapphire Excavator board: - Required root node properties: - - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; - -- Theobroma Systems RK3368-uQ7 Haikou Baseboard: - Required root node properties: - - compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368"; - -- Theobroma Systems RK3399-Q7 Haikou Baseboard: - Required root node properties: - - compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399"; - -- Tronsmart Orion R68 Meta - Required root node properties: - - compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368"; diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml new file mode 100644 index 000000000000..b12958bda09c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -0,0 +1,423 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/rockchip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip platforms device tree bindings + +maintainers: + - Heiko Stuebner + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: 96boards RK3399 Ficus (ROCK960 Enterprise Edition) + items: + - const: vamrs,ficus + - const: rockchip,rk3399 + + - description: 96boards RK3399 Rock960 (ROCK960 Consumer Edition) + items: + - const: vamrs,rock960 + - const: rockchip,rk3399 + + - description: Amarula Vyasa RK3288 + items: + - const: amarula,vyasa-rk3288 + - const: rockchip,rk3288 + + - description: Asus Tinker board + items: + - const: asus,rk3288-tinker + - const: rockchip,rk3288 + + - description: Asus Tinker board S + items: + - const: asus,rk3288-tinker-s + - const: rockchip,rk3288 + + - description: bq Curie 2 tablet + items: + - const: mundoreader,bq-curie2 + - const: rockchip,rk3066a + + - description: bq Edison 2 Quad-Core tablet + items: + - const: mundoreader,bq-edison2qc + - const: rockchip,rk3188 + + - description: ChipSPARK PopMetal-RK3288 + items: + - const: chipspark,popmetal-rk3288 + - const: rockchip,rk3288 + + - description: ChipSPARK Rayeager PX2 + items: + - const: chipspark,rayeager-px2 + - const: rockchip,rk3066a + + - description: Firefly Firefly-RK3288 + items: + - enum: + - firefly,firefly-rk3288 + - firefly,firefly-rk3288-beta + - const: rockchip,rk3288 + + - description: Firefly Firefly-RK3288 Reload + items: + - const: firefly,firefly-rk3288-reload + - const: rockchip,rk3288 + + - description: Firefly Firefly-RK3399 + items: + - const: firefly,firefly-rk3399 + - const: rockchip,rk3399 + + - description: Firefly roc-rk3328-cc + items: + - const: firefly,roc-rk3328-cc + - const: rockchip,rk3328 + + - description: Firefly ROC-RK3399-PC + items: + - const: firefly,roc-rk3399-pc + - const: rockchip,rk3399 + + - description: GeekBuying GeekBox + items: + - const: geekbuying,geekbox + - const: rockchip,rk3368 + + - description: Google Bob (Asus Chromebook Flip C101PA) + items: + - const: google,bob-rev13 + - const: google,bob-rev12 + - const: google,bob-rev11 + - const: google,bob-rev10 + - const: google,bob-rev9 + - const: google,bob-rev8 + - const: google,bob-rev7 + - const: google,bob-rev6 + - const: google,bob-rev5 + - const: google,bob-rev4 + - const: google,bob + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Brain (dev-board) + items: + - const: google,veyron-brain-rev0 + - const: google,veyron-brain + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Gru (dev-board) + items: + - const: google,gru-rev15 + - const: google,gru-rev14 + - const: google,gru-rev13 + - const: google,gru-rev12 + - const: google,gru-rev11 + - const: google,gru-rev10 + - const: google,gru-rev9 + - const: google,gru-rev8 + - const: google,gru-rev7 + - const: google,gru-rev6 + - const: google,gru-rev5 + - const: google,gru-rev4 + - const: google,gru-rev3 + - const: google,gru-rev2 + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Jaq (Haier Chromebook 11 and more) + items: + - const: google,veyron-jaq-rev5 + - const: google,veyron-jaq-rev4 + - const: google,veyron-jaq-rev3 + - const: google,veyron-jaq-rev2 + - const: google,veyron-jaq-rev1 + - const: google,veyron-jaq + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Jerry (Hisense Chromebook C11 and more) + items: + - const: google,veyron-jerry-rev7 + - const: google,veyron-jerry-rev6 + - const: google,veyron-jerry-rev5 + - const: google,veyron-jerry-rev4 + - const: google,veyron-jerry-rev3 + - const: google,veyron-jerry + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Kevin (Samsung Chromebook Plus) + items: + - const: google,kevin-rev15 + - const: google,kevin-rev14 + - const: google,kevin-rev13 + - const: google,kevin-rev12 + - const: google,kevin-rev11 + - const: google,kevin-rev10 + - const: google,kevin-rev9 + - const: google,kevin-rev8 + - const: google,kevin-rev7 + - const: google,kevin-rev6 + - const: google,kevin + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Mickey (Asus Chromebit CS10) + items: + - const: google,veyron-mickey-rev8 + - const: google,veyron-mickey-rev7 + - const: google,veyron-mickey-rev6 + - const: google,veyron-mickey-rev5 + - const: google,veyron-mickey-rev4 + - const: google,veyron-mickey-rev3 + - const: google,veyron-mickey-rev2 + - const: google,veyron-mickey-rev1 + - const: google,veyron-mickey-rev0 + - const: google,veyron-mickey + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Minnie (Asus Chromebook Flip C100P) + items: + - const: google,veyron-minnie-rev4 + - const: google,veyron-minnie-rev3 + - const: google,veyron-minnie-rev2 + - const: google,veyron-minnie-rev1 + - const: google,veyron-minnie-rev0 + - const: google,veyron-minnie + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Pinky (dev-board) + items: + - const: google,veyron-pinky-rev2 + - const: google,veyron-pinky + - const: google,veyron + - const: rockchip,rk3288 + + - description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10) + items: + - const: google,scarlet-rev15-sku7 + - const: google,scarlet-rev15 + - const: google,scarlet-rev14-sku7 + - const: google,scarlet-rev14 + - const: google,scarlet-rev13-sku7 + - const: google,scarlet-rev13 + - const: google,scarlet-rev12-sku7 + - const: google,scarlet-rev12 + - const: google,scarlet-rev11-sku7 + - const: google,scarlet-rev11 + - const: google,scarlet-rev10-sku7 + - const: google,scarlet-rev10 + - const: google,scarlet-rev9-sku7 + - const: google,scarlet-rev9 + - const: google,scarlet-rev8-sku7 + - const: google,scarlet-rev8 + - const: google,scarlet-rev7-sku7 + - const: google,scarlet-rev7 + - const: google,scarlet-rev6-sku7 + - const: google,scarlet-rev6 + - const: google,scarlet-rev5-sku7 + - const: google,scarlet-rev5 + - const: google,scarlet-rev4-sku7 + - const: google,scarlet-rev4 + - const: google,scarlet-rev3-sku7 + - const: google,scarlet-rev3 + - const: google,scarlet + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Scarlet - Innolux display (Acer Chromebook Tab 10) + items: + - const: google,scarlet-rev15-sku6 + - const: google,scarlet-rev15 + - const: google,scarlet-rev14-sku6 + - const: google,scarlet-rev14 + - const: google,scarlet-rev13-sku6 + - const: google,scarlet-rev13 + - const: google,scarlet-rev12-sku6 + - const: google,scarlet-rev12 + - const: google,scarlet-rev11-sku6 + - const: google,scarlet-rev11 + - const: google,scarlet-rev10-sku6 + - const: google,scarlet-rev10 + - const: google,scarlet-rev9-sku6 + - const: google,scarlet-rev9 + - const: google,scarlet-rev8-sku6 + - const: google,scarlet-rev8 + - const: google,scarlet-rev7-sku6 + - const: google,scarlet-rev7 + - const: google,scarlet-rev6-sku6 + - const: google,scarlet-rev6 + - const: google,scarlet-rev5-sku6 + - const: google,scarlet-rev5 + - const: google,scarlet-rev4-sku6 + - const: google,scarlet-rev4 + - const: google,scarlet + - const: google,gru + - const: rockchip,rk3399 + + - description: Google Speedy (Asus C201 Chromebook) + items: + - const: google,veyron-speedy-rev9 + - const: google,veyron-speedy-rev8 + - const: google,veyron-speedy-rev7 + - const: google,veyron-speedy-rev6 + - const: google,veyron-speedy-rev5 + - const: google,veyron-speedy-rev4 + - const: google,veyron-speedy-rev3 + - const: google,veyron-speedy-rev2 + - const: google,veyron-speedy + - const: google,veyron + - const: rockchip,rk3288 + + - description: Haoyu MarsBoard RK3066 + items: + - const: haoyu,marsboard-rk3066 + - const: rockchip,rk3066a + + - description: mqmaker MiQi + items: + - const: mqmaker,miqi + - const: rockchip,rk3288 + + - description: Netxeon R89 board + items: + - const: netxeon,r89 + - const: rockchip,rk3288 + + - description: Phytec phyCORE-RK3288 Rapid Development Kit + items: + - const: phytec,rk3288-pcm-947 + - const: phytec,rk3288-phycore-som + - const: rockchip,rk3288 + + - description: Pine64 Rock64 + items: + - const: pine64,rock64 + - const: rockchip,rk3328 + + - description: Pine64 RockPro64 + items: + - const: pine64,rockpro64 + - const: rockchip,rk3399 + + - description: Radxa Rock + items: + - const: radxa,rock + - const: rockchip,rk3188 + + - description: Radxa Rock2 Square + items: + - const: radxa,rock2-square + - const: rockchip,rk3288 + + - description: Rikomagic MK808 v1 + items: + - const: rikomagic,mk808 + - const: rockchip,rk3066a + + - description: Rockchip Kylin + items: + - const: rockchip,kylin-rk3036 + - const: rockchip,rk3036 + + - description: Rockchip PX3 Evaluation board + items: + - const: rockchip,px3-evb + - const: rockchip,px3 + - const: rockchip,rk3188 + + - description: Rockchip PX30 Evaluation board + items: + - const: rockchip,px30-evb + - const: rockchip,px30 + + - description: Rockchip PX5 Evaluation board + items: + - const: rockchip,px5-evb + - const: rockchip,px5 + - const: rockchip,rk3368 + + - description: Rockchip R88 + items: + - const: rockchip,r88 + - const: rockchip,rk3368 + + - description: Rockchip RK3228 Evaluation board + items: + - const: rockchip,rk3228-evb + - const: rockchip,rk3228 + + - description: Rockchip RK3229 Evaluation board + items: + - const: rockchip,rk3229-evb + - const: rockchip,rk3229 + + - description: Rockchip RK3288 Evaluation board + items: + - enum: + - rockchip,rk3288-evb-act8846 + - rockchip,rk3288-evb-rk808 + - const: rockchip,rk3288 + + - description: Rockchip RK3288 Fennec + items: + - const: rockchip,rk3288-fennec + - const: rockchip,rk3288 + + - description: Rockchip RK3328 Evaluation board + items: + - const: rockchip,rk3328-evb + - const: rockchip,rk3328 + + - description: Rockchip RK3368 Evaluation board (act8846 pmic) + items: + - const: rockchip,rk3368-evb-act8846 + - const: rockchip,rk3368 + + - description: Rockchip RK3399 Evaluation board + items: + - const: rockchip,rk3399-evb + - const: rockchip,rk3399 + + - description: Rockchip RK3399 Sapphire standalone + items: + - const: rockchip,rk3399-sapphire + - const: rockchip,rk3399 + + - description: Rockchip RK3399 Sapphire with Excavator Baseboard + items: + - const: rockchip,rk3399-sapphire-excavator + - const: rockchip,rk3399 + + - description: Rockchip RV1108 Evaluation board + items: + - const: rockchip,rv1108-evb + - const: rockchip,rv1108 + + - description: Theobroma Systems RK3368-uQ7 with Haikou baseboard + items: + - const: tsd,rk3368-uq7-haikou + - const: rockchip,rk3368 + + - description: Theobroma Systems RK3399-Q7 with Haikou baseboard + items: + - const: tsd,rk3399-q7-haikou + - const: rockchip,rk3399 + + - description: Tronsmart Orion R68 Meta + items: + - const: tronsmart,orion-r68-meta + - const: rockchip,rk3368 +... -- cgit From b8222335938a9c6425b9f14e61c3ca67c8189dfc Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 12 Dec 2018 15:46:16 -0800 Subject: ARM: dts: Fix wrong address for omap5 sata phy Looks like I missed converting the omap5 sata phy addresses to use offset from the module base instead of full physical address. While at it, we can also more it to be a direct child of the interconnect target module, it is not really a child of the ocp2scp control device. Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-l4.dtsi | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index 5e00147522b6..2e926dd38b08 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -515,19 +515,19 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0 0x20>; - ranges = <0 0 0x4000>; - sata_phy: phy@4a096000 { - compatible = "ti,phy-pipe3-sata"; - reg = <0x6000 0x80>, /* phy_rx */ - <0x4A096400 0x64>, /* phy_tx */ - <0x4A096800 0x40>; /* pll_ctrl */ - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - syscon-phy-power = <&scm_conf 0x374>; - clocks = <&sys_clkin>, - <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; - clock-names = "sysclk", "refclk"; - #phy-cells = <0>; - }; + }; + + sata_phy: phy@6000 { + compatible = "ti,phy-pipe3-sata"; + reg = <0x6000 0x80>, /* phy_rx */ + <0x6400 0x64>, /* phy_tx */ + <0x6800 0x40>; /* pll_ctrl */ + reg-names = "phy_rx", "phy_tx", "pll_ctrl"; + syscon-phy-power = <&scm_conf 0x374>; + clocks = <&sys_clkin>, + <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; + clock-names = "sysclk", "refclk"; + #phy-cells = <0>; }; }; -- cgit From c7a851b7050e2b7b8ed6e96c1437e19ca5720851 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 12 Dec 2018 15:57:27 -0800 Subject: ARM: dts: Cosmetic fix for omap5 USB node names These should be now using offset from the module base and not the full physical address. Cc: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-l4.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index 2e926dd38b08..9c7e309d9c2c 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -195,7 +195,7 @@ #size-cells = <1>; utmi-mode = <2>; ranges = <0 0 0x20000>; - dwc3: dwc3@4a030000 { + dwc3: dwc3@10000 { compatible = "snps,dwc3"; reg = <0x10000 0x10000>; interrupts = , @@ -332,14 +332,14 @@ "refclk_60m_ext_p1", "refclk_60m_ext_p2"; - usbhsohci: ohci@4a064800 { + usbhsohci: ohci@800 { compatible = "ti,ohci-omap3"; reg = <0x800 0x400>; interrupts = ; remote-wakeup-connected; }; - usbhsehci: ehci@4a064c00 { + usbhsehci: ehci@c00 { compatible = "ti,ehci-omap"; reg = <0xc00 0x400>; interrupts = ; -- cgit From 497f1bcb9009fbcf1376aaa19b0b23a7e6988832 Mon Sep 17 00:00:00 2001 From: Markus Reichl Date: Sat, 8 Dec 2018 21:56:56 +0100 Subject: ARM: dts: exynos: Add missing CPUs in cooling maps for Odroid X2 While updating cooling maps, the exynos4412-prime.dtsi was left untouched. This is not a problem with Odroid U3 because it uses its own map with fan (which was updated). However the cooling maps of Odroid X2 rely only on exynos4412-prime.dtsi. Signed-off-by: Markus Reichl Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-prime.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-prime.dtsi b/arch/arm/boot/dts/exynos4412-prime.dtsi index 8e7a7fb98124..d83fbd4e434c 100644 --- a/arch/arm/boot/dts/exynos4412-prime.dtsi +++ b/arch/arm/boot/dts/exynos4412-prime.dtsi @@ -30,9 +30,11 @@ }; &cooling_map0 { - cooling-device = <&cpu0 9 9>; + cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, + <&cpu2 9 9>, <&cpu3 9 9>; }; &cooling_map1 { - cooling-device = <&cpu0 15 15>; + cooling-device = <&cpu0 15 15>, <&cpu1 15 15>, + <&cpu2 15 15>, <&cpu3 15 15>; }; -- cgit From 8ac686d7dfed721102860ff2571e6b9f529ae81a Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 12 Dec 2018 18:57:44 +0100 Subject: ARM: dts: exynos: Specify I2S assigned clocks in proper node The assigned parent clocks should be normally specified in the consumer device's DT node, this ensures respective driver always sees correct clock settings when required. This patch fixes regression in audio subsystem on Odroid XU3/XU4 boards that appeared after commits: commit 647d04f8e07a ("ASoC: samsung: i2s: Ensure the RCLK rate is properly determined") commit 995e73e55f46 ("ASoC: samsung: i2s: Fix rclk_srcrate handling") commit 48279c53fd1d ("ASoC: samsung: i2s: Prevent external abort on exynos5433 I2S1 access") Without this patch the driver gets wrong clock as the I2S function clock (op_clk) in probe() and effectively the clock which is finally assigned from DT is not being enabled/disabled in the runtime resume/suspend ops. Without the above listed commits the EXYNOS_I2S_BUS clock was always set as parent of CLK_I2S_RCLK_SRC regardless of DT settings so there was no issue with not enabled EXYNOS_SCLK_I2S. Cc: # 4.17.x Signed-off-by: Sylwester Nawrocki Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 9 ++++----- arch/arm/boot/dts/exynos5422-odroidxu4.dts | 9 ++++----- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi index 03611d50c5a9..e84544b220b9 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi @@ -26,8 +26,7 @@ "Speakers", "SPKL", "Speakers", "SPKR"; - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>, - <&clock CLK_MOUT_EPLL>, + assigned-clocks = <&clock CLK_MOUT_EPLL>, <&clock CLK_MOUT_MAU_EPLL>, <&clock CLK_MOUT_USER_MAU_EPLL>, <&clock_audss EXYNOS_MOUT_AUDSS>, @@ -36,8 +35,7 @@ <&clock_audss EXYNOS_DOUT_AUD_BUS>, <&clock_audss EXYNOS_DOUT_I2S>; - assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>, - <&clock CLK_FOUT_EPLL>, + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, <&clock CLK_MOUT_EPLL>, <&clock CLK_MOUT_MAU_EPLL>, <&clock CLK_MAU_EPLL>, @@ -48,7 +46,6 @@ <0>, <0>, <0>, - <0>, <196608001>, <(196608002 / 2)>, <196608000>; @@ -84,4 +81,6 @@ &i2s0 { status = "okay"; + assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; + assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 4a30cc849b00..122174ea9e0a 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -33,8 +33,7 @@ compatible = "samsung,odroid-xu3-audio"; model = "Odroid-XU4"; - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>, - <&clock CLK_MOUT_EPLL>, + assigned-clocks = <&clock CLK_MOUT_EPLL>, <&clock CLK_MOUT_MAU_EPLL>, <&clock CLK_MOUT_USER_MAU_EPLL>, <&clock_audss EXYNOS_MOUT_AUDSS>, @@ -43,8 +42,7 @@ <&clock_audss EXYNOS_DOUT_AUD_BUS>, <&clock_audss EXYNOS_DOUT_I2S>; - assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>, - <&clock CLK_FOUT_EPLL>, + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, <&clock CLK_MOUT_EPLL>, <&clock CLK_MOUT_MAU_EPLL>, <&clock CLK_MAU_EPLL>, @@ -55,7 +53,6 @@ <0>, <0>, <0>, - <0>, <196608001>, <(196608002 / 2)>, <196608000>; @@ -79,6 +76,8 @@ &i2s0 { status = "okay"; + assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; + assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; }; &pwm { -- cgit From fc66393ab5d695533a5eb0bce8ceffa11d747933 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 13 Nov 2018 11:31:08 +0530 Subject: dt-bindings: pinctrl: k3: Introduce pinmux definitions The dt-bindings header for TI K3 AM6 SoCs define a set of macros for defining pinmux configs in human readable form, instead of raw-coded hex values. Signed-off-by: Vignesh R Acked-by: Linus Walleij Reviewed-by: Rob Herring Acked-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Tero Kristo --- MAINTAINERS | 1 + include/dt-bindings/pinctrl/k3.h | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 include/dt-bindings/pinctrl/k3.h diff --git a/MAINTAINERS b/MAINTAINERS index f4855974f325..9ac39fa34b23 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2204,6 +2204,7 @@ S: Supported F: Documentation/devicetree/bindings/arm/ti/k3.txt F: arch/arm64/boot/dts/ti/Makefile F: arch/arm64/boot/dts/ti/k3-* +F: include/dt-bindings/pinctrl/k3.h ARM/TEXAS INSTRUMENT KEYSTONE ARCHITECTURE M: Santosh Shilimkar diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h new file mode 100644 index 000000000000..45e11b6170ca --- /dev/null +++ b/include/dt-bindings/pinctrl/k3.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for pinctrl bindings for TI's K3 SoC + * family. + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ +#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H +#define _DT_BINDINGS_PINCTRL_TI_K3_H + +#define PULLUDEN_SHIFT (16) +#define PULLTYPESEL_SHIFT (17) +#define RXACTIVE_SHIFT (18) + +#define PULL_DISABLE (1 << PULLUDEN_SHIFT) +#define PULL_ENABLE (0 << PULLUDEN_SHIFT) + +#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) +#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) + +#define INPUT_EN (1 << RXACTIVE_SHIFT) +#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) + +/* Only these macros are expected be used directly in device tree files */ +#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) + +#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#endif -- cgit From 1d79b4375fbc9ba4a113529090dab6b98e7b572c Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 13 Nov 2018 11:31:09 +0530 Subject: arm64: dts: ti: k3-am65: Add pinctrl regions Add pinctrl regions for the main and wkup mmr. The range for main pinctrl region contains a gap at offset 0x2e4, and because of this, the pinctrl range is split into two sections. Signed-off-by: Tero Kristo Signed-off-by: Vignesh R Acked-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 + 3 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index adcd6341e40c..f7c2a60d5c80 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -69,4 +69,20 @@ clock-frequency = <48000000>; current-speed = <115200>; }; + + main_pmx0: pinmux@11c000 { + compatible = "pinctrl-single"; + reg = <0x0 0x11c000 0x0 0x2e4>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_pmx1: pinmux@11c2e8 { + compatible = "pinctrl-single"; + reg = <0x0 0x11c2e8 0x0 0x24>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 8d7b47f9dfbf..19b46f40789b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -34,6 +34,14 @@ }; }; + wkup_pmx0: pinmux@4301c000 { + compatible = "pinctrl-single"; + reg = <0x4301c000 0x118>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + wkup_uart0: serial@42300000 { compatible = "ti,am654-uart"; reg = <0x42300000 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 3d4bf369d030..6fdfc7815811 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { model = "Texas Instruments K3 AM654 SoC"; -- cgit From 3f94859fd7ba4f5efa84767dba569d82e060b295 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 13 Nov 2018 11:31:10 +0530 Subject: arm64: dts: ti: am654-base-board: Add pinmux for main uart0 Add pinmux for main uart0 that is serves as console on AM654 EVM Signed-off-by: Vignesh R Acked-by: Nishanth Menon Signed-off-by: Tero Kristo --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index e146ac2ad781..cbf9d3dfeaa3 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -35,7 +35,23 @@ }; }; +&main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ + AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ + AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ + AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ + >; + }; +}; + &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "disabled"; }; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; -- cgit From 19a1768fc34acc57d3ce2d945a676dfa032e6ba4 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 13 Nov 2018 11:31:11 +0530 Subject: arm64: dts: ti: k3-am654-base-board: Add I2C nodes Add DT entries for I2C instances present in AM654 SoC. Signed-off-by: Vignesh R Acked-by: Nishanth Menon Signed-off-by: Tero Kristo --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 44 ++++++++++++++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 11 ++++ arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 11 ++++ arch/arm64/boot/dts/ti/k3-am65.dtsi | 6 +++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 70 ++++++++++++++++++++++++++ 5 files changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index f7c2a60d5c80..916434839603 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -85,4 +85,48 @@ pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; + + main_i2c0: i2c@2000000 { + compatible = "ti,am654-i2c", "ti,omap4-i2c"; + reg = <0x0 0x2000000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 110 1>; + power-domains = <&k3_pds 110>; + }; + + main_i2c1: i2c@2010000 { + compatible = "ti,am654-i2c", "ti,omap4-i2c"; + reg = <0x0 0x2010000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 111 1>; + power-domains = <&k3_pds 111>; + }; + + main_i2c2: i2c@2020000 { + compatible = "ti,am654-i2c", "ti,omap4-i2c"; + reg = <0x0 0x2020000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 112 1>; + power-domains = <&k3_pds 112>; + }; + + main_i2c3: i2c@2030000 { + compatible = "ti,am654-i2c", "ti,omap4-i2c"; + reg = <0x0 0x2030000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 113 1>; + power-domains = <&k3_pds 113>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 8c611d16df44..1fd027748e1f 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -15,4 +15,15 @@ clock-frequency = <96000000>; current-speed = <115200>; }; + + mcu_i2c0: i2c@40b00000 { + compatible = "ti,am654-i2c", "ti,omap4-i2c"; + reg = <0x0 0x40b00000 0x0 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 114 1>; + power-domains = <&k3_pds 114>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 19b46f40789b..9e8467ce7ad8 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -51,4 +51,15 @@ clock-frequency = <48000000>; current-speed = <115200>; }; + + wkup_i2c0: i2c@42120000 { + compatible = "ti,am654-i2c", "ti,omap4-i2c"; + reg = <0x42120000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 115 1>; + power-domains = <&k3_pds 115>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 6fdfc7815811..50f4be2047a9 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -23,6 +23,12 @@ serial2 = &main_uart0; serial3 = &main_uart1; serial4 = &main_uart2; + i2c0 = &wkup_i2c0; + i2c1 = &mcu_i2c0; + i2c2 = &main_i2c0; + i2c3 = &main_i2c1; + i2c4 = &main_i2c2; + i2c5 = &main_i2c3; }; chosen { }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index cbf9d3dfeaa3..bd5a0069191d 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -35,6 +35,15 @@ }; }; +&wkup_pmx0 { + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ + AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */ + >; + }; +}; + &main_pmx0 { main_uart0_pins_default: main-uart0-pins-default { pinctrl-single,pins = < @@ -44,6 +53,29 @@ AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ >; }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */ + AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ + >; + }; +}; + +&main_pmx1 { + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ + AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ + AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ + >; + }; }; &wkup_uart0 { @@ -55,3 +87,41 @@ pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + pca9554: gpio@39 { + compatible = "nxp,pca9554"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + pca9555: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; +}; -- cgit From 07c663b0ee576a33c29f211d2e23484a9aa5ff30 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Fri, 7 Dec 2018 15:05:34 +0530 Subject: arm64: dts: ti: k3-am65-main: Add ECAP PWM node Add DT entry for ECAP0 PWM node present in main domain Signed-off-by: Vignesh R Signed-off-by: Tero Kristo --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 916434839603..0a0a8fc5df64 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -129,4 +129,13 @@ clocks = <&k3_clks 113 1>; power-domains = <&k3_pds 113>; }; + + ecap0: pwm@3100000 { + compatible = "ti,am654-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x0 0x03100000 0x0 0x60>; + power-domains = <&k3_pds 39>; + clocks = <&k3_clks 39 0>; + clock-names = "fck"; + }; }; -- cgit From e577d79424c07af63d0f19817a425bf4ccf0ec81 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Fri, 7 Dec 2018 15:05:35 +0530 Subject: arm64: dts: ti: k3-am654-base-board: Enable ECAP PWM Enable ECAP PWM which is used for LCD backlight. Signed-off-by: Vignesh R Signed-off-by: Tero Kristo --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index bd5a0069191d..49ec2c3f5ef1 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -76,6 +76,12 @@ AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ >; }; + + ecap0_pins_default: ecap0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ + >; + }; }; &wkup_uart0 { @@ -125,3 +131,8 @@ pinctrl-0 = <&main_i2c2_pins_default>; clock-frequency = <400000>; }; + +&ecap0 { + pinctrl-names = "default"; + pinctrl-0 = <&ecap0_pins_default>; +}; -- cgit From c484fc957219e95e023efe74bfc6cc189303e6f4 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Wed, 12 Dec 2018 10:48:06 +0530 Subject: arm64: dts: ti: k3-am654: Populate power-domain property for UART nodes Populate power-domain property for UART nodes, this is required for Linux to enable UART clocks via PM calls. Without this UART instances not initialized by bootloader (like main_uart1) fails to work in Linux. Also, drop current-speed property from main_uart1 and main_uart2 nodes as these UARTs are not initialized before Linux boots up and current speed is unknown. Signed-off-by: Vignesh R Signed-off-by: Tero Kristo --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 1 + 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 0a0a8fc5df64..6446652850c6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -48,6 +48,7 @@ interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; + power-domains = <&k3_pds 146>; }; main_uart1: serial@2810000 { @@ -57,7 +58,7 @@ reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; + power-domains = <&k3_pds 147>; }; main_uart2: serial@2820000 { @@ -67,7 +68,7 @@ reg-io-width = <4>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; + power-domains = <&k3_pds 148>; }; main_pmx0: pinmux@11c000 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 1fd027748e1f..3b7a519960b9 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -14,6 +14,7 @@ interrupts = ; clock-frequency = <96000000>; current-speed = <115200>; + power-domains = <&k3_pds 149>; }; mcu_i2c0: i2c@40b00000 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 9e8467ce7ad8..7cbdc0912ab7 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -50,6 +50,7 @@ interrupts = ; clock-frequency = <48000000>; current-speed = <115200>; + power-domains = <&k3_pds 150>; }; wkup_i2c0: i2c@42120000 { -- cgit From 2cd7d393f461b931bd6ba2f3971f20b087a1b952 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Sun, 9 Dec 2018 15:52:21 +0530 Subject: arm64: dts: ti: k3-am654: Add McSPI DT nodes There are 3 instances of McSPI in MCU domain and 4 instances in Main domain. Add DT nodes for all McSPI instances present on AM654 SoC. Signed-off-by: Vignesh R Signed-off-by: Tero Kristo --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 52 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 30 ++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 6446652850c6..272cf8fc8d30 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -139,4 +139,56 @@ clocks = <&k3_clks 39 0>; clock-names = "fck"; }; + + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x2100000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 137 1>; + power-domains = <&k3_pds 137>; + #address-cells = <1>; + #size-cells = <0>; + }; + + main_spi1: spi@2110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x2110000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 138 1>; + power-domains = <&k3_pds 138>; + #address-cells = <1>; + #size-cells = <0>; + assigned-clocks = <&k3_clks 137 1>; + assigned-clock-rates = <48000000>; + }; + + main_spi2: spi@2120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x2120000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 139 1>; + power-domains = <&k3_pds 139>; + #address-cells = <1>; + #size-cells = <0>; + }; + + main_spi3: spi@2130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x2130000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 140 1>; + power-domains = <&k3_pds 140>; + #address-cells = <1>; + #size-cells = <0>; + }; + + main_spi4: spi@2140000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x2140000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 141 1>; + power-domains = <&k3_pds 141>; + #address-cells = <1>; + #size-cells = <0>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 3b7a519960b9..593f718e8fb5 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -27,4 +27,34 @@ clocks = <&k3_clks 114 1>; power-domains = <&k3_pds 114>; }; + + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x40300000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 142 1>; + power-domains = <&k3_pds 142>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x40310000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 143 1>; + power-domains = <&k3_pds 143>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x40320000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 144 1>; + power-domains = <&k3_pds 144>; + #address-cells = <1>; + #size-cells = <0>; + }; }; -- cgit From 5da94b50475acaa728560e8c1d3f7291e1062eb3 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Sun, 9 Dec 2018 15:52:22 +0530 Subject: arm64: dts: ti: k3-am654: Enable main domain McSPI0 Enable McSPI0 of main domain and add DT node for the SPI NOR flash connected to CS0. Signed-off-by: Vignesh R Signed-off-by: Tero Kristo --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 49ec2c3f5ef1..e41fc3a5987b 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -60,6 +60,15 @@ AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ >; }; + + main_spi0_pins_default: main-spi0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ + AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ + AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */ + AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ + >; + }; }; &main_pmx1 { @@ -136,3 +145,21 @@ pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins_default>; }; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi0_pins_default>; + #address-cells = <1>; + #size-cells= <0>; + ti,pindir-d0-out-d1-in = <1>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + spi-max-frequency = <48000000>; + #address-cells = <1>; + #size-cells= <1>; + }; +}; -- cgit From 63f2d2a34011e8326c18d691b7c6261624e39667 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 10 Dec 2018 16:28:48 +0000 Subject: ARM: dts: Remove unused properties from FSL QSPI driver nodes The properties 'bus-num', 'fsl,spi-num-chipselects' and 'fsl,spi-flash-chipselects' were never read by the driver and can be removed. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts index d01f64b252b1..6bb7ce05ccf3 100644 --- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts +++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts @@ -203,9 +203,6 @@ }; &qspi { - bus-num = <0>; - fsl,spi-num-chipselects = <2>; - fsl,spi-flash-chipselects = <0>; fsl,qspi-has-second-chip; status = "okay"; -- cgit From 00b79b07cb2aab508e00d4a80ba2525e34b8b9c6 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 10 Dec 2018 16:28:49 +0000 Subject: ARM: dts: imx6sx-sdb: Fix the reg properties for the FSL QSPI nodes The current driver does not use the reg properties, but we will add a new driver soon. To make sure we have a consistent scheme, let's fix the reg properties here. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sdb-reva.dts | 4 ++-- arch/arm/boot/dts/imx6sx-sdb.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index 53241ae09ee9..028985823dc8 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -130,8 +130,8 @@ spi-max-frequency = <66000000>; }; - flash1: s25fl128s@1 { - reg = <1>; + flash1: s25fl128s@2 { + reg = <2>; #address-cells = <1>; #size-cells = <1>; compatible = "spansion,s25fl128s", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index b1b33ad001d9..f0a2244a3b2e 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -116,12 +116,12 @@ reg = <0>; }; - flash1: n25q256a@1 { + flash1: n25q256a@2 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; spi-max-frequency = <29000000>; - reg = <1>; + reg = <2>; }; }; -- cgit From 4f15a4e0d21b9b171aaa78efde2fd60f44f2e62c Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 10 Dec 2018 16:28:50 +0000 Subject: ARM: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller We will move the FSL QSPI driver to the SPI framework soon. To prepare and to make sure the full buswidth is used (as it is with the current driver), let's add the right properties. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sdb-reva.dts | 4 ++++ arch/arm/boot/dts/imx6sx-sdb.dts | 4 ++++ arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 2 ++ arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 2 ++ 4 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index 028985823dc8..00c485482301 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -128,6 +128,8 @@ #size-cells = <1>; compatible = "spansion,s25fl128s", "jedec,spi-nor"; spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; }; flash1: s25fl128s@2 { @@ -136,6 +138,8 @@ #size-cells = <1>; compatible = "spansion,s25fl128s", "jedec,spi-nor"; spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; }; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index f0a2244a3b2e..998e3e13a005 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -113,6 +113,8 @@ #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; reg = <0>; }; @@ -121,6 +123,8 @@ #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; reg = <2>; }; }; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index 5223ada4fe31..9207d5d071f1 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -217,6 +217,8 @@ #size-cells = <1>; compatible = "micron,n25q256a"; spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; reg = <0>; }; }; diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts index 6bb7ce05ccf3..6a83f30029ea 100644 --- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts +++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts @@ -211,6 +211,8 @@ #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; reg = <0>; partitions@0 { -- cgit From a0578d2419e1833b3014c6ef63ba8139549d875b Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 10 Dec 2018 16:28:48 +0000 Subject: arm64: dts: Remove unused properties from FSL QSPI driver nodes The properties 'num-cs' and 'bus-num' were never read by the driver and can be removed. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 1 - arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 2 -- arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 2 -- 3 files changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts index dff3d648172e..d2c06ad40b0e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts @@ -135,7 +135,6 @@ }; &qspi { - bus-num = <0>; status = "okay"; qflash0: s25fl128s@0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts index e58a8ca1386c..6ec1adb2dc8b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts @@ -163,8 +163,6 @@ }; &qspi { - num-cs = <2>; - bus-num = <0>; status = "okay"; qflash0: s25fl128s@0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index a59b48203688..17f1298f448d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -99,8 +99,6 @@ }; &qspi { - num-cs = <2>; - bus-num = <0>; status = "okay"; qflash0: s25fs512s@0 { -- cgit From 30648e9f864774388d261f42e79955362f4739e7 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 10 Dec 2018 16:28:49 +0000 Subject: arm64: dts: Add spi-[tx/rx]-bus-width for the FSL QSPI controller We will move the FSL QSPI driver to the SPI framework soon. To prepare and to make sure the full buswidth is used (as it is with the current driver), let's add the right properties. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 2 ++ arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 2 ++ arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++++ arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 4 ++++ 4 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts index d2c06ad40b0e..8a500940f124 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts @@ -142,6 +142,8 @@ #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; reg = <0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts index 6ec1adb2dc8b..2f220ec4947b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts @@ -170,6 +170,8 @@ #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; reg = <0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index 17f1298f448d..07c665c6e0dc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -106,6 +106,8 @@ #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; reg = <0>; }; @@ -114,6 +116,8 @@ #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; reg = <1>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi index c11f52e7ae9a..10d2fe091965 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi @@ -134,6 +134,8 @@ #size-cells = <1>; compatible = "st,m25p80"; spi-max-frequency = <20000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; reg = <0>; }; flash2: s25fl256s1@2 { @@ -141,6 +143,8 @@ #size-cells = <1>; compatible = "st,m25p80"; spi-max-frequency = <20000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; reg = <2>; }; }; -- cgit From b7b69fb840f50d7037b3ab0fd95a3a89086c8fad Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 14 Dec 2018 10:55:38 +0100 Subject: ARM: dts: suniv: Fix improper bindings include patch The clock and reset bindings are going through different trees, and while the patch doesn't contain any value defined in that header, it still includes those files and result in a build breakage when building the DT without the matching clock and reset patches applied. Signed-off-by: Maxime Ripard Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index aff5f9022cd6..6100d3b75f61 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -4,9 +4,6 @@ * Copyright 2018 Mesih Kilinc */ -#include -#include - / { #address-cells = <1>; #size-cells = <1>; -- cgit From c266a2b4407af7a6fc39f449782aa5c0be48be5a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 17 Dec 2018 12:04:49 +0800 Subject: arm64: dts: allwinner: a64: bananapi-m64: Add Bluetooth device node The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side identifies as BCM43430, while the Bluetooth side identifies as BCM43438. The Bluetooth side is connected to UART1 in a 4 wire configuration. Same as the WiFi side, due to being the same chip and package, DLDO2 provides overall power via VBAT, and DLDO4 provides I/O power via VDDIO. The RTC clock output provides the LPO low power clock at 32.768 kHz. This patch enables Bluetooth on this board, and also adds the missing LPO clock on the WiFi side. There is also a PCM connection for Bluetooth, but this is not covered here. Acked-by: Maxime Ripard Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 83e30e0afe5b..9d0afd7d50ec 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -94,6 +94,8 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; }; @@ -364,7 +366,19 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_dldo2>; + vddio-supply = <®_dldo4>; + device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + }; }; &usb_otg { -- cgit From afdd273e269ca8dee3c70c150d96b4de4f83d39e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 17 Dec 2018 12:04:48 +0800 Subject: ARM: dts: sunxi: Enable Broadcom-based Bluetooth for multiple boards This patch adds the Bluetooth node, and the underlying UART node if it's missing, to the board device tree file for several boards. The LPO clock is also added to the WiFi side's power sequencing node if it's missing, to correctly represent the shared connections. There is also a PCM connection for Bluetooth, but this is not covered in this patch. These boards all have a WiFi+BT module from AMPAK, which contains one or two Broadcom chips, depending on the model. The older AP6210 contains two, while the newer AP6212 and AP6330 contain just one, as they use two-in-one combo chips. The Bluetooth side of the module is always connected to a UART on the same pingroup as the SDIO pins for the WiFi side, in a 4 wire configuration. Power to the VBAT and VDDIO pins are provided either by the PMIC, using one or several of its regulator outputs, or other fixed regulators on the board. The VBAT and VDDIO pins are shared with the WiFi side, which would correspond to vmmc-supply and vqmmc-supply in the mmc host node. A clock output from the SoC or the external X-Powers RTC provides the LPO low power clock at 32.768 kHz. All the boards covered in this patch are ones that do not require extra changes to the SoC's dtsi file. For the remaining boards that I have worked on, properties or device nodes for the LPO clock's source are missing. For the Cubietruck, the LPO clock is fed from CLK_OUT_A, which needs to be muxed on pin PI12. This can be represented in multiple ways. This patch puts the pinctrl property in the pin controller node. This is due to limitations in Linux, where pinmux settings, even the same one, can not be shared by multiple devices. Thus we cannot put it in both the WiFi and Bluetooth device nodes. Putting it the CCU node is another option, but Linux's CCU driver does not handle pinctrl. Also the pin controller is guaranteed to be initialized after the CCU, when clocks are available. And any other devices that use muxed pins are guaranteed to be initialized after the pin controller. Thus having the CLK_OUT_A pinmux reference be in the pin controller node is a good choice without having to deal with implementation issues. Acked-by: Maxime Ripard Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 25 ++++++++++++++++++++++++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 18 +++++++++++++++++ arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 18 +++++++++++++++++ arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 14 +++++++++++++ 4 files changed, 75 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 15c5eae4ca7b..99f531b8d2a7 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -99,6 +99,8 @@ mmc3_pwrseq: mmc3_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ + clocks = <&ccu CLK_OUT_A>; + clock-names = "ext_clock"; }; sound { @@ -227,6 +229,12 @@ status = "okay"; }; +&pio { + /* Pin outputs low power clock for WiFi and BT */ + pinctrl-0 = <&clk_out_a_pin>; + pinctrl-names = "default"; +}; + &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>; @@ -298,6 +306,23 @@ status = "okay"; }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm20702a1"; + clocks = <&ccu CLK_OUT_A>; + clock-names = "lpo"; + device-wakeup-gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */ + host-wakeup-gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */ + shutdown-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */ + max-speed = <1500000>; + }; +}; + &usb_otg { dr_mode = "otg"; status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index 742d2946b08b..c21320c4f4c2 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -363,6 +363,24 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&ac100_rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_dldo1>; + vddio-supply = <®_dldo1>; + device-wakeup-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + }; +}; + &usbphy { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index e5f0645e53a7..a5a9f5a0603e 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -394,6 +394,24 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + clocks = <&ac100_rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_dcdc1>; + vddio-supply = <®_sw>; + device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + host-wakeup-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + }; +}; + &usbphy { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts index 83d32a1a2a63..e1c75f7fa3ca 100644 --- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts @@ -91,6 +91,8 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; }; }; @@ -276,7 +278,19 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>; + uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_dldo1>; + vddio-supply = <®_aldo3>; + device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + host-wakeup-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ + shutdown-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + }; }; &usb_otg { -- cgit From ea096315361bbec7d0b40de4937e7e09fd85f8e7 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 14 Dec 2018 10:55:38 +0100 Subject: ARM: dts: suniv: Fix improper bindings include patch The clock and reset bindings are going through different trees, and while the patch doesn't contain any value defined in that header, it still includes those files and result in a build breakage when building the DT without the matching clock and reset patches applied. Signed-off-by: Maxime Ripard Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index aff5f9022cd6..6100d3b75f61 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -4,9 +4,6 @@ * Copyright 2018 Mesih Kilinc */ -#include -#include - / { #address-cells = <1>; #size-cells = <1>; -- cgit