From d619f253bbbf43fceef141ee40d0b138d84a107e Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Thu, 7 Apr 2022 15:52:20 +0100 Subject: net: mtk_eth_soc: add mask and update PCS speed definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PCS speed setting is a two bit field, but it is defined as two separate bits. Add a bitfield mask for the speed definitions, and use the FIELD_PREP() macro to define each PCS speed. Tested-by: Marek Behún Signed-off-by: Russell King (Oracle) --- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 8a10761adda0..f31ef594008a 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -17,6 +17,7 @@ #include #include #include +#include #include "mtk_ppe.h" #define MTK_QDMA_PAGE_SIZE 2048 @@ -485,9 +486,10 @@ #define SGMSYS_SGMII_MODE 0x20 #define SGMII_IF_MODE_BIT0 BIT(0) #define SGMII_SPEED_DUPLEX_AN BIT(1) -#define SGMII_SPEED_10 0x0 -#define SGMII_SPEED_100 BIT(2) -#define SGMII_SPEED_1000 BIT(3) +#define SGMII_SPEED_MASK GENMASK(3, 2) +#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0) +#define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1) +#define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2) #define SGMII_DUPLEX_FULL BIT(4) #define SGMII_IF_MODE_BIT5 BIT(5) #define SGMII_REMOTE_FAULT_DIS BIT(8) -- cgit