From 814f5a42520ebf0bf26a06e2d0ddd1c7d08f32c2 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Mon, 3 Apr 2023 21:32:50 +0200 Subject: soc: rockchip: power-domain: add rk3588 mem module support On RK3588 it's also possible to power down the memory used by the particular power domains via PMU_MEM_PWR_GATE_SFTCON. This adds support for this feature. Tested-by: Vincent Legoll Co-Developed-by: Finley Xiao Signed-off-by: Finley Xiao Signed-off-by: Boris Brezillon Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230403193250.108693-3-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/pm_domains.c | 160 +++++++++++++++++++++++++++++--------- 1 file changed, 125 insertions(+), 35 deletions(-) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 84bc022f9e5b..e3de49e671dc 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -43,8 +43,10 @@ struct rockchip_domain_info { bool active_wakeup; int pwr_w_mask; int req_w_mask; + int mem_status_mask; int repair_status_mask; u32 pwr_offset; + u32 mem_offset; u32 req_offset; }; @@ -54,6 +56,9 @@ struct rockchip_pmu_info { u32 req_offset; u32 idle_offset; u32 ack_offset; + u32 mem_pwr_offset; + u32 chain_status_offset; + u32 mem_status_offset; u32 repair_status_offset; u32 core_pwrcnt_offset; @@ -119,13 +124,15 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup) \ +#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \ { \ .name = _name, \ .pwr_offset = p_offset, \ .pwr_w_mask = (pwr) << 16, \ .pwr_mask = (pwr), \ .status_mask = (status), \ + .mem_offset = m_offset, \ + .mem_status_mask = (m_status), \ .repair_status_mask = (r_status), \ .req_offset = r_offset, \ .req_w_mask = (req) << 16, \ @@ -269,8 +276,8 @@ void rockchip_pmu_unblock(void) } EXPORT_SYMBOL_GPL(rockchip_pmu_unblock); -#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \ - DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup) +#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \ + DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup) static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { @@ -408,17 +415,92 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd) return !(val & pd->info->status_mask); } +static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd) +{ + struct rockchip_pmu *pmu = pd->pmu; + unsigned int val; + + regmap_read(pmu->regmap, + pmu->info->mem_status_offset + pd->info->mem_offset, &val); + + /* 1'b0: power on, 1'b1: power off */ + return !(val & pd->info->mem_status_mask); +} + +static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd) +{ + struct rockchip_pmu *pmu = pd->pmu; + unsigned int val; + + regmap_read(pmu->regmap, + pmu->info->chain_status_offset + pd->info->mem_offset, &val); + + /* 1'b1: power on, 1'b0: power off */ + return val & pd->info->mem_status_mask; +} + +static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd) +{ + struct rockchip_pmu *pmu = pd->pmu; + struct generic_pm_domain *genpd = &pd->genpd; + bool is_on; + int ret = 0; + + ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on, + is_on == true, 0, 10000); + if (ret) { + dev_err(pmu->dev, + "failed to get chain status '%s', target_on=1, val=%d\n", + genpd->name, is_on); + goto error; + } + + udelay(20); + + regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, + (pd->info->pwr_mask | pd->info->pwr_w_mask)); + wmb(); + + ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on, + is_on == false, 0, 10000); + if (ret) { + dev_err(pmu->dev, + "failed to get mem status '%s', target_on=0, val=%d\n", + genpd->name, is_on); + goto error; + } + + regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, + pd->info->pwr_w_mask); + wmb(); + + ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on, + is_on == true, 0, 10000); + if (ret) { + dev_err(pmu->dev, + "failed to get mem status '%s', target_on=1, val=%d\n", + genpd->name, is_on); + } + +error: + return ret; +} + static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, bool on) { struct rockchip_pmu *pmu = pd->pmu; struct generic_pm_domain *genpd = &pd->genpd; u32 pd_pwr_offset = pd->info->pwr_offset; - bool is_on; + bool is_on, is_mem_on = false; if (pd->info->pwr_mask == 0) return; - else if (pd->info->pwr_w_mask) + + if (on && pd->info->mem_status_mask) + is_mem_on = rockchip_pmu_domain_is_mem_on(pd); + + if (pd->info->pwr_w_mask) regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, on ? pd->info->pwr_w_mask : (pd->info->pwr_mask | pd->info->pwr_w_mask)); @@ -428,6 +510,9 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, wmb(); + if (is_mem_on && rockchip_pmu_domain_mem_reset(pd)) + return; + if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, is_on == on, 0, 10000)) { dev_err(pmu->dev, @@ -645,7 +730,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, pd->genpd.flags = GENPD_FLAG_PM_CLK; if (pd_info->active_wakeup) pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; - pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd)); + pm_genpd_init(&pd->genpd, NULL, + !rockchip_pmu_domain_is_on(pd) || + (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd))); pmu->genpd_data.domains[id] = &pd->genpd; return 0; @@ -1024,35 +1111,35 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = { }; static const struct rockchip_domain_info rk3588_pm_domains[] = { - [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, BIT(1), 0x0, BIT(0), BIT(0), false), - [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0, 0x0, 0, 0, false), - [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0, 0x0, 0, 0, false), - [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, BIT(2), 0x0, BIT(1), BIT(1), false), - [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, BIT(3), 0x0, BIT(2), BIT(2), false), - [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, BIT(4), 0x0, BIT(3), BIT(3), false), - [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, BIT(5), 0x0, BIT(4), BIT(4), false), - [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, BIT(6), 0x0, BIT(5), BIT(5), false), - [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, BIT(7), 0x0, BIT(6), BIT(6), false), - [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, BIT(8), 0x0, BIT(7), BIT(7), false), - [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, BIT(9), 0x0, BIT(8), BIT(8), false), - [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, BIT(10), 0x0, 0, 0, false), - [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, BIT(11), 0x0, BIT(9), BIT(9), false), - [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, BIT(12), 0x0, BIT(10), BIT(10), false), - [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, BIT(13), 0x0, 0, 0, false), - [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, BIT(14), 0x0, BIT(11), BIT(11), false), - [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, BIT(15), 0x0, BIT(12), BIT(12), false), - [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false), - [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, BIT(17), 0x0, BIT(15), BIT(15), false), - [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, BIT(18), 0x4, BIT(0), BIT(16), false), - [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, BIT(19), 0x4, BIT(1), BIT(17), false), - [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, BIT(20), 0x4, BIT(5), BIT(21), false), - [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, BIT(21), 0x0, 0, 0, false), - [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, BIT(22), 0x0, 0, 0, true), - [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0, 0x4, BIT(2), BIT(18), false), - [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, BIT(23), 0x0, 0, 0, false), - [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, BIT(24), 0x4, BIT(3), BIT(19), false), - [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, BIT(25), 0x4, BIT(4), BIT(20), true), - [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, BIT(26), 0x0, 0, 0, false), + [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false), + [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false), + [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false), + [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false), + [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false), + [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false), + [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false), + [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false), + [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false), + [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false), + [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false), + [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false), + [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false), + [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false), + [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false), + [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false), + [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false), + [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false), + [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false), + [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false), + [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false), + [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false), + [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false), + [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true), + [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false), + [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false), + [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false), + [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true), + [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false), }; static const struct rockchip_pmu_info px30_pmu = { @@ -1207,6 +1294,9 @@ static const struct rockchip_pmu_info rk3588_pmu = { .req_offset = 0x10c, .idle_offset = 0x120, .ack_offset = 0x118, + .mem_pwr_offset = 0x1a0, + .chain_status_offset = 0x1f0, + .mem_status_offset = 0x1f8, .repair_status_offset = 0x290, .num_domains = ARRAY_SIZE(rk3588_pm_domains), -- cgit From 7224aefbdf66280880b0fd90c516bb968232ed2c Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 3 Apr 2023 22:23:01 +0200 Subject: dt-bindings: soc: rockchip: add rk3588 usb2phy syscon The usb2phy is accessible via a syscon registers on RK3588, similar to rk3399. Signed-off-by: Sebastian Reichel Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230403202307.120562-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 65a2d5a4f28d..e8fca419cc8e 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -52,6 +52,7 @@ properties: - rockchip,rk3399-pmugrf - rockchip,rk3568-grf - rockchip,rk3568-pmugrf + - rockchip,rk3588-usb2phy-grf - rockchip,rv1108-grf - rockchip,rv1108-pmugrf - rockchip,rv1126-grf @@ -199,6 +200,7 @@ allOf: - rockchip,rk3308-usb2phy-grf - rockchip,rk3328-usb2phy-grf - rockchip,rk3399-grf + - rockchip,rk3588-usb2phy-grf - rockchip,rv1108-grf then: -- cgit From 41ccb3a0eb57741eebd72e51e011ef098bb1493d Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Thu, 16 Feb 2023 10:49:10 +0800 Subject: reset: ath79: Use devm_platform_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to Use devm_platform_ioremap_resource(), as this is exactly what this function does. Suggested-by: Philipp Zabel Signed-off-by: Ye Xingchen Link: https://lore.kernel.org/r/202302161049100728015@zte.com.cn Signed-off-by: Philipp Zabel --- drivers/reset/reset-ath79.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/reset/reset-ath79.c b/drivers/reset/reset-ath79.c index e48d8fcb3133..a8b8f5ea77ec 100644 --- a/drivers/reset/reset-ath79.c +++ b/drivers/reset/reset-ath79.c @@ -86,7 +86,6 @@ static int ath79_reset_restart_handler(struct notifier_block *nb, static int ath79_reset_probe(struct platform_device *pdev) { struct ath79_reset *ath79_reset; - struct resource *res; int err; ath79_reset = devm_kzalloc(&pdev->dev, @@ -96,8 +95,7 @@ static int ath79_reset_probe(struct platform_device *pdev) platform_set_drvdata(pdev, ath79_reset); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ath79_reset->base = devm_ioremap_resource(&pdev->dev, res); + ath79_reset->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(ath79_reset->base)) return PTR_ERR(ath79_reset->base); -- cgit From 9bf9276f371e9247ac77c20955f127d1dbce9220 Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Thu, 16 Feb 2023 10:50:33 +0800 Subject: reset: axs10x: Use devm_platform_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to Use devm_platform_ioremap_resource(), as this is exactly what this function does. Suggested-by: Philipp Zabel Signed-off-by: Ye Xingchen Link: https://lore.kernel.org/r/202302161050336958071@zte.com.cn Signed-off-by: Philipp Zabel --- drivers/reset/reset-axs10x.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/reset/reset-axs10x.c b/drivers/reset/reset-axs10x.c index a854ef41364d..115f69e0db33 100644 --- a/drivers/reset/reset-axs10x.c +++ b/drivers/reset/reset-axs10x.c @@ -44,14 +44,12 @@ static const struct reset_control_ops axs10x_reset_ops = { static int axs10x_reset_probe(struct platform_device *pdev) { struct axs10x_rst *rst; - struct resource *mem; rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL); if (!rst) return -ENOMEM; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem); + rst->regs_rst = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rst->regs_rst)) return PTR_ERR(rst->regs_rst); -- cgit From 68fda5a961cb36bfbc634ae55543f871e1ddcf5e Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Thu, 16 Feb 2023 10:53:36 +0800 Subject: reset: lpc18xx: Use devm_platform_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to Use devm_platform_ioremap_resource(), as this is exactly what this function does. Suggested-by: Philipp Zabel Signed-off-by: Ye Xingchen Link: https://lore.kernel.org/r/202302161053360618204@zte.com.cn Signed-off-by: Philipp Zabel --- drivers/reset/reset-lpc18xx.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/reset/reset-lpc18xx.c b/drivers/reset/reset-lpc18xx.c index 35d8dd4cccfc..36ec95518905 100644 --- a/drivers/reset/reset-lpc18xx.c +++ b/drivers/reset/reset-lpc18xx.c @@ -139,7 +139,6 @@ static const struct reset_control_ops lpc18xx_rgu_ops = { static int lpc18xx_rgu_probe(struct platform_device *pdev) { struct lpc18xx_rgu_data *rc; - struct resource *res; u32 fcclk, firc; int ret; @@ -147,8 +146,7 @@ static int lpc18xx_rgu_probe(struct platform_device *pdev) if (!rc) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - rc->base = devm_ioremap_resource(&pdev->dev, res); + rc->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rc->base)) return PTR_ERR(rc->base); -- cgit From 1d81ba35df80a67e242878b7630d323c7bbfbb00 Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Thu, 16 Feb 2023 10:56:30 +0800 Subject: reset: reset-hsdk: Use devm_platform_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to Use devm_platform_ioremap_resource(), as this is exactly what this function does. Suggested-by: Philipp Zabel Signed-off-by: Ye Xingchen Link: https://lore.kernel.org/r/202302161056304138337@zte.com.cn Signed-off-by: Philipp Zabel --- drivers/reset/reset-hsdk.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/reset/reset-hsdk.c b/drivers/reset/reset-hsdk.c index 4c7b8647b49c..98460e08752c 100644 --- a/drivers/reset/reset-hsdk.c +++ b/drivers/reset/reset-hsdk.c @@ -92,19 +92,16 @@ static const struct reset_control_ops hsdk_reset_ops = { static int hsdk_reset_probe(struct platform_device *pdev) { struct hsdk_rst *rst; - struct resource *mem; rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL); if (!rst) return -ENOMEM; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - rst->regs_ctl = devm_ioremap_resource(&pdev->dev, mem); + rst->regs_ctl = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rst->regs_ctl)) return PTR_ERR(rst->regs_ctl); - mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); - rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem); + rst->regs_rst = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(rst->regs_rst)) return PTR_ERR(rst->regs_rst); -- cgit From cabf1ce35764ff74cb67d633d1b8eeface1b90f6 Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Thu, 16 Feb 2023 10:54:59 +0800 Subject: reset: meson: Use devm_platform_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to Use devm_platform_ioremap_resource(), as this is exactly what this function does. Suggested-by: Philipp Zabel Signed-off-by: Ye Xingchen Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/202302161054598138273@zte.com.cn Signed-off-by: Philipp Zabel --- drivers/reset/reset-meson.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index 26dc54778615..13878ca2779d 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -116,14 +116,12 @@ MODULE_DEVICE_TABLE(of, meson_reset_dt_ids); static int meson_reset_probe(struct platform_device *pdev) { struct meson_reset *data; - struct resource *res; data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - data->reg_base = devm_ioremap_resource(&pdev->dev, res); + data->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(data->reg_base)) return PTR_ERR(data->reg_base); -- cgit From fdcfdb230c67c7f37df2fdfa5369f560f4a06c9d Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Thu, 16 Feb 2023 10:52:12 +0800 Subject: reset: brcmstb-rescal: Use devm_platform_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to Use devm_platform_ioremap_resource(), as this is exactly what this function does. Suggested-by: Philipp Zabel Signed-off-by: Ye Xingchen Acked-by: Florian Fainelli Link: https://lore.kernel.org/r/202302161052126378140@zte.com.cn Signed-off-by: Philipp Zabel --- drivers/reset/reset-brcmstb-rescal.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/reset/reset-brcmstb-rescal.c b/drivers/reset/reset-brcmstb-rescal.c index 433fa0c40e47..823317772bac 100644 --- a/drivers/reset/reset-brcmstb-rescal.c +++ b/drivers/reset/reset-brcmstb-rescal.c @@ -66,14 +66,12 @@ static const struct reset_control_ops brcm_rescal_reset_ops = { static int brcm_rescal_reset_probe(struct platform_device *pdev) { struct brcm_rescal_reset *data; - struct resource *res; data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - data->base = devm_ioremap_resource(&pdev->dev, res); + data->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(data->base)) return PTR_ERR(data->base); -- cgit From 2db4da59485f9c25837acc8024fc58b7a4143aaa Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 10 Feb 2023 23:43:31 +0100 Subject: reset: sti: rely on regmap_field_read_poll_timeout for ack wait Use regmap_field_read_poll_timeout function when waiting for the ack bit upon performing the reset control. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard Link: https://lore.kernel.org/r/20230210224332.98482-1-avolmat@me.com Signed-off-by: Philipp Zabel --- drivers/reset/sti/reset-syscfg.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/drivers/reset/sti/reset-syscfg.c b/drivers/reset/sti/reset-syscfg.c index b4b46e0f207e..c1ba04f6f155 100644 --- a/drivers/reset/sti/reset-syscfg.c +++ b/drivers/reset/sti/reset-syscfg.c @@ -64,22 +64,12 @@ static int syscfg_reset_program_hw(struct reset_controller_dev *rcdev, return err; if (ch->ack) { - unsigned long timeout = jiffies + msecs_to_jiffies(1000); u32 ack_val; - while (true) { - err = regmap_field_read(ch->ack, &ack_val); - if (err) - return err; - - if (ack_val == ctrl_val) - break; - - if (time_after(jiffies, timeout)) - return -ETIME; - - cpu_relax(); - } + err = regmap_field_read_poll_timeout(ch->ack, ack_val, (ack_val == ctrl_val), + 100, USEC_PER_SEC); + if (err) + return err; } return 0; -- cgit From da46de512f8b9febdb085594815c91b45c940bef Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Thu, 23 Mar 2023 16:53:44 +0800 Subject: reset: meson-audio-arb: Use dev_err_probe() Replace the open-code with dev_err_probe() to simplify the code. Signed-off-by: Ye Xingchen Reviewed-by: Philipp Zabel Link: https://lore.kernel.org/r/202303231653447704556@zte.com.cn Signed-off-by: Philipp Zabel --- drivers/reset/reset-meson-audio-arb.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/reset/reset-meson-audio-arb.c b/drivers/reset/reset-meson-audio-arb.c index 1dc06e08a8da..6a3f6a6a3bbf 100644 --- a/drivers/reset/reset-meson-audio-arb.c +++ b/drivers/reset/reset-meson-audio-arb.c @@ -151,11 +151,8 @@ static int meson_audio_arb_probe(struct platform_device *pdev) platform_set_drvdata(pdev, arb); arb->clk = devm_clk_get(dev, NULL); - if (IS_ERR(arb->clk)) { - if (PTR_ERR(arb->clk) != -EPROBE_DEFER) - dev_err(dev, "failed to get clock\n"); - return PTR_ERR(arb->clk); - } + if (IS_ERR(arb->clk)) + return dev_err_probe(dev, PTR_ERR(arb->clk), "failed to get clock\n"); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); arb->regs = devm_ioremap_resource(dev, res); -- cgit From 20a6a4d7226691473cde40ed1e1f03964cbd5be7 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Thu, 30 Mar 2023 13:23:47 +0200 Subject: reset: sti: simplify driver's config and build With commit 64933513e461 ("reset: sti: Remove STiH415/6 reset support"), there is only one sti reset driver left and there no need to define a dedicated config STI_RESET_SYSCFG, which is selected by the config for the STiH407 reset driver. Simply add reset-syscfg.c to the build for the STiH407 reset driver. Signed-off-by: Lukas Bulwahn Reviewed-by: Patrice Chotard Link: https://lore.kernel.org/r/20230330112347.31137-2-lukas.bulwahn@gmail.com Signed-off-by: Philipp Zabel --- drivers/reset/sti/Kconfig | 4 ---- drivers/reset/sti/Makefile | 4 +--- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/reset/sti/Kconfig b/drivers/reset/sti/Kconfig index 9455e1c7a5aa..a2622e146b8b 100644 --- a/drivers/reset/sti/Kconfig +++ b/drivers/reset/sti/Kconfig @@ -1,11 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only if ARCH_STI -config STI_RESET_SYSCFG - bool - config STIH407_RESET bool - select STI_RESET_SYSCFG endif diff --git a/drivers/reset/sti/Makefile b/drivers/reset/sti/Makefile index 3eb30f7e8e3d..5e833496cee3 100644 --- a/drivers/reset/sti/Makefile +++ b/drivers/reset/sti/Makefile @@ -1,4 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o - -obj-$(CONFIG_STIH407_RESET) += reset-stih407.o +obj-$(CONFIG_STIH407_RESET) += reset-stih407.o reset-syscfg.o -- cgit From ac59ed9cdb80bdb7f6584af5253790f51a9404a7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 31 Mar 2023 10:34:55 +0200 Subject: reset: oxnas: remove obsolete reset driver Due to lack of maintainance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 peripheral reset. Signed-off-by: Neil Armstrong Acked-by: Daniel Golle Acked-by: Arnd Bergmann Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20230331-topic-oxnas-upstream-remove-v1-17-5bd58fd1dd1f@linaro.org Signed-off-by: Philipp Zabel --- .../devicetree/bindings/reset/oxnas,reset.txt | 32 ------ drivers/reset/Kconfig | 3 - drivers/reset/Makefile | 1 - drivers/reset/reset-oxnas.c | 114 --------------------- 4 files changed, 150 deletions(-) delete mode 100644 Documentation/devicetree/bindings/reset/oxnas,reset.txt delete mode 100644 drivers/reset/reset-oxnas.c diff --git a/Documentation/devicetree/bindings/reset/oxnas,reset.txt b/Documentation/devicetree/bindings/reset/oxnas,reset.txt deleted file mode 100644 index d27ccb5d04fc..000000000000 --- a/Documentation/devicetree/bindings/reset/oxnas,reset.txt +++ /dev/null @@ -1,32 +0,0 @@ -Oxford Semiconductor OXNAS SoC Family RESET Controller -================================================ - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: For OX810SE, should be "oxsemi,ox810se-reset" - For OX820, should be "oxsemi,ox820-reset" -- #reset-cells: 1, see below - -Parent node should have the following properties : -- compatible: For OX810SE, should be : - "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" - For OX820, should be : - "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd" - -Reset indices are in dt-bindings include files : -- For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h -- For OX820: include/dt-bindings/reset/oxsemi,ox820.h - -example: - -sys: sys-ctrl@000000 { - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; - reg = <0x000000 0x100000>; - - reset: reset-controller { - compatible = "oxsemi,ox810se-reset"; - #reset-cells = <1>; - }; -}; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 6aa8f243b30c..b31ccee234e1 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -143,9 +143,6 @@ config RESET_NPCM This enables the reset controller driver for Nuvoton NPCM BMC SoCs. -config RESET_OXNAS - bool - config RESET_PISTACHIO bool "Pistachio Reset Driver" depends on MIPS || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 7fec5af6c964..acb6f824837d 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -21,7 +21,6 @@ obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) += reset-npcm.o -obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o diff --git a/drivers/reset/reset-oxnas.c b/drivers/reset/reset-oxnas.c deleted file mode 100644 index 8209f922dc16..000000000000 --- a/drivers/reset/reset-oxnas.c +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Oxford Semiconductor Reset Controller driver - * - * Copyright (C) 2016 Neil Armstrong - * Copyright (C) 2014 Ma Haijun - * Copyright (C) 2009 Oxford Semiconductor Ltd - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Regmap offsets */ -#define RST_SET_REGOFFSET 0x34 -#define RST_CLR_REGOFFSET 0x38 - -struct oxnas_reset { - struct regmap *regmap; - struct reset_controller_dev rcdev; -}; - -static int oxnas_reset_reset(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct oxnas_reset *data = - container_of(rcdev, struct oxnas_reset, rcdev); - - regmap_write(data->regmap, RST_SET_REGOFFSET, BIT(id)); - msleep(50); - regmap_write(data->regmap, RST_CLR_REGOFFSET, BIT(id)); - - return 0; -} - -static int oxnas_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct oxnas_reset *data = - container_of(rcdev, struct oxnas_reset, rcdev); - - regmap_write(data->regmap, RST_SET_REGOFFSET, BIT(id)); - - return 0; -} - -static int oxnas_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct oxnas_reset *data = - container_of(rcdev, struct oxnas_reset, rcdev); - - regmap_write(data->regmap, RST_CLR_REGOFFSET, BIT(id)); - - return 0; -} - -static const struct reset_control_ops oxnas_reset_ops = { - .reset = oxnas_reset_reset, - .assert = oxnas_reset_assert, - .deassert = oxnas_reset_deassert, -}; - -static const struct of_device_id oxnas_reset_dt_ids[] = { - { .compatible = "oxsemi,ox810se-reset", }, - { .compatible = "oxsemi,ox820-reset", }, - { /* sentinel */ }, -}; - -static int oxnas_reset_probe(struct platform_device *pdev) -{ - struct oxnas_reset *data; - struct device *parent; - - parent = pdev->dev.parent; - if (!parent) { - dev_err(&pdev->dev, "no parent\n"); - return -ENODEV; - } - - data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - data->regmap = syscon_node_to_regmap(parent->of_node); - if (IS_ERR(data->regmap)) { - dev_err(&pdev->dev, "failed to get parent regmap\n"); - return PTR_ERR(data->regmap); - } - - platform_set_drvdata(pdev, data); - - data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = 32; - data->rcdev.ops = &oxnas_reset_ops; - data->rcdev.of_node = pdev->dev.of_node; - - return devm_reset_controller_register(&pdev->dev, &data->rcdev); -} - -static struct platform_driver oxnas_reset_driver = { - .probe = oxnas_reset_probe, - .driver = { - .name = "oxnas-reset", - .of_match_table = oxnas_reset_dt_ids, - }, -}; -builtin_platform_driver(oxnas_reset_driver); -- cgit From 52990390f91c1c39ca742fc8f390b29891d95127 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Tue, 2 May 2023 12:20:50 +0200 Subject: reset: starfive: select AUXILIARY_BUS CONFIG_AUXILIARY_BUS is not a user-visible symbol, replace 'depends on' with 'select'. Suggested-by: Arnd Bergmann Reviewed-by: Hal Feng Reviewed-by: Arnd Bergmann Reviewed-by: Emil Renner Berthing Link: https://lore.kernel.org/r/20230502102050.1418417-1-p.zabel@pengutronix.de Signed-off-by: Philipp Zabel --- drivers/reset/starfive/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig index 1fa706a2c3dc..d832339f61bc 100644 --- a/drivers/reset/starfive/Kconfig +++ b/drivers/reset/starfive/Kconfig @@ -13,7 +13,8 @@ config RESET_STARFIVE_JH7100 config RESET_STARFIVE_JH7110 bool "StarFive JH7110 Reset Driver" - depends on AUXILIARY_BUS && CLK_STARFIVE_JH7110_SYS + depends on CLK_STARFIVE_JH7110_SYS + select AUXILIARY_BUS select RESET_STARFIVE_JH71X0 default ARCH_STARFIVE help -- cgit From afb39e2bd36af1d80913bb6851caece829526217 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Tue, 2 May 2023 12:20:41 +0200 Subject: reset: mpfs: select AUXILIARY_BUS CONFIG_AUXILIARY_BUS is not a user-visible symbol, replace 'depends on' with 'select'. Cc: Daire McNamara Suggested-by: Arnd Bergmann Reviewed-by: Conor Dooley Reviewed-by: Arnd Bergmann Link: https://lore.kernel.org/r/20230502102041.1418397-1-p.zabel@pengutronix.de Signed-off-by: Philipp Zabel --- drivers/reset/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index b31ccee234e1..010f7b2c527c 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -151,7 +151,8 @@ config RESET_PISTACHIO config RESET_POLARFIRE_SOC bool "Microchip PolarFire SoC (MPFS) Reset Driver" - depends on AUXILIARY_BUS && MCHP_CLK_MPFS + depends on MCHP_CLK_MPFS + select AUXILIARY_BUS default MCHP_CLK_MPFS help This driver supports peripheral reset for the Microchip PolarFire SoC -- cgit From 3d56c7364389fce14547803fef56d6f2cab5d366 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 19 Apr 2023 15:02:34 +0200 Subject: memory: renesas-rpc-if: Fix PHYCNT.STRTIM setting According to the datasheets, the Strobe Timing Adjustment bit (STRTIM) setting is different on R-Car SoCs, i.e. R-Car M3 ES1.* : STRTIM[2:0] is set to 0x6 other R-Car Gen3: STRTIM[2:0] is set to 0x7 other R-Car Gen4: STRTIM[3:0] is set to 0xf To fix this issue, a DT match data was added to specify the setting for special use cases. Signed-off-by: Cong Dang Signed-off-by: Hai Pham [wsa: rebased, restructured, added Gen4 support] Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230419130234.44321-1-wsa+renesas@sang-engineering.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/renesas-rpc-if.c | 53 ++++++++++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 14 deletions(-) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index 025bb628aaf3..75fcba45ec1b 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -7,6 +7,7 @@ * Copyright (C) 2019-2020 Cogent Embedded, Inc. */ +#include #include #include #include @@ -163,6 +164,11 @@ static const struct regmap_access_table rpcif_volatile_table = { .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges), }; +struct rpcif_info { + enum rpcif_type type; + u8 strtim; +}; + struct rpcif_priv { struct device *dev; void __iomem *base; @@ -171,7 +177,7 @@ struct rpcif_priv { struct reset_control *rstc; struct platform_device *vdev; size_t size; - enum rpcif_type type; + const struct rpcif_info *info; enum rpcif_data_dir dir; u8 bus_size; u8 xfer_size; @@ -186,6 +192,26 @@ struct rpcif_priv { u32 ddr; /* DRDRENR or SMDRENR */ }; +static const struct rpcif_info rpcif_info_r8a7796 = { + .type = RPCIF_RCAR_GEN3, + .strtim = 6, +}; + +static const struct rpcif_info rpcif_info_gen3 = { + .type = RPCIF_RCAR_GEN3, + .strtim = 7, +}; + +static const struct rpcif_info rpcif_info_rz_g2l = { + .type = RPCIF_RZ_G2L, + .strtim = 7, +}; + +static const struct rpcif_info rpcif_info_gen4 = { + .type = RPCIF_RCAR_GEN4, + .strtim = 15, +}; + /* * Custom accessor functions to ensure SM[RW]DR[01] are always accessed with * proper width. Requires rpcif_priv.xfer_size to be correctly set before! @@ -310,7 +336,7 @@ int rpcif_hw_init(struct device *dev, bool hyperflash) if (ret) return ret; - if (rpc->type == RPCIF_RZ_G2L) { + if (rpc->info->type == RPCIF_RZ_G2L) { ret = reset_control_reset(rpc->rstc); if (ret) return ret; @@ -324,12 +350,10 @@ int rpcif_hw_init(struct device *dev, bool hyperflash) /* DMA Transfer is not supported */ regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0); - if (rpc->type == RPCIF_RCAR_GEN3) - regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, - RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7)); - else if (rpc->type == RPCIF_RCAR_GEN4) - regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, - RPCIF_PHYCNT_STRTIM(15), RPCIF_PHYCNT_STRTIM(15)); + regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, + /* create mask with all affected bits set */ + RPCIF_PHYCNT_STRTIM(BIT(fls(rpc->info->strtim)) - 1), + RPCIF_PHYCNT_STRTIM(rpc->info->strtim)); regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3), RPCIF_PHYOFFSET1_DDRTMG(3)); @@ -340,7 +364,7 @@ int rpcif_hw_init(struct device *dev, bool hyperflash) regmap_update_bits(rpc->regmap, RPCIF_PHYINT, RPCIF_PHYINT_WPVAL, 0); - if (rpc->type == RPCIF_RZ_G2L) + if (rpc->info->type == RPCIF_RZ_G2L) regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) | RPCIF_CMNCR_BSZ(3), @@ -729,9 +753,9 @@ static int rpcif_probe(struct platform_device *pdev) rpc->dirmap = devm_ioremap_resource(dev, res); if (IS_ERR(rpc->dirmap)) return PTR_ERR(rpc->dirmap); - rpc->size = resource_size(res); - rpc->type = (uintptr_t)of_device_get_match_data(dev); + rpc->size = resource_size(res); + rpc->info = of_device_get_match_data(dev); rpc->rstc = devm_reset_control_get_exclusive(dev, NULL); if (IS_ERR(rpc->rstc)) return PTR_ERR(rpc->rstc); @@ -764,9 +788,10 @@ static int rpcif_remove(struct platform_device *pdev) } static const struct of_device_id rpcif_of_match[] = { - { .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 }, - { .compatible = "renesas,rcar-gen4-rpc-if", .data = (void *)RPCIF_RCAR_GEN4 }, - { .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L }, + { .compatible = "renesas,r8a7796-rpc-if", .data = &rpcif_info_r8a7796 }, + { .compatible = "renesas,rcar-gen3-rpc-if", .data = &rpcif_info_gen3 }, + { .compatible = "renesas,rcar-gen4-rpc-if", .data = &rpcif_info_gen4 }, + { .compatible = "renesas,rzg2l-rpc-if", .data = &rpcif_info_rz_g2l }, {}, }; MODULE_DEVICE_TABLE(of, rpcif_of_match); -- cgit From 8f9d530cffc1c035974a320c51c67abfdddf01ac Mon Sep 17 00:00:00 2001 From: Nikunj Kela Date: Sat, 6 May 2023 11:24:27 -0700 Subject: dt-bindings: firmware: arm,scmi: support for parameter in smc/hvc call Currently, smc/hvc calls are made with smc-id only. The parameters are all set to zeros. This change defines a new compatible string that can be used to pass shmem address(4KB-page, offset) as two parameters in SMC/HVC doorbell. This is useful when multiple scmi instances are used with common smc-id. Signed-off-by: Nikunj Kela Reviewed-by: Rob Herring Reviewed-by: Florian Fainelli Link: https://lore.kernel.org/r/20230506182428.25343-2-quic_nkela@quicinc.com Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/firmware/arm,scmi.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index 5824c43e9893..ad776911f990 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -34,6 +34,10 @@ properties: - description: SCMI compliant firmware with ARM SMC/HVC transport items: - const: arm,scmi-smc + - description: SCMI compliant firmware with ARM SMC/HVC transport + with shmem address(4KB-page, offset) as parameters + items: + - const: arm,scmi-smc-param - description: SCMI compliant firmware with SCMI Virtio transport. The virtio transport only supports a single device. items: @@ -299,7 +303,9 @@ else: properties: compatible: contains: - const: arm,scmi-smc + enum: + - arm,scmi-smc + - arm,scmi-smc-param then: required: - arm,smc-id -- cgit From 5f2ea10a808aef0086ad46240fab0a3e7ae90e95 Mon Sep 17 00:00:00 2001 From: Nikunj Kela Date: Sat, 6 May 2023 11:24:28 -0700 Subject: firmware: arm_scmi: Augment SMC/HVC to allow optional parameters This change adds support for passing shmem channel address as parameters in smc/hvc call. The address is split into 4KB-page and offset. This is useful when multiple scmi instances are using same smc-id and firmware needs to distinguish among the instances. Signed-off-by: Nikunj Kela Reviewed-by: Florian Fainelli Link: https://lore.kernel.org/r/20230506182428.25343-3-quic_nkela@quicinc.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/driver.c | 1 + drivers/firmware/arm_scmi/smc.c | 30 +++++++++++++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index e7d97b59963b..b5957cc12fee 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -2914,6 +2914,7 @@ static const struct of_device_id scmi_of_match[] = { #endif #ifdef CONFIG_ARM_SCMI_TRANSPORT_SMC { .compatible = "arm,scmi-smc", .data = &scmi_smc_desc}, + { .compatible = "arm,scmi-smc-param", .data = &scmi_smc_desc}, #endif #ifdef CONFIG_ARM_SCMI_TRANSPORT_VIRTIO { .compatible = "arm,scmi-virtio", .data = &scmi_virtio_desc}, diff --git a/drivers/firmware/arm_scmi/smc.c b/drivers/firmware/arm_scmi/smc.c index 93272e4bbd12..621c37efe3ec 100644 --- a/drivers/firmware/arm_scmi/smc.c +++ b/drivers/firmware/arm_scmi/smc.c @@ -20,6 +20,23 @@ #include "common.h" +/* + * The shmem address is split into 4K page and offset. + * This is to make sure the parameters fit in 32bit arguments of the + * smc/hvc call to keep it uniform across smc32/smc64 conventions. + * This however limits the shmem address to 44 bit. + * + * These optional parameters can be used to distinguish among multiple + * scmi instances that are using the same smc-id. + * The page parameter is passed in r1/x1/w1 register and the offset parameter + * is passed in r2/x2/w2 register. + */ + +#define SHMEM_SIZE (SZ_4K) +#define SHMEM_SHIFT 12 +#define SHMEM_PAGE(x) (_UL((x) >> SHMEM_SHIFT)) +#define SHMEM_OFFSET(x) ((x) & (SHMEM_SIZE - 1)) + /** * struct scmi_smc - Structure representing a SCMI smc transport * @@ -30,6 +47,8 @@ * @inflight: Atomic flag to protect access to Tx/Rx shared memory area. * Used when operating in atomic mode. * @func_id: smc/hvc call function id + * @param_page: 4K page number of the shmem channel + * @param_offset: Offset within the 4K page of the shmem channel */ struct scmi_smc { @@ -40,6 +59,8 @@ struct scmi_smc { #define INFLIGHT_NONE MSG_TOKEN_MAX atomic_t inflight; u32 func_id; + u32 param_page; + u32 param_offset; }; static irqreturn_t smc_msg_done_isr(int irq, void *data) @@ -137,6 +158,10 @@ static int smc_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, if (ret < 0) return ret; + if (of_device_is_compatible(dev->of_node, "arm,scmi-smc-param")) { + scmi_info->param_page = SHMEM_PAGE(res.start); + scmi_info->param_offset = SHMEM_OFFSET(res.start); + } /* * If there is an interrupt named "a2p", then the service and * completion of a message is signaled by an interrupt rather than by @@ -179,6 +204,8 @@ static int smc_send_message(struct scmi_chan_info *cinfo, { struct scmi_smc *scmi_info = cinfo->transport_info; struct arm_smccc_res res; + unsigned long page = scmi_info->param_page; + unsigned long offset = scmi_info->param_offset; /* * Channel will be released only once response has been @@ -188,7 +215,8 @@ static int smc_send_message(struct scmi_chan_info *cinfo, shmem_tx_prepare(scmi_info->shmem, xfer, cinfo); - arm_smccc_1_1_invoke(scmi_info->func_id, 0, 0, 0, 0, 0, 0, 0, &res); + arm_smccc_1_1_invoke(scmi_info->func_id, page, offset, 0, 0, 0, 0, 0, + &res); /* Only SMCCC_RET_NOT_SUPPORTED is valid error code */ if (res.a0) { -- cgit From 8a19d4a1508c62ff28ba427c3209cdb57379d325 Mon Sep 17 00:00:00 2001 From: Artur Weber Date: Mon, 1 May 2023 21:55:13 +0200 Subject: dt-bindings: soc: samsung: exynos-pmu: add Exynos4212 compatible Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add back the relevant compatible. This reverts part of commit c40610198f35 ("soc: samsung: Remove Exynos4212 related dead code"). Signed-off-by: Artur Weber Link: https://lore.kernel.org/r/20230501195525.6268-2-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 5d8d9497f18e..e1d716df5dfa 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -17,6 +17,7 @@ select: enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5260-pmu @@ -36,6 +37,7 @@ properties: - enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5260-pmu @@ -50,6 +52,7 @@ properties: - enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5420-pmu @@ -125,6 +128,7 @@ allOf: enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5410-pmu @@ -143,6 +147,7 @@ allOf: enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5420-pmu -- cgit From 514a935fd0d4d522a08257f5acbc5439174c7cf0 Mon Sep 17 00:00:00 2001 From: Artur Weber Date: Mon, 1 May 2023 21:55:16 +0200 Subject: soc: samsung: exynos-pmu: Re-introduce Exynos4212 support Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit c40610198f35e8264f9175dafe74db6288a07eda. Signed-off-by: Artur Weber Link: https://lore.kernel.org/r/20230501195525.6268-5-aweber.kernel@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/exynos-pmu.c | 9 +++++++++ drivers/soc/samsung/exynos-pmu.h | 2 ++ drivers/soc/samsung/exynos4-pmu.c | 13 +++++++++++-- 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index 732c86ce2be8..5b2664da9853 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -57,6 +57,12 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) if (pmu_data->powerdown_conf_extra) pmu_data->powerdown_conf_extra(mode); + + if (pmu_data->pmu_config_extra) { + for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++) + pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode], + pmu_data->pmu_config_extra[i].offset); + } } /* @@ -79,6 +85,9 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = { }, { .compatible = "samsung,exynos4210-pmu", .data = exynos_pmu_data_arm_ptr(exynos4210_pmu_data), + }, { + .compatible = "samsung,exynos4212-pmu", + .data = exynos_pmu_data_arm_ptr(exynos4212_pmu_data), }, { .compatible = "samsung,exynos4412-pmu", .data = exynos_pmu_data_arm_ptr(exynos4412_pmu_data), diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h index 5e851f32307e..1c652ffd79b4 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -20,6 +20,7 @@ struct exynos_pmu_conf { struct exynos_pmu_data { const struct exynos_pmu_conf *pmu_config; + const struct exynos_pmu_conf *pmu_config_extra; void (*pmu_init)(void); void (*powerdown_conf)(enum sys_powerdown); @@ -32,6 +33,7 @@ extern void __iomem *pmu_base_addr; /* list of all exported SoC specific data */ extern const struct exynos_pmu_data exynos3250_pmu_data; extern const struct exynos_pmu_data exynos4210_pmu_data; +extern const struct exynos_pmu_data exynos4212_pmu_data; extern const struct exynos_pmu_data exynos4412_pmu_data; extern const struct exynos_pmu_data exynos5250_pmu_data; extern const struct exynos_pmu_data exynos5420_pmu_data; diff --git a/drivers/soc/samsung/exynos4-pmu.c b/drivers/soc/samsung/exynos4-pmu.c index cb35103565a6..f8092190b938 100644 --- a/drivers/soc/samsung/exynos4-pmu.c +++ b/drivers/soc/samsung/exynos4-pmu.c @@ -86,7 +86,7 @@ static const struct exynos_pmu_conf exynos4210_pmu_config[] = { { PMU_TABLE_END,}, }; -static const struct exynos_pmu_conf exynos4412_pmu_config[] = { +static const struct exynos_pmu_conf exynos4x12_pmu_config[] = { { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, @@ -191,6 +191,10 @@ static const struct exynos_pmu_conf exynos4412_pmu_config[] = { { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, + { PMU_TABLE_END,}, +}; + +static const struct exynos_pmu_conf exynos4412_pmu_config[] = { { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, @@ -204,6 +208,11 @@ const struct exynos_pmu_data exynos4210_pmu_data = { .pmu_config = exynos4210_pmu_config, }; +const struct exynos_pmu_data exynos4212_pmu_data = { + .pmu_config = exynos4x12_pmu_config, +}; + const struct exynos_pmu_data exynos4412_pmu_data = { - .pmu_config = exynos4412_pmu_config, + .pmu_config = exynos4x12_pmu_config, + .pmu_config_extra = exynos4412_pmu_config, }; -- cgit From be11d67a144db79408a19642d0a8d65fb9f52105 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 10 Mar 2023 08:47:24 -0600 Subject: soc: xilinx: Use of_property_present() for testing DT property presence It is preferred to use typed property access functions (i.e. of_property_read_ functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230310144725.1545315-1-robh@kernel.org Signed-off-by: Michal Simek --- drivers/soc/xilinx/zynqmp_power.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/xilinx/zynqmp_power.c b/drivers/soc/xilinx/zynqmp_power.c index 78a8a7545d1e..641dcc958911 100644 --- a/drivers/soc/xilinx/zynqmp_power.c +++ b/drivers/soc/xilinx/zynqmp_power.c @@ -218,7 +218,7 @@ static int zynqmp_pm_probe(struct platform_device *pdev) } else if (ret != -EACCES && ret != -ENODEV) { dev_err(&pdev->dev, "Failed to Register with Xilinx Event manager %d\n", ret); return ret; - } else if (of_find_property(pdev->dev.of_node, "mboxes", NULL)) { + } else if (of_property_present(pdev->dev.of_node, "mboxes")) { zynqmp_pm_init_suspend_work = devm_kzalloc(&pdev->dev, sizeof(struct zynqmp_pm_work_struct), @@ -240,7 +240,7 @@ static int zynqmp_pm_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Failed to request rx channel\n"); return PTR_ERR(rx_chan); } - } else if (of_find_property(pdev->dev.of_node, "interrupts", NULL)) { + } else if (of_property_present(pdev->dev.of_node, "interrupts")) { irq = platform_get_irq(pdev, 0); if (irq <= 0) return -ENXIO; -- cgit From c58da0ba3e5c86e51e2c1557afaf6f71e00c4533 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 21 Apr 2023 13:44:54 +0300 Subject: driver: soc: xilinx: use _safe loop iterator to avoid a use after free The hash_for_each_possible() loop dereferences "eve_data" to get the next item on the list. However the loop frees eve_data so it leads to a use after free. Use hash_for_each_possible_safe() instead. Fixes: c7fdb2404f66 ("drivers: soc: xilinx: add xilinx event management driver") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/761e0e4a-4caf-4a71-8f47-1c6ad908a848@kili.mountain Signed-off-by: Michal Simek --- drivers/soc/xilinx/xlnx_event_manager.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/soc/xilinx/xlnx_event_manager.c b/drivers/soc/xilinx/xlnx_event_manager.c index c76381899ef4..f9d9b82b562d 100644 --- a/drivers/soc/xilinx/xlnx_event_manager.c +++ b/drivers/soc/xilinx/xlnx_event_manager.c @@ -192,11 +192,12 @@ static int xlnx_remove_cb_for_suspend(event_cb_func_t cb_fun) struct registered_event_data *eve_data; struct agent_cb *cb_pos; struct agent_cb *cb_next; + struct hlist_node *tmp; is_need_to_unregister = false; /* Check for existing entry in hash table for given cb_type */ - hash_for_each_possible(reg_driver_map, eve_data, hentry, PM_INIT_SUSPEND_CB) { + hash_for_each_possible_safe(reg_driver_map, eve_data, tmp, hentry, PM_INIT_SUSPEND_CB) { if (eve_data->cb_type == PM_INIT_SUSPEND_CB) { /* Delete the list of callback */ list_for_each_entry_safe(cb_pos, cb_next, &eve_data->cb_list_head, list) { @@ -228,11 +229,12 @@ static int xlnx_remove_cb_for_notify_event(const u32 node_id, const u32 event, u64 key = ((u64)node_id << 32U) | (u64)event; struct agent_cb *cb_pos; struct agent_cb *cb_next; + struct hlist_node *tmp; is_need_to_unregister = false; /* Check for existing entry in hash table for given key id */ - hash_for_each_possible(reg_driver_map, eve_data, hentry, key) { + hash_for_each_possible_safe(reg_driver_map, eve_data, tmp, hentry, key) { if (eve_data->key == key) { /* Delete the list of callback */ list_for_each_entry_safe(cb_pos, cb_next, &eve_data->cb_list_head, list) { -- cgit From e2ebc05da260d216c2158e17409982ad1e4f3b58 Mon Sep 17 00:00:00 2001 From: Nava kishore Manne Date: Wed, 3 May 2023 10:31:58 +0530 Subject: firmware: xilinx: Update the zynqmp_pm_fpga_load() API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the zynqmp_pm_fpga_load() API to handle the firmware error’s properly. Signed-off-by: Nava kishore Manne Link: https://lore.kernel.org/r/20230503050158.1936467-1-nava.kishore.manne@amd.com Signed-off-by: Michal Simek --- drivers/firmware/xilinx/zynqmp.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index a736db4a5825..9e585b5646df 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -942,8 +942,16 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_reset_get_status); */ int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags) { - return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address), - upper_32_bits(address), size, flags, NULL); + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + ret = zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address), + upper_32_bits(address), size, flags, + ret_payload); + if (ret_payload[0]) + return -ret_payload[0]; + + return ret; } EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_load); -- cgit From 538af6e5856b1aa971975c747a2974a74db48928 Mon Sep 17 00:00:00 2001 From: Aakarsh Jain Date: Tue, 28 Mar 2023 17:17:29 +0530 Subject: dt-bindings: media: s5p-mfc: convert bindings to json-schema Convert s5p-mfc bindings to DT schema format using json-schema. Signed-off-by: Aakarsh Jain Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230328114729.61436-1-aakarsh.jain@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/media/s5p-mfc.txt | 78 --------- .../devicetree/bindings/media/samsung,s5p-mfc.yaml | 184 +++++++++++++++++++++ 2 files changed, 184 insertions(+), 78 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt index 8eb90c043d5d..e69de29bb2d1 100644 --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt @@ -1,78 +0,0 @@ -* Samsung Multi Format Codec (MFC) - -Multi Format Codec (MFC) is the IP present in Samsung SoCs which -supports high resolution decoding and encoding functionalities. -The MFC device driver is a v4l2 driver which can encode/decode -video raw/elementary streams and has support for all popular -video codecs. - -Required properties: - - compatible : value should be either one among the following - (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs - (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs - (c) "samsung,exynos3250-mfc", "samsung,mfc-v7" for MFC v7 - present in Exynos3250 SoC - (d) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC - (e) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC - (f) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC - (g) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : MFC interrupt number to the CPU. - - clocks : from common clock binding: handle to mfc clock. - - clock-names : from common clock binding: must contain "mfc", - corresponding to entry in the clocks property. - -Optional properties: - - power-domains : power-domain property defined with a phandle - to respective power domain. - - memory-region : from reserved memory binding: phandles to two reserved - memory regions, first is for "left" mfc memory bus interfaces, - second if for the "right" mfc memory bus, used when no SYSMMU - support is available; used only by MFC v5 present in Exynos4 SoCs - -Obsolete properties: - - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region - property instead - - -Example: -SoC specific DT entry: - -mfc: codec@13400000 { - compatible = "samsung,mfc-v5"; - reg = <0x13400000 0x10000>; - interrupts = <0 94 0>; - power-domains = <&pd_mfc>; - clocks = <&clock 273>; - clock-names = "mfc"; -}; - -Reserved memory specific DT entry for given board (see reserved memory binding -for more information): - -reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mfc_left: region@51000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x51000000 0x800000>; - }; - - mfc_right: region@43000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x43000000 0x800000>; - }; -}; - -Board specific DT entry: - -codec@13400000 { - memory-region = <&mfc_left>, <&mfc_right>; -}; diff --git a/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml new file mode 100644 index 000000000000..084b44582a43 --- /dev/null +++ b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/samsung,s5p-mfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Multi Format Codec (MFC) + +maintainers: + - Marek Szyprowski + - Aakarsh Jain + +description: + Multi Format Codec (MFC) is the IP present in Samsung SoCs which + supports high resolution decoding and encoding functionalities. + +properties: + compatible: + oneOf: + - enum: + - samsung,exynos5433-mfc # Exynos5433 + - samsung,mfc-v5 # Exynos4 + - samsung,mfc-v6 # Exynos5 + - samsung,mfc-v7 # Exynos5420 + - samsung,mfc-v8 # Exynos5800 + - samsung,mfc-v10 # Exynos7880 + - items: + - enum: + - samsung,exynos3250-mfc # Exynos3250 + - const: samsung,mfc-v7 # Fall back for Exynos3250 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + + interrupts: + maxItems: 1 + + iommus: + minItems: 1 + maxItems: 2 + + iommu-names: + minItems: 1 + maxItems: 2 + + power-domains: + maxItems: 1 + + memory-region: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos3250-mfc + then: + properties: + clocks: + maxItems: 2 + clock-names: + items: + - const: mfc + - const: sclk_mfc + iommus: + maxItems: 1 + iommus-names: false + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos5433-mfc + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: pclk + - const: aclk + - const: aclk_xiu + iommus: + maxItems: 2 + iommus-names: + items: + - const: left + - const: right + + - if: + properties: + compatible: + contains: + enum: + - samsung,mfc-v5 + then: + properties: + clocks: + maxItems: 2 + clock-names: + items: + - const: mfc + - const: sclk_mfc + iommus: + maxItems: 2 + iommus-names: + items: + - const: left + - const: right + + - if: + properties: + compatible: + contains: + enum: + - samsung,mfc-v6 + - samsung,mfc-v8 + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: mfc + iommus: + maxItems: 2 + iommus-names: + items: + - const: left + - const: right + + - if: + properties: + compatible: + contains: + enum: + - samsung,mfc-v7 + then: + properties: + clocks: + minItems: 1 + maxItems: 2 + iommus: + minItems: 1 + maxItems: 2 + +examples: + - | + #include + #include + #include + #include + + codec@13400000 { + compatible = "samsung,mfc-v5"; + reg = <0x13400000 0x10000>; + interrupts = ; + power-domains = <&pd_mfc>; + clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; + clock-names = "mfc", "sclk_mfc"; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; + }; -- cgit From 0dc608855195c8f79e499e2a608b26e56e259810 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 4 May 2023 18:17:54 +0200 Subject: dt-bindings: soc: qcom: aoss-qmp: add compatible for sa8775p Document the AOSS QMP compatible for SA8775P. Signed-off-by: Bartosz Golaszewski Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230504161755.197417-1-brgl@bgdev.pl --- Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index 798f15588ee2..9dc8e48c8af4 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -26,6 +26,7 @@ properties: items: - enum: - qcom,qdu1000-aoss-qmp + - qcom,sa8775p-aoss-qmp - qcom,sc7180-aoss-qmp - qcom,sc7280-aoss-qmp - qcom,sc8180x-aoss-qmp -- cgit From cb9a39aacd3d6387b6f1f178a96eadceba90454e Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 19 Apr 2023 22:15:11 +0200 Subject: soc: renesas: rcar-rst: Allow WDT reset on R-Car V3U V3U firmware misses to enable WDT resets. Because there won't be any updates to the firmware anymore, enable that in Linux. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230419201511.31648-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/rcar-rst.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c index e1c7e91f5a86..98fd97da6cd4 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c @@ -12,6 +12,7 @@ #define WDTRSTCR_RESET 0xA55A0002 #define WDTRSTCR 0x0054 +#define GEN4_WDTRSTCR 0x0010 #define CR7BAR 0x0070 #define CR7BAREN BIT(4) @@ -27,6 +28,12 @@ static int rcar_rst_enable_wdt_reset(void __iomem *base) return 0; } +static int rcar_rst_v3u_enable_wdt_reset(void __iomem *base) +{ + iowrite32(WDTRSTCR_RESET, base + GEN4_WDTRSTCR); + return 0; +} + /* * Most of the R-Car Gen3 SoCs have an ARM Realtime Core. * Firmware boot address has to be set in CR7BAR before @@ -66,6 +73,12 @@ static const struct rst_config rcar_rst_gen3 __initconst = { .set_rproc_boot_addr = rcar_rst_set_gen3_rproc_boot_addr, }; +/* V3U firmware doesn't enable WDT reset and there won't be updates anymore */ +static const struct rst_config rcar_rst_v3u __initconst = { + .modemr = 0x00, /* MODEMR0 and it has CPG related bits */ + .configure = rcar_rst_v3u_enable_wdt_reset, +}; + static const struct rst_config rcar_rst_gen4 __initconst = { .modemr = 0x00, /* MODEMR0 and it has CPG related bits */ }; @@ -101,7 +114,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { { .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 }, { .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 }, /* R-Car Gen4 */ - { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_gen4 }, + { .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_v3u }, { .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 }, { .compatible = "renesas,r8a779g0-rst", .data = &rcar_rst_gen4 }, { /* sentinel */ } -- cgit From d94436465152465555c8e5efbe611db40c9749f7 Mon Sep 17 00:00:00 2001 From: Stefan Kristiansson Date: Thu, 11 May 2023 16:20:48 +0300 Subject: soc/tegra: fuse: Add support for Tegra264 Add support for Tegra264 to the fuse handling code. Signed-off-by: Stefan Kristiansson Signed-off-by: Peter De Schrijver Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/tegra-apbmisc.c | 3 ++- include/soc/tegra/fuse.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index 4591c5bcb690..eb0a1d924526 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. */ #include @@ -62,6 +62,7 @@ bool tegra_is_silicon(void) switch (tegra_get_chip_id()) { case TEGRA194: case TEGRA234: + case TEGRA264: if (tegra_get_platform() == 0) return true; diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index a63de5da8124..3a513be50243 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2023, NVIDIA CORPORATION. All rights reserved. */ #ifndef __SOC_TEGRA_FUSE_H__ @@ -17,6 +17,7 @@ #define TEGRA186 0x18 #define TEGRA194 0x19 #define TEGRA234 0x23 +#define TEGRA264 0x26 #define TEGRA_FUSE_SKU_CALIB_0 0xf0 #define TEGRA30_FUSE_SATA_CALIB 0x124 -- cgit From 9a38cb27668e275ed912e67388cf11f454a24cc6 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Thu, 11 May 2023 23:02:04 +0530 Subject: memory: tegra: Add interconnect support for DRAM scaling in Tegra234 Add Interconnect framework support to dynamically set the DRAM bandwidth from different clients. Both the MC and EMC drivers are added as ICC providers. The path for any request is: MC-Client[1-n] -> MC -> EMC -> EMEM/DRAM MC client's request for bandwidth will go to the MC driver which passes the client request info like BPMP Client ID, Client type and the Bandwidth to the BPMP-FW. The final DRAM freq to achieve the requested bandwidth is set by the BPMP-FW based on the passed parameters. Signed-off-by: Sumit Gupta Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- drivers/memory/tegra/mc.c | 5 ++ drivers/memory/tegra/tegra186-emc.c | 133 ++++++++++++++++++++++++++++++++++ drivers/memory/tegra/tegra234.c | 138 +++++++++++++++++++++++++++++++++++- include/linux/tegra-icc.h | 65 +++++++++++++++++ include/soc/tegra/mc.h | 7 ++ 5 files changed, 347 insertions(+), 1 deletion(-) create mode 100644 include/linux/tegra-icc.h diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 9082b6c3763d..983455b1f98d 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include @@ -792,6 +793,8 @@ static int tegra_mc_interconnect_setup(struct tegra_mc *mc) mc->provider.data = &mc->provider; mc->provider.set = mc->soc->icc_ops->set; mc->provider.aggregate = mc->soc->icc_ops->aggregate; + mc->provider.get_bw = mc->soc->icc_ops->get_bw; + mc->provider.xlate = mc->soc->icc_ops->xlate; mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; icc_provider_init(&mc->provider); @@ -824,6 +827,8 @@ static int tegra_mc_interconnect_setup(struct tegra_mc *mc) err = icc_link_create(node, TEGRA_ICC_MC); if (err) goto remove_nodes; + + node->data = (struct tegra_mc_client *)&(mc->soc->clients[i]); } err = icc_provider_register(&mc->provider); diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index e935ad4e95b6..6ad8a4023dd7 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -7,9 +7,11 @@ #include #include #include +#include #include #include +#include "mc.h" struct tegra186_emc_dvfs { unsigned long latency; @@ -29,8 +31,15 @@ struct tegra186_emc { unsigned long min_rate; unsigned long max_rate; } debugfs; + + struct icc_provider provider; }; +static inline struct tegra186_emc *to_tegra186_emc(struct icc_provider *provider) +{ + return container_of(provider, struct tegra186_emc, provider); +} + /* * debugfs interface * @@ -146,8 +155,102 @@ DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops, tegra186_emc_debug_max_rate_get, tegra186_emc_debug_max_rate_set, "%llu\n"); +/* + * tegra_emc_icc_set_bw() - Set BW api for EMC provider + * @src: ICC node for External Memory Controller (EMC) + * @dst: ICC node for External Memory (DRAM) + * + * Do nothing here as info to BPMP-FW is now passed in the BW set function + * of the MC driver. BPMP-FW sets the final Freq based on the passed values. + */ +static int tegra_emc_icc_set_bw(struct icc_node *src, struct icc_node *dst) +{ + return 0; +} + +static struct icc_node * +tegra_emc_of_icc_xlate(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id != TEGRA_ICC_EMEM) + continue; + + return node; + } + + return ERR_PTR(-EPROBE_DEFER); +} + +static int tegra_emc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak) +{ + *avg = 0; + *peak = 0; + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra186_emc *emc) +{ + struct tegra_mc *mc = dev_get_drvdata(emc->dev->parent); + const struct tegra_mc_soc *soc = mc->soc; + struct icc_node *node; + int err; + + emc->provider.dev = emc->dev; + emc->provider.set = tegra_emc_icc_set_bw; + emc->provider.data = &emc->provider; + emc->provider.aggregate = soc->icc_ops->aggregate; + emc->provider.xlate = tegra_emc_of_icc_xlate; + emc->provider.get_bw = tegra_emc_icc_get_init_bw; + + icc_provider_init(&emc->provider); + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto err_msg; + } + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + err = icc_provider_register(&emc->provider); + if (err) + goto remove_nodes; + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + static int tegra186_emc_probe(struct platform_device *pdev) { + struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent); struct mrq_emc_dvfs_latency_response response; struct tegra_bpmp_message msg; struct tegra186_emc *emc; @@ -236,6 +339,32 @@ static int tegra186_emc_probe(struct platform_device *pdev) debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, emc, &tegra186_emc_debug_max_rate_fops); + if (mc && mc->soc->icc_ops) { + if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) { + mc->bwmgr_mrq_supported = true; + + /* + * MC driver probe can't get BPMP reference as it gets probed + * earlier than BPMP. So, save the BPMP ref got from the EMC + * DT node in the mc->bpmp and use it in MC's icc_set hook. + */ + mc->bpmp = emc->bpmp; + barrier(); + } + + /* + * Initialize the ICC even if BPMP-FW doesn't support 'MRQ_BWMGR_INT'. + * Use the flag 'mc->bwmgr_mrq_supported' within MC driver and return + * EINVAL instead of passing the request to BPMP-FW later when the BW + * request is made by client with 'icc_set_bw()' call. + */ + err = tegra_emc_interconnect_init(emc); + if (err) { + mc->bpmp = NULL; + goto put_bpmp; + } + } + return 0; put_bpmp: @@ -245,9 +374,12 @@ put_bpmp: static int tegra186_emc_remove(struct platform_device *pdev) { + struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent); struct tegra186_emc *emc = platform_get_drvdata(pdev); debugfs_remove_recursive(emc->debugfs.root); + + mc->bpmp = NULL; tegra_bpmp_put(emc->bpmp); return 0; @@ -272,6 +404,7 @@ static struct platform_driver tegra186_emc_driver = { .name = "tegra186-emc", .of_match_table = tegra186_emc_of_match, .suppress_bind_attrs = true, + .sync_state = icc_sync_state, }, .probe = tegra186_emc_probe, .remove = tegra186_emc_remove, diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 02dcc5748bba..56d911926d54 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -1,18 +1,23 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2021-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2022-2023, NVIDIA CORPORATION. All rights reserved. */ #include #include +#include +#include +#include #include "mc.h" static const struct tegra_mc_client tegra234_mc_clients[] = { { .id = TEGRA234_MEMORY_CLIENT_MGBEARD, .name = "mgbeard", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE, .regs = { .sid = { @@ -23,6 +28,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_MGBEBRD, .name = "mgbebrd", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE_VF1, .regs = { .sid = { @@ -33,6 +40,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_MGBECRD, .name = "mgbecrd", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE_VF2, .regs = { .sid = { @@ -43,6 +52,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_MGBEDRD, .name = "mgbedrd", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE_VF3, .regs = { .sid = { @@ -52,6 +63,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, }, { .id = TEGRA234_MEMORY_CLIENT_MGBEAWR, + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .name = "mgbeawr", .sid = TEGRA234_SID_MGBE, .regs = { @@ -63,6 +76,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_MGBEBWR, .name = "mgbebwr", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE_VF1, .regs = { .sid = { @@ -73,6 +88,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_MGBECWR, .name = "mgbecwr", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE_VF2, .regs = { .sid = { @@ -83,6 +100,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_SDMMCRAB, .name = "sdmmcrab", + .bpmp_id = TEGRA_ICC_BPMP_SDMMC_4, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_SDMMC4, .regs = { .sid = { @@ -93,6 +112,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_MGBEDWR, .name = "mgbedwr", + .bpmp_id = TEGRA_ICC_BPMP_EQOS, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_MGBE_VF3, .regs = { .sid = { @@ -103,6 +124,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_SDMMCWAB, .name = "sdmmcwab", + .bpmp_id = TEGRA_ICC_BPMP_SDMMC_4, + .type = TEGRA_ICC_NISO, .sid = TEGRA234_SID_SDMMC4, .regs = { .sid = { @@ -153,6 +176,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_APEDMAR, .name = "apedmar", + .bpmp_id = TEGRA_ICC_BPMP_APEDMA, + .type = TEGRA_ICC_ISO_AUDIO, .sid = TEGRA234_SID_APE, .regs = { .sid = { @@ -163,6 +188,8 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, { .id = TEGRA234_MEMORY_CLIENT_APEDMAW, .name = "apedmaw", + .bpmp_id = TEGRA_ICC_BPMP_APEDMA, + .type = TEGRA_ICC_ISO_AUDIO, .sid = TEGRA234_SID_APE, .regs = { .sid = { @@ -333,6 +360,114 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { }, }; +/* + * tegra234_mc_icc_set() - Pass MC client info to the BPMP-FW + * @src: ICC node for Memory Controller's (MC) Client + * @dst: ICC node for Memory Controller (MC) + * + * Passing the current request info from the MC to the BPMP-FW where + * LA and PTSA registers are accessed and the final EMC freq is set + * based on client_id, type, latency and bandwidth. + * icc_set_bw() makes set_bw calls for both MC and EMC providers in + * sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'. + * So, the data passed won't be updated by concurrent set calls from + * other clients. + */ +static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider); + struct mrq_bwmgr_int_request bwmgr_req = { 0 }; + struct mrq_bwmgr_int_response bwmgr_resp = { 0 }; + const struct tegra_mc_client *pclient = src->data; + struct tegra_bpmp_message msg; + int ret; + + /* + * Same Src and Dst node will happen during boot from icc_node_add(). + * This can be used to pre-initialize and set bandwidth for all clients + * before their drivers are loaded. We are skipping this case as for us, + * the pre-initialization already happened in Bootloader(MB2) and BPMP-FW. + */ + if (src->id == dst->id) + return 0; + + if (!mc->bwmgr_mrq_supported) + return -EINVAL; + + if (!mc->bpmp) { + dev_err(mc->dev, "BPMP reference NULL\n"); + return -ENOENT; + } + + if (pclient->type == TEGRA_ICC_NISO) + bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw; + else + bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw; + + bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id; + + bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET; + bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw; + bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS; + + memset(&msg, 0, sizeof(msg)); + msg.mrq = MRQ_BWMGR_INT; + msg.tx.data = &bwmgr_req; + msg.tx.size = sizeof(bwmgr_req); + msg.rx.data = &bwmgr_resp; + msg.rx.size = sizeof(bwmgr_resp); + + ret = tegra_bpmp_transfer(mc->bpmp, &msg); + if (ret < 0) { + dev_err(mc->dev, "BPMP transfer failed: %d\n", ret); + goto error; + } + if (msg.rx.ret < 0) { + pr_err("failed to set bandwidth for %u: %d\n", + bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret); + ret = -EINVAL; + } + +error: + return ret; +} + +static struct icc_node* +tegra234_mc_of_icc_xlate(struct of_phandle_args *spec, void *data) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(data); + unsigned int cl_id = spec->args[0]; + struct icc_node *node; + + list_for_each_entry(node, &mc->provider.nodes, node_list) { + if (node->id != cl_id) + continue; + + return node; + } + + /* + * If a client driver calls devm_of_icc_get() before the MC driver + * is probed, then return EPROBE_DEFER to the client driver. + */ + return ERR_PTR(-EPROBE_DEFER); +} + +static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak) +{ + *avg = 0; + *peak = 0; + + return 0; +} + +static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = { + .xlate = tegra234_mc_of_icc_xlate, + .aggregate = icc_std_aggregate, + .get_bw = tegra234_mc_icc_get_init_bw, + .set = tegra234_mc_icc_set, +}; + const struct tegra_mc_soc tegra234_mc_soc = { .num_clients = ARRAY_SIZE(tegra234_mc_clients), .clients = tegra234_mc_clients, @@ -345,6 +480,7 @@ const struct tegra_mc_soc tegra234_mc_soc = { MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .has_addr_hi_reg = true, .ops = &tegra186_mc_ops, + .icc_ops = &tegra234_mc_icc_ops, .ch_intmask = 0x0000ff00, .global_intstatus_channel_shift = 8, /* diff --git a/include/linux/tegra-icc.h b/include/linux/tegra-icc.h new file mode 100644 index 000000000000..4b4d4bee290c --- /dev/null +++ b/include/linux/tegra-icc.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022-2023 NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef LINUX_TEGRA_ICC_H +#define LINUX_TEGRA_ICC_H + +enum tegra_icc_client_type { + TEGRA_ICC_NONE, + TEGRA_ICC_NISO, + TEGRA_ICC_ISO_DISPLAY, + TEGRA_ICC_ISO_VI, + TEGRA_ICC_ISO_AUDIO, + TEGRA_ICC_ISO_VIFAL, +}; + +/* ICC ID's for MC client's used in BPMP */ +#define TEGRA_ICC_BPMP_DEBUG 1 +#define TEGRA_ICC_BPMP_CPU_CLUSTER0 2 +#define TEGRA_ICC_BPMP_CPU_CLUSTER1 3 +#define TEGRA_ICC_BPMP_CPU_CLUSTER2 4 +#define TEGRA_ICC_BPMP_GPU 5 +#define TEGRA_ICC_BPMP_CACTMON 6 +#define TEGRA_ICC_BPMP_DISPLAY 7 +#define TEGRA_ICC_BPMP_VI 8 +#define TEGRA_ICC_BPMP_EQOS 9 +#define TEGRA_ICC_BPMP_PCIE_0 10 +#define TEGRA_ICC_BPMP_PCIE_1 11 +#define TEGRA_ICC_BPMP_PCIE_2 12 +#define TEGRA_ICC_BPMP_PCIE_3 13 +#define TEGRA_ICC_BPMP_PCIE_4 14 +#define TEGRA_ICC_BPMP_PCIE_5 15 +#define TEGRA_ICC_BPMP_PCIE_6 16 +#define TEGRA_ICC_BPMP_PCIE_7 17 +#define TEGRA_ICC_BPMP_PCIE_8 18 +#define TEGRA_ICC_BPMP_PCIE_9 19 +#define TEGRA_ICC_BPMP_PCIE_10 20 +#define TEGRA_ICC_BPMP_DLA_0 21 +#define TEGRA_ICC_BPMP_DLA_1 22 +#define TEGRA_ICC_BPMP_SDMMC_1 23 +#define TEGRA_ICC_BPMP_SDMMC_2 24 +#define TEGRA_ICC_BPMP_SDMMC_3 25 +#define TEGRA_ICC_BPMP_SDMMC_4 26 +#define TEGRA_ICC_BPMP_NVDEC 27 +#define TEGRA_ICC_BPMP_NVENC 28 +#define TEGRA_ICC_BPMP_NVJPG_0 29 +#define TEGRA_ICC_BPMP_NVJPG_1 30 +#define TEGRA_ICC_BPMP_OFAA 31 +#define TEGRA_ICC_BPMP_XUSB_HOST 32 +#define TEGRA_ICC_BPMP_XUSB_DEV 33 +#define TEGRA_ICC_BPMP_TSEC 34 +#define TEGRA_ICC_BPMP_VIC 35 +#define TEGRA_ICC_BPMP_APE 36 +#define TEGRA_ICC_BPMP_APEDMA 37 +#define TEGRA_ICC_BPMP_SE 38 +#define TEGRA_ICC_BPMP_ISP 39 +#define TEGRA_ICC_BPMP_HDA 40 +#define TEGRA_ICC_BPMP_VIFAL 41 +#define TEGRA_ICC_BPMP_VI2FAL 42 +#define TEGRA_ICC_BPMP_VI2 43 +#define TEGRA_ICC_BPMP_RCE 44 +#define TEGRA_ICC_BPMP_PVA 45 + +#endif /* LINUX_TEGRA_ICC_H */ diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 51a2263e1bc5..900d88b26fae 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -13,6 +13,7 @@ #include #include #include +#include struct clk; struct device; @@ -26,6 +27,8 @@ struct tegra_mc_timing { struct tegra_mc_client { unsigned int id; + unsigned int bpmp_id; + enum tegra_icc_client_type type; const char *name; /* * For Tegra210 and earlier, this is the SWGROUP ID used for IOVA translations in the @@ -166,8 +169,10 @@ struct tegra_mc_icc_ops { int (*set)(struct icc_node *src, struct icc_node *dst); int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw, u32 peak_bw, u32 *agg_avg, u32 *agg_peak); + struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data); struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec, void *data); + int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak); }; struct tegra_mc_ops { @@ -214,6 +219,7 @@ struct tegra_mc_soc { }; struct tegra_mc { + struct tegra_bpmp *bpmp; struct device *dev; struct tegra_smmu *smmu; struct gart_device *gart; @@ -229,6 +235,7 @@ struct tegra_mc { struct tegra_mc_timing *timings; unsigned int num_timings; + bool bwmgr_mrq_supported; struct reset_controller_dev reset; struct icc_provider provider; -- cgit From aecc83f11dd8712f9b0bcdb4cf1eb0f30f12b226 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Thu, 11 May 2023 23:02:05 +0530 Subject: memory: tegra: Add memory clients for Tegra234 Add few isochronous (ISO) and non-ISO memory clients. ISO clients have guaranteed bandwidth requirement. PCIe clients added to the memory client table represent each controller in Tegra234. Signed-off-by: Sumit Gupta Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra234.c | 420 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 420 insertions(+) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 56d911926d54..a4ea181e1090 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -14,6 +14,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { { + .id = TEGRA234_MEMORY_CLIENT_HDAR, + .name = "hdar", + .bpmp_id = TEGRA_ICC_BPMP_HDA, + .type = TEGRA_ICC_ISO_AUDIO, + .sid = TEGRA234_SID_HDA, + .regs = { + .sid = { + .override = 0xa8, + .security = 0xac, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_HDAW, + .name = "hdaw", + .bpmp_id = TEGRA_ICC_BPMP_HDA, + .type = TEGRA_ICC_ISO_AUDIO, + .sid = TEGRA234_SID_HDA, + .regs = { + .sid = { + .override = 0x1a8, + .security = 0x1ac, + }, + }, + }, { .id = TEGRA234_MEMORY_CLIENT_MGBEARD, .name = "mgbeard", .bpmp_id = TEGRA_ICC_BPMP_EQOS, @@ -133,6 +157,90 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x33c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VI2W, + .name = "vi2w", + .bpmp_id = TEGRA_ICC_BPMP_VI2, + .type = TEGRA_ICC_ISO_VI, + .sid = TEGRA234_SID_ISO_VI2, + .regs = { + .sid = { + .override = 0x380, + .security = 0x384, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VI2FALR, + .name = "vi2falr", + .bpmp_id = TEGRA_ICC_BPMP_VI2FAL, + .type = TEGRA_ICC_ISO_VIFAL, + .sid = TEGRA234_SID_ISO_VI2FALC, + .regs = { + .sid = { + .override = 0x388, + .security = 0x38c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VI2FALW, + .name = "vi2falw", + .bpmp_id = TEGRA_ICC_BPMP_VI2FAL, + .type = TEGRA_ICC_ISO_VIFAL, + .sid = TEGRA234_SID_ISO_VI2FALC, + .regs = { + .sid = { + .override = 0x3e0, + .security = 0x3e4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_APER, + .name = "aper", + .bpmp_id = TEGRA_ICC_BPMP_APE, + .type = TEGRA_ICC_ISO_AUDIO, + .sid = TEGRA234_SID_APE, + .regs = { + .sid = { + .override = 0x3d0, + .security = 0x3d4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_APEW, + .name = "apew", + .bpmp_id = TEGRA_ICC_BPMP_APE, + .type = TEGRA_ICC_ISO_AUDIO, + .sid = TEGRA234_SID_APE, + .regs = { + .sid = { + .override = 0x3d8, + .security = 0x3dc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR, + .name = "nvdisplayr", + .bpmp_id = TEGRA_ICC_BPMP_DISPLAY, + .type = TEGRA_ICC_ISO_DISPLAY, + .sid = TEGRA234_SID_ISO_NVDISPLAY, + .regs = { + .sid = { + .override = 0x490, + .security = 0x494, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, + .name = "nvdisplayr1", + .bpmp_id = TEGRA_ICC_BPMP_DISPLAY, + .type = TEGRA_ICC_ISO_DISPLAY, + .sid = TEGRA234_SID_ISO_NVDISPLAY, + .regs = { + .sid = { + .override = 0x508, + .security = 0x50c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_BPMPR, .name = "bpmpr", @@ -357,6 +465,318 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x37c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE0R, + .name = "pcie0r", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_0, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE0, + .regs = { + .sid = { + .override = 0x6c0, + .security = 0x6c4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE0W, + .name = "pcie0w", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_0, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE0, + .regs = { + .sid = { + .override = 0x6c8, + .security = 0x6cc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE1R, + .name = "pcie1r", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_1, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE1, + .regs = { + .sid = { + .override = 0x6d0, + .security = 0x6d4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE1W, + .name = "pcie1w", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_1, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE1, + .regs = { + .sid = { + .override = 0x6d8, + .security = 0x6dc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE2AR, + .name = "pcie2ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_2, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE2, + .regs = { + .sid = { + .override = 0x6e0, + .security = 0x6e4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE2AW, + .name = "pcie2aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_2, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE2, + .regs = { + .sid = { + .override = 0x6e8, + .security = 0x6ec, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE3R, + .name = "pcie3r", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_3, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE3, + .regs = { + .sid = { + .override = 0x6f0, + .security = 0x6f4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE3W, + .name = "pcie3w", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_3, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE3, + .regs = { + .sid = { + .override = 0x6f8, + .security = 0x6fc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE4R, + .name = "pcie4r", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_4, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE4, + .regs = { + .sid = { + .override = 0x700, + .security = 0x704, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE4W, + .name = "pcie4w", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_4, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE4, + .regs = { + .sid = { + .override = 0x708, + .security = 0x70c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE5R, + .name = "pcie5r", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_5, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE5, + .regs = { + .sid = { + .override = 0x710, + .security = 0x714, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE5W, + .name = "pcie5w", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_5, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE5, + .regs = { + .sid = { + .override = 0x718, + .security = 0x71c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE5R1, + .name = "pcie5r1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_5, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE5, + .regs = { + .sid = { + .override = 0x778, + .security = 0x77c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AR, + .name = "pcie6ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x140, + .security = 0x144, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AW, + .name = "pcie6aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x148, + .security = 0x14c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1, + .name = "pcie6ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x1e8, + .security = 0x1ec, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AR, + .name = "pcie7ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x150, + .security = 0x154, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AW, + .name = "pcie7aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x180, + .security = 0x184, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1, + .name = "pcie7ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x248, + .security = 0x24c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE8AR, + .name = "pcie8ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE8, + .regs = { + .sid = { + .override = 0x190, + .security = 0x194, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE8AW, + .name = "pcie8aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE8, + .regs = { + .sid = { + .override = 0x1d8, + .security = 0x1dc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE9AR, + .name = "pcie9ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE9, + .regs = { + .sid = { + .override = 0x1e0, + .security = 0x1e4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE9AW, + .name = "pcie9aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE9, + .regs = { + .sid = { + .override = 0x1f0, + .security = 0x1f4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AR, + .name = "pcie10ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x1f8, + .security = 0x1fc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AW, + .name = "pcie10aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x200, + .security = 0x204, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1, + .name = "pcie10ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x240, + .security = 0x244, + }, + }, }, }; -- cgit From 80b19e09c8fb04a6397278b1c16403042629614f Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Thu, 11 May 2023 23:02:06 +0530 Subject: memory: tegra: Add software memory clients in Tegra234 Add dummy memory controller clients to represent CPU clusters. They will be used by the CPUFREQ driver to scale DRAM FREQ with the CPU FREQ. Signed-off-by: Sumit Gupta Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra234.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index a4ea181e1090..0fa68862749f 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -777,6 +777,21 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x244, }, }, + }, { + .id = TEGRA_ICC_MC_CPU_CLUSTER0, + .name = "sw_cluster0", + .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA_ICC_MC_CPU_CLUSTER1, + .name = "sw_cluster1", + .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER1, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA_ICC_MC_CPU_CLUSTER2, + .name = "sw_cluster2", + .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2, + .type = TEGRA_ICC_NISO, }, }; -- cgit From e852af72a7f21f4d25994365af86a92438d68014 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Thu, 11 May 2023 23:02:08 +0530 Subject: memory: tegra: Make CPU cluster BW request a multiple of MC channels Make CPU cluster's bandwidth (BW) request a multiple of MC channels. CPU OPP tables have BW info per MC channel. But, the actual BW depends on the number of MC channels which can change as per the boot config. Get the number of MC channels which are actually enabled in current boot configuration and multiply the BW request from a CPU cluster with the number of enabled MC channels. This is not required to be done for other MC clients. Signed-off-by: Sumit Gupta Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- drivers/memory/tegra/mc.c | 19 +++++++++++++++++++ drivers/memory/tegra/mc.h | 1 + drivers/memory/tegra/tegra234.c | 24 +++++++++++++++++++++++- include/soc/tegra/mc.h | 1 + 4 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 983455b1f98d..4a750da1c12a 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -843,6 +843,23 @@ remove_nodes: return err; } +static void tegra_mc_num_channel_enabled(struct tegra_mc *mc) +{ + unsigned int i; + u32 value; + + value = mc_ch_readl(mc, 0, MC_EMEM_ADR_CFG_CHANNEL_ENABLE); + if (value <= 0) { + mc->num_channels = mc->soc->num_channels; + return; + } + + for (i = 0; i < 32; i++) { + if (value & BIT(i)) + mc->num_channels++; + } +} + static int tegra_mc_probe(struct platform_device *pdev) { struct tegra_mc *mc; @@ -881,6 +898,8 @@ static int tegra_mc_probe(struct platform_device *pdev) return err; } + tegra_mc_num_channel_enabled(mc); + if (mc->soc->ops && mc->soc->ops->handle_irq) { mc->irq = platform_get_irq(pdev, 0); if (mc->irq < 0) diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index bc01586b6560..c3f6655bec60 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -53,6 +53,7 @@ #define MC_ERR_ROUTE_SANITY_ADR 0x9c4 #define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 #define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 +#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8 #define MC_GLOBAL_INTSTATUS 0xf24 #define MC_ERR_ADR_HI 0x11fc diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 0fa68862749f..8e873a7bc34f 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -867,6 +867,28 @@ error: return ret; } +static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + struct icc_provider *p = node->provider; + struct tegra_mc *mc = icc_provider_to_tegra_mc(p); + + if (!mc->bwmgr_mrq_supported) + return -EINVAL; + + if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 || + node->id == TEGRA_ICC_MC_CPU_CLUSTER1 || + node->id == TEGRA_ICC_MC_CPU_CLUSTER2) { + if (mc) + peak_bw = peak_bw * mc->num_channels; + } + + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + static struct icc_node* tegra234_mc_of_icc_xlate(struct of_phandle_args *spec, void *data) { @@ -898,7 +920,7 @@ static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *pea static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = { .xlate = tegra234_mc_of_icc_xlate, - .aggregate = icc_std_aggregate, + .aggregate = tegra234_mc_icc_aggregate, .get_bw = tegra234_mc_icc_get_init_bw, .set = tegra234_mc_icc_set, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 900d88b26fae..fc3001483e62 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -234,6 +234,7 @@ struct tegra_mc { struct tegra_mc_timing *timings; unsigned int num_timings; + unsigned int num_channels; bool bwmgr_mrq_supported; struct reset_controller_dev reset; -- cgit From 205b3d02d57ce6dce96f6d2b9c230f56a9bf9817 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Thu, 11 May 2023 23:02:09 +0530 Subject: PCI: tegra194: Fix possible array out of bounds access Add check to fix the possible array out of bounds violation by making speed equal to GEN1_CORE_CLK_FREQ when its value is more than the size of "pcie_gen_freq" array. This array has size of four but possible speed (CLS) values are from "0 to 0xF". So, "speed - 1" values are "-1 to 0xE". Suggested-by: Bjorn Helgaas Signed-off-by: Sumit Gupta Link: https://lore.kernel.org/lkml/72b9168b-d4d6-4312-32ea-69358df2f2d0@nvidia.com/ Acked-by: Lorenzo Pieralisi Signed-off-by: Thierry Reding --- drivers/pci/controller/dwc/pcie-tegra194.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 09825b4a075e..e6eec85480ca 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -223,6 +223,7 @@ #define EP_STATE_ENABLED 1 static const unsigned int pcie_gen_freq[] = { + GEN1_CORE_CLK_FREQ, /* PCI_EXP_LNKSTA_CLS == 0; undefined */ GEN1_CORE_CLK_FREQ, GEN2_CORE_CLK_FREQ, GEN3_CORE_CLK_FREQ, @@ -459,7 +460,11 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg) speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & PCI_EXP_LNKSTA_CLS; - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); + + if (speed >= ARRAY_SIZE(pcie_gen_freq)) + speed = 0; + + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); if (pcie->of_data->has_ltr_req_fix) return IRQ_HANDLED; @@ -1020,7 +1025,11 @@ retry_link: speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & PCI_EXP_LNKSTA_CLS; - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); + + if (speed >= ARRAY_SIZE(pcie_gen_freq)) + speed = 0; + + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); tegra_pcie_enable_interrupts(pp); -- cgit From 9365bf006f53d04b69d560ef7e2bf4be4c4d693a Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Thu, 11 May 2023 23:02:10 +0530 Subject: PCI: tegra194: Add interconnect support in Tegra234 Add support to request DRAM bandwidth (BW) with Memory Interconnect in Tegra234 SoC. The DRAM BW required for different modes depends on the link speed (Gen-1/2/3/4) and width/lanes (x1/x2/x4/x8). Currently, the DRAM frequency is always set to the maximum available but that results in the highest power consumption. The Memory Interconnect is a software feature which uses Interconnect framework (ICC). It adds the capability for Memory Controller (MC) clients to request bandwidth and therefore scale DRAM frequency dynamically depending on the required link speed so that the DRAM energy consumption can be optimized. Suggested-by: Manikanta Maddireddy Signed-off-by: Sumit Gupta Acked-by: Lorenzo Pieralisi Signed-off-by: Thierry Reding --- drivers/pci/controller/dwc/pcie-tegra194.c | 51 ++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index e6eec85480ca..4fdadc7b045f 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -288,6 +289,7 @@ struct tegra_pcie_dw { unsigned int pex_rst_irq; int ep_state; long link_status; + struct icc_path *icc_path; }; static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci) @@ -310,6 +312,27 @@ struct tegra_pcie_soc { enum dw_pcie_device_mode mode; }; +static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie) +{ + struct dw_pcie *pci = &pcie->pci; + u32 val, speed, width; + + val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); + + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val); + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val); + + val = width * (PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]) / BITS_PER_BYTE); + + if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0)) + dev_err(pcie->dev, "can't set bw[%u]\n", val); + + if (speed >= ARRAY_SIZE(pcie_gen_freq)) + speed = 0; + + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); +} + static void apply_bad_link_workaround(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -453,18 +476,12 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg) struct tegra_pcie_dw *pcie = arg; struct dw_pcie_ep *ep = &pcie->pci.ep; struct dw_pcie *pci = &pcie->pci; - u32 val, speed; + u32 val; if (test_and_clear_bit(0, &pcie->link_status)) dw_pcie_ep_linkup(ep); - speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & - PCI_EXP_LNKSTA_CLS; - - if (speed >= ARRAY_SIZE(pcie_gen_freq)) - speed = 0; - - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); + tegra_pcie_icc_set(pcie); if (pcie->of_data->has_ltr_req_fix) return IRQ_HANDLED; @@ -950,9 +967,9 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) static int tegra_pcie_dw_start_link(struct dw_pcie *pci) { - u32 val, offset, speed, tmp; struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); struct dw_pcie_rp *pp = &pci->pp; + u32 val, offset, tmp; bool retry = true; if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { @@ -1023,13 +1040,7 @@ retry_link: goto retry_link; } - speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & - PCI_EXP_LNKSTA_CLS; - - if (speed >= ARRAY_SIZE(pcie_gen_freq)) - speed = 0; - - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); + tegra_pcie_icc_set(pcie); tegra_pcie_enable_interrupts(pp); @@ -2233,6 +2244,14 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); + pcie->icc_path = devm_of_icc_get(&pdev->dev, "write"); + ret = PTR_ERR_OR_ZERO(pcie->icc_path); + if (ret) { + tegra_bpmp_put(pcie->bpmp); + dev_err_probe(&pdev->dev, ret, "failed to get write interconnect\n"); + return ret; + } + switch (pcie->of_data->mode) { case DW_PCIE_RC_TYPE: ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, -- cgit From 38bd22dac71ef7b1dbaa44fdc99f7722c116a01d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 20 Apr 2023 23:17:34 +0200 Subject: dt-bindings: sram: Add compatible for ST-Ericsson U8500 eSRAM This adds an SoC-specific binding for the banks of eSRAM available in the ST-Ericsson U8500. Acked-by: Rob Herring Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20230417-ux500-sram-v2-1-6e62ad551faa@linaro.org --- Documentation/devicetree/bindings/sram/sram.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 993430be355b..0922d1f71ba8 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -94,6 +94,7 @@ patternProperties: - samsung,exynos4210-sysram - samsung,exynos4210-sysram-ns - socionext,milbeaut-smp-sram + - stericsson,u8500-esram reg: description: -- cgit From 21e5a2d10c8f319be4126f320855429842473640 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 20 Apr 2023 23:17:35 +0200 Subject: misc: sram: Generate unique names for subpools The current code will, if we do not specify unique labels for the SRAM subnodes, fail to register several nodes named the same. Example: sram@40020000 { (...) sram@0 { (...) }; sram@1000 { (...) }; }; Since the child->name in both cases will be "sram" the gen_pool_create() will fail because the name is not unique. Use dev_name() for the device as this will have bus ID set to the fully translated address for the node, and that will always be unique. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20230417-ux500-sram-v2-2-6e62ad551faa@linaro.org --- drivers/misc/sram.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/misc/sram.c b/drivers/misc/sram.c index 99413310956b..5757adf418b1 100644 --- a/drivers/misc/sram.c +++ b/drivers/misc/sram.c @@ -235,10 +235,11 @@ static int sram_reserve_regions(struct sram_dev *sram, struct resource *res) goto err_chunks; } if (!label) - label = child->name; - - block->label = devm_kstrdup(sram->dev, - label, GFP_KERNEL); + block->label = devm_kasprintf(sram->dev, GFP_KERNEL, + "%s", dev_name(sram->dev)); + else + block->label = devm_kstrdup(sram->dev, + label, GFP_KERNEL); if (!block->label) { ret = -ENOMEM; goto err_chunks; -- cgit From f620596fa347170852da499e778a5736d79a4b79 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 17 May 2023 10:04:16 +0300 Subject: bus: ti-sysc: Fix dispc quirk masking bool variables Fix warning drivers/bus/ti-sysc.c:1806 sysc_quirk_dispc() warn: masking a bool. While at it let's add a comment for what were doing to make the code a bit easier to follow. Fixes: 7324a7a0d5e2 ("bus: ti-sysc: Implement display subsystem reset quirk") Reported-by: Dan Carpenter Closes: https://lore.kernel.org/linux-omap/a8ec8a68-9c2c-4076-bf47-09fccce7659f@kili.mountain/ Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 6c49de37d5e9..21fe9854703f 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1791,7 +1791,7 @@ static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, if (!ddata->module_va) return -EIO; - /* DISP_CONTROL */ + /* DISP_CONTROL, shut down lcd and digit on disable if enabled */ val = sysc_read(ddata, dispc_offset + 0x40); lcd_en = val & lcd_en_mask; digit_en = val & digit_en_mask; @@ -1803,7 +1803,7 @@ static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, else irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ } - if (disable & (lcd_en | digit_en)) + if (disable && (lcd_en || digit_en)) sysc_write(ddata, dispc_offset + 0x40, val & ~(lcd_en_mask | digit_en_mask)); -- cgit From 9f60d9d310b94c5869a5b6a2f1707b90bd60245c Mon Sep 17 00:00:00 2001 From: Yang Li Date: Fri, 28 Apr 2023 14:28:25 +0800 Subject: soc: ti: smartreflex: Use devm_platform_ioremap_resource() Convert platform_get_resource(),devm_ioremap_resource() to a single call to devm_platform_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yang Li Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20230428062825.126448-1-yang.lee@linux.alibaba.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/smartreflex.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/soc/ti/smartreflex.c b/drivers/soc/ti/smartreflex.c index da7898239a46..62b2f1464e46 100644 --- a/drivers/soc/ti/smartreflex.c +++ b/drivers/soc/ti/smartreflex.c @@ -815,7 +815,6 @@ static int omap_sr_probe(struct platform_device *pdev) { struct omap_sr *sr_info; struct omap_sr_data *pdata = pdev->dev.platform_data; - struct resource *mem; struct dentry *nvalue_dir; int i, ret = 0; @@ -835,8 +834,7 @@ static int omap_sr_probe(struct platform_device *pdev) return -EINVAL; } - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - sr_info->base = devm_ioremap_resource(&pdev->dev, mem); + sr_info->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(sr_info->base)) return PTR_ERR(sr_info->base); -- cgit From 413552b360e72604b8c0cf3f60f9e6f01c8ff963 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 18 Apr 2023 13:41:48 +0200 Subject: soc: ti: pruss: Avoid cast to incompatible function type Rather than casting clk_unregister_mux to an incompatible function type provide a trivial wrapper with the correct signature for the use-case. Reported by clang-16 with W=1: drivers/soc/ti/pruss.c:158:38: error: cast from 'void (*)(struct clk *)' to 'void (*)(void *)' converts to incompatible function type [-Werror,-Wcast-function-type-strict] ret = devm_add_action_or_reset(dev, (void(*)(void *))clk_unregister_mux, No functional change intended. Compile tested only. Signed-off-by: Simon Horman Reviewed-by: MD Danish Anwar Reviewed-by: Nick Desaulniers Reviewed-by: Nathan Chancellor Link: https://lore.kernel.org/r/20230418-pruss-clk-cb-v1-1-549a7e7febe4@kernel.org Signed-off-by: Nishanth Menon --- drivers/soc/ti/pruss.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index 6882c86b3ce5..e68441bd7b30 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -38,6 +38,11 @@ static void pruss_of_free_clk_provider(void *data) of_node_put(clk_mux_np); } +static void pruss_clk_unregister_mux(void *data) +{ + clk_unregister_mux(data); +} + static int pruss_clk_mux_setup(struct pruss *pruss, struct clk *clk_mux, char *mux_name, struct device_node *clks_np) { @@ -93,8 +98,7 @@ static int pruss_clk_mux_setup(struct pruss *pruss, struct clk *clk_mux, goto put_clk_mux_np; } - ret = devm_add_action_or_reset(dev, (void(*)(void *))clk_unregister_mux, - clk_mux); + ret = devm_add_action_or_reset(dev, pruss_clk_unregister_mux, clk_mux); if (ret) { dev_err(dev, "failed to add clkmux unregister action %d", ret); goto put_clk_mux_np; -- cgit From e752f9b924a1fd1afcf36e51b03dfa9c3096a3bd Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 11 May 2023 16:54:36 +0200 Subject: soc: ti: pruss: Allow compile-testing Allow compile testing of TI PRU-ICSS Subsystem Platform drivers. This allows for improved build-test coverage. No functional change intended. Signed-off-by: Simon Horman Link: https://lore.kernel.org/r/20230511-ti-pruss-compile-testing-v1-1-56291309a60c@kernel.org Signed-off-by: Nishanth Menon --- drivers/soc/ti/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 8c2a1036bef5..2cae17b65fd9 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -85,7 +85,7 @@ config TI_K3_SOCINFO config TI_PRUSS tristate "TI PRU-ICSS Subsystem Platform drivers" - depends on SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 + depends on SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST select MFD_SYSCON help TI PRU-ICSS Subsystem platform specific support. -- cgit From 67d1b0a1030fb20d54b720df6e976c06b893fb00 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 14 Apr 2023 10:25:39 +0530 Subject: soc: ti: pruss: Add pruss_get()/put() API Add two new get and put API, pruss_get() and pruss_put() to the PRUSS platform driver to allow client drivers to request a handle to a PRUSS device. This handle will be used by client drivers to request various operations of the PRUSS platform driver through additional API that will be added in the following patches. The pruss_get() function returns the pruss handle corresponding to a PRUSS device referenced by a PRU remoteproc instance. The pruss_put() is the complimentary function to pruss_get(). Co-developed-by: Suman Anna Signed-off-by: Suman Anna Signed-off-by: Tero Kristo Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Signed-off-by: Puranjay Mohan Reviewed-by: Roger Quadros Reviewed-by: Tony Lindgren Reviewed-by: Simon Horman Acked-by: Mathieu Poirier Signed-off-by: MD Danish Anwar Link: https://lore.kernel.org/r/20230414045542.3249939-2-danishanwar@ti.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/pruss.c | 62 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/pruss_driver.h | 18 +++++++++++++ 2 files changed, 80 insertions(+) diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index e68441bd7b30..f836660dac64 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -6,6 +6,7 @@ * Author(s): * Suman Anna * Andrew F. Davis + * Tero Kristo */ #include @@ -18,6 +19,7 @@ #include #include #include +#include #include /** @@ -30,6 +32,66 @@ struct pruss_private_data { bool has_core_mux_clock; }; +/** + * pruss_get() - get the pruss for a given PRU remoteproc + * @rproc: remoteproc handle of a PRU instance + * + * Finds the parent pruss device for a PRU given the @rproc handle of the + * PRU remote processor. This function increments the pruss device's refcount, + * so always use pruss_put() to decrement it back once pruss isn't needed + * anymore. + * + * This API doesn't check if @rproc is valid or not. It is expected the caller + * will have done a pru_rproc_get() on @rproc, before calling this API to make + * sure that @rproc is valid. + * + * Return: pruss handle on success, and an ERR_PTR on failure using one + * of the following error values + * -EINVAL if invalid parameter + * -ENODEV if PRU device or PRUSS device is not found + */ +struct pruss *pruss_get(struct rproc *rproc) +{ + struct pruss *pruss; + struct device *dev; + struct platform_device *ppdev; + + if (IS_ERR_OR_NULL(rproc)) + return ERR_PTR(-EINVAL); + + dev = &rproc->dev; + + /* make sure it is PRU rproc */ + if (!dev->parent || !is_pru_rproc(dev->parent)) + return ERR_PTR(-ENODEV); + + ppdev = to_platform_device(dev->parent->parent); + pruss = platform_get_drvdata(ppdev); + if (!pruss) + return ERR_PTR(-ENODEV); + + get_device(pruss->dev); + + return pruss; +} +EXPORT_SYMBOL_GPL(pruss_get); + +/** + * pruss_put() - decrement pruss device's usecount + * @pruss: pruss handle + * + * Complimentary function for pruss_get(). Needs to be called + * after the PRUSS is used, and only if the pruss_get() succeeds. + */ +void pruss_put(struct pruss *pruss) +{ + if (IS_ERR_OR_NULL(pruss)) + return; + + put_device(pruss->dev); +} +EXPORT_SYMBOL_GPL(pruss_put); + static void pruss_of_free_clk_provider(void *data) { struct device_node *clk_mux_np = data; diff --git a/include/linux/pruss_driver.h b/include/linux/pruss_driver.h index ecfded30ed05..cb40c2b31045 100644 --- a/include/linux/pruss_driver.h +++ b/include/linux/pruss_driver.h @@ -9,7 +9,9 @@ #ifndef _PRUSS_DRIVER_H_ #define _PRUSS_DRIVER_H_ +#include #include +#include /* * enum pruss_mem - PRUSS memory range identifiers @@ -51,4 +53,20 @@ struct pruss { struct clk *iep_clk_mux; }; +#if IS_ENABLED(CONFIG_TI_PRUSS) + +struct pruss *pruss_get(struct rproc *rproc); +void pruss_put(struct pruss *pruss); + +#else + +static inline struct pruss *pruss_get(struct rproc *rproc) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline void pruss_put(struct pruss *pruss) { } + +#endif /* CONFIG_TI_PRUSS */ + #endif /* _PRUSS_DRIVER_H_ */ -- cgit From b789ca1e3380ab63b60c3356c026a7e8eb26ba01 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 14 Apr 2023 10:25:40 +0530 Subject: soc: ti: pruss: Add pruss_{request,release}_mem_region() API Add two new API - pruss_request_mem_region() & pruss_release_mem_region(), to the PRUSS platform driver to allow client drivers to acquire and release the common memory resources present within a PRU-ICSS subsystem. This allows the client drivers to directly manipulate the respective memories, as per their design contract with the associated firmware. Co-developed-by: Suman Anna Signed-off-by: Suman Anna Signed-off-by: Andrew F. Davis Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Roger Quadros Acked-by: Mathieu Poirier Reviewed-by: Tony Lindgren Reviewed-by: Simon Horman Signed-off-by: MD Danish Anwar Link: https://lore.kernel.org/r/20230414045542.3249939-3-danishanwar@ti.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/pruss.c | 77 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/pruss_driver.h | 22 +++++++++++++ 2 files changed, 99 insertions(+) diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index f836660dac64..df5eb4d959f8 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -92,6 +92,82 @@ void pruss_put(struct pruss *pruss) } EXPORT_SYMBOL_GPL(pruss_put); +/** + * pruss_request_mem_region() - request a memory resource + * @pruss: the pruss instance + * @mem_id: the memory resource id + * @region: pointer to memory region structure to be filled in + * + * This function allows a client driver to request a memory resource, + * and if successful, will let the client driver own the particular + * memory region until released using the pruss_release_mem_region() + * API. + * + * Return: 0 if requested memory region is available (in such case pointer to + * memory region is returned via @region), an error otherwise + */ +int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id, + struct pruss_mem_region *region) +{ + if (!pruss || !region || mem_id >= PRUSS_MEM_MAX) + return -EINVAL; + + mutex_lock(&pruss->lock); + + if (pruss->mem_in_use[mem_id]) { + mutex_unlock(&pruss->lock); + return -EBUSY; + } + + *region = pruss->mem_regions[mem_id]; + pruss->mem_in_use[mem_id] = region; + + mutex_unlock(&pruss->lock); + + return 0; +} +EXPORT_SYMBOL_GPL(pruss_request_mem_region); + +/** + * pruss_release_mem_region() - release a memory resource + * @pruss: the pruss instance + * @region: the memory region to release + * + * This function is the complimentary function to + * pruss_request_mem_region(), and allows the client drivers to + * release back a memory resource. + * + * Return: 0 on success, an error code otherwise + */ +int pruss_release_mem_region(struct pruss *pruss, + struct pruss_mem_region *region) +{ + int id; + + if (!pruss || !region) + return -EINVAL; + + mutex_lock(&pruss->lock); + + /* find out the memory region being released */ + for (id = 0; id < PRUSS_MEM_MAX; id++) { + if (pruss->mem_in_use[id] == region) + break; + } + + if (id == PRUSS_MEM_MAX) { + mutex_unlock(&pruss->lock); + return -EINVAL; + } + + pruss->mem_in_use[id] = NULL; + + mutex_unlock(&pruss->lock); + + return 0; +} +EXPORT_SYMBOL_GPL(pruss_release_mem_region); + static void pruss_of_free_clk_provider(void *data) { struct device_node *clk_mux_np = data; @@ -298,6 +374,7 @@ static int pruss_probe(struct platform_device *pdev) return -ENOMEM; pruss->dev = dev; + mutex_init(&pruss->lock); child = of_get_child_by_name(np, "memories"); if (!child) { diff --git a/include/linux/pruss_driver.h b/include/linux/pruss_driver.h index cb40c2b31045..c8f2e53b911b 100644 --- a/include/linux/pruss_driver.h +++ b/include/linux/pruss_driver.h @@ -9,6 +9,7 @@ #ifndef _PRUSS_DRIVER_H_ #define _PRUSS_DRIVER_H_ +#include #include #include #include @@ -41,6 +42,8 @@ struct pruss_mem_region { * @cfg_base: base iomap for CFG region * @cfg_regmap: regmap for config region * @mem_regions: data for each of the PRUSS memory regions + * @mem_in_use: to indicate if memory resource is in use + * @lock: mutex to serialize access to resources * @core_clk_mux: clk handle for PRUSS CORE_CLK_MUX * @iep_clk_mux: clk handle for PRUSS IEP_CLK_MUX */ @@ -49,6 +52,8 @@ struct pruss { void __iomem *cfg_base; struct regmap *cfg_regmap; struct pruss_mem_region mem_regions[PRUSS_MEM_MAX]; + struct pruss_mem_region *mem_in_use[PRUSS_MEM_MAX]; + struct mutex lock; /* PRU resource lock */ struct clk *core_clk_mux; struct clk *iep_clk_mux; }; @@ -57,6 +62,10 @@ struct pruss { struct pruss *pruss_get(struct rproc *rproc); void pruss_put(struct pruss *pruss); +int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id, + struct pruss_mem_region *region); +int pruss_release_mem_region(struct pruss *pruss, + struct pruss_mem_region *region); #else @@ -67,6 +76,19 @@ static inline struct pruss *pruss_get(struct rproc *rproc) static inline void pruss_put(struct pruss *pruss) { } +static inline int pruss_request_mem_region(struct pruss *pruss, + enum pruss_mem mem_id, + struct pruss_mem_region *region) +{ + return -EOPNOTSUPP; +} + +static inline int pruss_release_mem_region(struct pruss *pruss, + struct pruss_mem_region *region) +{ + return -EOPNOTSUPP; +} + #endif /* CONFIG_TI_PRUSS */ #endif /* _PRUSS_DRIVER_H_ */ -- cgit From 51b5760e56ef19106a3c4487a66d186d46ccc6f4 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 14 Apr 2023 10:25:41 +0530 Subject: soc: ti: pruss: Add pruss_cfg_read()/update(), pruss_cfg_get_gpmux()/set_gpmux() APIs Add two new generic API pruss_cfg_read() and pruss_cfg_update() to the PRUSS platform driver to read and program respectively a register within the PRUSS CFG sub-module represented by a syscon driver. These APIs are internal to PRUSS driver. Add two new helper functions pruss_cfg_get_gpmux() & pruss_cfg_set_gpmux() to get and set the GP MUX mode for programming the PRUSS internal wrapper mux functionality as needed by usecases. Various useful registers and macros for certain register bit-fields and their values have also been added. Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Signed-off-by: Puranjay Mohan Reviewed-by: Roger Quadros Reviewed-by: Tony Lindgren Reviewed-by: Simon Horman Acked-by: Mathieu Poirier Signed-off-by: MD Danish Anwar Link: https://lore.kernel.org/r/20230414045542.3249939-4-danishanwar@ti.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/pruss.c | 45 ++++++++++++++++++++++ drivers/soc/ti/pruss.h | 88 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/pruss_driver.h | 32 ++++++++++++++++ 3 files changed, 165 insertions(+) create mode 100644 drivers/soc/ti/pruss.h diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index df5eb4d959f8..2c44913c083b 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -21,6 +21,7 @@ #include #include #include +#include "pruss.h" /** * struct pruss_private_data - PRUSS driver private data @@ -168,6 +169,50 @@ int pruss_release_mem_region(struct pruss *pruss, } EXPORT_SYMBOL_GPL(pruss_release_mem_region); +/** + * pruss_cfg_get_gpmux() - get the current GPMUX value for a PRU device + * @pruss: pruss instance + * @pru_id: PRU identifier (0-1) + * @mux: pointer to store the current mux value into + * + * Return: 0 on success, or an error code otherwise + */ +int pruss_cfg_get_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 *mux) +{ + int ret; + u32 val; + + if (pru_id >= PRUSS_NUM_PRUS || !mux) + return -EINVAL; + + ret = pruss_cfg_read(pruss, PRUSS_CFG_GPCFG(pru_id), &val); + if (!ret) + *mux = (u8)((val & PRUSS_GPCFG_PRU_MUX_SEL_MASK) >> + PRUSS_GPCFG_PRU_MUX_SEL_SHIFT); + return ret; +} +EXPORT_SYMBOL_GPL(pruss_cfg_get_gpmux); + +/** + * pruss_cfg_set_gpmux() - set the GPMUX value for a PRU device + * @pruss: pruss instance + * @pru_id: PRU identifier (0-1) + * @mux: new mux value for PRU + * + * Return: 0 on success, or an error code otherwise + */ +int pruss_cfg_set_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 mux) +{ + if (mux >= PRUSS_GP_MUX_SEL_MAX || + pru_id >= PRUSS_NUM_PRUS) + return -EINVAL; + + return pruss_cfg_update(pruss, PRUSS_CFG_GPCFG(pru_id), + PRUSS_GPCFG_PRU_MUX_SEL_MASK, + (u32)mux << PRUSS_GPCFG_PRU_MUX_SEL_SHIFT); +} +EXPORT_SYMBOL_GPL(pruss_cfg_set_gpmux); + static void pruss_of_free_clk_provider(void *data) { struct device_node *clk_mux_np = data; diff --git a/drivers/soc/ti/pruss.h b/drivers/soc/ti/pruss.h new file mode 100644 index 000000000000..6c55987e0e55 --- /dev/null +++ b/drivers/soc/ti/pruss.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * PRU-ICSS Subsystem user interfaces + * + * Copyright (C) 2015-2023 Texas Instruments Incorporated - http://www.ti.com + * MD Danish Anwar + */ + +#ifndef _SOC_TI_PRUSS_H_ +#define _SOC_TI_PRUSS_H_ + +#include +#include + +/* + * PRU_ICSS_CFG registers + * SYSCFG, ISRP, ISP, IESP, IECP, SCRP applicable on AMxxxx devices only + */ +#define PRUSS_CFG_REVID 0x00 +#define PRUSS_CFG_SYSCFG 0x04 +#define PRUSS_CFG_GPCFG(x) (0x08 + (x) * 4) +#define PRUSS_CFG_CGR 0x10 +#define PRUSS_CFG_ISRP 0x14 +#define PRUSS_CFG_ISP 0x18 +#define PRUSS_CFG_IESP 0x1C +#define PRUSS_CFG_IECP 0x20 +#define PRUSS_CFG_SCRP 0x24 +#define PRUSS_CFG_PMAO 0x28 +#define PRUSS_CFG_MII_RT 0x2C +#define PRUSS_CFG_IEPCLK 0x30 +#define PRUSS_CFG_SPP 0x34 +#define PRUSS_CFG_PIN_MX 0x40 + +/* PRUSS_GPCFG register bits */ +#define PRUSS_GPCFG_PRU_GPI_MODE_MASK GENMASK(1, 0) +#define PRUSS_GPCFG_PRU_GPI_MODE_SHIFT 0 + +#define PRUSS_GPCFG_PRU_MUX_SEL_SHIFT 26 +#define PRUSS_GPCFG_PRU_MUX_SEL_MASK GENMASK(29, 26) + +/* PRUSS_MII_RT register bits */ +#define PRUSS_MII_RT_EVENT_EN BIT(0) + +/* PRUSS_SPP register bits */ +#define PRUSS_SPP_XFER_SHIFT_EN BIT(1) +#define PRUSS_SPP_PRU1_PAD_HP_EN BIT(0) +#define PRUSS_SPP_RTU_XFR_SHIFT_EN BIT(3) + +/** + * pruss_cfg_read() - read a PRUSS CFG sub-module register + * @pruss: the pruss instance handle + * @reg: register offset within the CFG sub-module + * @val: pointer to return the value in + * + * Reads a given register within the PRUSS CFG sub-module and + * returns it through the passed-in @val pointer + * + * Return: 0 on success, or an error code otherwise + */ +static int pruss_cfg_read(struct pruss *pruss, unsigned int reg, unsigned int *val) +{ + if (IS_ERR_OR_NULL(pruss)) + return -EINVAL; + + return regmap_read(pruss->cfg_regmap, reg, val); +} + +/** + * pruss_cfg_update() - configure a PRUSS CFG sub-module register + * @pruss: the pruss instance handle + * @reg: register offset within the CFG sub-module + * @mask: bit mask to use for programming the @val + * @val: value to write + * + * Programs a given register within the PRUSS CFG sub-module + * + * Return: 0 on success, or an error code otherwise + */ +static int pruss_cfg_update(struct pruss *pruss, unsigned int reg, + unsigned int mask, unsigned int val) +{ + if (IS_ERR_OR_NULL(pruss)) + return -EINVAL; + + return regmap_update_bits(pruss->cfg_regmap, reg, mask, val); +} + +#endif /* _SOC_TI_PRUSS_H_ */ diff --git a/include/linux/pruss_driver.h b/include/linux/pruss_driver.h index c8f2e53b911b..5bb8897724a9 100644 --- a/include/linux/pruss_driver.h +++ b/include/linux/pruss_driver.h @@ -14,6 +14,24 @@ #include #include +/* + * enum pruss_gp_mux_sel - PRUSS GPI/O Mux modes for the + * PRUSS_GPCFG0/1 registers + * + * NOTE: The below defines are the most common values, but there + * are some exceptions like on 66AK2G, where the RESERVED and MII2 + * values are interchanged. Also, this bit-field does not exist on + * AM335x SoCs + */ +enum pruss_gp_mux_sel { + PRUSS_GP_MUX_SEL_GP, + PRUSS_GP_MUX_SEL_ENDAT, + PRUSS_GP_MUX_SEL_RESERVED, + PRUSS_GP_MUX_SEL_SD, + PRUSS_GP_MUX_SEL_MII2, + PRUSS_GP_MUX_SEL_MAX, +}; + /* * enum pruss_mem - PRUSS memory range identifiers */ @@ -66,6 +84,8 @@ int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id, struct pruss_mem_region *region); int pruss_release_mem_region(struct pruss *pruss, struct pruss_mem_region *region); +int pruss_cfg_get_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 *mux); +int pruss_cfg_set_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 mux); #else @@ -89,6 +109,18 @@ static inline int pruss_release_mem_region(struct pruss *pruss, return -EOPNOTSUPP; } +static inline int pruss_cfg_get_gpmux(struct pruss *pruss, + enum pruss_pru_id pru_id, u8 *mux) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline int pruss_cfg_set_gpmux(struct pruss *pruss, + enum pruss_pru_id pru_id, u8 mux) +{ + return ERR_PTR(-EOPNOTSUPP); +} + #endif /* CONFIG_TI_PRUSS */ #endif /* _PRUSS_DRIVER_H_ */ -- cgit From 0211cc1e4fbbc81853227147bf0982c47362c567 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Fri, 14 Apr 2023 10:25:42 +0530 Subject: soc: ti: pruss: Add helper functions to set GPI mode, MII_RT_event and XFR The PRUSS CFG module is represented as a syscon node and is currently managed by the PRUSS platform driver. Add easy accessor functions to set GPI mode, MII_RT event enable/disable and XFR (XIN XOUT) enable/disable to enable the PRUSS Ethernet usecase. These functions reuse the generic pruss_cfg_update() API function. Signed-off-by: Suman Anna Co-developed-by: Grzegorz Jaszczyk Signed-off-by: Grzegorz Jaszczyk Signed-off-by: Puranjay Mohan Reviewed-by: Roger Quadros Reviewed-by: Tony Lindgren Reviewed-by: Simon Horman Reviewed-by: Mathieu Poirier Signed-off-by: MD Danish Anwar Link: https://lore.kernel.org/r/20230414045542.3249939-5-danishanwar@ti.com Signed-off-by: Nishanth Menon --- drivers/remoteproc/pru_rproc.c | 15 --------- drivers/soc/ti/pruss.c | 71 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pruss_driver.h | 51 ++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+), 15 deletions(-) diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 095f66130f48..54f5ce302e7a 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -81,21 +81,6 @@ enum pru_iomem { PRU_IOMEM_MAX, }; -/** - * enum pru_type - PRU core type identifier - * - * @PRU_TYPE_PRU: Programmable Real-time Unit - * @PRU_TYPE_RTU: Auxiliary Programmable Real-Time Unit - * @PRU_TYPE_TX_PRU: Transmit Programmable Real-Time Unit - * @PRU_TYPE_MAX: just keep this one at the end - */ -enum pru_type { - PRU_TYPE_PRU = 0, - PRU_TYPE_RTU, - PRU_TYPE_TX_PRU, - PRU_TYPE_MAX, -}; - /** * struct pru_private_data - device data for a PRU core * @type: type of the PRU core (PRU, RTU, Tx_PRU) diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index 2c44913c083b..7fdefee1ed87 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -213,6 +213,77 @@ int pruss_cfg_set_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 mux) } EXPORT_SYMBOL_GPL(pruss_cfg_set_gpmux); +/** + * pruss_cfg_gpimode() - set the GPI mode of the PRU + * @pruss: the pruss instance handle + * @pru_id: id of the PRU core within the PRUSS + * @mode: GPI mode to set + * + * Sets the GPI mode for a given PRU by programming the + * corresponding PRUSS_CFG_GPCFGx register + * + * Return: 0 on success, or an error code otherwise + */ +int pruss_cfg_gpimode(struct pruss *pruss, enum pruss_pru_id pru_id, + enum pruss_gpi_mode mode) +{ + if (pru_id >= PRUSS_NUM_PRUS || mode >= PRUSS_GPI_MODE_MAX) + return -EINVAL; + + return pruss_cfg_update(pruss, PRUSS_CFG_GPCFG(pru_id), + PRUSS_GPCFG_PRU_GPI_MODE_MASK, + mode << PRUSS_GPCFG_PRU_GPI_MODE_SHIFT); +} +EXPORT_SYMBOL_GPL(pruss_cfg_gpimode); + +/** + * pruss_cfg_miirt_enable() - Enable/disable MII RT Events + * @pruss: the pruss instance + * @enable: enable/disable + * + * Enable/disable the MII RT Events for the PRUSS. + * + * Return: 0 on success, or an error code otherwise + */ +int pruss_cfg_miirt_enable(struct pruss *pruss, bool enable) +{ + u32 set = enable ? PRUSS_MII_RT_EVENT_EN : 0; + + return pruss_cfg_update(pruss, PRUSS_CFG_MII_RT, + PRUSS_MII_RT_EVENT_EN, set); +} +EXPORT_SYMBOL_GPL(pruss_cfg_miirt_enable); + +/** + * pruss_cfg_xfr_enable() - Enable/disable XIN XOUT shift functionality + * @pruss: the pruss instance + * @pru_type: PRU core type identifier + * @enable: enable/disable + * + * Return: 0 on success, or an error code otherwise + */ +int pruss_cfg_xfr_enable(struct pruss *pruss, enum pru_type pru_type, + bool enable) +{ + u32 mask, set; + + switch (pru_type) { + case PRU_TYPE_PRU: + mask = PRUSS_SPP_XFER_SHIFT_EN; + break; + case PRU_TYPE_RTU: + mask = PRUSS_SPP_RTU_XFR_SHIFT_EN; + break; + default: + return -EINVAL; + } + + set = enable ? mask : 0; + + return pruss_cfg_update(pruss, PRUSS_CFG_SPP, mask, set); +} +EXPORT_SYMBOL_GPL(pruss_cfg_xfr_enable); + static void pruss_of_free_clk_provider(void *data) { struct device_node *clk_mux_np = data; diff --git a/include/linux/pruss_driver.h b/include/linux/pruss_driver.h index 5bb8897724a9..c9a31c567e85 100644 --- a/include/linux/pruss_driver.h +++ b/include/linux/pruss_driver.h @@ -32,6 +32,33 @@ enum pruss_gp_mux_sel { PRUSS_GP_MUX_SEL_MAX, }; +/* + * enum pruss_gpi_mode - PRUSS GPI configuration modes, used + * to program the PRUSS_GPCFG0/1 registers + */ +enum pruss_gpi_mode { + PRUSS_GPI_MODE_DIRECT, + PRUSS_GPI_MODE_PARALLEL, + PRUSS_GPI_MODE_28BIT_SHIFT, + PRUSS_GPI_MODE_MII, + PRUSS_GPI_MODE_MAX, +}; + +/** + * enum pru_type - PRU core type identifier + * + * @PRU_TYPE_PRU: Programmable Real-time Unit + * @PRU_TYPE_RTU: Auxiliary Programmable Real-Time Unit + * @PRU_TYPE_TX_PRU: Transmit Programmable Real-Time Unit + * @PRU_TYPE_MAX: just keep this one at the end + */ +enum pru_type { + PRU_TYPE_PRU, + PRU_TYPE_RTU, + PRU_TYPE_TX_PRU, + PRU_TYPE_MAX, +}; + /* * enum pruss_mem - PRUSS memory range identifiers */ @@ -86,6 +113,11 @@ int pruss_release_mem_region(struct pruss *pruss, struct pruss_mem_region *region); int pruss_cfg_get_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 *mux); int pruss_cfg_set_gpmux(struct pruss *pruss, enum pruss_pru_id pru_id, u8 mux); +int pruss_cfg_gpimode(struct pruss *pruss, enum pruss_pru_id pru_id, + enum pruss_gpi_mode mode); +int pruss_cfg_miirt_enable(struct pruss *pruss, bool enable); +int pruss_cfg_xfr_enable(struct pruss *pruss, enum pru_type pru_type, + bool enable); #else @@ -121,6 +153,25 @@ static inline int pruss_cfg_set_gpmux(struct pruss *pruss, return ERR_PTR(-EOPNOTSUPP); } +static inline int pruss_cfg_gpimode(struct pruss *pruss, + enum pruss_pru_id pru_id, + enum pruss_gpi_mode mode) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline int pruss_cfg_miirt_enable(struct pruss *pruss, bool enable) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline int pruss_cfg_xfr_enable(struct pruss *pruss, + enum pru_type pru_type, + bool enable); +{ + return ERR_PTR(-EOPNOTSUPP); +} + #endif /* CONFIG_TI_PRUSS */ #endif /* _PRUSS_DRIVER_H_ */ -- cgit From 3dde7aa2fad5df0cf623f73e775f516997a74e89 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 16 May 2023 15:47:15 +0200 Subject: MAINTAINERS: Remove Hyun and Anurag from maintainer list There is no activity from them for these drivers. All of them have Laurent as active maintainer and their emails no longer works that's why remove them from the list. Reviewed-by: Laurent Pinchart Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/18700dda117076510baf87a090acbb29cb3ba3ba.1684244832.git.michal.simek@amd.com --- MAINTAINERS | 4 ---- 1 file changed, 4 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e..60f6effb168c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7077,7 +7077,6 @@ F: Documentation/gpu/xen-front.rst F: drivers/gpu/drm/xen/ DRM DRIVERS FOR XILINX -M: Hyun Kwon M: Laurent Pinchart L: dri-devel@lists.freedesktop.org S: Maintained @@ -23162,7 +23161,6 @@ S: Maintained F: drivers/tty/serial/uartlite.c XILINX VIDEO IP CORES -M: Hyun Kwon M: Laurent Pinchart L: linux-media@vger.kernel.org S: Supported @@ -23191,7 +23189,6 @@ F: include/linux/dma/amd_xdma.h F: include/linux/platform_data/amd_xdma.h XILINX ZYNQMP DPDMA DRIVER -M: Hyun Kwon M: Laurent Pinchart L: dmaengine@vger.kernel.org S: Supported @@ -23207,7 +23204,6 @@ F: Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yam F: drivers/edac/zynqmp_edac.c XILINX ZYNQMP PSGTR PHY DRIVER -M: Anurag Kumar Vulisha M: Laurent Pinchart L: linux-kernel@vger.kernel.org S: Supported -- cgit From 4b11fa4f0737aae1a3fc3cdf367acd4ebb5bc941 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 23 May 2023 09:15:50 +0200 Subject: qcom: pmic_glink: enable altmode for SM8450 Create a separate bitmask for sm8550 and enable altmode aux driver for sm8450 platform to enable pmic-glink altmode events. Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230503-topic-sm8450-graphics-dp-next-v3-6-6c43d293995f@linaro.org --- drivers/soc/qcom/pmic_glink.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index 8bf95df0a56a..c87056769ebd 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -338,13 +338,17 @@ static int pmic_glink_remove(struct platform_device *pdev) return 0; } -/* Do not handle altmode for now on those platforms */ static const unsigned long pmic_glink_sm8450_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | + BIT(PMIC_GLINK_CLIENT_ALTMODE) | + BIT(PMIC_GLINK_CLIENT_UCSI); + +/* Do not handle altmode for now on those platforms */ +static const unsigned long pmic_glink_sm8550_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | BIT(PMIC_GLINK_CLIENT_UCSI); static const struct of_device_id pmic_glink_of_match[] = { { .compatible = "qcom,sm8450-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, - { .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, + { .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8550_client_mask }, { .compatible = "qcom,pmic-glink" }, {} }; -- cgit From 210d12c8197a551caa2979be421aa42381156aec Mon Sep 17 00:00:00 2001 From: Gokul krishna Krishnakumar Date: Mon, 8 May 2023 17:18:21 -0700 Subject: soc: qcom: mdt_loader: Enhance split binary detection It may be that the offset of the first program header lies inside the mdt's filesize, in this case the loader would incorrectly assume that the bins were not split and in this scenario the firmware authentication fails. This change updates the logic used by the mdt loader to understand whether the firmware images are split or not. It figures this out by checking if each programs header's segment lies within the file or not. Co-developed-by: Melody Olvera Signed-off-by: Melody Olvera Signed-off-by: Gokul krishna Krishnakumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230509001821.24010-1-quic_gokukris@quicinc.com --- drivers/soc/qcom/mdt_loader.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index 33dd8c315eb7..892b1648d693 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -258,6 +258,26 @@ out: } EXPORT_SYMBOL_GPL(qcom_mdt_pas_init); +static bool qcom_mdt_bins_are_split(const struct firmware *fw, const char *fw_name) +{ + const struct elf32_phdr *phdrs; + const struct elf32_hdr *ehdr; + uint64_t seg_start, seg_end; + int i; + + ehdr = (struct elf32_hdr *)fw->data; + phdrs = (struct elf32_phdr *)(ehdr + 1); + + for (i = 0; i < ehdr->e_phnum; i++) { + seg_start = phdrs[i].p_offset; + seg_end = phdrs[i].p_offset + phdrs[i].p_filesz; + if (seg_start > fw->size || seg_end > fw->size) + return true; + } + + return false; +} + static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, void *mem_region, phys_addr_t mem_phys, size_t mem_size, @@ -270,6 +290,7 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, phys_addr_t min_addr = PHYS_ADDR_MAX; ssize_t offset; bool relocate = false; + bool is_split; void *ptr; int ret = 0; int i; @@ -277,6 +298,7 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, if (!fw || !mem_region || !mem_phys || !mem_size) return -EINVAL; + is_split = qcom_mdt_bins_are_split(fw, fw_name); ehdr = (struct elf32_hdr *)fw->data; phdrs = (struct elf32_phdr *)(ehdr + 1); @@ -330,8 +352,7 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, ptr = mem_region + offset; - if (phdr->p_filesz && phdr->p_offset < fw->size && - phdr->p_offset + phdr->p_filesz <= fw->size) { + if (phdr->p_filesz && !is_split) { /* Firmware is large enough to be non-split */ if (phdr->p_offset + phdr->p_filesz > fw->size) { dev_err(dev, "file %s segment %d would be truncated\n", -- cgit From 6ade5ce20c466298c04b10fe66091b9055aa9988 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 2 May 2023 15:09:59 +0530 Subject: dt-bindings: soc: qcom: eud: Fix compatible string in the example As noted by Konrad while reviewing [1], the example node in the EUD yaml documentation has a compatible string with no space after a comma. Fix the same. [1]. https://lore.kernel.org/linux-arm-msm/20221231131945.3286639-1-bhupesh.sharma@linaro.org Signed-off-by: Bhupesh Sharma Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230502093959.1258889-3-bhupesh.sharma@linaro.org --- Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index 14dd29471c80..f2c5ec7e6437 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -55,9 +55,10 @@ additionalProperties: false examples: - | eud@88e0000 { - compatible = "qcom,sc7280-eud","qcom,eud"; + compatible = "qcom,sc7280-eud", "qcom,eud"; reg = <0x88e0000 0x2000>, <0x88e2000 0x1000>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -67,6 +68,7 @@ examples: remote-endpoint = <&usb2_role_switch>; }; }; + port@1 { reg = <1>; eud_con: endpoint { -- cgit From 4b819e7e89fedc90150a78152bfa6e6e3534e64b Mon Sep 17 00:00:00 2001 From: Min-Hua Chen Date: Tue, 23 May 2023 00:07:56 +0800 Subject: soc: qcom: rpmpd: use correct __le32 type Use cpu_to_le32 to cast constants to __le32 before comparing them with __le32 type pd->key. This fixes the following sparse warnings: drivers/soc/qcom/rpmpd.c:895:31: sparse: warning: restricted __le32 degrades to integer drivers/soc/qcom/rpmpd.c:896:15: sparse: warning: restricted __le32 degrades to integer Signed-off-by: Min-Hua Chen Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230522160757.284165-1-minhuadotchen@gmail.com --- drivers/soc/qcom/rpmpd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index f8397dcb146c..99b017fd76b7 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -892,8 +892,8 @@ static int rpmpd_set_performance(struct generic_pm_domain *domain, pd->corner = state; /* Always send updates for vfc and vfl */ - if (!pd->enabled && pd->key != KEY_FLOOR_CORNER && - pd->key != KEY_FLOOR_LEVEL) + if (!pd->enabled && pd->key != cpu_to_le32(KEY_FLOOR_CORNER) && + pd->key != cpu_to_le32(KEY_FLOOR_LEVEL)) goto out; ret = rpmpd_aggregate_corner(pd); -- cgit From 1252ea653bff14eb1a2184245a977ecb8505be68 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 10 Apr 2023 20:10:36 +0200 Subject: dt-bindings: soc: qcom: smd-rpm: allow MSM8226 over SMD The MSM8226 RPM uses SMD, so it must allow qcom,smd-channels: qcom-msm8226-samsung-s3ve3g.dtb: rpm-requests: qcom,smd-channels: False schema does not allow ['rpm_requests'] Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230410181036.25943-1-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index ea86569a40d3..65c02a7fef80 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -81,6 +81,7 @@ if: contains: enum: - qcom,rpm-apq8084 + - qcom,rpm-msm8226 - qcom,rpm-msm8916 - qcom,rpm-msm8936 - qcom,rpm-msm8974 -- cgit From c72e31718a8fb9bc070ee99f273446e05caa687d Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Sat, 15 Apr 2023 22:18:48 +0200 Subject: soc: qcom: ramp_controller: Improve error message for failure in .remove() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When a platform_driver's .remove() callback returns an error, the driver core emits remove callback returned a non-zero value. This will be ignored. . Replace this by a more specific error message. Then convert to .remove_new() which is equivalent to returning zero unconditionally in .remove(). See commit 5c5a7680e67b ("platform: Provide a remove callback that returns no value") for its rationale. Signed-off-by: Uwe Kleine-König Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230415201848.3779001-1-u.kleine-koenig@pengutronix.de --- drivers/soc/qcom/ramp_controller.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/ramp_controller.c b/drivers/soc/qcom/ramp_controller.c index dc74d2a19de2..1ff13661bcce 100644 --- a/drivers/soc/qcom/ramp_controller.c +++ b/drivers/soc/qcom/ramp_controller.c @@ -308,12 +308,15 @@ static int qcom_ramp_controller_probe(struct platform_device *pdev) return qcom_ramp_controller_start(qrc); } -static int qcom_ramp_controller_remove(struct platform_device *pdev) +static void qcom_ramp_controller_remove(struct platform_device *pdev) { struct qcom_ramp_controller *qrc = platform_get_drvdata(pdev); + int ret; - return rc_write_cfg(qrc, qrc->desc->cfg_ramp_dis, - RC_DCVS_CFG_SID, qrc->desc->num_ramp_dis); + ret = rc_write_cfg(qrc, qrc->desc->cfg_ramp_dis, + RC_DCVS_CFG_SID, qrc->desc->num_ramp_dis); + if (ret) + dev_err(&pdev->dev, "Failed to send disable sequence\n"); } static const struct of_device_id qcom_ramp_controller_match_table[] = { @@ -329,7 +332,7 @@ static struct platform_driver qcom_ramp_controller_driver = { .suppress_bind_attrs = true, }, .probe = qcom_ramp_controller_probe, - .remove = qcom_ramp_controller_remove, + .remove_new = qcom_ramp_controller_remove, }; static int __init qcom_ramp_controller_init(void) -- cgit From 56310520308ab863030e9baa9a8f63bb31c94e27 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Thu, 20 Apr 2023 16:50:38 -1000 Subject: soc: qcom: qmi: Use alloc_ordered_workqueue() to create ordered workqueues BACKGROUND ========== When multiple work items are queued to a workqueue, their execution order doesn't match the queueing order. They may get executed in any order and simultaneously. When fully serialized execution - one by one in the queueing order - is needed, an ordered workqueue should be used which can be created with alloc_ordered_workqueue(). However, alloc_ordered_workqueue() was a later addition. Before it, an ordered workqueue could be obtained by creating an UNBOUND workqueue with @max_active==1. This originally was an implementation side-effect which was broken by 4c16bd327c74 ("workqueue: restore WQ_UNBOUND/max_active==1 to be ordered"). Because there were users that depended on the ordered execution, 5c0338c68706 ("workqueue: restore WQ_UNBOUND/max_active==1 to be ordered") made workqueue allocation path to implicitly promote UNBOUND workqueues w/ @max_active==1 to ordered workqueues. While this has worked okay, overloading the UNBOUND allocation interface this way creates other issues. It's difficult to tell whether a given workqueue actually needs to be ordered and users that legitimately want a min concurrency level wq unexpectedly gets an ordered one instead. With planned UNBOUND workqueue updates to improve execution locality and more prevalence of chiplet designs which can benefit from such improvements, this isn't a state we wanna be in forever. This patch series audits all callsites that create an UNBOUND workqueue w/ @max_active==1 and converts them to alloc_ordered_workqueue() as necessary. WHAT TO LOOK FOR ================ The conversions are from alloc_workqueue(WQ_UNBOUND | flags, 1, args..) to alloc_ordered_workqueue(flags, args...) which don't cause any functional changes. If you know that fully ordered execution is not ncessary, please let me know. I'll drop the conversion and instead add a comment noting the fact to reduce confusion while conversion is in progress. If you aren't fully sure, it's completely fine to let the conversion through. The behavior will stay exactly the same and we can always reconsider later. As there are follow-up workqueue core changes, I'd really appreciate if the patch can be routed through the workqueue tree w/ your acks. Thanks. Signed-off-by: Tejun Heo Cc: Andy Gross Cc: Bjorn Andersson Cc: Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230421025046.4008499-15-tj@kernel.org --- drivers/soc/qcom/qmi_interface.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/qmi_interface.c b/drivers/soc/qcom/qmi_interface.c index 820bdd9f8e46..78d7361fdcf2 100644 --- a/drivers/soc/qcom/qmi_interface.c +++ b/drivers/soc/qcom/qmi_interface.c @@ -650,7 +650,7 @@ int qmi_handle_init(struct qmi_handle *qmi, size_t recv_buf_size, if (!qmi->recv_buf) return -ENOMEM; - qmi->wq = alloc_workqueue("qmi_msg_handler", WQ_UNBOUND, 1); + qmi->wq = alloc_ordered_workqueue("qmi_msg_handler", 0); if (!qmi->wq) { ret = -ENOMEM; goto err_free_recv_buf; -- cgit From 0be4392435a6a0e16b3eb56a8815ebdbcd44e1a7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 20 Apr 2023 19:36:17 +0200 Subject: dt-bindings: soc: qcom: Add RPM Master stats The RPM MSG RAM contains per-RPM-master (e.g. APPS, ADSP etc.) sleep statistics. They let one assess which core is actively preventing the system from entering a true low-power mode. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230405-topic-master_stats-v6-1-2277b4433748@linaro.org --- .../bindings/soc/qcom/qcom,rpm-master-stats.yaml | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml new file mode 100644 index 000000000000..031800985b5e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,rpm-master-stats.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) RPM Master Stats + +maintainers: + - Konrad Dybcio + +description: | + The Qualcomm RPM (Resource Power Manager) architecture includes a concept + of "RPM Masters". They can be thought of as "the local gang leaders", usually + spanning a single subsystem (e.g. APSS, ADSP, CDSP). All of the RPM decisions + (particularly around entering hardware-driven low power modes: XO shutdown + and total system-wide power collapse) are first made at Master-level, and + only then aggregated for the entire system. + + The Master Stats provide a few useful bits that can be used to assess whether + our device has entered the desired low-power mode, how long it took to do so, + the duration of that residence, how long it took to come back online, + how many times a given sleep state was entered and which cores are actively + voting for staying awake. + + This scheme has been used on various SoCs in the 2013-2023 era, with some + newer or higher-end designs providing this information through an SMEM query. + +properties: + compatible: + const: qcom,rpm-master-stats + + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Phandle to an RPM MSG RAM slice containing the master stats + minItems: 1 + maxItems: 5 + + qcom,master-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: + The name of the RPM Master which owns the MSG RAM slice where this + instance of Master Stats resides + minItems: 1 + maxItems: 5 + +required: + - compatible + - qcom,rpm-msg-ram + - qcom,master-names + +additionalProperties: false + +examples: + - | + stats { + compatible = "qcom,rpm-master-stats"; + qcom,rpm-msg-ram = <&apss_master_stats>, + <&mpss_master_stats>, + <&adsp_master_stats>, + <&cdsp_master_stats>, + <&tz_master_stats>; + qcom,master-names = "APSS", + "MPSS", + "ADSP", + "CDSP", + "TZ"; + }; +... -- cgit From a77b2a0b12801a232226d227636236ed89b77043 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 20 Apr 2023 19:36:18 +0200 Subject: soc: qcom: Introduce RPM master stats driver Introduce a driver to query and expose detailed, per-subsystem (as opposed to the existing qcom_stats driver which exposes SoC-wide data) about low power mode states of a given RPM master. That includes the APSS (ARM), MPSS (modem) and other remote cores, depending on the platform configuration. This is a vastly cleaned up and restructured version of a similar driver found in msm-5.4. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230405-topic-master_stats-v6-2-2277b4433748@linaro.org --- drivers/soc/qcom/Kconfig | 11 +++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/rpm_master_stats.c | 163 ++++++++++++++++++++++++++++++++++++ 3 files changed, 175 insertions(+) create mode 100644 drivers/soc/qcom/rpm_master_stats.c diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a491718f8064..e597799e8121 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -135,6 +135,17 @@ config QCOM_RMTFS_MEM Say y here if you intend to boot the modem remoteproc. +config QCOM_RPM_MASTER_STATS + tristate "Qualcomm RPM Master stats" + depends on ARCH_QCOM || COMPILE_TEST + help + The RPM Master sleep stats driver provides detailed per-subsystem + sleep/wake data, read from the RPM message RAM. It can be used to + assess whether all the low-power modes available are entered as + expected or to check which part of the SoC prevents it from sleeping. + + Say y here if you intend to debug or monitor platform sleep. + config QCOM_RPMH tristate "Qualcomm RPM-Hardened (RPMH) Communication" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 0f43a88b4894..7349371fdea1 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_QCOM_QMI_HELPERS) += qmi_helpers.o qmi_helpers-y += qmi_encdec.o qmi_interface.o obj-$(CONFIG_QCOM_RAMP_CTRL) += ramp_controller.o obj-$(CONFIG_QCOM_RMTFS_MEM) += rmtfs_mem.o +obj-$(CONFIG_QCOM_RPM_MASTER_STATS) += rpm_master_stats.o obj-$(CONFIG_QCOM_RPMH) += qcom_rpmh.o qcom_rpmh-y += rpmh-rsc.o qcom_rpmh-y += rpmh.o diff --git a/drivers/soc/qcom/rpm_master_stats.c b/drivers/soc/qcom/rpm_master_stats.c new file mode 100644 index 000000000000..6dd98b9f7129 --- /dev/null +++ b/drivers/soc/qcom/rpm_master_stats.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + * + * This driver supports what is known as "Master Stats v2" in Qualcomm + * downstream kernel terms, which seems to be the only version which has + * ever shipped, all the way from 2013 to 2023. + */ + +#include +#include +#include +#include +#include +#include + +struct master_stats_data { + void __iomem *base; + const char *label; +}; + +struct rpm_master_stats { + u32 active_cores; + u32 num_shutdowns; + u64 shutdown_req; + u64 wakeup_idx; + u64 bringup_req; + u64 bringup_ack; + u32 wakeup_reason; /* 0 = "rude wakeup", 1 = scheduled wakeup */ + u32 last_sleep_trans_dur; + u32 last_wake_trans_dur; + + /* Per-subsystem (*not necessarily* SoC-wide) XO shutdown stats */ + u32 xo_count; + u64 xo_last_enter; + u64 last_exit; + u64 xo_total_dur; +} __packed; + +static int master_stats_show(struct seq_file *s, void *unused) +{ + struct master_stats_data *data = s->private; + struct rpm_master_stats stat; + + memcpy_fromio(&stat, data->base, sizeof(stat)); + + seq_printf(s, "%s:\n", data->label); + + seq_printf(s, "\tLast shutdown @ %llu\n", stat.shutdown_req); + seq_printf(s, "\tLast bringup req @ %llu\n", stat.bringup_req); + seq_printf(s, "\tLast bringup ack @ %llu\n", stat.bringup_ack); + seq_printf(s, "\tLast wakeup idx: %llu\n", stat.wakeup_idx); + seq_printf(s, "\tLast XO shutdown enter @ %llu\n", stat.xo_last_enter); + seq_printf(s, "\tLast XO shutdown exit @ %llu\n", stat.last_exit); + seq_printf(s, "\tXO total duration: %llu\n", stat.xo_total_dur); + seq_printf(s, "\tLast sleep transition duration: %u\n", stat.last_sleep_trans_dur); + seq_printf(s, "\tLast wake transition duration: %u\n", stat.last_wake_trans_dur); + seq_printf(s, "\tXO shutdown count: %u\n", stat.xo_count); + seq_printf(s, "\tWakeup reason: 0x%x\n", stat.wakeup_reason); + seq_printf(s, "\tShutdown count: %u\n", stat.num_shutdowns); + seq_printf(s, "\tActive cores bitmask: 0x%x\n", stat.active_cores); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(master_stats); + +static int master_stats_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct master_stats_data *data; + struct device_node *msgram_np; + struct dentry *dent, *root; + struct resource res; + int count, i, ret; + + count = of_property_count_strings(dev->of_node, "qcom,master-names"); + if (count < 0) + return count; + + data = devm_kzalloc(dev, count * sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + root = debugfs_create_dir("qcom_rpm_master_stats", NULL); + platform_set_drvdata(pdev, root); + + for (i = 0; i < count; i++) { + msgram_np = of_parse_phandle(dev->of_node, "qcom,rpm-msg-ram", i); + if (!msgram_np) { + debugfs_remove_recursive(root); + return dev_err_probe(dev, -ENODEV, + "Couldn't parse MSG RAM phandle idx %d", i); + } + + /* + * Purposefully skip devm_platform helpers as we're using a + * shared resource. + */ + ret = of_address_to_resource(msgram_np, 0, &res); + of_node_put(msgram_np); + if (ret < 0) { + debugfs_remove_recursive(root); + return ret; + } + + data[i].base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(data[i].base)) { + debugfs_remove_recursive(root); + return dev_err_probe(dev, -EINVAL, + "Could not map the MSG RAM slice idx %d!\n", i); + } + + ret = of_property_read_string_index(dev->of_node, "qcom,master-names", i, + &data[i].label); + if (ret < 0) { + debugfs_remove_recursive(root); + return dev_err_probe(dev, ret, + "Could not read name idx %d!\n", i); + } + + /* + * Generally it's not advised to fail on debugfs errors, but this + * driver's only job is exposing data therein. + */ + dent = debugfs_create_file(data[i].label, 0444, root, + &data[i], &master_stats_fops); + if (IS_ERR(dent)) { + debugfs_remove_recursive(root); + return dev_err_probe(dev, PTR_ERR(dent), + "Failed to create debugfs file %s!\n", data[i].label); + } + } + + device_set_pm_not_required(dev); + + return 0; +} + +static void master_stats_remove(struct platform_device *pdev) +{ + struct dentry *root = platform_get_drvdata(pdev); + + debugfs_remove_recursive(root); +} + +static const struct of_device_id rpm_master_table[] = { + { .compatible = "qcom,rpm-master-stats" }, + { }, +}; + +static struct platform_driver master_stats_driver = { + .probe = master_stats_probe, + .remove_new = master_stats_remove, + .driver = { + .name = "qcom_rpm_master_stats", + .of_match_table = rpm_master_table, + }, +}; +module_platform_driver(master_stats_driver); + +MODULE_DESCRIPTION("Qualcomm RPM Master Statistics driver"); +MODULE_LICENSE("GPL"); -- cgit From e5b03cd101bd3dbbc7cbbe4c6e55a37070386494 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sat, 29 Apr 2023 21:33:35 +0200 Subject: dt-bindings: arm: qcom,ids: Add IDs for IPQ5018 family Add SOC IDs for the IPQ5018 family. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230429193336.600629-1-robimarko@gmail.com --- include/dt-bindings/arm/qcom,ids.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 802495b20276..c1283bad81e1 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -216,6 +216,9 @@ #define QCOM_ID_SM8350 439 #define QCOM_ID_QCM2290 441 #define QCOM_ID_SM6115 444 +#define QCOM_ID_IPQ5010 446 +#define QCOM_ID_IPQ5018 447 +#define QCOM_ID_IPQ5028 448 #define QCOM_ID_SC8280XP 449 #define QCOM_ID_IPQ6005 453 #define QCOM_ID_QRB5165 455 @@ -229,6 +232,9 @@ #define QCOM_ID_SM8450_3 482 #define QCOM_ID_SC7280 487 #define QCOM_ID_SC7180P 495 +#define QCOM_ID_IPQ5000 503 +#define QCOM_ID_IPQ0509 504 +#define QCOM_ID_IPQ0518 505 #define QCOM_ID_SM6375 507 #define QCOM_ID_IPQ9514 510 #define QCOM_ID_IPQ9550 511 @@ -236,6 +242,7 @@ #define QCOM_ID_IPQ9570 513 #define QCOM_ID_IPQ9574 514 #define QCOM_ID_SM8550 519 +#define QCOM_ID_IPQ5016 520 #define QCOM_ID_IPQ9510 521 #define QCOM_ID_QRB4210 523 #define QCOM_ID_QRB2210 524 @@ -243,6 +250,7 @@ #define QCOM_ID_QRU1000 539 #define QCOM_ID_QDU1000 545 #define QCOM_ID_QDU1010 587 +#define QCOM_ID_IPQ5019 569 #define QCOM_ID_QRU1032 588 #define QCOM_ID_QRU1052 589 #define QCOM_ID_QRU1062 590 -- cgit From 0369a5906e46a2431a8fe04aa79cba6583e53e73 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sat, 29 Apr 2023 21:33:36 +0200 Subject: soc: qcom: socinfo: Add IDs for IPQ5018 family Add SOC IDs for the IPQ5018 family. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230429193336.600629-2-robimarko@gmail.com --- drivers/soc/qcom/socinfo.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index c2e4a57dd666..c61a93b4dcaf 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -434,6 +434,9 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SM8350) }, { qcom_board_id(QCM2290) }, { qcom_board_id(SM6115) }, + { qcom_board_id(IPQ5010) }, + { qcom_board_id(IPQ5018) }, + { qcom_board_id(IPQ5028) }, { qcom_board_id(SC8280XP) }, { qcom_board_id(IPQ6005) }, { qcom_board_id(QRB5165) }, @@ -447,6 +450,9 @@ static const struct soc_id soc_id[] = { { qcom_board_id_named(SM8450_3, "SM8450") }, { qcom_board_id(SC7280) }, { qcom_board_id(SC7180P) }, + { qcom_board_id(IPQ5000) }, + { qcom_board_id(IPQ0509) }, + { qcom_board_id(IPQ0518) }, { qcom_board_id(SM6375) }, { qcom_board_id(IPQ9514) }, { qcom_board_id(IPQ9550) }, @@ -454,6 +460,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(IPQ9570) }, { qcom_board_id(IPQ9574) }, { qcom_board_id(SM8550) }, + { qcom_board_id(IPQ5016) }, { qcom_board_id(IPQ9510) }, { qcom_board_id(QRB4210) }, { qcom_board_id(QRB2210) }, @@ -461,6 +468,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QRU1000) }, { qcom_board_id(QDU1000) }, { qcom_board_id(QDU1010) }, + { qcom_board_id(IPQ5019) }, { qcom_board_id(QRU1032) }, { qcom_board_id(QRU1052) }, { qcom_board_id(QRU1062) }, -- cgit From fe78d73a914d86070ac15c9a6d1f885ce5bc4a69 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 9 May 2023 09:05:30 +0530 Subject: dt-bindings: arm: qcom,ids: add SoC ID for IPQ5312 and IPQ5302 Add the SoC ID for IPQ5312 and IPQ5302, which belong to the family of IPQ5332 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230509033531.21468-2-quic_kathirav@quicinc.com --- include/dt-bindings/arm/qcom,ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index c1283bad81e1..69c2d8fa79f4 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -256,6 +256,8 @@ #define QCOM_ID_QRU1062 590 #define QCOM_ID_IPQ5332 592 #define QCOM_ID_IPQ5322 593 +#define QCOM_ID_IPQ5312 594 +#define QCOM_ID_IPQ5302 595 /* * The board type and revision information, used by Qualcomm bootloaders and -- cgit From 7f6e0028a0ca4317aeb070084e72d44ca39ace7e Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 9 May 2023 09:05:31 +0530 Subject: soc: qcom: socinfo: Add Soc ID for IPQ5312 and IPQ5302 Add the SoC ID for IPQ5312 and IPQ5302, which belong to the family of IPQ5332 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230509033531.21468-3-quic_kathirav@quicinc.com --- drivers/soc/qcom/socinfo.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index c61a93b4dcaf..0decf0a08468 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -474,6 +474,8 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QRU1062) }, { qcom_board_id(IPQ5332) }, { qcom_board_id(IPQ5322) }, + { qcom_board_id(IPQ5312) }, + { qcom_board_id(IPQ5302) }, }; static const char *socinfo_machine(struct device *dev, unsigned int id) -- cgit From 13ac2620f0c0ee7f463a486baf5a56ab9d8b7fdb Mon Sep 17 00:00:00 2001 From: Matti Lehtimäki Date: Sat, 20 May 2023 15:19:30 +0300 Subject: dt-bindings: sram: qcom,imem: Document MSM8226 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add compatible for MSM8226 IMEM. Signed-off-by: Matti Lehtimäki Acked-by: Conor Dooley Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230520121933.15533-2-matti.lehtimaki@gmail.com --- Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index 0548e8e0d30b..d9599ee51204 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - qcom,apq8064-imem + - qcom,msm8226-imem - qcom,msm8974-imem - qcom,qcs404-imem - qcom,sc7180-imem -- cgit From 2e43c85b0d96c6ae2ab60132313bb7a814bcfb44 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 22 May 2023 23:23:39 +0200 Subject: MAINTAINERS: Add Konrad Dybcio as linux-arm-msm co-maintainer As discussed with Bjorn Andersson in private, step up to co-maintainership. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230522-topic-maintainers-v1-1-2b91eb8e4f65@linaro.org --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e..332db39d3ca8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2572,7 +2572,7 @@ N: oxnas ARM/QUALCOMM SUPPORT M: Andy Gross M: Bjorn Andersson -R: Konrad Dybcio +M: Konrad Dybcio L: linux-arm-msm@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git -- cgit From db967cf828fc134ba17c5e4539b1a3687cdd3f2d Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 16 May 2023 22:12:12 +0200 Subject: arm-cci: add cci_enable_port_for_self prototype The cci_enable_port_for_self() is called from assembler, so add the prototype only to shut up the W=1 warning: drivers/bus/arm-cci.c:298:25: error: no previous prototype for 'cci_enable_port_for_self' [-Werror=missing-prototypes] Link: https://lore.kernel.org/r/20230516201218.556437-1-arnd@kernel.org Signed-off-by: Arnd Bergmann --- include/linux/arm-cci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/arm-cci.h b/include/linux/arm-cci.h index d0e44201d855..7f7a576267bc 100644 --- a/include/linux/arm-cci.h +++ b/include/linux/arm-cci.h @@ -43,6 +43,8 @@ static inline int __cci_control_port_by_index(u32 port, bool enable) } #endif +void cci_enable_port_for_self(void); + #define cci_disable_port_by_device(dev) \ __cci_control_port_by_device(dev, false) #define cci_enable_port_by_device(dev) \ -- cgit From bcb889891371c3cf767f2b9e8768cfe2fdd3810f Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 26 May 2023 13:55:11 +0200 Subject: soc: qcom: mdt_loader: Fix unconditional call to scm_pas_mem_setup Commit ebeb20a9cd3f ("soc: qcom: mdt_loader: Always invoke PAS mem_setup") dropped the relocate check and made pas_mem_setup run unconditionally. The code was later moved with commit f4e526ff7e38 ("soc: qcom: mdt_loader: Extract PAS operations") to qcom_mdt_pas_init() effectively losing track of what was actually done. The assumption that PAS mem_setup can be done anytime was effectively wrong, with no good reason and this caused regression on some SoC that use remoteproc to bringup ath11k. One example is IPQ8074 SoC that effectively broke resulting in remoteproc silently die and ath11k not working. On this SoC FW relocate is not enabled and PAS mem_setup was correctly skipped in previous kernel version resulting in correct bringup and function of remoteproc and ath11k. To fix the regression, reintroduce the relocate check in qcom_mdt_pas_init() and correctly skip PAS mem_setup where relocate is not enabled. Fixes: ebeb20a9cd3f ("soc: qcom: mdt_loader: Always invoke PAS mem_setup") Tested-by: Robert Marko Co-developed-by: Robert Marko Signed-off-by: Robert Marko Signed-off-by: Christian Marangi Cc: stable@vger.kernel.org Reviewed-by: Mukesh Ojha Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526115511.3328-1-ansuelsmth@gmail.com --- drivers/soc/qcom/mdt_loader.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index 892b1648d693..9418993a3a92 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -210,6 +210,7 @@ int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, const struct elf32_hdr *ehdr; phys_addr_t min_addr = PHYS_ADDR_MAX; phys_addr_t max_addr = 0; + bool relocate = false; size_t metadata_len; void *metadata; int ret; @@ -224,6 +225,9 @@ int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, if (!mdt_phdr_valid(phdr)) continue; + if (phdr->p_flags & QCOM_MDT_RELOCATABLE) + relocate = true; + if (phdr->p_paddr < min_addr) min_addr = phdr->p_paddr; @@ -246,11 +250,13 @@ int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, goto out; } - ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); - if (ret) { - /* Unable to set up relocation */ - dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name); - goto out; + if (relocate) { + ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); + if (ret) { + /* Unable to set up relocation */ + dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name); + goto out; + } } out: -- cgit From ec001bb71e4476f7f5be9db693d5f43e65b9d8cb Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 26 May 2023 22:47:58 +0200 Subject: soc: qcom: socinfo: move SMEM item struct and defines to a header Move SMEM item struct and related defines to a header in order to be able to reuse them in the SMEM driver instead of duplicating them. Signed-off-by: Robert Marko Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526204802.3081168-1-robimarko@gmail.com --- drivers/soc/qcom/socinfo.c | 67 +------------------------------------- include/linux/soc/qcom/socinfo.h | 70 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+), 66 deletions(-) create mode 100644 include/linux/soc/qcom/socinfo.h diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 0decf0a08468..dfd4330daef5 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -32,15 +33,6 @@ #define qcom_board_id(id) QCOM_ID_ ## id, __stringify(id) #define qcom_board_id_named(id, name) QCOM_ID_ ## id, (name) -#define SMEM_SOCINFO_BUILD_ID_LENGTH 32 -#define SMEM_SOCINFO_CHIP_ID_LENGTH 32 - -/* - * SMEM item id, used to acquire handles to respective - * SMEM region. - */ -#define SMEM_HW_SW_BUILD_ID 137 - #ifdef CONFIG_DEBUG_FS #define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32 #define SMEM_IMAGE_VERSION_SIZE 4096 @@ -126,64 +118,7 @@ static const char *const pmic_models[] = { [58] = "PM8450", [65] = "PM8010", }; -#endif /* CONFIG_DEBUG_FS */ - -/* Socinfo SMEM item structure */ -struct socinfo { - __le32 fmt; - __le32 id; - __le32 ver; - char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH]; - /* Version 2 */ - __le32 raw_id; - __le32 raw_ver; - /* Version 3 */ - __le32 hw_plat; - /* Version 4 */ - __le32 plat_ver; - /* Version 5 */ - __le32 accessory_chip; - /* Version 6 */ - __le32 hw_plat_subtype; - /* Version 7 */ - __le32 pmic_model; - __le32 pmic_die_rev; - /* Version 8 */ - __le32 pmic_model_1; - __le32 pmic_die_rev_1; - __le32 pmic_model_2; - __le32 pmic_die_rev_2; - /* Version 9 */ - __le32 foundry_id; - /* Version 10 */ - __le32 serial_num; - /* Version 11 */ - __le32 num_pmics; - __le32 pmic_array_offset; - /* Version 12 */ - __le32 chip_family; - __le32 raw_device_family; - __le32 raw_device_num; - /* Version 13 */ - __le32 nproduct_id; - char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH]; - /* Version 14 */ - __le32 num_clusters; - __le32 ncluster_array_offset; - __le32 num_defective_parts; - __le32 ndefective_parts_array_offset; - /* Version 15 */ - __le32 nmodem_supported; - /* Version 16 */ - __le32 feature_code; - __le32 pcode; - __le32 npartnamemap_offset; - __le32 nnum_partname_mapping; - /* Version 17 */ - __le32 oem_variant; -}; -#ifdef CONFIG_DEBUG_FS struct socinfo_params { u32 raw_device_family; u32 hw_plat_subtype; diff --git a/include/linux/soc/qcom/socinfo.h b/include/linux/soc/qcom/socinfo.h new file mode 100644 index 000000000000..d1cbc49a2a2d --- /dev/null +++ b/include/linux/soc/qcom/socinfo.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __QCOM_SOCINFO_H__ +#define __QCOM_SOCINFO_H__ + +/* + * SMEM item id, used to acquire handles to respective + * SMEM region. + */ +#define SMEM_HW_SW_BUILD_ID 137 + +#define SMEM_SOCINFO_BUILD_ID_LENGTH 32 +#define SMEM_SOCINFO_CHIP_ID_LENGTH 32 + +/* Socinfo SMEM item structure */ +struct socinfo { + __le32 fmt; + __le32 id; + __le32 ver; + char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH]; + /* Version 2 */ + __le32 raw_id; + __le32 raw_ver; + /* Version 3 */ + __le32 hw_plat; + /* Version 4 */ + __le32 plat_ver; + /* Version 5 */ + __le32 accessory_chip; + /* Version 6 */ + __le32 hw_plat_subtype; + /* Version 7 */ + __le32 pmic_model; + __le32 pmic_die_rev; + /* Version 8 */ + __le32 pmic_model_1; + __le32 pmic_die_rev_1; + __le32 pmic_model_2; + __le32 pmic_die_rev_2; + /* Version 9 */ + __le32 foundry_id; + /* Version 10 */ + __le32 serial_num; + /* Version 11 */ + __le32 num_pmics; + __le32 pmic_array_offset; + /* Version 12 */ + __le32 chip_family; + __le32 raw_device_family; + __le32 raw_device_num; + /* Version 13 */ + __le32 nproduct_id; + char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH]; + /* Version 14 */ + __le32 num_clusters; + __le32 ncluster_array_offset; + __le32 num_defective_parts; + __le32 ndefective_parts_array_offset; + /* Version 15 */ + __le32 nmodem_supported; + /* Version 16 */ + __le32 feature_code; + __le32 pcode; + __le32 npartnamemap_offset; + __le32 nnum_partname_mapping; + /* Version 17 */ + __le32 oem_variant; +}; + +#endif -- cgit From 10615007483b6938da9df290fe5bf460f6a07c60 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 26 May 2023 22:47:59 +0200 Subject: soc: qcom: smem: Switch to EXPORT_SYMBOL_GPL() SMEM has been GPL licensed from the start, and there is no reason to use EXPORT_SYMBOL() so switch to the GPL version. Signed-off-by: Robert Marko Reviewed-by: Konrad Dybcio Reviewed-by: Trilok Soni Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526204802.3081168-2-robimarko@gmail.com --- drivers/soc/qcom/smem.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 6be7ea93c78c..bc98520c4969 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -500,7 +500,7 @@ int qcom_smem_alloc(unsigned host, unsigned item, size_t size) return ret; } -EXPORT_SYMBOL(qcom_smem_alloc); +EXPORT_SYMBOL_GPL(qcom_smem_alloc); static void *qcom_smem_get_global(struct qcom_smem *smem, unsigned item, @@ -674,7 +674,7 @@ void *qcom_smem_get(unsigned host, unsigned item, size_t *size) return ptr; } -EXPORT_SYMBOL(qcom_smem_get); +EXPORT_SYMBOL_GPL(qcom_smem_get); /** * qcom_smem_get_free_space() - retrieve amount of free space in a partition @@ -719,7 +719,7 @@ int qcom_smem_get_free_space(unsigned host) return ret; } -EXPORT_SYMBOL(qcom_smem_get_free_space); +EXPORT_SYMBOL_GPL(qcom_smem_get_free_space); static bool addr_in_range(void __iomem *base, size_t size, void *addr) { @@ -770,7 +770,7 @@ phys_addr_t qcom_smem_virt_to_phys(void *p) return 0; } -EXPORT_SYMBOL(qcom_smem_virt_to_phys); +EXPORT_SYMBOL_GPL(qcom_smem_virt_to_phys); static int qcom_smem_get_sbl_version(struct qcom_smem *smem) { -- cgit From 17051d2c3cd696439adb900e9af547ba162fb982 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 26 May 2023 22:48:00 +0200 Subject: soc: qcom: smem: introduce qcom_smem_get_soc_id() Introduce a helper to return the SoC SMEM ID, which is used to identify the exact SoC model as there may be differences in the same SoC family. Currently, cpufreq-nvmem does this completely in the driver and there has been more interest expresed for other drivers to use this information so lets expose a common helper to prevent redoing it in individual drivers since this field is present on every SMEM table version. Signed-off-by: Robert Marko Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526204802.3081168-3-robimarko@gmail.com --- drivers/soc/qcom/smem.c | 23 +++++++++++++++++++++++ include/linux/soc/qcom/smem.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index bc98520c4969..b0d59e815c3b 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -14,6 +14,7 @@ #include #include #include +#include /* * The Qualcomm shared memory system is a allocate only heap structure that @@ -772,6 +773,28 @@ phys_addr_t qcom_smem_virt_to_phys(void *p) } EXPORT_SYMBOL_GPL(qcom_smem_virt_to_phys); +/** + * qcom_smem_get_soc_id() - return the SoC ID + * @id: On success, we return the SoC ID here. + * + * Look up SoC ID from HW/SW build ID and return it. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_smem_get_soc_id(u32 *id) +{ + struct socinfo *info; + + info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL); + if (IS_ERR(info)) + return PTR_ERR(info); + + *id = __le32_to_cpu(info->id); + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_smem_get_soc_id); + static int qcom_smem_get_sbl_version(struct qcom_smem *smem) { struct smem_header *header; diff --git a/include/linux/soc/qcom/smem.h b/include/linux/soc/qcom/smem.h index 86e1b358688a..223db6a9c733 100644 --- a/include/linux/soc/qcom/smem.h +++ b/include/linux/soc/qcom/smem.h @@ -11,4 +11,6 @@ int qcom_smem_get_free_space(unsigned host); phys_addr_t qcom_smem_virt_to_phys(void *p); +int qcom_smem_get_soc_id(u32 *id); + #endif -- cgit From 865d7e719262e9845a3c847040fbd4d84c8b5bd9 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 26 May 2023 22:48:01 +0200 Subject: cpufreq: qcom-nvmem: use SoC ID-s from bindings SMEM SoC ID-s are now stored in DT bindings so lets use those instead of defining them in the driver again. Signed-off-by: Robert Marko Reviewed-by: Konrad Dybcio Reviewed-by: Bjorn Andersson Acked-by: Viresh Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526204802.3081168-4-robimarko@gmail.com --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index a577586b23be..60e99be2d3db 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -31,12 +31,7 @@ #define MSM_ID_SMEM 137 -enum _msm_id { - MSM8996V3 = 0xF6ul, - APQ8096V3 = 0x123ul, - MSM8996SG = 0x131ul, - APQ8096SG = 0x138ul, -}; +#include enum _msm8996_version { MSM8996_V3, @@ -154,12 +149,12 @@ static enum _msm8996_version qcom_cpufreq_get_msm_id(void) msm_id++; switch ((enum _msm_id)*msm_id) { - case MSM8996V3: - case APQ8096V3: + case QCOM_ID_MSM8996: + case QCOM_ID_APQ8096: version = MSM8996_V3; break; - case MSM8996SG: - case APQ8096SG: + case QCOM_ID_MSM8996SG: + case QCOM_ID_APQ8096SG: version = MSM8996_SG; break; default: -- cgit From 7d0f03d104e576da2a7689d0eb8560c67efc03ff Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 26 May 2023 22:48:02 +0200 Subject: cpufreq: qcom-nvmem: use helper to get SMEM SoC ID Now that SMEM exports a helper to get the SMEM SoC ID lets utilize it. Currently qcom_cpufreq_get_msm_id() is encoding the returned SMEM SoC ID into an enum, however there is no reason to do so and we can just match directly on the SMEM SoC ID as returned by qcom_smem_get_soc_id(). Signed-off-by: Robert Marko Acked-by: Viresh Kumar Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230526204802.3081168-5-robimarko@gmail.com --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 56 +++++++----------------------------- 1 file changed, 10 insertions(+), 46 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 60e99be2d3db..a88b6fe5db50 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -29,16 +29,8 @@ #include #include -#define MSM_ID_SMEM 137 - #include -enum _msm8996_version { - MSM8996_V3, - MSM8996_SG, - NUM_OF_MSM8996_VERSIONS, -}; - struct qcom_cpufreq_drv; struct qcom_cpufreq_match_data { @@ -135,60 +127,32 @@ static void get_krait_bin_format_b(struct device *cpu_dev, dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver); } -static enum _msm8996_version qcom_cpufreq_get_msm_id(void) -{ - size_t len; - u32 *msm_id; - enum _msm8996_version version; - - msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len); - if (IS_ERR(msm_id)) - return NUM_OF_MSM8996_VERSIONS; - - /* The first 4 bytes are format, next to them is the actual msm-id */ - msm_id++; - - switch ((enum _msm_id)*msm_id) { - case QCOM_ID_MSM8996: - case QCOM_ID_APQ8096: - version = MSM8996_V3; - break; - case QCOM_ID_MSM8996SG: - case QCOM_ID_APQ8096SG: - version = MSM8996_SG; - break; - default: - version = NUM_OF_MSM8996_VERSIONS; - } - - return version; -} - static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, struct nvmem_cell *speedbin_nvmem, char **pvs_name, struct qcom_cpufreq_drv *drv) { size_t len; + u32 msm_id; u8 *speedbin; - enum _msm8996_version msm8996_version; + int ret; *pvs_name = NULL; - msm8996_version = qcom_cpufreq_get_msm_id(); - if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { - dev_err(cpu_dev, "Not Snapdragon 820/821!"); - return -ENODEV; - } + ret = qcom_smem_get_soc_id(&msm_id); + if (ret) + return ret; speedbin = nvmem_cell_read(speedbin_nvmem, &len); if (IS_ERR(speedbin)) return PTR_ERR(speedbin); - switch (msm8996_version) { - case MSM8996_V3: + switch (msm_id) { + case QCOM_ID_MSM8996: + case QCOM_ID_APQ8096: drv->versions = 1 << (unsigned int)(*speedbin); break; - case MSM8996_SG: + case QCOM_ID_MSM8996SG: + case QCOM_ID_APQ8096SG: drv->versions = 1 << ((unsigned int)(*speedbin) + 4); break; default: -- cgit From e829f1fc942f0190d169636f4a33f85cc4509fbd Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 15:12:11 +0200 Subject: dt-bindings: soc: mediatek: pwrap: Add compatible for MT6795 Helio X10 Add a compatible for the PMIC Wrapper found on the MT6795 Helio X10 SoC. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230412131216.198313-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml index 3fefd634bc69..a06ac2177444 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt2701-pwrap - mediatek,mt6765-pwrap - mediatek,mt6779-pwrap + - mediatek,mt6795-pwrap - mediatek,mt6797-pwrap - mediatek,mt6873-pwrap - mediatek,mt7622-pwrap -- cgit From db9f132122afe5b2a7bb9ba132b9e562b9ca1aef Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 15:12:12 +0200 Subject: soc: mediatek: pwrap: Move PMIC read test sequence in function The PMIC read test is performed in two places: pwrap_init_dual_io() and pwrap_init_sidly(). In preparation for adding support for PMICs requiring a companion part, move this sequence to a new function pwrap_pmic_read_test(). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230412131216.198313-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pmic-wrap.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 15789a03e6c6..5c500be48f7c 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -1455,6 +1455,18 @@ static int pwrap_regmap_write(void *context, u32 adr, u32 wdata) return pwrap_write(context, adr, wdata); } +static bool pwrap_pmic_read_test(struct pmic_wrapper *wrp, const u32 *dew_regs, + u16 read_test_val) +{ + bool is_success; + u32 rdata; + + pwrap_read(wrp, dew_regs[PWRAP_DEW_READ_TEST], &rdata); + is_success = ((rdata & U16_MAX) == read_test_val); + + return is_success; +} + static int pwrap_reset_spislave(struct pmic_wrapper *wrp) { bool tmp; @@ -1498,18 +1510,18 @@ static int pwrap_reset_spislave(struct pmic_wrapper *wrp) */ static int pwrap_init_sidly(struct pmic_wrapper *wrp) { - u32 rdata; u32 i; u32 pass = 0; + bool read_ok; signed char dly[16] = { -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1 }; for (i = 0; i < 4; i++) { pwrap_writel(wrp, i, PWRAP_SIDLY); - pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], - &rdata); - if (rdata == PWRAP_DEW_READ_TEST_VAL) { + read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, + PWRAP_DEW_READ_TEST_VAL); + if (read_ok) { dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i); pass |= 1 << i; } @@ -1529,8 +1541,7 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp) static int pwrap_init_dual_io(struct pmic_wrapper *wrp) { int ret; - bool tmp; - u32 rdata; + bool read_ok, tmp; /* Enable dual IO mode */ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); @@ -1546,12 +1557,9 @@ static int pwrap_init_dual_io(struct pmic_wrapper *wrp) pwrap_writel(wrp, 1, PWRAP_DIO_EN); /* Read Test */ - pwrap_read(wrp, - wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); - if (rdata != PWRAP_DEW_READ_TEST_VAL) { - dev_err(wrp->dev, - "Read failed on DIO mode: 0x%04x!=0x%04x\n", - PWRAP_DEW_READ_TEST_VAL, rdata); + read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_READ_TEST_VAL); + if (!read_ok) { + dev_err(wrp->dev, "Read failed on DIO mode.\n"); return -EFAULT; } -- cgit From 2eb27302346520908f89ee4db80fdba12c686278 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 15:12:13 +0200 Subject: soc: mediatek: pwrap: Add kerneldoc for struct pwrap_slv_type In preparation for adding new members with name abbreviations describe the struct pwrap_slv_type with kerneldoc to enhance human readability. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230412131216.198313-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pmic-wrap.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 5c500be48f7c..a33a1b1820cb 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -1218,11 +1218,17 @@ struct pwrap_slv_regops { int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata); }; +/** + * struct pwrap_slv_type - PMIC device wrapper definitions + * @dew_regs: Device Wrapper (DeW) register offsets + * @type: PMIC Type (model) + * @regops: Register R/W ops + * @caps: Capability flags for the target device + */ struct pwrap_slv_type { const u32 *dew_regs; enum pmic_type type; const struct pwrap_slv_regops *regops; - /* Flags indicating the capability for the target slave */ u32 caps; }; -- cgit From 41ae95aaa0d7576a5be1d9fd9225beafc179e019 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 15:12:14 +0200 Subject: soc: mediatek: mtk-pmic-wrap: Add support for companion PMICs Some PMICs are designed to work with a companion part, which provides more regulators and/or companion devices such as LED controllers, display backlight controllers, battery charging, fuel gauge, etc: this kind of PMICs are usually present in smartphone platforms, where tight integration is required. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230412131216.198313-5-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pmic-wrap.c | 73 +++++++++++++++++++++++++++++------- 1 file changed, 59 insertions(+), 14 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index a33a1b1820cb..366e40b802e4 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -47,6 +47,7 @@ /* macro for device wrapper default value */ #define PWRAP_DEW_READ_TEST_VAL 0x5aa5 +#define PWRAP_DEW_COMP_READ_TEST_VAL 0xa55a #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a /* macro for manual command */ @@ -1222,12 +1223,16 @@ struct pwrap_slv_regops { * struct pwrap_slv_type - PMIC device wrapper definitions * @dew_regs: Device Wrapper (DeW) register offsets * @type: PMIC Type (model) + * @comp_dew_regs: Device Wrapper (DeW) register offsets for companion device + * @comp_type: Companion PMIC Type (model) * @regops: Register R/W ops * @caps: Capability flags for the target device */ struct pwrap_slv_type { const u32 *dew_regs; enum pmic_type type; + const u32 *comp_dew_regs; + enum pmic_type comp_type; const struct pwrap_slv_regops *regops; u32 caps; }; @@ -1548,9 +1553,12 @@ static int pwrap_init_dual_io(struct pmic_wrapper *wrp) { int ret; bool read_ok, tmp; + bool comp_read_ok = true; /* Enable dual IO mode */ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); + if (wrp->slave->comp_dew_regs) + pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_DIO_EN], 1); /* Check IDLE & INIT_DONE in advance */ ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp, @@ -1564,8 +1572,14 @@ static int pwrap_init_dual_io(struct pmic_wrapper *wrp) /* Read Test */ read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_READ_TEST_VAL); - if (!read_ok) { - dev_err(wrp->dev, "Read failed on DIO mode.\n"); + if (wrp->slave->comp_dew_regs) + comp_read_ok = pwrap_pmic_read_test(wrp, wrp->slave->comp_dew_regs, + PWRAP_DEW_COMP_READ_TEST_VAL); + if (!read_ok || !comp_read_ok) { + dev_err(wrp->dev, "Read failed on DIO mode. Main PMIC %s%s\n", + !read_ok ? "fail" : "success", + wrp->slave->comp_dew_regs && !comp_read_ok ? + ", Companion PMIC fail" : ""); return -EFAULT; } @@ -1640,19 +1654,41 @@ static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp) return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1; } -static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) +static bool __pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp, const u32 *dew_regs) { u32 rdata; int ret; - ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY], - &rdata); + ret = pwrap_read(wrp, dew_regs[PWRAP_DEW_CIPHER_RDY], &rdata); if (ret) return false; return rdata == 1; } + +static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) +{ + bool ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->dew_regs); + + if (!ret) + return ret; + + /* If there's any companion, wait for it to be ready too */ + if (wrp->slave->comp_dew_regs) + ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->comp_dew_regs); + + return ret; +} + +static void pwrap_config_cipher(struct pmic_wrapper *wrp, const u32 *dew_regs) +{ + pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1); + pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0); + pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1); + pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2); +} + static int pwrap_init_cipher(struct pmic_wrapper *wrp) { int ret; @@ -1689,10 +1725,11 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) } /* Config cipher mode @PMIC */ - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1); - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0); - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1); - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2); + pwrap_config_cipher(wrp, wrp->slave->dew_regs); + + /* If there is any companion PMIC, configure cipher mode there too */ + if (wrp->slave->comp_type > 0) + pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs); switch (wrp->slave->type) { case PMIC_MT6397: @@ -1754,6 +1791,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) static int pwrap_init_security(struct pmic_wrapper *wrp) { + u32 crc_val; int ret; /* Enable encryption */ @@ -1762,14 +1800,21 @@ static int pwrap_init_security(struct pmic_wrapper *wrp) return ret; /* Signature checking - using CRC */ - if (pwrap_write(wrp, - wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1)) - return -EFAULT; + ret = pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1); + if (ret == 0 && wrp->slave->comp_dew_regs) + ret = pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_EN], 0x1); pwrap_writel(wrp, 0x1, PWRAP_CRC_EN); pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE); - pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL], - PWRAP_SIG_ADR); + + /* CRC value */ + crc_val = wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL]; + if (wrp->slave->comp_dew_regs) + crc_val |= wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_VAL] << 16; + + pwrap_writel(wrp, crc_val, PWRAP_SIG_ADR); + + /* PMIC Wrapper Arbiter priority */ pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); -- cgit From 10f5c409a81a327743f15441f7fed3975e7a5a0f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 15:12:15 +0200 Subject: soc: mediatek: mtk-pmic-wrap: Add support for MT6331 w/ MT6332 companion Add support for the MT6331 PMIC and for its companion MT6332 PMIC. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230412131216.198313-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pmic-wrap.c | 47 ++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 366e40b802e4..ceeac43f7bd1 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -170,6 +170,40 @@ static const u32 mt6323_regs[] = { [PWRAP_DEW_RDDMY_NO] = 0x01a4, }; +static const u32 mt6331_regs[] = { + [PWRAP_DEW_DIO_EN] = 0x018c, + [PWRAP_DEW_READ_TEST] = 0x018e, + [PWRAP_DEW_WRITE_TEST] = 0x0190, + [PWRAP_DEW_CRC_SWRST] = 0x0192, + [PWRAP_DEW_CRC_EN] = 0x0194, + [PWRAP_DEW_CRC_VAL] = 0x0196, + [PWRAP_DEW_MON_GRP_SEL] = 0x0198, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x019a, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x019c, + [PWRAP_DEW_CIPHER_EN] = 0x019e, + [PWRAP_DEW_CIPHER_RDY] = 0x01a0, + [PWRAP_DEW_CIPHER_MODE] = 0x01a2, + [PWRAP_DEW_CIPHER_SWRST] = 0x01a4, + [PWRAP_DEW_RDDMY_NO] = 0x01a6, +}; + +static const u32 mt6332_regs[] = { + [PWRAP_DEW_DIO_EN] = 0x80f6, + [PWRAP_DEW_READ_TEST] = 0x80f8, + [PWRAP_DEW_WRITE_TEST] = 0x80fa, + [PWRAP_DEW_CRC_SWRST] = 0x80fc, + [PWRAP_DEW_CRC_EN] = 0x80fe, + [PWRAP_DEW_CRC_VAL] = 0x8100, + [PWRAP_DEW_MON_GRP_SEL] = 0x8102, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x8104, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x8106, + [PWRAP_DEW_CIPHER_EN] = 0x8108, + [PWRAP_DEW_CIPHER_RDY] = 0x810a, + [PWRAP_DEW_CIPHER_MODE] = 0x810c, + [PWRAP_DEW_CIPHER_SWRST] = 0x810e, + [PWRAP_DEW_RDDMY_NO] = 0x8110, +}; + static const u32 mt6351_regs[] = { [PWRAP_DEW_DIO_EN] = 0x02F2, [PWRAP_DEW_READ_TEST] = 0x02F4, @@ -1182,6 +1216,8 @@ static int mt8186_regs[] = { enum pmic_type { PMIC_MT6323, + PMIC_MT6331, + PMIC_MT6332, PMIC_MT6351, PMIC_MT6357, PMIC_MT6358, @@ -2041,6 +2077,16 @@ static const struct pwrap_slv_type pmic_mt6323 = { PWRAP_SLV_CAP_SECURITY, }; +static const struct pwrap_slv_type pmic_mt6331 = { + .dew_regs = mt6331_regs, + .type = PMIC_MT6331, + .comp_dew_regs = mt6332_regs, + .comp_type = PMIC_MT6332, + .regops = &pwrap_regops16, + .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | + PWRAP_SLV_CAP_SECURITY, +}; + static const struct pwrap_slv_type pmic_mt6351 = { .dew_regs = mt6351_regs, .type = PMIC_MT6351, @@ -2086,6 +2132,7 @@ static const struct pwrap_slv_type pmic_mt6397 = { static const struct of_device_id of_slave_match_tbl[] = { { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 }, + { .compatible = "mediatek,mt6331", .data = &pmic_mt6331 }, { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 }, { .compatible = "mediatek,mt6357", .data = &pmic_mt6357 }, { .compatible = "mediatek,mt6358", .data = &pmic_mt6358 }, -- cgit From b7f61f9c7ec402633c10f6456415cab04d3838d5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 15:12:16 +0200 Subject: soc: mediatek: pwrap: Add support for MT6795 Helio X10 Add the necessary bits to support the MT6795 Helio X10 smartphone SoC: this is always paired with a MT6331 PMIC, with MT6332 companion. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230412131216.198313-7-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pmic-wrap.c | 136 ++++++++++++++++++++++++++++++++++- 1 file changed, 135 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index ceeac43f7bd1..11095b8de71a 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -639,6 +639,91 @@ static int mt6779_regs[] = { [PWRAP_WACS2_VLDCLR] = 0xC28, }; +static int mt6795_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_SIDLY] = 0xc, + [PWRAP_RDDMY] = 0x10, + [PWRAP_SI_CK_CON] = 0x14, + [PWRAP_CSHEXT_WRITE] = 0x18, + [PWRAP_CSHEXT_READ] = 0x1c, + [PWRAP_CSLEXT_START] = 0x20, + [PWRAP_CSLEXT_END] = 0x24, + [PWRAP_STAUPD_PRD] = 0x28, + [PWRAP_STAUPD_GRPEN] = 0x2c, + [PWRAP_EINT_STA0_ADR] = 0x30, + [PWRAP_EINT_STA1_ADR] = 0x34, + [PWRAP_STAUPD_MAN_TRIG] = 0x40, + [PWRAP_STAUPD_STA] = 0x44, + [PWRAP_WRAP_STA] = 0x48, + [PWRAP_HARB_INIT] = 0x4c, + [PWRAP_HARB_HPRIO] = 0x50, + [PWRAP_HIPRIO_ARB_EN] = 0x54, + [PWRAP_HARB_STA0] = 0x58, + [PWRAP_HARB_STA1] = 0x5c, + [PWRAP_MAN_EN] = 0x60, + [PWRAP_MAN_CMD] = 0x64, + [PWRAP_MAN_RDATA] = 0x68, + [PWRAP_MAN_VLDCLR] = 0x6c, + [PWRAP_WACS0_EN] = 0x70, + [PWRAP_INIT_DONE0] = 0x74, + [PWRAP_WACS0_CMD] = 0x78, + [PWRAP_WACS0_RDATA] = 0x7c, + [PWRAP_WACS0_VLDCLR] = 0x80, + [PWRAP_WACS1_EN] = 0x84, + [PWRAP_INIT_DONE1] = 0x88, + [PWRAP_WACS1_CMD] = 0x8c, + [PWRAP_WACS1_RDATA] = 0x90, + [PWRAP_WACS1_VLDCLR] = 0x94, + [PWRAP_WACS2_EN] = 0x98, + [PWRAP_INIT_DONE2] = 0x9c, + [PWRAP_WACS2_CMD] = 0xa0, + [PWRAP_WACS2_RDATA] = 0xa4, + [PWRAP_WACS2_VLDCLR] = 0xa8, + [PWRAP_INT_EN] = 0xac, + [PWRAP_INT_FLG_RAW] = 0xb0, + [PWRAP_INT_FLG] = 0xb4, + [PWRAP_INT_CLR] = 0xb8, + [PWRAP_SIG_ADR] = 0xbc, + [PWRAP_SIG_MODE] = 0xc0, + [PWRAP_SIG_VALUE] = 0xc4, + [PWRAP_SIG_ERRVAL] = 0xc8, + [PWRAP_CRC_EN] = 0xcc, + [PWRAP_TIMER_EN] = 0xd0, + [PWRAP_TIMER_STA] = 0xd4, + [PWRAP_WDT_UNIT] = 0xd8, + [PWRAP_WDT_SRC_EN] = 0xdc, + [PWRAP_WDT_FLG] = 0xe0, + [PWRAP_DEBUG_INT_SEL] = 0xe4, + [PWRAP_DVFS_ADR0] = 0xe8, + [PWRAP_DVFS_WDATA0] = 0xec, + [PWRAP_DVFS_ADR1] = 0xf0, + [PWRAP_DVFS_WDATA1] = 0xf4, + [PWRAP_DVFS_ADR2] = 0xf8, + [PWRAP_DVFS_WDATA2] = 0xfc, + [PWRAP_DVFS_ADR3] = 0x100, + [PWRAP_DVFS_WDATA3] = 0x104, + [PWRAP_DVFS_ADR4] = 0x108, + [PWRAP_DVFS_WDATA4] = 0x10c, + [PWRAP_DVFS_ADR5] = 0x110, + [PWRAP_DVFS_WDATA5] = 0x114, + [PWRAP_DVFS_ADR6] = 0x118, + [PWRAP_DVFS_WDATA6] = 0x11c, + [PWRAP_DVFS_ADR7] = 0x120, + [PWRAP_DVFS_WDATA7] = 0x124, + [PWRAP_SPMINF_STA] = 0x128, + [PWRAP_CIPHER_KEY_SEL] = 0x12c, + [PWRAP_CIPHER_IV_SEL] = 0x130, + [PWRAP_CIPHER_EN] = 0x134, + [PWRAP_CIPHER_RDY] = 0x138, + [PWRAP_CIPHER_MODE] = 0x13c, + [PWRAP_CIPHER_SWRST] = 0x140, + [PWRAP_DCM_EN] = 0x144, + [PWRAP_DCM_DBC_PRD] = 0x148, + [PWRAP_EXT_CK] = 0x14c, +}; + static int mt6797_regs[] = { [PWRAP_MUX_SEL] = 0x0, [PWRAP_WRAP_EN] = 0x4, @@ -1230,6 +1315,7 @@ enum pwrap_type { PWRAP_MT2701, PWRAP_MT6765, PWRAP_MT6779, + PWRAP_MT6795, PWRAP_MT6797, PWRAP_MT6873, PWRAP_MT7622, @@ -1650,6 +1736,20 @@ static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write, static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) { switch (wrp->master->type) { + case PWRAP_MT6795: + if (wrp->slave->type == PMIC_MT6331) { + const u32 *dew_regs = wrp->slave->dew_regs; + + pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); + + if (wrp->slave->comp_type == PMIC_MT6332) { + dew_regs = wrp->slave->comp_dew_regs; + pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); + } + } + pwrap_writel(wrp, 0x88, PWRAP_RDDMY); + pwrap_init_chip_select_ext(wrp, 15, 15, 15, 15); + break; case PWRAP_MT8173: pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); break; @@ -1744,6 +1844,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) case PWRAP_MT2701: case PWRAP_MT6765: case PWRAP_MT6779: + case PWRAP_MT6795: case PWRAP_MT6797: case PWRAP_MT8173: case PWRAP_MT8186: @@ -1914,6 +2015,19 @@ static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp) return 0; } +static int pwrap_mt6795_init_soc_specific(struct pmic_wrapper *wrp) +{ + pwrap_writel(wrp, 0xf, PWRAP_STAUPD_GRPEN); + + if (wrp->slave->type == PMIC_MT6331) + pwrap_writel(wrp, 0x1b4, PWRAP_EINT_STA0_ADR); + + if (wrp->slave->comp_type == PMIC_MT6332) + pwrap_writel(wrp, 0x8112, PWRAP_EINT_STA1_ADR); + + return 0; +} + static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp) { pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD); @@ -1949,10 +2063,16 @@ static int pwrap_init(struct pmic_wrapper *wrp) if (wrp->rstc_bridge) reset_control_reset(wrp->rstc_bridge); - if (wrp->master->type == PWRAP_MT8173) { + switch (wrp->master->type) { + case PWRAP_MT6795: + fallthrough; + case PWRAP_MT8173: /* Enable DCM */ pwrap_writel(wrp, 3, PWRAP_DCM_EN); pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); + break; + default: + break; } if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { @@ -2185,6 +2305,19 @@ static const struct pmic_wrapper_type pwrap_mt6779 = { .init_soc_specific = NULL, }; +static const struct pmic_wrapper_type pwrap_mt6795 = { + .regs = mt6795_regs, + .type = PWRAP_MT6795, + .arb_en_all = 0x3f, + .int_en_all = ~(u32)(BIT(31) | BIT(2) | BIT(1)), + .int1_en_all = 0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, + .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM, + .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = pwrap_mt6795_init_soc_specific, +}; + static const struct pmic_wrapper_type pwrap_mt6797 = { .regs = mt6797_regs, .type = PWRAP_MT6797, @@ -2318,6 +2451,7 @@ static const struct of_device_id of_pwrap_match_tbl[] = { { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 }, { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 }, { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 }, + { .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 }, { .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797 }, { .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 }, { .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 }, -- cgit From 54e94ca9e3087f6a42025c42e0e2a22df8d2d0e5 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 24 Mar 2023 10:12:54 +0800 Subject: dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi The mt8186-spmi is used as compatible with mt8195-spmi on the MT8186, document this situation. Signed-off-by: Allen-KH Cheng Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Link: https://lore.kernel.org/r/20230324021258.15863-3-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml index abcbbe13723f..e4f465abcfe9 100644 --- a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml +++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml @@ -18,9 +18,14 @@ allOf: properties: compatible: - enum: - - mediatek,mt6873-spmi - - mediatek,mt8195-spmi + oneOf: + - enum: + - mediatek,mt6873-spmi + - mediatek,mt8195-spmi + - items: + - enum: + - mediatek,mt8186-spmi + - const: mediatek,mt8195-spmi reg: maxItems: 2 -- cgit From c55953358dfba2feaa81c9b01a82d9a4267e79bd Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 13:27:13 +0200 Subject: dt-bindings: pwm: Add compatible for MediaTek MT6795 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a compatible string for MediaTek Helio X10 MT6795's display PWM block: this is the same as MT8173. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Acked-by: Uwe Kleine-König Reviewed-by: Matthias Brugger Link: https://lore.kernel.org/r/20230412112739.160376-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 0088bc8e7c54..153e146df7d4 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -22,7 +22,9 @@ properties: - mediatek,mt8173-disp-pwm - mediatek,mt8183-disp-pwm - items: - - const: mediatek,mt8167-disp-pwm + - enum: + - mediatek,mt6795-disp-pwm + - mediatek,mt8167-disp-pwm - const: mediatek,mt8173-disp-pwm - items: - enum: -- cgit From 3ba589b5fe684305bf23c1c7e27bb93d4b9552cf Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 13:27:14 +0200 Subject: dt-bindings: phy: mediatek,dsi-phy: Add compatible for MT6795 Helio X10 Add a compatible string for MediaTek Helio X10 MT6795: this SoC uses the same DSI PHY as MT8173. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Reviewed-by: Alexandre Mergnat Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230412112739.160376-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml index 26f2b887cfc1..a9f78344efdb 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml @@ -24,6 +24,10 @@ properties: - enum: - mediatek,mt7623-mipi-tx - const: mediatek,mt2701-mipi-tx + - items: + - enum: + - mediatek,mt6795-mipi-tx + - const: mediatek,mt8173-mipi-tx - items: - enum: - mediatek,mt8365-mipi-tx -- cgit From 57bf5b2d1002cfd6e8d363fc2caebe415bf33ba4 Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Fri, 5 May 2023 14:19:50 +0800 Subject: soc: mediatek: mtk-mutex: Remove unnecessary .owner Remove .owner field if calls are used which set it automatically. ./drivers/soc/mediatek/mtk-mutex.c:1054:3-8: No need to set .owner here. The core will do it. Reported-by: Abaci Robot Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4869 Signed-off-by: Jiapeng Chong Link: https://lore.kernel.org/r/20230505061950.25977-1-jiapeng.chong@linux.alibaba.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mutex.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 26f3d9a41496..4aa0913817ae 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -1051,7 +1051,6 @@ static struct platform_driver mtk_mutex_driver = { .probe = mtk_mutex_probe, .driver = { .name = "mediatek-mutex", - .owner = THIS_MODULE, .of_match_table = mutex_driver_dt_match, }, }; -- cgit From e81a16e77259294cd4ff0a9c1fbe5aa0e311a47d Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 29 May 2023 10:41:15 +0200 Subject: soc: qcom: ocmem: Add OCMEM hardware version print It might be useful to know what hardware version of the OCMEM block the SoC contains. Add a debug print for that. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230509-ocmem-hwver-v3-1-e51f3488e0f4@z3ntu.xyz --- drivers/soc/qcom/ocmem.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/soc/qcom/ocmem.c b/drivers/soc/qcom/ocmem.c index 199fe9872035..aaddc3cc53b7 100644 --- a/drivers/soc/qcom/ocmem.c +++ b/drivers/soc/qcom/ocmem.c @@ -76,6 +76,10 @@ struct ocmem { #define OCMEM_REG_GFX_MPU_START 0x00001004 #define OCMEM_REG_GFX_MPU_END 0x00001008 +#define OCMEM_HW_VERSION_MAJOR(val) FIELD_GET(GENMASK(31, 28), val) +#define OCMEM_HW_VERSION_MINOR(val) FIELD_GET(GENMASK(27, 16), val) +#define OCMEM_HW_VERSION_STEP(val) FIELD_GET(GENMASK(15, 0), val) + #define OCMEM_HW_PROFILE_NUM_PORTS(val) FIELD_PREP(0x0000000f, (val)) #define OCMEM_HW_PROFILE_NUM_MACROS(val) FIELD_PREP(0x00003f00, (val)) @@ -355,6 +359,12 @@ static int ocmem_dev_probe(struct platform_device *pdev) } } + reg = ocmem_read(ocmem, OCMEM_REG_HW_VERSION); + dev_dbg(dev, "OCMEM hardware version: %lu.%lu.%lu\n", + OCMEM_HW_VERSION_MAJOR(reg), + OCMEM_HW_VERSION_MINOR(reg), + OCMEM_HW_VERSION_STEP(reg)); + reg = ocmem_read(ocmem, OCMEM_REG_HW_PROFILE); ocmem->num_ports = OCMEM_HW_PROFILE_NUM_PORTS(reg); ocmem->num_macros = OCMEM_HW_PROFILE_NUM_MACROS(reg); -- cgit From 1d9e93fad549bc38f593147479ee063f2872c170 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 13 May 2023 13:29:31 +0200 Subject: memory: brcmstb_dpfe: fix testing array offset after use Code should first check for valid value of array offset, then use it as the index. Fixes smatch warning: drivers/memory/brcmstb_dpfe.c:443 __send_command() error: testing array offset 'cmd' after use. Fixes: 2f330caff577 ("memory: brcmstb: Add driver for DPFE") Acked-by: Markus Mayer Reviewed-by: Florian Fainelli Link: https://lore.kernel.org/r/20230513112931.176066-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/memory/brcmstb_dpfe.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/memory/brcmstb_dpfe.c b/drivers/memory/brcmstb_dpfe.c index 76c82e9c8fce..9339f80b21c5 100644 --- a/drivers/memory/brcmstb_dpfe.c +++ b/drivers/memory/brcmstb_dpfe.c @@ -434,15 +434,17 @@ static void __finalize_command(struct brcmstb_dpfe_priv *priv) static int __send_command(struct brcmstb_dpfe_priv *priv, unsigned int cmd, u32 result[]) { - const u32 *msg = priv->dpfe_api->command[cmd]; void __iomem *regs = priv->regs; unsigned int i, chksum, chksum_idx; + const u32 *msg; int ret = 0; u32 resp; if (cmd >= DPFE_CMD_MAX) return -1; + msg = priv->dpfe_api->command[cmd]; + mutex_lock(&priv->lock); /* Wait for DCPU to become ready */ -- cgit From b816b9444c105b159ffc710579a204b75ed61261 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 10 Mar 2023 23:41:23 +0100 Subject: bus: fsl-mc: Only warn once about errors on device unbind MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If a platform driver's remove function returns an error code, this results in a (generic and little helpful) error message. Otherwise the value is ignored. As fsl_mc_driver_remove() already emit an error message, return 0 also in the error case. The only effect is to suppress the device core's error message. Signed-off-by: Uwe Kleine-König Reviewed-by: Ioana Ciornei Tested-by: Ioana Ciornei # sanity checks Reviewed-by: Laurentiu Tudor Tested-by: Laurentiu Tudor Signed-off-by: Li Yang --- drivers/bus/fsl-mc/fsl-mc-bus.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c index 653e2d4c116f..410693ff7335 100644 --- a/drivers/bus/fsl-mc/fsl-mc-bus.c +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c @@ -457,10 +457,8 @@ static int fsl_mc_driver_remove(struct device *dev) int error; error = mc_drv->remove(mc_dev); - if (error < 0) { + if (error < 0) dev_err(dev, "%s failed: %d\n", __func__, error); - return error; - } return 0; } -- cgit From f8fce8318366ad4a85aba7a6c9fca900876b01f9 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 10 Mar 2023 23:41:24 +0100 Subject: bus: fsl-mc: dprc: Push down error message from fsl_mc_driver_remove() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The error message emitted in fsl_mc_driver_remove() is very generic. Replace it by a message that mentions the reason for the failure. Returning zero instead of a negative value has no side effect apart from suppressing the generic error message. The first if condition in dprc_remove() can never be true, as this would prevent successful probing of the device and then .remove wasn't called. So this can just be dropped. Signed-off-by: Uwe Kleine-König Reviewed-by: Ioana Ciornei Tested-by: Ioana Ciornei # sanity checks Reviewed-by: Laurentiu Tudor Tested-by: Laurentiu Tudor Signed-off-by: Li Yang --- drivers/bus/fsl-mc/dprc-driver.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/bus/fsl-mc/dprc-driver.c b/drivers/bus/fsl-mc/dprc-driver.c index 4c84be378bf2..ef4f43f67b80 100644 --- a/drivers/bus/fsl-mc/dprc-driver.c +++ b/drivers/bus/fsl-mc/dprc-driver.c @@ -839,11 +839,10 @@ static int dprc_remove(struct fsl_mc_device *mc_dev) { struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); - if (!is_fsl_mc_bus_dprc(mc_dev)) - return -EINVAL; - - if (!mc_bus->irq_resources) - return -EINVAL; + if (!mc_bus->irq_resources) { + dev_err(&mc_dev->dev, "No irq resources, so unbinding the device failed\n"); + return 0; + } if (dev_get_msi_domain(&mc_dev->dev)) dprc_teardown_irq(mc_dev); -- cgit From e0ac89361cfb45d7c84de81563367745d2056f16 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 10 Mar 2023 23:41:25 +0100 Subject: bus: fsl-mc: fsl-mc-allocator: Drop if block with always wrong condition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If fsl_mc_is_allocatable(mc_dev) evaluates to false, the driver won't have bound to that device and then fsl_mc_allocator_remove() is never called for that device. fsl_mc_allocator_remove() is the only caller of fsl_mc_resource_pool_remove_device(), so the same check can be removed from there. Signed-off-by: Uwe Kleine-König Reviewed-by: Ioana Ciornei Tested-by: Ioana Ciornei # sanity checks Reviewed-by: Laurentiu Tudor Tested-by: Laurentiu Tudor Signed-off-by: Li Yang --- drivers/bus/fsl-mc/fsl-mc-allocator.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/bus/fsl-mc/fsl-mc-allocator.c b/drivers/bus/fsl-mc/fsl-mc-allocator.c index dced427ca8ba..e60faf8edaa1 100644 --- a/drivers/bus/fsl-mc/fsl-mc-allocator.c +++ b/drivers/bus/fsl-mc/fsl-mc-allocator.c @@ -103,9 +103,6 @@ static int __must_check fsl_mc_resource_pool_remove_device(struct fsl_mc_device struct fsl_mc_resource *resource; int error = -EINVAL; - if (!fsl_mc_is_allocatable(mc_dev)) - goto out; - resource = mc_dev->resource; if (!resource || resource->data != mc_dev) goto out; @@ -613,9 +610,6 @@ static int fsl_mc_allocator_remove(struct fsl_mc_device *mc_dev) { int error; - if (!fsl_mc_is_allocatable(mc_dev)) - return -EINVAL; - if (mc_dev->resource) { error = fsl_mc_resource_pool_remove_device(mc_dev); if (error < 0) -- cgit From b3134039c5b3cf879841e3ec84c8cbf7675554ec Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 10 Mar 2023 23:41:26 +0100 Subject: bus: fsl-mc: fsl-mc-allocator: Improve error reporting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of silently returning an error in the remove callback (which yields a generic and little informing error message), annotate each error path of fsl_mc_resource_pool_remove_device() with an error message and return zero in the remove callback to suppress the error message. Note that changing the return value has no other effect than suppressing the error message by the fsl_mc bus driver. Signed-off-by: Uwe Kleine-König Reviewed-by: Ioana Ciornei Tested-by: Ioana Ciornei # sanity checks Reviewed-by: Laurentiu Tudor Tested-by: Laurentiu Tudor Signed-off-by: Li Yang --- drivers/bus/fsl-mc/fsl-mc-allocator.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/bus/fsl-mc/fsl-mc-allocator.c b/drivers/bus/fsl-mc/fsl-mc-allocator.c index e60faf8edaa1..36f70e5e418b 100644 --- a/drivers/bus/fsl-mc/fsl-mc-allocator.c +++ b/drivers/bus/fsl-mc/fsl-mc-allocator.c @@ -104,22 +104,30 @@ static int __must_check fsl_mc_resource_pool_remove_device(struct fsl_mc_device int error = -EINVAL; resource = mc_dev->resource; - if (!resource || resource->data != mc_dev) + if (!resource || resource->data != mc_dev) { + dev_err(&mc_bus_dev->dev, "resource mismatch\n"); goto out; + } mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); mc_bus = to_fsl_mc_bus(mc_bus_dev); res_pool = resource->parent_pool; - if (res_pool != &mc_bus->resource_pools[resource->type]) + if (res_pool != &mc_bus->resource_pools[resource->type]) { + dev_err(&mc_bus_dev->dev, "pool mismatch\n"); goto out; + } mutex_lock(&res_pool->mutex); - if (res_pool->max_count <= 0) + if (res_pool->max_count <= 0) { + dev_err(&mc_bus_dev->dev, "max_count underflow\n"); goto out_unlock; + } if (res_pool->free_count <= 0 || - res_pool->free_count > res_pool->max_count) + res_pool->free_count > res_pool->max_count) { + dev_err(&mc_bus_dev->dev, "free_count mismatch\n"); goto out_unlock; + } /* * If the device is currently allocated, its resource is not @@ -613,7 +621,7 @@ static int fsl_mc_allocator_remove(struct fsl_mc_device *mc_dev) if (mc_dev->resource) { error = fsl_mc_resource_pool_remove_device(mc_dev); if (error < 0) - return error; + return 0; } dev_dbg(&mc_dev->dev, -- cgit From c27ea8e6325cad44c8c5bc2e8e7cc7635f358f31 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 10 Mar 2023 23:41:27 +0100 Subject: soc: fsl: dpio: Suppress duplicated error reporting on device remove MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Returning an error code from a fsl_mc_driver's remove callback results in a generic error message, otherwise the value is ignored and the device gets unbound. As the only error path in dpaa2_dpio_remove() already emits an error message, return zero unconditionally to suppress another (less helpful) error report. Signed-off-by: Uwe Kleine-König Reviewed-by: Ioana Ciornei Tested-by: Ioana Ciornei # sanity checks Reviewed-by: Laurentiu Tudor Tested-by: Laurentiu Tudor Signed-off-by: Li Yang --- drivers/soc/fsl/dpio/dpio-driver.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/soc/fsl/dpio/dpio-driver.c b/drivers/soc/fsl/dpio/dpio-driver.c index 74eace3109a1..09df5302d255 100644 --- a/drivers/soc/fsl/dpio/dpio-driver.c +++ b/drivers/soc/fsl/dpio/dpio-driver.c @@ -297,14 +297,10 @@ static int dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev) dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle); - fsl_mc_portal_free(dpio_dev->mc_io); - - return 0; - err_open: fsl_mc_portal_free(dpio_dev->mc_io); - return err; + return 0; } static const struct fsl_mc_device_id dpaa2_dpio_match_id_table[] = { -- cgit From 59272ad8d9e8ea6398a96f8c6d62da284bf2ae6e Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 10 Mar 2023 23:41:28 +0100 Subject: bus: fsl-mc: Make remove function return void MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The value returned by an fsl-mc driver's remove function is mostly ignored. (Only an error message is printed if the value is non-zero and then device removal continues unconditionally.) So change the prototype of the remove function to return no value. This way driver authors are not tempted to assume that passing an error to the upper layer is a good idea. All drivers are adapted accordingly. There is no intended change of behaviour, all callbacks were prepared to return 0 before. Signed-off-by: Uwe Kleine-König Reviewed-by: Ioana Ciornei Tested-by: Ioana Ciornei # sanity checks Reviewed-by: Laurentiu Tudor Tested-by: Laurentiu Tudor Signed-off-by: Li Yang --- drivers/bus/fsl-mc/dprc-driver.c | 5 ++--- drivers/bus/fsl-mc/fsl-mc-allocator.c | 5 ++--- drivers/bus/fsl-mc/fsl-mc-bus.c | 5 +---- drivers/crypto/caam/caamalg_qi2.c | 4 +--- drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c | 4 +--- drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c | 4 +--- drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c | 4 +--- drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c | 4 +--- drivers/soc/fsl/dpio/dpio-driver.c | 4 +--- drivers/vfio/fsl-mc/vfio_fsl_mc.c | 3 +-- include/linux/fsl/mc.h | 2 +- 11 files changed, 13 insertions(+), 31 deletions(-) diff --git a/drivers/bus/fsl-mc/dprc-driver.c b/drivers/bus/fsl-mc/dprc-driver.c index ef4f43f67b80..595d4cecd041 100644 --- a/drivers/bus/fsl-mc/dprc-driver.c +++ b/drivers/bus/fsl-mc/dprc-driver.c @@ -835,13 +835,13 @@ EXPORT_SYMBOL_GPL(dprc_cleanup); * It tears down the interrupts that were configured for the DPRC device. * It destroys the interrupt pool associated with this MC bus. */ -static int dprc_remove(struct fsl_mc_device *mc_dev) +static void dprc_remove(struct fsl_mc_device *mc_dev) { struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev); if (!mc_bus->irq_resources) { dev_err(&mc_dev->dev, "No irq resources, so unbinding the device failed\n"); - return 0; + return; } if (dev_get_msi_domain(&mc_dev->dev)) @@ -852,7 +852,6 @@ static int dprc_remove(struct fsl_mc_device *mc_dev) dprc_cleanup(mc_dev); dev_info(&mc_dev->dev, "DPRC device unbound from driver"); - return 0; } static const struct fsl_mc_device_id match_id_table[] = { diff --git a/drivers/bus/fsl-mc/fsl-mc-allocator.c b/drivers/bus/fsl-mc/fsl-mc-allocator.c index 36f70e5e418b..0ad68099684e 100644 --- a/drivers/bus/fsl-mc/fsl-mc-allocator.c +++ b/drivers/bus/fsl-mc/fsl-mc-allocator.c @@ -614,19 +614,18 @@ static int fsl_mc_allocator_probe(struct fsl_mc_device *mc_dev) * fsl_mc_allocator_remove - callback invoked when an allocatable device is * being removed from the system */ -static int fsl_mc_allocator_remove(struct fsl_mc_device *mc_dev) +static void fsl_mc_allocator_remove(struct fsl_mc_device *mc_dev) { int error; if (mc_dev->resource) { error = fsl_mc_resource_pool_remove_device(mc_dev); if (error < 0) - return 0; + return; } dev_dbg(&mc_dev->dev, "Allocatable fsl-mc device unbound from fsl_mc_allocator driver"); - return 0; } static const struct fsl_mc_device_id match_id_table[] = { diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c index 410693ff7335..4352745a923c 100644 --- a/drivers/bus/fsl-mc/fsl-mc-bus.c +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c @@ -454,11 +454,8 @@ static int fsl_mc_driver_remove(struct device *dev) { struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(dev->driver); struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - int error; - error = mc_drv->remove(mc_dev); - if (error < 0) - dev_err(dev, "%s failed: %d\n", __func__, error); + mc_drv->remove(mc_dev); return 0; } diff --git a/drivers/crypto/caam/caamalg_qi2.c b/drivers/crypto/caam/caamalg_qi2.c index 5c8d35edaa1c..9156bbe038b7 100644 --- a/drivers/crypto/caam/caamalg_qi2.c +++ b/drivers/crypto/caam/caamalg_qi2.c @@ -5402,7 +5402,7 @@ err_dma_mask: return err; } -static int __cold dpaa2_caam_remove(struct fsl_mc_device *ls_dev) +static void __cold dpaa2_caam_remove(struct fsl_mc_device *ls_dev) { struct device *dev; struct dpaa2_caam_priv *priv; @@ -5443,8 +5443,6 @@ static int __cold dpaa2_caam_remove(struct fsl_mc_device *ls_dev) free_percpu(priv->ppriv); fsl_mc_portal_free(priv->mc_io); kmem_cache_destroy(qi_cache); - - return 0; } int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req) diff --git a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c index 8dd40d00a672..a42a37634881 100644 --- a/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c +++ b/drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c @@ -765,7 +765,7 @@ err_mcportal: return err; } -static int dpaa2_qdma_remove(struct fsl_mc_device *ls_dev) +static void dpaa2_qdma_remove(struct fsl_mc_device *ls_dev) { struct dpaa2_qdma_engine *dpaa2_qdma; struct dpaa2_qdma_priv *priv; @@ -787,8 +787,6 @@ static int dpaa2_qdma_remove(struct fsl_mc_device *ls_dev) dma_async_device_unregister(&dpaa2_qdma->dma_dev); kfree(priv); kfree(dpaa2_qdma); - - return 0; } static void dpaa2_qdma_shutdown(struct fsl_mc_device *ls_dev) diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c index a62cffaf6ff1..a9676d0dece8 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c @@ -5025,7 +5025,7 @@ err_wq_alloc: return err; } -static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev) +static void dpaa2_eth_remove(struct fsl_mc_device *ls_dev) { struct device *dev; struct net_device *net_dev; @@ -5073,8 +5073,6 @@ static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev) dev_dbg(net_dev->dev.parent, "Removed interface %s\n", net_dev->name); free_netdev(net_dev); - - return 0; } static const struct fsl_mc_device_id dpaa2_eth_match_id_table[] = { diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c index 90d23ab1ce9d..4497e3c0456d 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c @@ -219,7 +219,7 @@ err_exit: return err; } -static int dpaa2_ptp_remove(struct fsl_mc_device *mc_dev) +static void dpaa2_ptp_remove(struct fsl_mc_device *mc_dev) { struct device *dev = &mc_dev->dev; struct ptp_qoriq *ptp_qoriq; @@ -232,8 +232,6 @@ static int dpaa2_ptp_remove(struct fsl_mc_device *mc_dev) fsl_mc_free_irqs(mc_dev); dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle); fsl_mc_portal_free(mc_dev->mc_io); - - return 0; } static const struct fsl_mc_device_id dpaa2_ptp_match_id_table[] = { diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c index f4ae4289c41a..21cc4e52425a 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c @@ -3221,7 +3221,7 @@ static void dpaa2_switch_teardown(struct fsl_mc_device *sw_dev) dev_warn(dev, "dpsw_close err %d\n", err); } -static int dpaa2_switch_remove(struct fsl_mc_device *sw_dev) +static void dpaa2_switch_remove(struct fsl_mc_device *sw_dev) { struct ethsw_port_priv *port_priv; struct ethsw_core *ethsw; @@ -3252,8 +3252,6 @@ static int dpaa2_switch_remove(struct fsl_mc_device *sw_dev) kfree(ethsw); dev_set_drvdata(dev, NULL); - - return 0; } static int dpaa2_switch_probe_port(struct ethsw_core *ethsw, diff --git a/drivers/soc/fsl/dpio/dpio-driver.c b/drivers/soc/fsl/dpio/dpio-driver.c index 09df5302d255..9e3fddd8f5a9 100644 --- a/drivers/soc/fsl/dpio/dpio-driver.c +++ b/drivers/soc/fsl/dpio/dpio-driver.c @@ -270,7 +270,7 @@ static void dpio_teardown_irqs(struct fsl_mc_device *dpio_dev) fsl_mc_free_irqs(dpio_dev); } -static int dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev) +static void dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev) { struct device *dev; struct dpio_priv *priv; @@ -299,8 +299,6 @@ static int dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev) err_open: fsl_mc_portal_free(dpio_dev->mc_io); - - return 0; } static const struct fsl_mc_device_id dpaa2_dpio_match_id_table[] = { diff --git a/drivers/vfio/fsl-mc/vfio_fsl_mc.c b/drivers/vfio/fsl-mc/vfio_fsl_mc.c index c89a047a4cd8..f2140e94d41e 100644 --- a/drivers/vfio/fsl-mc/vfio_fsl_mc.c +++ b/drivers/vfio/fsl-mc/vfio_fsl_mc.c @@ -570,7 +570,7 @@ static void vfio_fsl_mc_release_dev(struct vfio_device *core_vdev) mutex_destroy(&vdev->igate); } -static int vfio_fsl_mc_remove(struct fsl_mc_device *mc_dev) +static void vfio_fsl_mc_remove(struct fsl_mc_device *mc_dev) { struct device *dev = &mc_dev->dev; struct vfio_fsl_mc_device *vdev = dev_get_drvdata(dev); @@ -578,7 +578,6 @@ static int vfio_fsl_mc_remove(struct fsl_mc_device *mc_dev) vfio_unregister_group_dev(&vdev->vdev); dprc_remove_devices(mc_dev, NULL, 0); vfio_put_device(&vdev->vdev); - return 0; } static const struct vfio_device_ops vfio_fsl_mc_ops = { diff --git a/include/linux/fsl/mc.h b/include/linux/fsl/mc.h index a86115bc799c..a1b3de87a3d1 100644 --- a/include/linux/fsl/mc.h +++ b/include/linux/fsl/mc.h @@ -48,7 +48,7 @@ struct fsl_mc_driver { struct device_driver driver; const struct fsl_mc_device_id *match_id_table; int (*probe)(struct fsl_mc_device *dev); - int (*remove)(struct fsl_mc_device *dev); + void (*remove)(struct fsl_mc_device *dev); void (*shutdown)(struct fsl_mc_device *dev); int (*suspend)(struct fsl_mc_device *dev, pm_message_t state); int (*resume)(struct fsl_mc_device *dev); -- cgit From 7b1a78babd0d2cd27aa07255dee0c2d7ac0f31e3 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 21 May 2023 15:52:16 -0700 Subject: soc/fsl/qe: fix usb.c build errors Fix build errors in soc/fsl/qe/usb.c when QUICC_ENGINE is not set. This happens when PPC_EP88XC is set, which selects CPM1 & CPM. When CPM is set, USB_FSL_QE can be set without QUICC_ENGINE being set. When USB_FSL_QE is set, QE_USB deafults to y, which causes build errors when QUICC_ENGINE is not set. Making QE_USB depend on QUICC_ENGINE prevents QE_USB from defaulting to y. Fixes these build errors: drivers/soc/fsl/qe/usb.o: in function `qe_usb_clock_set': usb.c:(.text+0x1e): undefined reference to `qe_immr' powerpc-linux-ld: usb.c:(.text+0x2a): undefined reference to `qe_immr' powerpc-linux-ld: usb.c:(.text+0xbc): undefined reference to `qe_setbrg' powerpc-linux-ld: usb.c:(.text+0xca): undefined reference to `cmxgcr_lock' powerpc-linux-ld: usb.c:(.text+0xce): undefined reference to `cmxgcr_lock' Fixes: 5e41486c408e ("powerpc/QE: add support for QE USB clocks routing") Signed-off-by: Randy Dunlap Reported-by: kernel test robot Link: https://lore.kernel.org/all/202301101500.pillNv6R-lkp@intel.com/ Suggested-by: Michael Ellerman Cc: Christophe Leroy Cc: Leo Li Cc: Masahiro Yamada Cc: Nicolas Schier Cc: Qiang Zhao Cc: linuxppc-dev Cc: linux-arm-kernel@lists.infradead.org Cc: Kumar Gala Acked-by: Nicolas Schier Signed-off-by: Li Yang --- drivers/soc/fsl/qe/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig index 7268c2fbcbc1..160c8877b0c9 100644 --- a/drivers/soc/fsl/qe/Kconfig +++ b/drivers/soc/fsl/qe/Kconfig @@ -62,6 +62,7 @@ config QE_TDM config QE_USB bool + depends on QUICC_ENGINE default y if USB_FSL_QE help QE USB Controller support -- cgit From d3369a4b6f0164b8869a097547846ed4e5c9c47f Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 16 May 2023 10:24:05 +0300 Subject: memory: atmel-sdramc: remove the driver Driver does only clock request + enable for DDR clocks. DDR clocks are enabled by bootloader and need to stay that way in Linux. To avoid having these clocks disabled by clock subsystem in case there are no Linux consumers for them the clocks were marked as critical in clock drivers (in commit 68b3b6f1773d ("clk: at91: mark ddr clocks as critical")). With this, there is no need to have a separate driver that only does clock request + enable. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230516072405.2696225-1-claudiu.beznea@microchip.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-at91/Kconfig | 4 --- drivers/memory/Kconfig | 11 ------- drivers/memory/Makefile | 1 - drivers/memory/atmel-sdramc.c | 74 ------------------------------------------- 4 files changed, 90 deletions(-) delete mode 100644 drivers/memory/atmel-sdramc.c diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 3dd9e718661b..a8c022b4c053 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -97,7 +97,6 @@ config SOC_AT91SAM9 depends on ARCH_MULTI_V5 select ATMEL_AIC_IRQ select ATMEL_PM if PM - select ATMEL_SDRAMC select CPU_ARM926T select HAVE_AT91_SMD select HAVE_AT91_USB_CLK @@ -131,7 +130,6 @@ config SOC_SAM9X60 depends on ARCH_MULTI_V5 select ATMEL_AIC5_IRQ select ATMEL_PM if PM - select ATMEL_SDRAMC select CPU_ARM926T select HAVE_AT91_USB_CLK select HAVE_AT91_GENERATED_CLK @@ -213,7 +211,6 @@ config SOC_SAMA5 bool select ATMEL_AIC5_IRQ select ATMEL_PM if PM - select ATMEL_SDRAMC select MEMORY select SOC_SAM_V7 select SRAM if PM @@ -234,7 +231,6 @@ config SOC_SAMA7 bool select ARM_GIC select ATMEL_PM if PM - select ATMEL_SDRAMC select MEMORY select SOC_SAM_V7 select SRAM if PM diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 91774e6ee624..8efdd1f97139 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -30,17 +30,6 @@ config ARM_PL172_MPMC If you have an embedded system with an AMBA bus and a PL172 controller, say Y or M here. -config ATMEL_SDRAMC - bool "Atmel (Multi-port DDR-)SDRAM Controller" - default y if ARCH_AT91 - depends on ARCH_AT91 || COMPILE_TEST - depends on OF - help - This driver is for Atmel SDRAM Controller or Atmel Multi-port - DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs. - Starting with the at91sam9g45, this controller supports SDR, DDR and - LP-DDR memories. - config ATMEL_EBI bool "Atmel EBI driver" default y if ARCH_AT91 diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index ae14ded464a8..d2e6ca9abbe0 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -8,7 +8,6 @@ ifeq ($(CONFIG_DDR),y) obj-$(CONFIG_OF) += of_memory.o endif obj-$(CONFIG_ARM_PL172_MPMC) += pl172.o -obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o obj-$(CONFIG_ATMEL_EBI) += atmel-ebi.o obj-$(CONFIG_BRCMSTB_DPFE) += brcmstb_dpfe.o obj-$(CONFIG_BRCMSTB_MEMC) += brcmstb_memc.o diff --git a/drivers/memory/atmel-sdramc.c b/drivers/memory/atmel-sdramc.c deleted file mode 100644 index ea6e9e1eaf04..000000000000 --- a/drivers/memory/atmel-sdramc.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Atmel (Multi-port DDR-)SDRAM Controller driver - * - * Author: Alexandre Belloni - * - * Copyright (C) 2014 Atmel - */ - -#include -#include -#include -#include -#include -#include - -struct at91_ramc_caps { - bool has_ddrck; - bool has_mpddr_clk; -}; - -static const struct at91_ramc_caps at91rm9200_caps = { }; - -static const struct at91_ramc_caps at91sam9g45_caps = { - .has_ddrck = 1, - .has_mpddr_clk = 0, -}; - -static const struct at91_ramc_caps sama5d3_caps = { - .has_ddrck = 1, - .has_mpddr_clk = 1, -}; - -static const struct of_device_id atmel_ramc_of_match[] = { - { .compatible = "atmel,at91rm9200-sdramc", .data = &at91rm9200_caps, }, - { .compatible = "atmel,at91sam9260-sdramc", .data = &at91rm9200_caps, }, - { .compatible = "atmel,at91sam9g45-ddramc", .data = &at91sam9g45_caps, }, - { .compatible = "atmel,sama5d3-ddramc", .data = &sama5d3_caps, }, - {}, -}; - -static int atmel_ramc_probe(struct platform_device *pdev) -{ - const struct at91_ramc_caps *caps; - struct clk *clk; - - caps = of_device_get_match_data(&pdev->dev); - - if (caps->has_ddrck) { - clk = devm_clk_get_enabled(&pdev->dev, "ddrck"); - if (IS_ERR(clk)) - return PTR_ERR(clk); - } - - if (caps->has_mpddr_clk) { - clk = devm_clk_get_enabled(&pdev->dev, "mpddr"); - if (IS_ERR(clk)) { - pr_err("AT91 RAMC: couldn't get mpddr clock\n"); - return PTR_ERR(clk); - } - } - - return 0; -} - -static struct platform_driver atmel_ramc_driver = { - .probe = atmel_ramc_probe, - .driver = { - .name = "atmel-ramc", - .of_match_table = atmel_ramc_of_match, - }, -}; - -builtin_platform_driver(atmel_ramc_driver); -- cgit From a49e482c52d551b46ec10fb12bbf5ad242848a59 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 16 May 2023 15:48:52 +0200 Subject: MAINTAINERS: Switch to @amd.com emails @xilinx.com is still working but better to switch to new amd.com after AMD/Xilinx acquisition. Acked-by: Shubhrajyoti Datta Acked-by: Radhey Shyam Pandey Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f7773fdd002f89578b9e5262692a563fe7be4123.1684244928.git.michal.simek@amd.com --- MAINTAINERS | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 60f6effb168c..4b2ef60a4d01 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23115,7 +23115,7 @@ F: Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml F: drivers/iio/adc/xilinx-ams.c XILINX AXI ETHERNET DRIVER -M: Radhey Shyam Pandey +M: Radhey Shyam Pandey S: Maintained F: drivers/net/ethernet/xilinx/xilinx_axienet* @@ -23128,8 +23128,8 @@ F: Documentation/devicetree/bindings/net/can/xilinx,can.yaml F: drivers/net/can/xilinx_can.c XILINX GPIO DRIVER -M: Shubhrajyoti Datta -R: Srinivas Neeli +M: Shubhrajyoti Datta +R: Srinivas Neeli R: Michal Simek S: Maintained F: Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml @@ -23138,8 +23138,8 @@ F: drivers/gpio/gpio-xilinx.c F: drivers/gpio/gpio-zynq.c XILINX SD-FEC IP CORES -M: Derek Kiernan -M: Dragan Cvetic +M: Derek Kiernan +M: Dragan Cvetic S: Maintained F: Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt F: Documentation/misc-devices/xilinx_sdfec.rst @@ -23212,7 +23212,7 @@ F: Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml F: drivers/phy/xilinx/phy-zynqmp.c XILINX ZYNQMP SHA3 DRIVER -M: Harsha +M: Harsha S: Maintained F: drivers/crypto/xilinx/zynqmp-sha.c -- cgit From a00d47f7645d6e840a38a62fd961c8aa2c8fed6c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 2 Jun 2023 10:50:41 +0200 Subject: soc: renesas: rmobile-sysc: Convert to readl_poll_timeout_atomic() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use readl_poll_timeout_atomic() instead of open-coding the same operation. 1. rmobile_pd_power_down(): as typically less than 20 retries are needed, PSTR_RETRIES (100) µs is a suitable timeout value. 2. __rmobile_pd_power_up(): the old method of first polling some cycles with a 1 µs delay, followed by more polling cycles without any delay didn't make much sense, as the latter was insignificant compared to the former. Furthermore, typically no retries are needed. Hence just retain the polling with delay. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/ae4bf03ab8fd5a557c683086958d6764babc0723.1685692810.git.geert+renesas@glider.be --- drivers/soc/renesas/rmobile-sysc.c | 29 +++++++++-------------------- 1 file changed, 9 insertions(+), 20 deletions(-) diff --git a/drivers/soc/renesas/rmobile-sysc.c b/drivers/soc/renesas/rmobile-sysc.c index 728ebac98e14..912daadaa10d 100644 --- a/drivers/soc/renesas/rmobile-sysc.c +++ b/drivers/soc/renesas/rmobile-sysc.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include #include @@ -19,8 +21,6 @@ #include #include -#include - /* SYSC */ #define SPDCR 0x08 /* SYS Power Down Control Register */ #define SWUCR 0x14 /* SYS Wakeup Control Register */ @@ -47,6 +47,7 @@ static int rmobile_pd_power_down(struct generic_pm_domain *genpd) { struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd); unsigned int mask = BIT(rmobile_pd->bit_shift); + u32 val; if (rmobile_pd->suspend) { int ret = rmobile_pd->suspend(); @@ -56,14 +57,10 @@ static int rmobile_pd_power_down(struct generic_pm_domain *genpd) } if (readl(rmobile_pd->base + PSTR) & mask) { - unsigned int retry_count; writel(mask, rmobile_pd->base + SPDCR); - for (retry_count = PSTR_RETRIES; retry_count; retry_count--) { - if (!(readl(rmobile_pd->base + SPDCR) & mask)) - break; - cpu_relax(); - } + readl_poll_timeout_atomic(rmobile_pd->base + SPDCR, val, + !(val & mask), 0, PSTR_RETRIES); } pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n", genpd->name, mask, @@ -74,8 +71,7 @@ static int rmobile_pd_power_down(struct generic_pm_domain *genpd) static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd) { - unsigned int mask = BIT(rmobile_pd->bit_shift); - unsigned int retry_count; + unsigned int val, mask = BIT(rmobile_pd->bit_shift); int ret = 0; if (readl(rmobile_pd->base + PSTR) & mask) @@ -83,16 +79,9 @@ static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd) writel(mask, rmobile_pd->base + SWUCR); - for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) { - if (!(readl(rmobile_pd->base + SWUCR) & mask)) - break; - if (retry_count > PSTR_RETRIES) - udelay(PSTR_DELAY_US); - else - cpu_relax(); - } - if (!retry_count) - ret = -EIO; + ret = readl_poll_timeout_atomic(rmobile_pd->base + SWUCR, val, + (val & mask), PSTR_DELAY_US, + PSTR_RETRIES * PSTR_DELAY_US); pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n", rmobile_pd->genpd.name, mask, -- cgit From 4e1a53b4030e0a28e17548f8f380fa38207ec300 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Wed, 31 May 2023 16:20:37 +0100 Subject: firmware: arm_scmi: Refactor the internal powercap get/set helpers Refactor the SCMI powercap internal get/set helpers in preparation to adding the powercap protocol enable/disable support. Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20230531152039.2363181-2-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/powercap.c | 65 +++++++++++++++++++++++++----------- 1 file changed, 45 insertions(+), 20 deletions(-) diff --git a/drivers/firmware/arm_scmi/powercap.c b/drivers/firmware/arm_scmi/powercap.c index 83b90bde755c..2e490492f187 100644 --- a/drivers/firmware/arm_scmi/powercap.c +++ b/drivers/firmware/arm_scmi/powercap.c @@ -313,24 +313,33 @@ static int scmi_powercap_xfer_cap_get(const struct scmi_protocol_handle *ph, return ret; } -static int scmi_powercap_cap_get(const struct scmi_protocol_handle *ph, - u32 domain_id, u32 *power_cap) +static int __scmi_powercap_cap_get(const struct scmi_protocol_handle *ph, + const struct scmi_powercap_info *dom, + u32 *power_cap) { - struct scmi_powercap_info *dom; - struct powercap_info *pi = ph->get_priv(ph); - - if (!power_cap || domain_id >= pi->num_domains) - return -EINVAL; - - dom = pi->powercaps + domain_id; if (dom->fc_info && dom->fc_info[POWERCAP_FC_CAP].get_addr) { *power_cap = ioread32(dom->fc_info[POWERCAP_FC_CAP].get_addr); trace_scmi_fc_call(SCMI_PROTOCOL_POWERCAP, POWERCAP_CAP_GET, - domain_id, *power_cap, 0); + dom->id, *power_cap, 0); return 0; } - return scmi_powercap_xfer_cap_get(ph, domain_id, power_cap); + return scmi_powercap_xfer_cap_get(ph, dom->id, power_cap); +} + +static int scmi_powercap_cap_get(const struct scmi_protocol_handle *ph, + u32 domain_id, u32 *power_cap) +{ + const struct scmi_powercap_info *dom; + + if (!power_cap) + return -EINVAL; + + dom = scmi_powercap_dom_info_get(ph, domain_id); + if (!dom) + return -EINVAL; + + return __scmi_powercap_cap_get(ph, dom, power_cap); } static int scmi_powercap_xfer_cap_set(const struct scmi_protocol_handle *ph, @@ -375,17 +384,20 @@ static int scmi_powercap_xfer_cap_set(const struct scmi_protocol_handle *ph, return ret; } -static int scmi_powercap_cap_set(const struct scmi_protocol_handle *ph, - u32 domain_id, u32 power_cap, - bool ignore_dresp) +static int __scmi_powercap_cap_set(const struct scmi_protocol_handle *ph, + struct powercap_info *pi, u32 domain_id, + u32 power_cap, bool ignore_dresp) { + int ret = -EINVAL; const struct scmi_powercap_info *pc; pc = scmi_powercap_dom_info_get(ph, domain_id); - if (!pc || !pc->powercap_cap_config || !power_cap || - power_cap < pc->min_power_cap || - power_cap > pc->max_power_cap) - return -EINVAL; + if (!pc || !pc->powercap_cap_config) + return ret; + + if (power_cap && + (power_cap < pc->min_power_cap || power_cap > pc->max_power_cap)) + return ret; if (pc->fc_info && pc->fc_info[POWERCAP_FC_CAP].set_addr) { struct scmi_fc_info *fci = &pc->fc_info[POWERCAP_FC_CAP]; @@ -394,10 +406,23 @@ static int scmi_powercap_cap_set(const struct scmi_protocol_handle *ph, ph->hops->fastchannel_db_ring(fci->set_db); trace_scmi_fc_call(SCMI_PROTOCOL_POWERCAP, POWERCAP_CAP_SET, domain_id, power_cap, 0); - return 0; + ret = 0; + } else { + ret = scmi_powercap_xfer_cap_set(ph, pc, power_cap, + ignore_dresp); } - return scmi_powercap_xfer_cap_set(ph, pc, power_cap, ignore_dresp); + return ret; +} + +static int scmi_powercap_cap_set(const struct scmi_protocol_handle *ph, + u32 domain_id, u32 power_cap, + bool ignore_dresp) +{ + struct powercap_info *pi = ph->get_priv(ph); + + return __scmi_powercap_cap_set(ph, pi, domain_id, + power_cap, ignore_dresp); } static int scmi_powercap_xfer_pai_get(const struct scmi_protocol_handle *ph, -- cgit From 758cd5fc13b20a5874d33b7d381e78408743f587 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Wed, 31 May 2023 16:20:38 +0100 Subject: firmware: arm_scmi: Add Powercap protocol enable support SCMI powercap protocol v3.2 supports disabling the powercap on a zone by zone basis by providing a zero valued powercap. Expose new operations to enable/disable powercapping on a per-zone base. Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20230531152039.2363181-3-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/powercap.c | 110 +++++++++++++++++++++++++++++++++-- include/linux/scmi_protocol.h | 18 ++++++ 2 files changed, 122 insertions(+), 6 deletions(-) diff --git a/drivers/firmware/arm_scmi/powercap.c b/drivers/firmware/arm_scmi/powercap.c index 2e490492f187..244929cb4f3e 100644 --- a/drivers/firmware/arm_scmi/powercap.c +++ b/drivers/firmware/arm_scmi/powercap.c @@ -108,6 +108,8 @@ struct scmi_powercap_meas_changed_notify_payld { }; struct scmi_powercap_state { + bool enabled; + u32 last_pcap; bool meas_notif_enabled; u64 thresholds; #define THRESH_LOW(p, id) \ @@ -412,6 +414,10 @@ static int __scmi_powercap_cap_set(const struct scmi_protocol_handle *ph, ignore_dresp); } + /* Save the last explicitly set non-zero powercap value */ + if (PROTOCOL_REV_MAJOR(pi->version) >= 0x2 && !ret && power_cap) + pi->states[domain_id].last_pcap = power_cap; + return ret; } @@ -421,6 +427,20 @@ static int scmi_powercap_cap_set(const struct scmi_protocol_handle *ph, { struct powercap_info *pi = ph->get_priv(ph); + /* + * Disallow zero as a possible explicitly requested powercap: + * there are enable/disable operations for this. + */ + if (!power_cap) + return -EINVAL; + + /* Just log the last set request if acting on a disabled domain */ + if (PROTOCOL_REV_MAJOR(pi->version) >= 0x2 && + !pi->states[domain_id].enabled) { + pi->states[domain_id].last_pcap = power_cap; + return 0; + } + return __scmi_powercap_cap_set(ph, pi, domain_id, power_cap, ignore_dresp); } @@ -589,11 +609,78 @@ scmi_powercap_measurements_threshold_set(const struct scmi_protocol_handle *ph, return ret; } +static int scmi_powercap_cap_enable_set(const struct scmi_protocol_handle *ph, + u32 domain_id, bool enable) +{ + int ret; + u32 power_cap; + struct powercap_info *pi = ph->get_priv(ph); + + if (PROTOCOL_REV_MAJOR(pi->version) < 0x2) + return -EINVAL; + + if (enable == pi->states[domain_id].enabled) + return 0; + + if (enable) { + /* Cannot enable with a zero powercap. */ + if (!pi->states[domain_id].last_pcap) + return -EINVAL; + + ret = __scmi_powercap_cap_set(ph, pi, domain_id, + pi->states[domain_id].last_pcap, + true); + } else { + ret = __scmi_powercap_cap_set(ph, pi, domain_id, 0, true); + } + + if (ret) + return ret; + + /* + * Update our internal state to reflect final platform state: the SCMI + * server could have ignored a disable request and kept enforcing some + * powercap limit requested by other agents. + */ + ret = scmi_powercap_cap_get(ph, domain_id, &power_cap); + if (!ret) + pi->states[domain_id].enabled = !!power_cap; + + return ret; +} + +static int scmi_powercap_cap_enable_get(const struct scmi_protocol_handle *ph, + u32 domain_id, bool *enable) +{ + int ret; + u32 power_cap; + struct powercap_info *pi = ph->get_priv(ph); + + *enable = true; + if (PROTOCOL_REV_MAJOR(pi->version) < 0x2) + return 0; + + /* + * Report always real platform state; platform could have ignored + * a previous disable request. Default true on any error. + */ + ret = scmi_powercap_cap_get(ph, domain_id, &power_cap); + if (!ret) + *enable = !!power_cap; + + /* Update internal state with current real platform state */ + pi->states[domain_id].enabled = *enable; + + return 0; +} + static const struct scmi_powercap_proto_ops powercap_proto_ops = { .num_domains_get = scmi_powercap_num_domains_get, .info_get = scmi_powercap_dom_info_get, .cap_get = scmi_powercap_cap_get, .cap_set = scmi_powercap_cap_set, + .cap_enable_set = scmi_powercap_cap_enable_set, + .cap_enable_get = scmi_powercap_cap_enable_get, .pai_get = scmi_powercap_pai_get, .pai_set = scmi_powercap_pai_set, .measurements_get = scmi_powercap_measurements_get, @@ -854,6 +941,11 @@ scmi_powercap_protocol_init(const struct scmi_protocol_handle *ph) if (!pinfo->powercaps) return -ENOMEM; + pinfo->states = devm_kcalloc(ph->dev, pinfo->num_domains, + sizeof(*pinfo->states), GFP_KERNEL); + if (!pinfo->states) + return -ENOMEM; + /* * Note that any failure in retrieving any domain attribute leads to * the whole Powercap protocol initialization failure: this way the @@ -868,15 +960,21 @@ scmi_powercap_protocol_init(const struct scmi_protocol_handle *ph) if (pinfo->powercaps[domain].fastchannels) scmi_powercap_domain_init_fc(ph, domain, &pinfo->powercaps[domain].fc_info); - } - pinfo->states = devm_kcalloc(ph->dev, pinfo->num_domains, - sizeof(*pinfo->states), GFP_KERNEL); - if (!pinfo->states) - return -ENOMEM; + /* Grab initial state when disable is supported. */ + if (PROTOCOL_REV_MAJOR(version) >= 0x2) { + ret = __scmi_powercap_cap_get(ph, + &pinfo->powercaps[domain], + &pinfo->states[domain].last_pcap); + if (ret) + return ret; - pinfo->version = version; + pinfo->states[domain].enabled = + !!pinfo->states[domain].last_pcap; + } + } + pinfo->version = version; return ph->set_priv(ph, pinfo); } diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 0ce5746a4470..e6fe4f73ffe6 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -629,11 +629,25 @@ struct scmi_powercap_info { * @num_domains_get: get the count of powercap domains provided by SCMI. * @info_get: get the information for the specified domain. * @cap_get: get the current CAP value for the specified domain. + * On SCMI platforms supporting powercap zone disabling, this could + * report a zero value for a zone where powercapping is disabled. * @cap_set: set the CAP value for the specified domain to the provided value; * if the domain supports setting the CAP with an asynchronous command * this request will finally trigger an asynchronous transfer, but, if * @ignore_dresp here is set to true, this call will anyway return * immediately without waiting for the related delayed response. + * Note that the powercap requested value must NOT be zero, even if + * the platform supports disabling a powercap by setting its cap to + * zero (since SCMI v3.2): there are dedicated operations that should + * be used for that. (@cap_enable_set/get) + * @cap_enable_set: enable or disable the powercapping on the specified domain, + * if supported by the SCMI platform implementation. + * Note that, by the SCMI specification, the platform can + * silently ignore our disable request and decide to enforce + * anyway some other powercap value requested by another agent + * on the system: for this reason @cap_get and @cap_enable_get + * will always report the final platform view of the powercaps. + * @cap_enable_get: get the current CAP enable status for the specified domain. * @pai_get: get the current PAI value for the specified domain. * @pai_set: set the PAI value for the specified domain to the provided value. * @measurements_get: retrieve the current average power measurements for the @@ -662,6 +676,10 @@ struct scmi_powercap_proto_ops { u32 *power_cap); int (*cap_set)(const struct scmi_protocol_handle *ph, u32 domain_id, u32 power_cap, bool ignore_dresp); + int (*cap_enable_set)(const struct scmi_protocol_handle *ph, + u32 domain_id, bool enable); + int (*cap_enable_get)(const struct scmi_protocol_handle *ph, + u32 domain_id, bool *enable); int (*pai_get)(const struct scmi_protocol_handle *ph, u32 domain_id, u32 *pai); int (*pai_set)(const struct scmi_protocol_handle *ph, u32 domain_id, -- cgit From aaffb4cacd4c5546778a6e3b4bb2deef2dde4bd1 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Wed, 31 May 2023 16:20:39 +0100 Subject: powercap: arm_scmi: Add support for disabling powercaps on a zone Add support to disable/enable powercapping on a zone. Acked-by: Rafael J. Wysocki Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20230531152039.2363181-4-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- drivers/powercap/arm_scmi_powercap.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/powercap/arm_scmi_powercap.c b/drivers/powercap/arm_scmi_powercap.c index 05d0e516176a..5231f6d52ae3 100644 --- a/drivers/powercap/arm_scmi_powercap.c +++ b/drivers/powercap/arm_scmi_powercap.c @@ -70,10 +70,26 @@ static int scmi_powercap_get_power_uw(struct powercap_zone *pz, return 0; } +static int scmi_powercap_zone_enable_set(struct powercap_zone *pz, bool mode) +{ + struct scmi_powercap_zone *spz = to_scmi_powercap_zone(pz); + + return powercap_ops->cap_enable_set(spz->ph, spz->info->id, mode); +} + +static int scmi_powercap_zone_enable_get(struct powercap_zone *pz, bool *mode) +{ + struct scmi_powercap_zone *spz = to_scmi_powercap_zone(pz); + + return powercap_ops->cap_enable_get(spz->ph, spz->info->id, mode); +} + static const struct powercap_zone_ops zone_ops = { .get_max_power_range_uw = scmi_powercap_get_max_power_range_uw, .get_power_uw = scmi_powercap_get_power_uw, .release = scmi_powercap_zone_release, + .set_enable = scmi_powercap_zone_enable_set, + .get_enable = scmi_powercap_zone_enable_get, }; static void scmi_powercap_normalize_cap(const struct scmi_powercap_zone *spz, -- cgit From ea85370df14011255c60e1951ef4ef749806aa5c Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 22 May 2023 19:34:18 +0200 Subject: dt-bindings: soc: rockchip: add rk3588 pipe-phy syscon The pipe-phy syscon is used by rockchip,rk3588-naneng-combphy, which in turn is the PHY for USB3, PCIe and SATA. Acked-by: Rob Herring Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230522173423.64691-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index e8fca419cc8e..bf2370c66ed9 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -24,6 +24,7 @@ properties: - rockchip,rk3588-bigcore1-grf - rockchip,rk3588-ioc - rockchip,rk3588-php-grf + - rockchip,rk3588-pipe-phy-grf - rockchip,rk3588-sys-grf - rockchip,rk3588-pcie3-phy-grf - rockchip,rk3588-pcie3-pipe-grf -- cgit From b11403c93b7cddc8916b132a395b1524c02447a3 Mon Sep 17 00:00:00 2001 From: Osama Muhammad Date: Wed, 17 May 2023 22:24:31 +0500 Subject: wkup_m3_ipc.c: Fix error checking for debugfs_create_dir This patch fixes the error checking in wkup_m3_ipc.c in debugfs_create_dir. The correct way to check if an error occurred is 'IS_ERR' inline function. Signed-off-by: Osama Muhammad Link: https://lore.kernel.org/r/20230517172431.13507-1-osmtendev@gmail.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/wkup_m3_ipc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index c9197912ec24..3aff106fc11a 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -202,7 +202,7 @@ static int wkup_m3_ipc_dbg_init(struct wkup_m3_ipc *m3_ipc) { m3_ipc->dbg_path = debugfs_create_dir("wkup_m3_ipc", NULL); - if (!m3_ipc->dbg_path) + if (IS_ERR(m3_ipc->dbg_path)) return -EINVAL; (void)debugfs_create_file("enable_late_halt", 0644, -- cgit From c3a1c97c72601f8c00678f0ebafb574ec6e26d54 Mon Sep 17 00:00:00 2001 From: Viswanath L Date: Tue, 6 Jun 2023 16:36:07 +0100 Subject: soc/tegra: pmc: Add AON SW Wake support for Tegra234 Wake-up signal 83 on Tegra234 is triggered by software writing to WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0 register. This wake-up is mapped to CPU interrupt 179 and is used by the Sensor Processing Engine (SPE) in the Always-on (AON) power domain for waking up the system. Signed-off-by: Viswanath L Signed-off-by: Kartik Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 5d17799524c9..b562b005744d 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -4250,6 +4250,7 @@ static const struct tegra_wake_event tegra234_wake_events[] = { TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)), TEGRA_WAKE_IRQ("rtc", 73, 10), + TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179), }; static const struct tegra_pmc_soc tegra234_pmc_soc = { -- cgit From e180cf836433185d0674ade52f8db911d89f6422 Mon Sep 17 00:00:00 2001 From: Kartik Date: Tue, 6 Jun 2023 16:36:08 +0100 Subject: soc/tegra: fuse: Fix Tegra234 fuse size The Tegra234 fuse size is incorrectly defined as 0x98c. The actual size of the Tegra234 fuses is 0xf8c and so update the size of the Tegra234 fuses to fix this. Signed-off-by: Kartik Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index 932a03c64534..c759fb7c8adc 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -663,7 +663,7 @@ static const struct nvmem_keepout tegra234_fuse_keepouts[] = { static const struct tegra_fuse_info tegra234_fuse_info = { .read = tegra30_fuse_read, - .size = 0x98c, + .size = 0xf90, .spare = 0x280, }; -- cgit From e0d43ed6389733c518619ec5b0ad2052352e40a4 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Mon, 5 Jun 2023 13:20:24 +0200 Subject: bus: fsl-mc: fsl-mc-allocator: Initialize mc_bus_dev before use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes a clang compiler warning: >> drivers/bus/fsl-mc/fsl-mc-allocator.c:108:12: warning: variable 'mc_bus_dev' is uninitialized when used here [-Wuninitialized] dev_err(&mc_bus_dev->dev, "resource mismatch\n"); Fixes: b3134039c5b3 ("bus: fsl-mc: fsl-mc-allocator: Improve error reporting") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202306021936.OktTcMAT-lkp@intel.com/ Signed-off-by: Uwe Kleine-König Reviewed-by: Nathan Chancellor Signed-off-by: Li Yang --- drivers/bus/fsl-mc/fsl-mc-allocator.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/bus/fsl-mc/fsl-mc-allocator.c b/drivers/bus/fsl-mc/fsl-mc-allocator.c index 0ad68099684e..991273f956ce 100644 --- a/drivers/bus/fsl-mc/fsl-mc-allocator.c +++ b/drivers/bus/fsl-mc/fsl-mc-allocator.c @@ -103,14 +103,15 @@ static int __must_check fsl_mc_resource_pool_remove_device(struct fsl_mc_device struct fsl_mc_resource *resource; int error = -EINVAL; + mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); + mc_bus = to_fsl_mc_bus(mc_bus_dev); + resource = mc_dev->resource; if (!resource || resource->data != mc_dev) { dev_err(&mc_bus_dev->dev, "resource mismatch\n"); goto out; } - mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); - mc_bus = to_fsl_mc_bus(mc_bus_dev); res_pool = resource->parent_pool; if (res_pool != &mc_bus->resource_pools[resource->type]) { dev_err(&mc_bus_dev->dev, "pool mismatch\n"); -- cgit From fb9c384625dd604e8a5be1f42b35e83104b90670 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Mon, 5 Jun 2023 13:20:25 +0200 Subject: bus: fsl-mc: fsl-mc-allocator: Drop a write-only variable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes a clang compiler warning: drivers/bus/fsl-mc/fsl-mc-allocator.c:565:6: warning: variable 'free_count' set but not used [-Wunused-but-set-variable] int free_count = 0; Fixes: d8e026a44919 ("staging: fsl-mc: remove some superfluous WARN_ONs") Reported-by: kernel test robot Signed-off-by: Uwe Kleine-König Reviewed-by: Nathan Chancellor Signed-off-by: Li Yang --- drivers/bus/fsl-mc/fsl-mc-allocator.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/bus/fsl-mc/fsl-mc-allocator.c b/drivers/bus/fsl-mc/fsl-mc-allocator.c index 991273f956ce..b5e8c021fa1f 100644 --- a/drivers/bus/fsl-mc/fsl-mc-allocator.c +++ b/drivers/bus/fsl-mc/fsl-mc-allocator.c @@ -563,12 +563,9 @@ static void fsl_mc_cleanup_resource_pool(struct fsl_mc_device *mc_bus_dev, struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev); struct fsl_mc_resource_pool *res_pool = &mc_bus->resource_pools[pool_type]; - int free_count = 0; - list_for_each_entry_safe(resource, next, &res_pool->free_list, node) { - free_count++; + list_for_each_entry_safe(resource, next, &res_pool->free_list, node) devm_kfree(&mc_bus_dev->dev, resource); - } } void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev) -- cgit From 95094495401bdf6a0649d220dfd095e6079b5e39 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 31 May 2023 14:35:30 +0800 Subject: soc: mediatek: SVS: Fix MT8192 GPU node name Device tree node names should be generic. The planned device node name for the GPU, according to the bindings and posted DT changes, is "gpu", not "mali". Fix the GPU node name in the SVS driver to follow. Fixes: 0bbb09b2af9d ("soc: mediatek: SVS: add mt8192 SVS GPU driver") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230531063532.2240038-1-wenst@chromium.org Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 81585733c8a9..3a2f97cd5272 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2061,9 +2061,9 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) svsb = &svsp->banks[idx]; if (svsb->type == SVSB_HIGH) - svsb->opp_dev = svs_add_device_link(svsp, "mali"); + svsb->opp_dev = svs_add_device_link(svsp, "gpu"); else if (svsb->type == SVSB_LOW) - svsb->opp_dev = svs_get_subsys_device(svsp, "mali"); + svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); if (IS_ERR(svsb->opp_dev)) return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), -- cgit From 21d4631eedb136f101d2633b72cf42c20db79202 Mon Sep 17 00:00:00 2001 From: "Jason-JH.Lin" Date: Mon, 6 Mar 2023 16:06:59 +0800 Subject: soc: mediatek: remove DDP_DOMPONENT_DITHER from enum After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0, mmsys header can remove the useless DDP_COMPONENT_DITHER enum. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Acked-by: Matthias Brugger Link: https://lore.kernel.org/r/20230306080659.15261-3-jason-jh.lin@mediatek.com Signed-off-by: Matthias Brugger --- include/linux/soc/mediatek/mtk-mmsys.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 37544ea6286d..2475ef914746 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -27,8 +27,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_CCORR, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, - DDP_COMPONENT_DITHER, - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0, DDP_COMPONENT_DP_INTF1, -- cgit From bae9fb2d39b73822379b9bda02f3b9335fc77e13 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Jun 2023 16:42:24 +0200 Subject: soc/tegra: pmc: Simplify debugfs initialization debugfs calls should generally not be error-checked to simplify the case where debugfs is disabled. Since this driver is built-in and has the sysfs bind/unbind attributes disabled, it cannot be unloaded, so there is no need to hold onto a reference to the debugfs files that are created. We can further simplify this by moving the debugfs file creation to a later stage to avoid any cleanup we might have to do during error unwind operations. This is also a little cleaner because the debugfs file relies on data structures that are created at a later point than when the file was previously created. Suggested-by: Jon Hunter Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 26 ++++---------------------- 1 file changed, 4 insertions(+), 22 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index b562b005744d..438c30c5d473 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -396,7 +396,6 @@ struct tegra_pmc_soc { * @clk: pointer to pclk clock * @soc: pointer to SoC data structure * @tz_only: flag specifying if the PMC can only be accessed via TrustZone - * @debugfs: pointer to debugfs entry * @rate: currently configured rate of pclk * @suspend_mode: lowest suspend mode available * @cpu_good_time: CPU power good time (in microseconds) @@ -431,7 +430,6 @@ struct tegra_pmc { void __iomem *aotag; void __iomem *scratch; struct clk *clk; - struct dentry *debugfs; const struct tegra_pmc_soc *soc; bool tz_only; @@ -1190,16 +1188,6 @@ static int powergate_show(struct seq_file *s, void *data) DEFINE_SHOW_ATTRIBUTE(powergate); -static int tegra_powergate_debugfs_init(void) -{ - pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, - &powergate_fops); - if (!pmc->debugfs) - return -ENOMEM; - - return 0; -} - static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, struct device_node *np) { @@ -3026,19 +3014,13 @@ static int tegra_pmc_probe(struct platform_device *pdev) tegra_pmc_reset_sysfs_init(pmc); - if (IS_ENABLED(CONFIG_DEBUG_FS)) { - err = tegra_powergate_debugfs_init(); - if (err < 0) - goto cleanup_sysfs; - } - err = tegra_pmc_pinctrl_init(pmc); if (err) - goto cleanup_debugfs; + goto cleanup_sysfs; err = tegra_pmc_regmap_init(pmc); if (err < 0) - goto cleanup_debugfs; + goto cleanup_sysfs; err = tegra_powergate_init(pmc, pdev->dev.of_node); if (err < 0) @@ -3061,12 +3043,12 @@ static int tegra_pmc_probe(struct platform_device *pdev) if (pmc->soc->set_wake_filters) pmc->soc->set_wake_filters(pmc); + debugfs_create_file("powergate", 0444, NULL, NULL, &powergate_fops); + return 0; cleanup_powergates: tegra_powergate_remove_all(pdev->dev.of_node); -cleanup_debugfs: - debugfs_remove(pmc->debugfs); cleanup_sysfs: device_remove_file(&pdev->dev, &dev_attr_reset_reason); device_remove_file(&pdev->dev, &dev_attr_reset_level); -- cgit From c954cd7ad041251d903707c463a2c4d6cc30e5ae Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Jun 2023 16:42:25 +0200 Subject: soc/tegra: pmc: Use devm_clk_notifier_register() Move to the device-managed version of clk_notifier_register() to remove the need for manual cleanup. This fixes a potential issue where the clock notifier would stick around after the driver fails to probe at a later point. Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 438c30c5d473..162f52456f65 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -2992,7 +2992,8 @@ static int tegra_pmc_probe(struct platform_device *pdev) */ if (pmc->clk) { pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; - err = clk_notifier_register(pmc->clk, &pmc->clk_nb); + err = devm_clk_notifier_register(&pdev->dev, pmc->clk, + &pmc->clk_nb); if (err) { dev_err(&pdev->dev, "failed to register clk notifier\n"); @@ -3052,7 +3053,6 @@ cleanup_powergates: cleanup_sysfs: device_remove_file(&pdev->dev, &dev_attr_reset_reason); device_remove_file(&pdev->dev, &dev_attr_reset_level); - clk_notifier_unregister(pmc->clk, &pmc->clk_nb); return err; } -- cgit From 2abd484ca48f2e160c8d9c7241627c34855b621e Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Mon, 8 May 2023 15:20:54 +0300 Subject: firmware: tegra: bpmp: Add support for DRAM MRQ GSCs Implement support for DRAM MRQ GSCs. Signed-off-by: Peter De Schrijver [treding@nvidia.com: drop unnecessary discrimination enum] Signed-off-by: Thierry Reding --- drivers/firmware/tegra/bpmp-tegra186.c | 204 +++++++++++++++++++++++---------- drivers/firmware/tegra/bpmp.c | 4 +- 2 files changed, 147 insertions(+), 61 deletions(-) diff --git a/drivers/firmware/tegra/bpmp-tegra186.c b/drivers/firmware/tegra/bpmp-tegra186.c index 2e26199041cd..6f0d0511b486 100644 --- a/drivers/firmware/tegra/bpmp-tegra186.c +++ b/drivers/firmware/tegra/bpmp-tegra186.c @@ -4,7 +4,9 @@ */ #include +#include #include +#include #include #include @@ -18,7 +20,10 @@ struct tegra186_bpmp { struct { struct gen_pool *pool; - void __iomem *virt; + union { + void __iomem *sram; + void *dram; + }; dma_addr_t phys; } tx, rx; @@ -118,8 +123,13 @@ static int tegra186_bpmp_channel_init(struct tegra_bpmp_channel *channel, queue_size = tegra_ivc_total_queue_size(message_size); offset = queue_size * index; - iosys_map_set_vaddr_iomem(&rx, priv->rx.virt + offset); - iosys_map_set_vaddr_iomem(&tx, priv->tx.virt + offset); + if (priv->rx.pool) { + iosys_map_set_vaddr_iomem(&rx, priv->rx.sram + offset); + iosys_map_set_vaddr_iomem(&tx, priv->tx.sram + offset); + } else { + iosys_map_set_vaddr(&rx, priv->rx.dram + offset); + iosys_map_set_vaddr(&tx, priv->tx.dram + offset); + } err = tegra_ivc_init(channel->ivc, NULL, &rx, priv->rx.phys + offset, &tx, priv->tx.phys + offset, 1, message_size, tegra186_bpmp_ivc_notify, @@ -158,18 +168,72 @@ static void mbox_handle_rx(struct mbox_client *client, void *data) tegra_bpmp_handle_rx(bpmp); } -static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) +static void tegra186_bpmp_teardown_channels(struct tegra_bpmp *bpmp) { - struct tegra186_bpmp *priv; + struct tegra186_bpmp *priv = bpmp->priv; unsigned int i; + + for (i = 0; i < bpmp->threaded.count; i++) { + if (!bpmp->threaded_channels[i].bpmp) + continue; + + tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); + } + + tegra186_bpmp_channel_cleanup(bpmp->rx_channel); + tegra186_bpmp_channel_cleanup(bpmp->tx_channel); + + if (priv->tx.pool) { + gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.sram, 4096); + gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.sram, 4096); + } +} + +static int tegra186_bpmp_dram_init(struct tegra_bpmp *bpmp) +{ + struct tegra186_bpmp *priv = bpmp->priv; + struct device_node *np; + struct resource res; + size_t size; int err; - priv = devm_kzalloc(bpmp->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; + np = of_parse_phandle(bpmp->dev->of_node, "memory-region", 0); + if (!np) + return -ENODEV; - bpmp->priv = priv; - priv->parent = bpmp; + err = of_address_to_resource(np, 0, &res); + if (err < 0) { + dev_warn(bpmp->dev, "failed to parse memory region: %d\n", err); + return err; + } + + size = resource_size(&res); + + if (size < SZ_8K) { + dev_warn(bpmp->dev, "DRAM region must be larger than 8 KiB\n"); + return -EINVAL; + } + + priv->tx.phys = res.start; + priv->rx.phys = res.start + SZ_4K; + + priv->tx.dram = devm_memremap(bpmp->dev, priv->tx.phys, size, + MEMREMAP_WC); + if (IS_ERR(priv->tx.dram)) { + err = PTR_ERR(priv->tx.dram); + dev_warn(bpmp->dev, "failed to map DRAM region: %d\n", err); + return err; + } + + priv->rx.dram = priv->tx.dram + SZ_4K; + + return 0; +} + +static int tegra186_bpmp_sram_init(struct tegra_bpmp *bpmp) +{ + struct tegra186_bpmp *priv = bpmp->priv; + int err; priv->tx.pool = of_gen_pool_get(bpmp->dev->of_node, "shmem", 0); if (!priv->tx.pool) { @@ -177,8 +241,9 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) return -EPROBE_DEFER; } - priv->tx.virt = (void __iomem *)gen_pool_dma_alloc(priv->tx.pool, 4096, &priv->tx.phys); - if (!priv->tx.virt) { + priv->tx.sram = (void __iomem *)gen_pool_dma_alloc(priv->tx.pool, 4096, + &priv->tx.phys); + if (!priv->tx.sram) { dev_err(bpmp->dev, "failed to allocate from TX pool\n"); return -ENOMEM; } @@ -190,22 +255,45 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) goto free_tx; } - priv->rx.virt = (void __iomem *)gen_pool_dma_alloc(priv->rx.pool, 4096, &priv->rx.phys); - if (!priv->rx.virt) { + priv->rx.sram = (void __iomem *)gen_pool_dma_alloc(priv->rx.pool, 4096, + &priv->rx.phys); + if (!priv->rx.sram) { dev_err(bpmp->dev, "failed to allocate from RX pool\n"); err = -ENOMEM; goto free_tx; } + return 0; + +free_tx: + gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.sram, 4096); + + return err; +} + +static int tegra186_bpmp_setup_channels(struct tegra_bpmp *bpmp) +{ + unsigned int i; + int err; + + err = tegra186_bpmp_dram_init(bpmp); + if (err == -ENODEV) { + err = tegra186_bpmp_sram_init(bpmp); + if (err < 0) + return err; + } + err = tegra186_bpmp_channel_init(bpmp->tx_channel, bpmp, bpmp->soc->channels.cpu_tx.offset); if (err < 0) - goto free_rx; + return err; err = tegra186_bpmp_channel_init(bpmp->rx_channel, bpmp, bpmp->soc->channels.cpu_rx.offset); - if (err < 0) - goto cleanup_tx_channel; + if (err < 0) { + tegra186_bpmp_channel_cleanup(bpmp->tx_channel); + return err; + } for (i = 0; i < bpmp->threaded.count; i++) { unsigned int index = bpmp->soc->channels.thread.offset + i; @@ -213,9 +301,43 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) err = tegra186_bpmp_channel_init(&bpmp->threaded_channels[i], bpmp, index); if (err < 0) - goto cleanup_channels; + break; } + if (err < 0) + tegra186_bpmp_teardown_channels(bpmp); + + return err; +} + +static void tegra186_bpmp_reset_channels(struct tegra_bpmp *bpmp) +{ + unsigned int i; + + /* reset message channels */ + tegra186_bpmp_channel_reset(bpmp->tx_channel); + tegra186_bpmp_channel_reset(bpmp->rx_channel); + + for (i = 0; i < bpmp->threaded.count; i++) + tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); +} + +static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) +{ + struct tegra186_bpmp *priv; + int err; + + priv = devm_kzalloc(bpmp->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->parent = bpmp; + bpmp->priv = priv; + + err = tegra186_bpmp_setup_channels(bpmp); + if (err < 0) + return err; + /* mbox registration */ priv->mbox.client.dev = bpmp->dev; priv->mbox.client.rx_callback = mbox_handle_rx; @@ -226,63 +348,27 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) if (IS_ERR(priv->mbox.channel)) { err = PTR_ERR(priv->mbox.channel); dev_err(bpmp->dev, "failed to get HSP mailbox: %d\n", err); - goto cleanup_channels; + tegra186_bpmp_teardown_channels(bpmp); + return err; } - tegra186_bpmp_channel_reset(bpmp->tx_channel); - tegra186_bpmp_channel_reset(bpmp->rx_channel); - - for (i = 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); + tegra186_bpmp_reset_channels(bpmp); return 0; - -cleanup_channels: - for (i = 0; i < bpmp->threaded.count; i++) { - if (!bpmp->threaded_channels[i].bpmp) - continue; - - tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); - } - - tegra186_bpmp_channel_cleanup(bpmp->rx_channel); -cleanup_tx_channel: - tegra186_bpmp_channel_cleanup(bpmp->tx_channel); -free_rx: - gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.virt, 4096); -free_tx: - gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.virt, 4096); - - return err; } static void tegra186_bpmp_deinit(struct tegra_bpmp *bpmp) { struct tegra186_bpmp *priv = bpmp->priv; - unsigned int i; mbox_free_channel(priv->mbox.channel); - for (i = 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); - - tegra186_bpmp_channel_cleanup(bpmp->rx_channel); - tegra186_bpmp_channel_cleanup(bpmp->tx_channel); - - gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.virt, 4096); - gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.virt, 4096); + tegra186_bpmp_teardown_channels(bpmp); } static int tegra186_bpmp_resume(struct tegra_bpmp *bpmp) { - unsigned int i; - - /* reset message channels */ - tegra186_bpmp_channel_reset(bpmp->tx_channel); - tegra186_bpmp_channel_reset(bpmp->rx_channel); - - for (i = 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); + tegra186_bpmp_reset_channels(bpmp); return 0; } diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c index 8b5e5daa9fae..17bd3590aaa2 100644 --- a/drivers/firmware/tegra/bpmp.c +++ b/drivers/firmware/tegra/bpmp.c @@ -735,6 +735,8 @@ static int tegra_bpmp_probe(struct platform_device *pdev) if (!bpmp->threaded_channels) return -ENOMEM; + platform_set_drvdata(pdev, bpmp); + err = bpmp->soc->ops->init(bpmp); if (err < 0) return err; @@ -758,8 +760,6 @@ static int tegra_bpmp_probe(struct platform_device *pdev) dev_info(&pdev->dev, "firmware: %.*s\n", (int)sizeof(tag), tag); - platform_set_drvdata(pdev, bpmp); - err = of_platform_default_populate(pdev->dev.of_node, NULL, &pdev->dev); if (err < 0) goto free_mrq; -- cgit From a10b3841f901714dbe16a8f9b0f2bbe1034e6454 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 30 Apr 2023 19:49:50 -0700 Subject: soc: rockchip: dtpm: use C99 array init syntax Eliminate sparse warnings in soc/rockchip/dtpm.c: drivers/soc/rockchip/dtpm.c:15:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:17:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:20:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:23:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:26:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:29:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:32:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:35:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:38:12: sparse: warning: obsolete array initializer, use C99 syntax drivers/soc/rockchip/dtpm.c:41:12: sparse: warning: obsolete array initializer, use C99 syntax Fixes: b9d6c47a2be8 ("rockchip/soc/drivers: Add DTPM description for rk3399") Signed-off-by: Randy Dunlap Cc: Daniel Lezcano Cc: Heiko Stuebner Cc: linux-rockchip@lists.infradead.org Acked-by: Daniel Lezcano Link: https://lore.kernel.org/r/20230501024950.31518-1-rdunlap@infradead.org Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/dtpm.c | 54 ++++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/soc/rockchip/dtpm.c b/drivers/soc/rockchip/dtpm.c index 5a23784b5221..b36d4f752c30 100644 --- a/drivers/soc/rockchip/dtpm.c +++ b/drivers/soc/rockchip/dtpm.c @@ -12,33 +12,33 @@ #include static struct dtpm_node __initdata rk3399_hierarchy[] = { - [0]{ .name = "rk3399", - .type = DTPM_NODE_VIRTUAL }, - [1]{ .name = "package", - .type = DTPM_NODE_VIRTUAL, - .parent = &rk3399_hierarchy[0] }, - [2]{ .name = "/cpus/cpu@0", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [3]{ .name = "/cpus/cpu@1", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [4]{ .name = "/cpus/cpu@2", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [5]{ .name = "/cpus/cpu@3", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [6]{ .name = "/cpus/cpu@100", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [7]{ .name = "/cpus/cpu@101", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [8]{ .name = "/gpu@ff9a0000", - .type = DTPM_NODE_DT, - .parent = &rk3399_hierarchy[1] }, - [9]{ /* sentinel */ } + [0] = { .name = "rk3399", + .type = DTPM_NODE_VIRTUAL }, + [1] = { .name = "package", + .type = DTPM_NODE_VIRTUAL, + .parent = &rk3399_hierarchy[0] }, + [2] = { .name = "/cpus/cpu@0", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [3] = { .name = "/cpus/cpu@1", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [4] = { .name = "/cpus/cpu@2", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [5] = { .name = "/cpus/cpu@3", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [6] = { .name = "/cpus/cpu@100", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [7] = { .name = "/cpus/cpu@101", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [8] = { .name = "/gpu@ff9a0000", + .type = DTPM_NODE_DT, + .parent = &rk3399_hierarchy[1] }, + [9] = { /* sentinel */ } }; static struct of_device_id __initdata rockchip_dtpm_match_table[] = { -- cgit From 6a66fb9ffe7b4558c04f73593c01ee484a5c9ddf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 9 Jun 2023 16:07:20 +0200 Subject: dt-bindings: memory-controllers: drop unneeded quotes Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint. Link: https://lore.kernel.org/r/20230609140720.64743-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml | 2 +- Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml index 2fa44951cfde..f54e553e6c0e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml @@ -165,7 +165,7 @@ patternProperties: const: 0 lpddr2: - $ref: "ddr/jedec,lpddr2.yaml#" + $ref: ddr/jedec,lpddr2.yaml# type: object patternProperties: diff --git a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml index bc9406929f6c..b049837ee669 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml @@ -129,7 +129,7 @@ patternProperties: The child device node represents the device connected to the GPMC bus. The device can be a NAND chip, SRAM device, NOR device or an ASIC. - $ref: "ti,gpmc-child.yaml" + $ref: ti,gpmc-child.yaml required: -- cgit From 0d25da8e7e1e35bdbb521d586be1954bdedd1cca Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 12 Jun 2023 14:58:04 -0700 Subject: soc: qcom: mdt_loader: Fix split image detection The enhanced detection introduced in commit '210d12c8197a ("soc: qcom: mdt_loader: Enhance split binary detection")' requires that all segments lies within the file on disk. But the Qualcomm firmware files consistently has a BSS-like segment at the end, with a p_offset aligned to the next 4k boundary. As the p_size is 0 and there's nothing to load, the image is not padded to cover this (empty) segment. Ignore zero-sized segments when determining if the image is split, to avoid this problem. Fixes: 210d12c8197a ("soc: qcom: mdt_loader: Enhance split binary detection") Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov # qrb5165-rb5 Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230612215804.1883458-1-quic_bjorande@quicinc.com --- drivers/soc/qcom/mdt_loader.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index 9418993a3a92..6f177e46fa0f 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -275,6 +275,14 @@ static bool qcom_mdt_bins_are_split(const struct firmware *fw, const char *fw_na phdrs = (struct elf32_phdr *)(ehdr + 1); for (i = 0; i < ehdr->e_phnum; i++) { + /* + * The size of the MDT file is not padded to include any + * zero-sized segments at the end. Ignore these, as they should + * not affect the decision about image being split or not. + */ + if (!phdrs[i].p_filesz) + continue; + seg_start = phdrs[i].p_offset; seg_end = phdrs[i].p_offset + phdrs[i].p_filesz; if (seg_start > fw->size || seg_end > fw->size) -- cgit From 677b9e85e8691c0bddc35eebf6d01836e109e5f4 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Fri, 9 Jun 2023 17:20:35 +0530 Subject: dt-bindings: firmware: scm: Add compatible for SDX75 Add devicetree compatible for SCM present in SDX75 platform. Signed-off-by: Rohit Agarwal Acked-by: Conor Dooley Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1686311438-24177-3-git-send-email-quic_rohiagar@quicinc.com --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 367d04ad1923..09073e1d88ff 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -51,6 +51,7 @@ properties: - qcom,scm-sdm845 - qcom,scm-sdx55 - qcom,scm-sdx65 + - qcom,scm-sdx75 - qcom,scm-sm6115 - qcom,scm-sm6125 - qcom,scm-sm6350 -- cgit From 158826c73d48097f843bacc1bcafa6dbc114f4e5 Mon Sep 17 00:00:00 2001 From: Naman Jain Date: Tue, 6 Jun 2023 19:16:25 +0530 Subject: soc: qcom: socinfo: Add support for new fields in revision 18 Add support for below fields coming in socinfo structure under v18: * num_kvps: number of key value pairs (KVP) * kvps_offset: the offset of the KVP table from the base address of socinfo structure in SMEM KVP table has boolean values for certain feature flags, used to determine hardware configuration. Signed-off-by: Naman Jain Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230606134626.18790-2-quic_namajain@quicinc.com --- drivers/soc/qcom/socinfo.c | 1 + include/linux/soc/qcom/socinfo.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index dfd4330daef5..cb70f8439cfa 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -565,6 +565,7 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, &qcom_socinfo->info.fmt); switch (qcom_socinfo->info.fmt) { + case SOCINFO_VERSION(0, 18): case SOCINFO_VERSION(0, 17): qcom_socinfo->info.oem_variant = __le32_to_cpu(info->oem_variant); debugfs_create_u32("oem_variant", 0444, qcom_socinfo->dbg_root, diff --git a/include/linux/soc/qcom/socinfo.h b/include/linux/soc/qcom/socinfo.h index d1cbc49a2a2d..3cc266d8a8b4 100644 --- a/include/linux/soc/qcom/socinfo.h +++ b/include/linux/soc/qcom/socinfo.h @@ -65,6 +65,9 @@ struct socinfo { __le32 nnum_partname_mapping; /* Version 17 */ __le32 oem_variant; + /* Version 18 */ + __le32 num_kvps; + __le32 kvps_offset; }; #endif -- cgit From d9c2a255cfe026c8bf85a39631734f022ecefaff Mon Sep 17 00:00:00 2001 From: Naman Jain Date: Tue, 6 Jun 2023 19:16:26 +0530 Subject: soc: qcom: socinfo: Add support for new fields in revision 19 Add support for below fields coming in socinfo structure under v19: * num_func_clusters: number of clusters with at least one functional core * boot_cluster: cluster selected as boot cluster * boot_core: core selected as boot core While at it, rename some variables to align them with their functionalities. Signed-off-by: Naman Jain Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230606134626.18790-3-quic_namajain@quicinc.com --- drivers/soc/qcom/socinfo.c | 32 ++++++++++++++++++++++++-------- include/linux/soc/qcom/socinfo.h | 8 ++++++-- 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index cb70f8439cfa..a30d8bb6e938 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -133,12 +133,15 @@ struct socinfo_params { u32 nproduct_id; u32 num_clusters; u32 ncluster_array_offset; - u32 num_defective_parts; - u32 ndefective_parts_array_offset; + u32 num_subset_parts; + u32 nsubset_parts_array_offset; u32 nmodem_supported; u32 feature_code; u32 pcode; u32 oem_variant; + u32 num_func_clusters; + u32 boot_cluster; + u32 boot_core; }; struct smem_image_version { @@ -565,6 +568,18 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, &qcom_socinfo->info.fmt); switch (qcom_socinfo->info.fmt) { + case SOCINFO_VERSION(0, 19): + qcom_socinfo->info.num_func_clusters = __le32_to_cpu(info->num_func_clusters); + qcom_socinfo->info.boot_cluster = __le32_to_cpu(info->boot_cluster); + qcom_socinfo->info.boot_core = __le32_to_cpu(info->boot_core); + + debugfs_create_u32("num_func_clusters", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.num_func_clusters); + debugfs_create_u32("boot_cluster", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.boot_cluster); + debugfs_create_u32("boot_core", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.boot_core); + fallthrough; case SOCINFO_VERSION(0, 18): case SOCINFO_VERSION(0, 17): qcom_socinfo->info.oem_variant = __le32_to_cpu(info->oem_variant); @@ -589,17 +604,18 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, case SOCINFO_VERSION(0, 14): qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters); qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset); - qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts); - qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset); + qcom_socinfo->info.num_subset_parts = __le32_to_cpu(info->num_subset_parts); + qcom_socinfo->info.nsubset_parts_array_offset = + __le32_to_cpu(info->nsubset_parts_array_offset); debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.num_clusters); debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.ncluster_array_offset); - debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root, - &qcom_socinfo->info.num_defective_parts); - debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root, - &qcom_socinfo->info.ndefective_parts_array_offset); + debugfs_create_u32("num_subset_parts", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.num_subset_parts); + debugfs_create_u32("nsubset_parts_array_offset", 0444, qcom_socinfo->dbg_root, + &qcom_socinfo->info.nsubset_parts_array_offset); fallthrough; case SOCINFO_VERSION(0, 13): qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id); diff --git a/include/linux/soc/qcom/socinfo.h b/include/linux/soc/qcom/socinfo.h index 3cc266d8a8b4..e78777bb0f4a 100644 --- a/include/linux/soc/qcom/socinfo.h +++ b/include/linux/soc/qcom/socinfo.h @@ -54,8 +54,8 @@ struct socinfo { /* Version 14 */ __le32 num_clusters; __le32 ncluster_array_offset; - __le32 num_defective_parts; - __le32 ndefective_parts_array_offset; + __le32 num_subset_parts; + __le32 nsubset_parts_array_offset; /* Version 15 */ __le32 nmodem_supported; /* Version 16 */ @@ -68,6 +68,10 @@ struct socinfo { /* Version 18 */ __le32 num_kvps; __le32 kvps_offset; + /* Version 19 */ + __le32 num_func_clusters; + __le32 boot_cluster; + __le32 boot_core; }; #endif -- cgit From 3aed112953b1877ede66ae77afa4e5a5024be7cb Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 6 Jun 2023 11:21:22 +0300 Subject: soc: qcom: Fix a IS_ERR() vs NULL bug in probe The devm_ioremap() function returns NULL on error, it never returns error pointers. Fixes: a77b2a0b1280 ("soc: qcom: Introduce RPM master stats driver") Signed-off-by: Dan Carpenter Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/ZH7sgpLAN23bCz9v@moroto --- drivers/soc/qcom/rpm_master_stats.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/rpm_master_stats.c b/drivers/soc/qcom/rpm_master_stats.c index 6dd98b9f7129..9ca13bcf67d3 100644 --- a/drivers/soc/qcom/rpm_master_stats.c +++ b/drivers/soc/qcom/rpm_master_stats.c @@ -105,7 +105,7 @@ static int master_stats_probe(struct platform_device *pdev) } data[i].base = devm_ioremap(dev, res.start, resource_size(&res)); - if (IS_ERR(data[i].base)) { + if (!data[i].base) { debugfs_remove_recursive(root); return dev_err_probe(dev, -EINVAL, "Could not map the MSG RAM slice idx %d!\n", i); -- cgit From b56715957bc820ee4b01adfd6fa63fea63cd212a Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 5 Jun 2023 13:35:28 +0530 Subject: dt-bindings: arm: qcom,ids: add SoC ID for IPQ5300 Add the SoC ID for IPQ5300, which belong to the family of IPQ5332 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230605080531.3879-2-quic_kathirav@quicinc.com --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 69c2d8fa79f4..bcbe9ee2cdaf 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -258,6 +258,7 @@ #define QCOM_ID_IPQ5322 593 #define QCOM_ID_IPQ5312 594 #define QCOM_ID_IPQ5302 595 +#define QCOM_ID_IPQ5300 624 /* * The board type and revision information, used by Qualcomm bootloaders and -- cgit From f471f91a0d63539107004a8e826ff017ed4d2588 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 5 Jun 2023 13:35:29 +0530 Subject: soc: qcom: socinfo: Add Soc ID for IPQ5300 Add the SoC ID for IPQ5300, which belong to the family of IPQ5332 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230605080531.3879-3-quic_kathirav@quicinc.com --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index a30d8bb6e938..4d49945b3a35 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -414,6 +414,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(IPQ5322) }, { qcom_board_id(IPQ5312) }, { qcom_board_id(IPQ5302) }, + { qcom_board_id(IPQ5300) }, }; static const char *socinfo_machine(struct device *dev, unsigned int id) -- cgit From 66171d3fa08eca4e10384eee385cbdaaea6bb43e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 31 May 2023 15:22:35 +0200 Subject: dt-bindings: soc: qcom,rpmh-rsc: Require power-domains The Linux RPMh implementation refrains from sending some RPMh votes until the system is about to enter suspend (which is indicated by all CPU cores entering a low-power state). Lack of the power-domains property will make it such that these votes are never sent. Require the power-domains property as discussed in [1]. [1] https://lore.kernel.org/linux-arm-msm/20230512150425.3171122-1-quic_bjorande@quicinc.com/ Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531-topic-rsc-v1-1-b4a985f57b8b@linaro.org --- Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml index a4046ba60846..af632d0e0355 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml @@ -124,6 +124,7 @@ required: - qcom,tcs-offset - reg - reg-names + - power-domains additionalProperties: false @@ -179,6 +180,7 @@ examples: , , ; + power-domains = <&CLUSTER_PD>; }; - | -- cgit From 1c8267cd14ed6a592a2c2a8eb0fefad4eabe5b4f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 31 May 2023 18:33:03 +0200 Subject: soc: qcom: icc-bwmon: Fix MSM8998 count unit MSM8998's BWMON counts in megabytes. Fix it. Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230531-topic-msm8998-bwmon-v1-1-454f9d550ee5@linaro.org --- drivers/soc/qcom/icc-bwmon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index fd58c5b69897..6c6da73214e4 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -806,7 +806,7 @@ static int bwmon_remove(struct platform_device *pdev) static const struct icc_bwmon_data msm8998_bwmon_data = { .sample_ms = 4, - .count_unit_kb = 64, + .count_unit_kb = 1024, .default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */ .default_medbw_kbps = 512 * 1024, /* 512 MBps */ .default_lowbw_kbps = 0, -- cgit From 8d66f7a07bc1412c7ffd9aa45602eb6e527dd87e Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 22 May 2023 20:42:05 +0530 Subject: dt-bindings: sram: qcom,imem: document qdu1000 Add compatible for QDU1000 and QRU1000 SoCs IMEM. Signed-off-by: Komal Bajaj Acked-by: Conor Dooley Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230522151206.22654-2-quic_kbajaj@quicinc.com --- Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index d9599ee51204..8025a852bc9c 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -21,6 +21,7 @@ properties: - qcom,msm8226-imem - qcom,msm8974-imem - qcom,qcs404-imem + - qcom,qdu1000-imem - qcom,sc7180-imem - qcom,sc7280-imem - qcom,sdm630-imem -- cgit From 5d85ea2c879781d296bd770f562d33a58161d2b1 Mon Sep 17 00:00:00 2001 From: Vijaya Krishna Nivarthi Date: Wed, 14 Jun 2023 16:58:07 +0530 Subject: soc: qcom: geni-se: Do not bother about enable/disable of interrupts in secondary sequencer The select_fifo/dma_mode() functions in geni driver enable/disable interrupts (secondary included) conditionally for non-uart modes, while uart is supposed to manage this internally. However, only uart uses secondary IRQs while spi, i2c do not care about these at all making their enablement (or disablement) totally unnecessary for these protos. Similarly, select_gpi_mode() also does disable s_irq and its useless again. Drop enabling/disabling secondary IRQs. This doesn't solve any observed problem but only gets rid of code pieces that are not required. Signed-off-by: Vijaya Krishna Nivarthi Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1686742087-30731-1-git-send-email-quic_vnivarth@quicinc.com --- drivers/soc/qcom/qcom-geni-se.c | 28 ++++------------------------ 1 file changed, 4 insertions(+), 24 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 795a2e1d59b3..0e01a31dde7a 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -281,27 +281,14 @@ static void geni_se_select_fifo_mode(struct geni_se *se) geni_se_irq_clear(se); - /* - * The RX path for the UART is asynchronous and so needs more - * complex logic for enabling / disabling its interrupts. - * - * Specific notes: - * - The done and TX-related interrupts are managed manually. - * - We don't RX from the main sequencer (we use the secondary) so - * we don't need the RX-related interrupts enabled in the main - * sequencer for UART. - */ + /* UART driver manages enabling / disabling interrupts internally */ if (proto != GENI_SE_UART) { + /* Non-UART use only primary sequencer so dont bother about S_IRQ */ val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; if (val != val_old) writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); - - val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); - val |= S_CMD_DONE_EN; - if (val != val_old) - writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); } val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); @@ -317,17 +304,14 @@ static void geni_se_select_dma_mode(struct geni_se *se) geni_se_irq_clear(se); + /* UART driver manages enabling / disabling interrupts internally */ if (proto != GENI_SE_UART) { + /* Non-UART use only primary sequencer so dont bother about S_IRQ */ val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); if (val != val_old) writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); - - val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); - val &= ~S_CMD_DONE_EN; - if (val != val_old) - writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); } val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); @@ -344,10 +328,6 @@ static void geni_se_select_gpi_mode(struct geni_se *se) writel(0, se->base + SE_IRQ_EN); - val = readl(se->base + SE_GENI_S_IRQ_EN); - val &= ~S_CMD_DONE_EN; - writel(val, se->base + SE_GENI_S_IRQ_EN); - val = readl(se->base + SE_GENI_M_IRQ_EN); val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); -- cgit From 6a8b7e80105416cc7324fda295608ea2d3f98862 Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Tue, 13 Jun 2023 09:18:53 +0800 Subject: tee: optee: Use kmemdup() to replace kmalloc + memcpy Use kmemdup rather than duplicating its implementation. ./drivers/tee/optee/smc_abi.c:1542:12-19: WARNING opportunity for kmemdup. Reported-by: Abaci Robot Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5480 Signed-off-by: Jiapeng Chong Reviewed-by: Sumit Garg Signed-off-by: Jens Wiklander --- drivers/tee/optee/smc_abi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c index 49702cb08f4f..54414d4def7e 100644 --- a/drivers/tee/optee/smc_abi.c +++ b/drivers/tee/optee/smc_abi.c @@ -1539,12 +1539,11 @@ static int optee_load_fw(struct platform_device *pdev, * This uses the GFP_DMA flag to ensure we are allocated memory in the * 32-bit space since TF-A cannot map memory beyond the 32-bit boundary. */ - data_buf = kmalloc(fw->size, GFP_KERNEL | GFP_DMA); + data_buf = kmemdup(fw->data, fw->size, GFP_KERNEL | GFP_DMA); if (!data_buf) { rc = -ENOMEM; goto fw_err; } - memcpy(data_buf, fw->data, fw->size); data_pa = virt_to_phys(data_buf); reg_pair_from_64(&data_pa_high, &data_pa_low, data_pa); reg_pair_from_64(&data_size_high, &data_size_low, data_size); -- cgit From 0bb4644d583789c97e74d3e3047189f0c59c4742 Mon Sep 17 00:00:00 2001 From: Alexey Romanov Date: Sat, 10 Jun 2023 12:04:14 +0300 Subject: drivers: meson: secure-pwrc: always enable DMA domain Starting from commit e45f243409db ("firmware: meson_sm: populate platform devices from sm device tree data") pwrc is probed successfully and disables unused pwr domains. By A1 SoC family design, any TEE requires DMA pwr domain always enabled. Fixes: b3dde5013e13 ("soc: amlogic: Add support for Secure power domains controller") Signed-off-by: Alexey Romanov Acked-by: Neil Armstrong Link: https://lore.kernel.org/r/20230610090414.90529-1-avromanov@sberdevices.ru [narmstrong: added fixes tag] Signed-off-by: Neil Armstrong --- drivers/soc/amlogic/meson-secure-pwrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c b/drivers/soc/amlogic/meson-secure-pwrc.c index e93518763526..25b4b71df9b8 100644 --- a/drivers/soc/amlogic/meson-secure-pwrc.c +++ b/drivers/soc/amlogic/meson-secure-pwrc.c @@ -105,7 +105,7 @@ static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = { SEC_PD(ACODEC, 0), SEC_PD(AUDIO, 0), SEC_PD(OTP, 0), - SEC_PD(DMA, 0), + SEC_PD(DMA, GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_IRQ_SAFE), SEC_PD(SD_EMMC, 0), SEC_PD(RAMA, 0), /* SRAMB is used as ATF runtime memory, and should be always on */ -- cgit From 9e70e49474bb37ba8f43336d8a775d503b20aebc Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Sun, 15 Jan 2023 15:26:05 +0100 Subject: MAINTAINERS: add PHY-related files to Amlogic SoC file list Add PHY-related files to the Amlogic SoC file list. Signed-off-by: Heiner Kallweit Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/38f87b22-d9a8-b8d8-ba7b-a2c2d7311b04@gmail.com Signed-off-by: Neil Armstrong --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e..9f769aa65936 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1915,10 +1915,12 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-amlogic@lists.infradead.org S: Maintained W: http://linux-meson.com/ +F: Documentation/devicetree/bindings/phy/amlogic* F: arch/arm/boot/dts/meson* F: arch/arm/mach-meson/ F: arch/arm64/boot/dts/amlogic/ F: drivers/mmc/host/meson* +F: drivers/phy/amlogic/ F: drivers/pinctrl/meson/ F: drivers/rtc/rtc-meson* F: drivers/soc/amlogic/ -- cgit From 6b0139b372d40bd5dafc140b6618b57d13211168 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Sun, 12 Mar 2023 22:29:07 +0100 Subject: dt-bindings: interrupt-controller: Convert Amlogic Meson GPIO interrupt controller binding Convert Amlogic Meson GPIO interrupt controller binding to yaml. Reviewed-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Heiner Kallweit Link: https://lore.kernel.org/r/e06e9f26-cf55-5596-c799-d698e9d7b409@gmail.com Signed-off-by: Neil Armstrong --- .../amlogic,meson-gpio-intc.txt | 38 ------------ .../amlogic,meson-gpio-intc.yaml | 72 ++++++++++++++++++++++ 2 files changed, 72 insertions(+), 38 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt deleted file mode 100644 index bde63f8f090e..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ /dev/null @@ -1,38 +0,0 @@ -Amlogic meson GPIO interrupt controller - -Meson SoCs contains an interrupt controller which is able to watch the SoC -pads and generate an interrupt on edge or level. The controller is essentially -a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge -or level and polarity. It does not expose all 256 mux inputs because the -documentation shows that the upper part is not mapped to any pad. The actual -number of interrupt exposed depends on the SoC. - -Required properties: - -- compatible : must have "amlogic,meson8-gpio-intc" and either - "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or - "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or - "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or - "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912) - "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) - "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2) - "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3) - "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L) - "amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2) -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 2. -- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These - are the hwirqs used on the parent interrupt controller. - -Example: - -gpio_interrupt: interrupt-controller@9880 { - compatible = "amlogic,meson-gxbb-gpio-intc", - "amlogic,meson-gpio-intc"; - reg = <0x0 0x9880 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - meson,channel-interrupts = <64 65 66 67 68 69 70 71>; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml new file mode 100644 index 000000000000..e84e4f33b358 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/amlogic,meson-gpio-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson GPIO interrupt controller + +maintainers: + - Heiner Kallweit + +description: | + Meson SoCs contains an interrupt controller which is able to watch the SoC + pads and generate an interrupt on edge or level. The controller is essentially + a 256 pads to 8 or 12 GIC interrupt multiplexer, with a filter block to select + edge or level and polarity. It does not expose all 256 mux inputs because the + documentation shows that the upper part is not mapped to any pad. The actual + number of interrupts exposed depends on the SoC. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + oneOf: + - const: amlogic,meson-gpio-intc + - items: + - enum: + - amlogic,meson8-gpio-intc + - amlogic,meson8b-gpio-intc + - amlogic,meson-gxbb-gpio-intc + - amlogic,meson-gxl-gpio-intc + - amlogic,meson-axg-gpio-intc + - amlogic,meson-g12a-gpio-intc + - amlogic,meson-sm1-gpio-intc + - amlogic,meson-a1-gpio-intc + - amlogic,meson-s4-gpio-intc + - const: amlogic,meson-gpio-intc + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + amlogic,channel-interrupts: + description: Array with the upstream hwirq numbers + minItems: 8 + maxItems: 12 + $ref: /schemas/types.yaml#/definitions/uint32-array + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - amlogic,channel-interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@9880 { + compatible = "amlogic,meson-gxbb-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x9880 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; + }; -- cgit