From a8613e7070e771cea90d93eb1e8397246883065a Mon Sep 17 00:00:00 2001 From: Julien Grall Date: Thu, 3 Oct 2019 12:12:11 +0100 Subject: docs/arm64: cpu-feature-registers: Documents missing visible fields A couple of fields visible to userspace are not described in the documentation. So update it. Acked-by: Will Deacon Signed-off-by: Julien Grall Signed-off-by: Catalin Marinas --- Documentation/arm64/cpu-feature-registers.rst | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/arm64/cpu-feature-registers.rst') diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst index 2955287e9acc..ffcf4e2c71ef 100644 --- a/Documentation/arm64/cpu-feature-registers.rst +++ b/Documentation/arm64/cpu-feature-registers.rst @@ -193,6 +193,10 @@ infrastructure: +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ + | SB | [36-39] | y | + +------------------------------+---------+---------+ + | FRINTTS | [32-35] | y | + +------------------------------+---------+---------+ | GPI | [31-28] | y | +------------------------------+---------+---------+ | GPA | [27-24] | y | -- cgit From ade12b8631d91b9c2849facb0a1dc3af317ecbb3 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Wed, 23 Oct 2019 18:52:22 +0100 Subject: arm64: docs: cpu-feature-registers: Document ID_AA64PFR1_EL1 Commit d71be2b6c0e1 ("arm64: cpufeature: Detect SSBS and advertise to userspace") exposes ID_AA64PFR1_EL1 to userspace, but didn't update the documentation to match. Add it. Acked-by: Will Deacon Signed-off-by: Dave Martin Signed-off-by: Mark Brown Signed-off-by: Catalin Marinas --- Documentation/arm64/cpu-feature-registers.rst | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'Documentation/arm64/cpu-feature-registers.rst') diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst index 2955287e9acc..b86828f86e39 100644 --- a/Documentation/arm64/cpu-feature-registers.rst +++ b/Documentation/arm64/cpu-feature-registers.rst @@ -168,8 +168,15 @@ infrastructure: +------------------------------+---------+---------+ - 3) MIDR_EL1 - Main ID Register + 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 + +------------------------------+---------+---------+ + | Name | bits | visible | + +------------------------------+---------+---------+ + | SSBS | [7-4] | y | + +------------------------------+---------+---------+ + + 4) MIDR_EL1 - Main ID Register +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ @@ -188,7 +195,7 @@ infrastructure: as available on the CPU where it is fetched and is not a system wide safe value. - 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 + 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 +------------------------------+---------+---------+ | Name | bits | visible | @@ -210,7 +217,7 @@ infrastructure: | DPB | [3-0] | y | +------------------------------+---------+---------+ - 5) ID_AA64MMFR2_EL1 - Memory model feature register 2 + 6) ID_AA64MMFR2_EL1 - Memory model feature register 2 +------------------------------+---------+---------+ | Name | bits | visible | @@ -218,7 +225,7 @@ infrastructure: | AT | [35-32] | y | +------------------------------+---------+---------+ - 6) ID_AA64ZFR0_EL1 - SVE feature ID register 0 + 7) ID_AA64ZFR0_EL1 - SVE feature ID register 0 +------------------------------+---------+---------+ | Name | bits | visible | -- cgit From 478016c3839d53bd4c89af1f095195be543fa1a3 Mon Sep 17 00:00:00 2001 From: Julien Grall Date: Fri, 1 Nov 2019 15:20:22 +0000 Subject: docs/arm64: cpu-feature-registers: Rewrite bitfields that don't follow [e, s] Commit "docs/arm64: cpu-feature-registers: Documents missing visible fields" added bitfields following the convention [s, e]. However, the documentation is following [s, e] and so does the Arm ARM. Rewrite the bitfields to match the format [s, e]. Fixes: a8613e7070e7 ("docs/arm64: cpu-feature-registers: Documents missing visible fields") Signed-off-by: Julien Grall Signed-off-by: Catalin Marinas --- Documentation/arm64/cpu-feature-registers.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/arm64/cpu-feature-registers.rst') diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst index ffcf4e2c71ef..7c40e4581bae 100644 --- a/Documentation/arm64/cpu-feature-registers.rst +++ b/Documentation/arm64/cpu-feature-registers.rst @@ -193,9 +193,9 @@ infrastructure: +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | SB | [36-39] | y | + | SB | [39-36] | y | +------------------------------+---------+---------+ - | FRINTTS | [32-35] | y | + | FRINTTS | [35-32] | y | +------------------------------+---------+---------+ | GPI | [31-28] | y | +------------------------------+---------+---------+ -- cgit