From 7e5700ae64f6a8921c130f34946af4de4483bb7c Mon Sep 17 00:00:00 2001 From: Rishabh Bhatnagar Date: Wed, 23 May 2018 17:35:20 -0700 Subject: dt-bindings: Documentation for qcom, llcc Documentation for last level cache controller device tree bindings, client bindings usage examples. Signed-off-by: Channagoud Kadabi Signed-off-by: Rishabh Bhatnagar Reviewed-by: Evan Green Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../devicetree/bindings/arm/msm/qcom,llcc.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt (limited to 'Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt') diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file mode 100644 index 000000000000..5e85749262ae --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -0,0 +1,26 @@ +== Introduction== + +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, +that can be shared by multiple clients. Clients here are different cores in the +SOC, the idea is to minimize the local caches at the clients and migrate to +common pool of memory. Cache memory is divided into partitions called slices +which are assigned to clients. Clients can query the slice details, activate +and deactivate them. + +Properties: +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdm845-llcc" + +- reg: + Usage: required + Value Type: + Definition: Start address and the the size of the register region. + +Example: + + cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x250000>; + }; -- cgit