From d838ff33ec3a6262f44476d8edc0303acdc16580 Mon Sep 17 00:00:00 2001 From: Emilio López Date: Mon, 23 Dec 2013 00:32:34 -0300 Subject: clk: sunxi: add gating support to PLL1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds gating support to PLL1 on the clock driver. This makes the PLL1 implementation fully compatible with PLL4 as well. Signed-off-by: Emilio López Acked-by: Maxime Ripard Acked-by: Mike Turquette --- Documentation/devicetree/bindings/clock/sunxi.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/clock/sunxi.txt') diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 91a748fed13d..b8c6cc449a3e 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -7,7 +7,7 @@ This binding uses the common clock binding[1]. Required properties: - compatible : shall be one of the following: "allwinner,sun4i-osc-clk" - for a gatable oscillator - "allwinner,sun4i-pll1-clk" - for the main PLL clock + "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock "allwinner,sun4i-axi-clk" - for the AXI clock -- cgit