From a5e0a69dc34b2acf211785e9ad9642c5aaea098b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 May 2023 09:56:57 +0200 Subject: dt-bindings: xilinx: Remove Rajan, Jolly and Manish Rajan, Jolly and Manish are no longer work for AMD/Xilinx and there is no activity from them to continue to maintain bindings that's why remove them. Acked-by: Conor Dooley Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9b252dd71c82593fa6b137eca2174d9ab6e57f7a.1684828606.git.michal.simek@amd.com --- Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml') diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 93ae349cf9e9..5cbb34d0b61b 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -8,8 +8,6 @@ title: Xilinx Versal clock controller maintainers: - Michal Simek - - Jolly Shah - - Rajan Vaja description: | The clock controller is a hardware block of Xilinx versal clock tree. It -- cgit