From 4d4f2121369d5f2a4180a6b64046c8494817619f Mon Sep 17 00:00:00 2001 From: Abhishek Sahu Date: Wed, 19 Jul 2017 17:17:54 +0530 Subject: dt-bindings: qcom_nandc: remove chip select compatible string MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently the compatible “qcom,nandcs” is being used for each connected NAND device to support for multiple NAND devices in the same bus. The same thing can be achieved by looking reg property for each sub nodes which contains the chip select number so this patch removes the use of “qcom,nandcs” for specifying NAND device sub nodes. Since there is no user for this driver currently in so changing compatible string is safe. Signed-off-by: Abhishek Sahu Acked-by: Rob Herring Signed-off-by: Boris Brezillon --- Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 -- 1 file changed, 2 deletions(-) (limited to 'Documentation/devicetree/bindings/mtd') diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt index 70dd5118a324..26360fe51663 100644 --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt @@ -26,7 +26,6 @@ chip-selects which (may) contain NAND flash chips. Their properties are as follows. Required properties: -- compatible: should contain "qcom,nandcs" - reg: a single integer representing the chip-select number (e.g., 0, 1, 2, etc.) - #address-cells: see partition.txt @@ -60,7 +59,6 @@ nand@1ac00000 { #size-cells = <0>; nandcs@0 { - compatible = "qcom,nandcs"; reg = <0>; nand-ecc-strength = <4>; -- cgit From 24d8735708b086a8cfb40d962ea2080af558bd1b Mon Sep 17 00:00:00 2001 From: Abhishek Sahu Date: Thu, 17 Aug 2017 17:37:50 +0530 Subject: dt-bindings: qcom_nandc: fix the ipq806x device tree example 1. Correct the compatible string for IPQ806x 2. Change the NAND controller and NAND chip nodes name for more clarity. Acked-by: Rob Herring Signed-off-by: Abhishek Sahu Signed-off-by: Boris Brezillon --- Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree/bindings/mtd') diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt index 26360fe51663..f475b652d9b8 100644 --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt @@ -42,8 +42,8 @@ partition.txt for more detail. Example: -nand@1ac00000 { - compatible = "qcom,ebi2-nandc"; +nand-controller@1ac00000 { + compatible = "qcom,ipq806x-nand"; reg = <0x1ac00000 0x800>; clocks = <&gcc EBI2_CLK>, @@ -58,7 +58,7 @@ nand@1ac00000 { #address-cells = <1>; #size-cells = <0>; - nandcs@0 { + nand@0 { reg = <0>; nand-ecc-strength = <4>; -- cgit From ec170cc853ad4e8c01ee71e619739b9c379eb643 Mon Sep 17 00:00:00 2001 From: Abhishek Sahu Date: Thu, 17 Aug 2017 17:37:51 +0530 Subject: dt-bindings: qcom_nandc: IPQ4019 QPIC NAND documentation 1. Qualcom IPQ4019 SoC uses QPIC NAND controller version 1.4.0 which uses BAM DMA Engine while IPQ806x uses EBI2 NAND which uses ADM DMA Engine. 2. QPIC NAND will 3 BAM channels: command, data tx and data rx while EBI2 NAND uses only single ADM channel. 3. CRCI is only required for ADM DMA and its not required for BAM DMA. Acked-by: Rob Herring Signed-off-by: Abhishek Sahu Signed-off-by: Boris Brezillon --- .../devicetree/bindings/mtd/qcom_nandc.txt | 55 +++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/mtd') diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt index f475b652d9b8..d93b952f4bd6 100644 --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt @@ -1,11 +1,18 @@ * Qualcomm NAND controller Required properties: -- compatible: should be "qcom,ipq806x-nand" +- compatible: must be one of the following: + * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x + SoC and it uses ADM DMA + * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in + IPQ4019 SoC and it uses BAM DMA + - reg: MMIO address range - clocks: must contain core clock and always on clock - clock-names: must contain "core" for the core clock and "aon" for the always on clock + +EBI2 specific properties: - dmas: DMA specifier, consisting of a phandle to the ADM DMA controller node and the channel number to be used for NAND. Refer to dma.txt and qcom_adm.txt for more details @@ -16,6 +23,12 @@ Required properties: - qcom,data-crci: must contain the ADM data type CRCI block instance number specified for the NAND controller on the given platform + +QPIC specific properties: +- dmas: DMA specifier, consisting of a phandle to the BAM DMA + and the channel number to be used for NAND. Refer to + dma.txt, qcom_bam_dma.txt for more details +- dma-names: must contain all 3 channel names : "tx", "rx", "cmd" - #address-cells: <1> - subnodes give the chip-select number - #size-cells: <0> @@ -82,3 +95,43 @@ nand-controller@1ac00000 { }; }; }; + +nand-controller@79b0000 { + compatible = "qcom,ipq4019-nand"; + reg = <0x79b0000 0x1000>; + + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "core", "aon"; + + dmas = <&qpicbam 0>, + <&qpicbam 1>, + <&qpicbam 2>; + dma-names = "tx", "rx", "cmd"; + + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot-nand"; + reg = <0 0x58a0000>; + }; + + partition@58a0000 { + label = "fs-nand"; + reg = <0x58a0000 0x4000000>; + }; + }; + }; +}; -- cgit From d440c4d3601d964dc742730a05f2534535a17f0b Mon Sep 17 00:00:00 2001 From: Abhishek Sahu Date: Thu, 17 Aug 2017 17:37:52 +0530 Subject: dt-bindings: qcom_nandc: IPQ8074 QPIC NAND documentation Qualcom IPQ8074 SoC uses QPIC NAND controller version 1.5.0 which uses BAM DMA Engine. Signed-off-by: Abhishek Sahu Signed-off-by: Boris Brezillon --- Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings/mtd') diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt index d93b952f4bd6..73d336befa08 100644 --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt @@ -6,6 +6,8 @@ Required properties: SoC and it uses ADM DMA * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in IPQ4019 SoC and it uses BAM DMA + * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in + IPQ8074 SoC and it uses BAM DMA - reg: MMIO address range - clocks: must contain core clock and always on clock -- cgit