From 3f2c154e1b3d31fd13bac4bfbb632db3168dfdb6 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Tue, 25 Apr 2023 14:10:06 +0530 Subject: dt-bindings: clock: qcom,ipq9574-gcc: Add maintainer Add Bjorn andersson to the maintainer's list. Signed-off-by: Devi Priya Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230425084010.15581-3-quic_devipriy@quicinc.com --- Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml index afc68eb9d7cc..944a0ea79cd6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller on IPQ9574 maintainers: + - Bjorn Andersson - Anusha Rao description: | -- cgit From de6d1f0c4919852514459f1876d7168212e5e1cd Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 22 May 2023 18:03:48 -0700 Subject: dt-bindings: clock: qcom: Accept power-domains for GPUCC In many designs the power-domains provided by the GPU clock controller are powered by some GFX rail, add power-domains as a valid property to allow this to be specified. Signed-off-by: Bjorn Andersson Acked-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230523010348.63043-1-quic_bjorande@quicinc.com --- Documentation/devicetree/bindings/clock/qcom,gpucc.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index 1e3dc9deded9..a00216b3b15a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -50,6 +50,9 @@ properties: - const: gcc_gpu_gpll0_clk_src - const: gcc_gpu_gpll0_div_clk_src + power-domains: + maxItems: 1 + '#clock-cells': const: 1 -- cgit From 1c305ea86bc32b3f38413ef3dbb1f3c288da024e Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 12 May 2023 17:53:44 +0530 Subject: dt-bindings: clock: qcom: Add GCC clocks for SDX75 Add support for qcom global clock controller bindings for SDX75 platform. Signed-off-by: Imran Shaik Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230512122347.1219-3-quic_tdas@quicinc.com --- .../devicetree/bindings/clock/qcom,sdx75-gcc.yaml | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml new file mode 100644 index 000000000000..98921fa236b1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SDX75 + +maintainers: + - Imran Shaik + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SDX75 + + See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h + +properties: + compatible: + const: qcom,sdx75-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: EMAC0 sgmiiphy mac rclk source + - description: EMAC0 sgmiiphy mac tclk source + - description: EMAC0 sgmiiphy rclk source + - description: EMAC0 sgmiiphy tclk source + - description: EMAC1 sgmiiphy mac rclk source + - description: EMAC1 sgmiiphy mac tclk source + - description: EMAC1 sgmiiphy rclk source + - description: EMAC1 sgmiiphy tclk source + - description: PCIE20 phy aux clock source + - description: PCIE_1 Pipe clock source + - description: PCIE_2 Pipe clock source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@80000 { + compatible = "qcom,sdx75-gcc"; + reg = <0x80000 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>, + <&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, + <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... -- cgit From 1e910b2ba0edd639cc89b5495a3a832b28f77c7f Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 24 May 2023 19:36:54 +0530 Subject: dt-bindings: clock: qcom: Add SM8450 video clock controller Add device tree bindings for the video clock controller on Qualcomm SM8450 platform. Signed-off-by: Taniya Das Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524140656.7076-2-quic_tdas@quicinc.com --- .../bindings/clock/qcom,sm8450-videocc.yaml | 77 ++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml new file mode 100644 index 000000000000..fe1fda77b835 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on SM8450 + +maintainers: + - Taniya Das + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on SM8450. + + See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h + +properties: + compatible: + const: qcom,sm8450-videocc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Video AHB clock from GCC + + power-domains: + maxItems: 1 + description: + MMCX power domain. + + required-opps: + maxItems: 1 + description: + A phandle to an OPP node describing required MMCX performance point. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - required-opps + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8450-videocc"; + reg = <0x0aaf0000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... -- cgit From 2aae5eaa941e356b5f6e78c207c7dc3a93286622 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 20 Apr 2023 19:32:50 +0200 Subject: dt-bindings: clock: Add SM8350 VIDEOCC SM8350, like most recent higher-end chips has a separate clock controller block just for the Venus IP. Document it. The binding was separated as the driver, unlike the earlier ones, doesn't expect clock-names to keep it easier to maintain. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-1-86c714a66a81@linaro.org --- .../bindings/clock/qcom,sm8350-videocc.yaml | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml new file mode 100644 index 000000000000..23505c8c3dbd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Video Clock & Reset Controller + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,videocc-sm8350.h + include/dt-bindings/reset/qcom,videocc-sm8350.h + +properties: + compatible: + const: qcom,sm8350-videocc + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Board sleep clock + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + - required-opps + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + clock-controller@abf0000 { + compatible = "qcom,sm8350-videocc"; + reg = <0x0abf0000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SM8350_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... -- cgit From c7d91f26f0f70f03a09bb6cdbfa1b7df28ab121e Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 24 May 2023 20:22:01 +0530 Subject: dt-bindings: clock: qcom: Add SM8550 video clock controller Add compatible string for SM8550 video clock controller. Signed-off-by: Jagadeesh Kona Acked-by: Conor Dooley Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524145203.13153-3-quic_jkona@quicinc.com --- Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index fe1fda77b835..f1c6dd50f184 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -17,7 +17,9 @@ description: | properties: compatible: - const: qcom,sm8450-videocc + enum: + - qcom,sm8450-videocc + - qcom,sm8550-videocc reg: maxItems: 1 -- cgit From 2f9b2096465da9f7eada1c3b297689b666a015cf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 8 Apr 2023 16:37:29 +0200 Subject: dt-bindings: clock: qcom,gcc-msm8953: split to separate schema The Qualcomm MSM8953 GCC clock controller has clock inputs, thus existing gcc-other.yaml was not describing it fully. Move the binding to its own schema file and document the clocks based on DTS. Add driver contributors as its maintainers. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230408143729.84097-1-krzysztof.kozlowski@linaro.org --- .../bindings/clock/qcom,gcc-msm8953.yaml | 73 ++++++++++++++++++++++ .../devicetree/bindings/clock/qcom,gcc-other.yaml | 1 - 2 files changed, 73 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml new file mode 100644 index 000000000000..fe9fd4cb185f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MSM8953 + +maintainers: + - Adam Skladowski + - Sireesh Kodali + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on MSM8953. + + See also: include/dt-bindings/clock/qcom,gcc-msm8953.h + +properties: + compatible: + const: qcom,gcc-msm8953 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + + clock-names: + items: + - const: xo + - const: sleep + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + clock-controller@1800000 { + compatible = "qcom,gcc-msm8953"; + reg = <0x01800000 0x80000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>; + clock-names = "xo", + "sleep", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml index ae01e7749534..ba969e7a57bf 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml @@ -30,7 +30,6 @@ properties: enum: - qcom,gcc-ipq6018 - qcom,gcc-mdm9607 - - qcom,gcc-msm8953 - qcom,gcc-mdm9615 required: -- cgit From 379d72721bc4308fbc038e9858b7d2e9191725b5 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 12 May 2023 17:53:45 +0530 Subject: dt-bindings: clock: qcom: Add RPMHCC for SDX75 Add compatible string for qcom RPMHCC for SDX75 platform. Signed-off-by: Imran Shaik Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230512122347.1219-4-quic_tdas@quicinc.com --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index d5a250b7c2af..267cf8c26823 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -27,6 +27,7 @@ properties: - qcom,sdm845-rpmh-clk - qcom,sdx55-rpmh-clk - qcom,sdx65-rpmh-clk + - qcom,sdx75-rpmh-clk - qcom,sm6350-rpmh-clk - qcom,sm8150-rpmh-clk - qcom,sm8250-rpmh-clk -- cgit From 2310ab77f1ee2611e34345ca1746c9e8aaa5bc31 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 May 2023 12:52:39 +0200 Subject: dt-bindings: clock: qcom,gcc-sm8250: add missing bi_tcxo_ao clock The initial SM8250 GCC driver added in commit 3e5770921a88 ("clk: qcom: gcc: Add global clock controller driver for SM8250") already consumed it on the clock. This fixes warnings like: sm8250-xiaomi-elish-csot.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too long Fixes: 98394efb48f5 ("dt-bindings: clock: Add SM8250 GCC clock bindings") Reviewed-by: Konrad Dybcio Acked-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Krzysztof Kozlowski Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516105241.30091-1-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml index b752542ee20c..ead6665b9a45 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml @@ -23,11 +23,13 @@ properties: clocks: items: - description: Board XO source + - description: Board active XO source - description: Sleep clock source clock-names: items: - const: bi_tcxo + - const: bi_tcxo_ao - const: sleep_clk required: @@ -47,8 +49,9 @@ examples: compatible = "qcom,gcc-sm8250"; reg = <0x00100000 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - clock-names = "bi_tcxo", "sleep_clk"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; -- cgit From 21a95637a3fda45e6d3fd7a57d6ada204e28e484 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 May 2023 12:52:40 +0200 Subject: dt-bindings: clock: qcom,gcc-sc7180: document CX power domain The GCC clock controller needs CX power domain, at least according to DTS: sc7180-trogdor-pompom-r3.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected) Acked-by: Rob Herring Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516105241.30091-2-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml index 06dce0c6b7d0..8bf9b6f49550 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml @@ -32,6 +32,10 @@ properties: - const: bi_tcxo_ao - const: sleep_clk + power-domains: + items: + - description: CX domain + required: - compatible - clocks @@ -45,6 +49,8 @@ unevaluatedProperties: false examples: - | #include + #include + clock-controller@100000 { compatible = "qcom,gcc-sc7180"; reg = <0x00100000 0x1f0000>; @@ -52,6 +58,7 @@ examples: <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + power-domains = <&rpmhpd SC7180_CX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; -- cgit From 7a52084ae14f49582b0ce19106cdad094499e204 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 May 2023 12:52:41 +0200 Subject: dt-bindings: clock: qcom,gcc-sc7280: document CX power domain The GCC clock controller needs CX power domain, at least according to DTS: sc7280-herobrine-crd-pro.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected) Acked-by: Rob Herring Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230516105241.30091-3-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml index 947b47168cec..ff0b18bbb0fc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml @@ -43,6 +43,10 @@ properties: - const: ufs_phy_tx_symbol_0_clk - const: usb3_phy_wrapper_gcc_usb30_pipe_clk + power-domains: + items: + - description: CX domain + required: - compatible - clocks @@ -56,6 +60,8 @@ unevaluatedProperties: false examples: - | #include + #include + clock-controller@100000 { compatible = "qcom,gcc-sc7280"; reg = <0x00100000 0x1f0000>; @@ -71,6 +77,7 @@ examples: "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + power-domains = <&rpmhpd SC7280_CX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; -- cgit From 17035787e20090a5ea347f1b8dfe867263419d26 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Thu, 6 Apr 2023 11:43:10 +0530 Subject: dt-bindings: clock: qcom,a53pll: add IPQ9574 compatible IPQ9574 uses A73 PLL of type Huayra. Add the IPQ9574 A73 compatible to A53 bindings as the PLL properties match with that of A53. Acked-by: Krzysztof Kozlowski Signed-off-by: Devi Priya Acked-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406061314.10916-2-quic_devipriy@quicinc.com --- Documentation/devicetree/bindings/clock/qcom,a53pll.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml index 659669bf224b..9436266828af 100644 --- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml @@ -19,6 +19,7 @@ properties: - qcom,ipq5332-a53pll - qcom,ipq6018-a53pll - qcom,ipq8074-a53pll + - qcom,ipq9574-a73pll - qcom,msm8916-a53pll - qcom,msm8939-a53pll -- cgit From 63f4e4b6f54cdde98ca9c484724d4012989e3454 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 17 May 2023 18:40:38 +0200 Subject: dt-bindings: clock: Add Qcom SM8450 GPUCC Add device tree bindings for the graphics clock controller on Qualcomm Technology Inc's SM8450 SoCs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-1-4f40e282af1d@linaro.org --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml new file mode 100644 index 000000000000..ad913b2daf0c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM8450 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,sm8450-gpucc.h + include/dt-bindings/reset/qcom,sm8450-gpucc.h + +properties: + compatible: + enum: + - qcom,sm8450-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sm8450-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... -- cgit From 778af143adc8813d8851be401f71dfb80b9144eb Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 24 May 2023 23:47:58 +0530 Subject: dt-bindings: clock: qcom: Add SM8550 graphics clock controller Add device tree bindings for the graphics clock controller on Qualcomm SM8550 platform. Signed-off-by: Jagadeesh Kona Acked-by: Conor Dooley Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230524181800.28717-2-quic_jkona@quicinc.com --- Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index ad913b2daf0c..2320be920a5f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -15,12 +15,14 @@ description: | See also:: include/dt-bindings/clock/qcom,sm8450-gpucc.h + include/dt-bindings/clock/qcom,sm8550-gpucc.h include/dt-bindings/reset/qcom,sm8450-gpucc.h properties: compatible: enum: - qcom,sm8450-gpucc + - qcom,sm8550-gpucc clocks: items: -- cgit From 5683f11aa194f1dfa7e7c63426379ac6c7bc84be Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 9 May 2023 23:16:36 +0200 Subject: dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226 Define clock/clock-names properties of the MMCC device node to be used on MSM8226 platform. Signed-off-by: Luca Weiss Acked-by: Jeffrey Hugo Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230509-msm8226-mmcc-parents-v1-2-83a2dfc986ab@z3ntu.xyz --- .../devicetree/bindings/clock/qcom,mmcc.yaml | 32 ++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml index acf0c923c24f..422f5776a771 100644 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml @@ -31,11 +31,11 @@ properties: - qcom,mmcc-sdm660 clocks: - minItems: 8 + minItems: 7 maxItems: 13 clock-names: - minItems: 8 + minItems: 7 maxItems: 13 '#clock-cells': @@ -99,6 +99,34 @@ allOf: - const: dsi2pllbyte - const: hdmipll + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-msm8226 + then: + properties: + clocks: + items: + - description: Board XO source + - description: MMSS GPLL0 voted clock + - description: GPLL0 voted clock + - description: GPLL1 voted clock + - description: GFX3D clock source + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + + clock-names: + items: + - const: xo + - const: mmss_gpll0_vote + - const: gpll0_vote + - const: gpll1_vote + - const: gfx3d_clk_src + - const: dsi0pll + - const: dsi0pllbyte + - if: properties: compatible: -- cgit From bfc43a9c0ce5f3fcf98c972d7b7f21a742b7c957 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 8 Jun 2023 13:53:10 +0100 Subject: dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP The LPASS (Low Power Audio Subsystem) clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230608125315.11454-2-srinivas.kandagatla@linaro.org --- .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml new file mode 100644 index 000000000000..047cae91f443 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm LPASS core and audio clock control module provides the clocks, + and reset on SC8280XP. + + See also:: + include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h + +properties: + compatible: + enum: + - qcom,sc8280xp-lpasscc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + lpasscc: clock-controller@33e0000 { + compatible = "qcom,sc8280xp-lpasscc"; + reg = <0x033e0000 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... -- cgit From 83da70da40c93f3515aebcd5f2b8ff6283f64ee3 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 8 Jun 2023 13:53:11 +0100 Subject: dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230608125315.11454-3-srinivas.kandagatla@linaro.org --- .../devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml index 047cae91f443..3326dcd6766c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -19,6 +19,7 @@ description: | properties: compatible: enum: + - qcom,sc8280xp-lpassaudiocc - qcom,sc8280xp-lpasscc reg: @@ -39,6 +40,15 @@ required: additionalProperties: false examples: + - | + #include + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0x032a9000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + - | #include lpasscc: clock-controller@33e0000 { -- cgit From 2f138c667cb94a3a150d3341ca5ebf62480b501f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 29 May 2023 15:14:23 +0200 Subject: dt-bindings: clock: sm6375-gpucc: Add VDD_GX The GPUCC block on SM6375 is powered by VDD_CX and VDD_GX. If the latter rail is not online, GX_GDSC will never turn on. Describe the missing handles. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230529-topic-sm6375gpuccpd-v1-1-8d57c41a6066@linaro.org --- .../devicetree/bindings/clock/qcom,sm6375-gpucc.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml index b480ead5bd69..cf4cad76f6c9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml @@ -27,9 +27,21 @@ properties: - description: GPLL0 div branch source - description: SNoC DVM GFX source + power-domains: + description: + A phandle and PM domain specifier for the VDD_GX power rail + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required VDD_GX performance point. + maxItems: 1 + required: - compatible - clocks + - power-domains + - required-opps allOf: - $ref: qcom,gcc.yaml# @@ -40,6 +52,7 @@ examples: - | #include #include + #include soc { #address-cells = <2>; @@ -52,6 +65,8 @@ examples: <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + power-domains = <&rpmpd SM6375_VDDGX>; + required-opps = <&rpmpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; -- cgit