From a4f5f39849f39f62f5d4e88cbb600f95f927003d Mon Sep 17 00:00:00 2001 From: Mayuresh Chitale Date: Wed, 13 Sep 2023 22:09:00 +0530 Subject: dt-bindings: riscv: Add smstateen entry Add an entry for the Smstateen extension to the riscv,isa-extensions property. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Signed-off-by: Anup Patel --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index cc1f546fdbdc..36ff6749fbba 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -128,6 +128,12 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: smstateen + description: | + The standard Smstateen extension for controlling access to CSRs + added by other RISC-V extensions in H/S/VS/U/VU modes and as + ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. + - const: ssaia description: | The standard Ssaia supervisor-level extension for the advanced -- cgit From 00c6f39c8247b0a5ddca4586d43aec1af7cbccb6 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Mon, 25 Sep 2023 14:46:25 +0530 Subject: dt-bindings: riscv: Add Zicond extension entry Add an entry for the Zicond extension to the riscv,isa-extensions property. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Signed-off-by: Anup Patel --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 36ff6749fbba..c91ab0e46648 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -218,6 +218,12 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification. + - const: zicond + description: + The standard Zicond extension for conditional arithmetic and + conditional-select/move operations as ratified in commit 95cf1f9 + ("Add changes requested by Ved during signoff") of riscv-zicond. + - const: zicsr description: | The standard Zicsr extension for control and status register -- cgit