From 33d5c207a9ed16e72f49b77b9387aea5a8a42219 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Jan 2019 13:59:55 +0530 Subject: dt-bindings: PCI: dra7xx: Add SoC specific compatible strings Add new compatible strings for dra74x SoC (also used by dra76x) and dra72x. This can be used to perform SoC specific configuration (like configuring PCIe in x2 lane mode). Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori Signed-off-by: Lorenzo Pieralisi Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti-pci.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 452fe48c4fdd..e03d23631f5b 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -1,8 +1,12 @@ TI PCI Controllers PCIe DesignWare Controller - - compatible: Should be "ti,dra7-pcie" for RC - Should be "ti,dra7-pcie-ep" for EP + - compatible: Should be "ti,dra7-pcie" for RC (deprecated) + Should be "ti,dra7-pcie-ep" for EP (deprecated) + Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode + Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode + Should be "ti,dra726-pcie-rc" for dra72x in RC mode + Should be "ti,dra726-pcie-ep" for dra72x in EP mode - phys : list of PHY specifiers (used by generic PHY framework) - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the number of PHYs as specified in *phys* property. -- cgit From 1c5d2cc7196c8c45c02114858efa4dca69a86583 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 24 Jan 2019 13:59:56 +0530 Subject: dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 Add syscon properties required for configuring PCIe in x2 lane mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti-pci.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index e03d23631f5b..d5cbfe6b0d89 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -13,6 +13,9 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", where is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt + - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control + module and the register offset to specify lane + selection. HOST MODE ========= -- cgit From 2d8ed461dbc9bc734185db92d2b9d1bb7b586b30 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Fri, 1 Feb 2019 16:15:23 -0800 Subject: PCI: imx6: Add support for i.MX8MQ Add code needed to support i.MX8MQ variant. Signed-off-by: Andrey Smirnov Signed-off-by: Lorenzo Pieralisi Reviewed-by: Lucas Stach Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index d514c1f2365f..920ca93870a8 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -9,6 +9,7 @@ Required properties: - "fsl,imx6sx-pcie", - "fsl,imx6qp-pcie" - "fsl,imx7d-pcie" + - "fsl,imx8mq-pcie" - reg: base address and length of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. @@ -45,7 +46,7 @@ Additional required properties for imx6sx-pcie: PCIE_PHY power domains - power-domain-names: Must be "pcie", "pcie_phy" -Additional required properties for imx7d-pcie: +Additional required properties for imx7d-pcie and imx8mq-pcie: - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain - resets: Must contain phandles to PCIe-related reset lines exposed by SRC IP block -- cgit From 2e2b7615e310994b4d59c98b7d114449a9f019e5 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Tue, 18 Dec 2018 12:02:42 +0000 Subject: dt-bindings: PCI: rcar: Add device tree support for r8a774c0 Add PCIe support for the RZ/G2E (a.k.a. R8A774C0). Signed-off-by: Fabrizio Castro Signed-off-by: Lorenzo Pieralisi Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Reviewed-by: Simon Horman --- Documentation/devicetree/bindings/pci/rcar-pci.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt index 976ef7bfff93..6904882a0e94 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt @@ -3,6 +3,7 @@ Required properties: compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; "renesas,pcie-r8a7744" for the R8A7744 SoC; + "renesas,pcie-r8a774c0" for the R8A774C0 SoC; "renesas,pcie-r8a7779" for the R8A7779 SoC; "renesas,pcie-r8a7790" for the R8A7790 SoC; "renesas,pcie-r8a7791" for the R8A7791 SoC; @@ -13,7 +14,8 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; "renesas,pcie-r8a77990" for the R8A77990 SoC; "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or RZ/G1 compatible device. - "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device. + "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 or + RZ/G2 compatible device. When compatible with the generic version, nodes must list the SoC-specific version corresponding to the platform first -- cgit From b7e312dea1d8378b8f311ce9096759b5accb1939 Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Tue, 5 Feb 2019 00:17:39 +0000 Subject: dt-bindings: imx6q-pcie: Add description of imx7d pcie phy There is a separate PHY device with its own registers on imx7d. It's currently unused, but a PCIe erratum on imx7d will require it for the workaround. Signed-off-by: Trent Piepho Signed-off-by: Lorenzo Pieralisi Acked-by: Lucas Stach --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 920ca93870a8..954f435dca8c 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -54,6 +54,7 @@ Additional required properties for imx7d-pcie and imx8mq-pcie: - "pciephy" - "apps" - "turnoff" +- fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node. Example: @@ -80,3 +81,13 @@ Example: clocks = <&clks 144>, <&clks 206>, <&clks 189>; clock-names = "pcie", "pcie_bus", "pcie_phy"; }; + +* Freescale i.MX7d PCIe PHY + +This is the PHY associated with the IMX7d PCIe controller. It's used by the +PCI-e controller via the fsl,imx7d-pcie-phy phandle. + +Required properties: +- compatible: + - "fsl,imx7d-pcie-phy" +- reg: base address and length of the PCIe PHY controller -- cgit From e1a6ba5dcb9b31c652214b49cada5529e6a38988 Mon Sep 17 00:00:00 2001 From: Xiaowei Bao Date: Thu, 21 Feb 2019 11:16:17 +0800 Subject: dt-bindings: add DT binding for the layerscape PCIe controller with EP mode Add the documentation for the Device Tree binding for the layerscape PCIe controller with EP mode. Signed-off-by: Xiaowei Bao Signed-off-by: Lorenzo Pieralisi Reviewed-by: Minghuan Lian Reviewed-by: Zhiqiang Hou Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 9b2b8d66d1f4..e20ceaab9b38 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -13,6 +13,7 @@ information. Required properties: - compatible: should contain the platform identifier such as: + RC mode: "fsl,ls1021a-pcie" "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" "fsl,ls2088a-pcie" @@ -20,6 +21,8 @@ Required properties: "fsl,ls1046a-pcie" "fsl,ls1043a-pcie" "fsl,ls1012a-pcie" + EP mode: + "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. -- cgit From d82ca49f3e8aa300819cd6c917cfd65ab998fccf Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 11 Feb 2019 17:51:07 -0800 Subject: dt-bindings: imx6q-pcie: Add "pcie_aux" clock for imx8mq Add a binding for an extra clock required on i.MX8MQ. Signed-off-by: Andrey Smirnov Signed-off-by: Lorenzo Pieralisi Reviewed-by: Lucas Stach Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: Rob Herring Cc: devicetree@vger.kernel.org --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 954f435dca8c..a7f5f5afa0e6 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -56,6 +56,10 @@ Additional required properties for imx7d-pcie and imx8mq-pcie: - "turnoff" - fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node. +Additional required properties for imx8mq-pcie: +- clock-names: Must include the following additional entries: + - "pcie_aux" + Example: pcie@01000000 { -- cgit From d13af797154f4e033a446ff759431c03e0f832d9 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Thu, 28 Feb 2019 18:52:52 +0800 Subject: dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 Add support for altr,pcie-root-port-2.0. Signed-off-by: Ley Foon Tan Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/altera-pcie.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt index 6c396f17c91a..816b244a221e 100644 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -1,11 +1,13 @@ * Altera PCIe controller Required properties: -- compatible : should contain "altr,pcie-root-port-1.0" +- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" - reg: a list of physical base address and length for TXS and CRA. + For "altr,pcie-root-port-2.0", additional HIP base address and length. - reg-names: must include the following entries: "Txs": TX slave port region "Cra": Control register access region + "Hip": Hard IP region (if "altr,pcie-root-port-2.0") - interrupts: specifies the interrupt source of the parent interrupt controller. The format of the interrupt specifier depends on the parent interrupt controller. -- cgit