From 04aa999eb96fdc8d3cf2b2d98363d6372befaef2 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Fri, 11 Oct 2024 15:00:43 +0100 Subject: dt-bindings: PCI: microchip,pcie-host: Allow dma-noncoherent PolarFire SoC may be configured in a way that requires non-coherent DMA handling. On RISC-V, buses are coherent by default & the dma-noncoherent property is required to denote buses or devices that are non-coherent. Link: https://lore.kernel.org/r/20241011140043.1250030-4-daire.mcnamara@microchip.com Signed-off-by: Conor Dooley Signed-off-by: Daire McNamara Signed-off-by: Bjorn Helgaas Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 2e1547569702..103574d18dbc 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -50,6 +50,8 @@ properties: items: pattern: '^fic[0-3]$' + dma-coherent: true + ranges: minItems: 1 maxItems: 3 -- cgit