From 16e0c2474fcfaa8a6c61abfaa981994c4564a628 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Mon, 22 Nov 2021 01:27:36 +0200 Subject: dt-bindings: clock: Add bindings for Exynos850 CMU_APM CMU_APM generates clocks for APM IP-core (Active Power Management). In particular it generates RTC clocks, which are needed to enable rtc-s3c driver on Exynos850 SoC. Add clock indices and binding documentation for CMU_APM. Signed-off-by: Sam Protsenko Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Acked-by: Chanwoo Choi Link: https://lore.kernel.org/r/20211121232741.6967-2-semen.protsenko@linaro.org --- .../bindings/clock/samsung,exynos850-clock.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml index 7f8c91a29b91..5618cfa62f80 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -32,6 +32,7 @@ properties: compatible: enum: - samsung,exynos850-cmu-top + - samsung,exynos850-cmu-apm - samsung,exynos850-cmu-core - samsung,exynos850-cmu-dpu - samsung,exynos850-cmu-hsi @@ -68,6 +69,24 @@ allOf: items: - const: oscclk + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-apm + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_APM bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_apm_bus + - if: properties: compatible: -- cgit From c2afeb79fdb24de4cea73f12d2ede84a5a68fa08 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Mon, 22 Nov 2021 01:27:38 +0200 Subject: dt-bindings: clock: Add bindings for Exynos850 CMU_CMGP CMU_CMGP generates USI and ADC clocks for BLK_ALIVE. In particular USI clocks are needed for HSI2C_3 and HSI2C_4 instances. Add clock indices and bindings documentation for CMU_CMGP domain. Signed-off-by: Sam Protsenko Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski Acked-by: Chanwoo Choi Link: https://lore.kernel.org/r/20211121232741.6967-4-semen.protsenko@linaro.org --- .../bindings/clock/samsung,exynos850-clock.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml index 5618cfa62f80..80ba60838f2b 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -33,6 +33,7 @@ properties: enum: - samsung,exynos850-cmu-top - samsung,exynos850-cmu-apm + - samsung,exynos850-cmu-cmgp - samsung,exynos850-cmu-core - samsung,exynos850-cmu-dpu - samsung,exynos850-cmu-hsi @@ -87,6 +88,24 @@ allOf: - const: oscclk - const: dout_clkcmu_apm_bus + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-cmgp + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CMGP bus clock (from CMU_APM) + + clock-names: + items: + - const: oscclk + - const: gout_clkcmu_cmgp_bus + - if: properties: compatible: -- cgit From aa848c8ee8915b2a8c973d90f1c7f8e96d17fd25 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Wed, 1 Dec 2021 16:21:34 -0800 Subject: dt-bindings: clock: Introduce RPMHCC bindings for SDX65 Add compatible for SDX65 RPMHCC. Signed-off-by: Vamsi Krishna Lanka Reviewed-by: Bjorn Andersson Acked-by: Rob Herring Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/91c10dde568098027833dfcc310748a92a90387e.1638402361.git.quic_vamslank@quicinc.com --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 72212970e6f5..0e7e05e38bb2 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -22,6 +22,7 @@ properties: - qcom,sc8180x-rpmh-clk - qcom,sdm845-rpmh-clk - qcom,sdx55-rpmh-clk + - qcom,sdx65-rpmh-clk - qcom,sm6350-rpmh-clk - qcom,sm8150-rpmh-clk - qcom,sm8250-rpmh-clk -- cgit From ea59846bd206614211ee43a31e001bed5062f21d Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 1 Dec 2021 12:53:08 +0530 Subject: dt-bindings: clock: Add RPMHCC bindings for SM8450 Add bindings and update documentation for clock rpmh driver on SM8450. Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201072310.3968679-3-vkoul@kernel.org --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 0e7e05e38bb2..8406dde17937 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -27,6 +27,7 @@ properties: - qcom,sm8150-rpmh-clk - qcom,sm8250-rpmh-clk - qcom,sm8350-rpmh-clk + - qcom,sm8450-rpmh-clk clocks: maxItems: 1 -- cgit From 8f8ef3860d4403d1bf0887380f9e3376be092c40 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Mon, 6 Dec 2021 23:32:49 -0800 Subject: dt-bindings: clock: Add SDX65 GCC clock bindings Add device tree bindings for global clock controller on SDX65 SOCs. Signed-off-by: Vamsi Krishna Lanka Reviewed-by: Rob Herring Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/e15509b2b7c9b600ab38c5269d4fac609c077b5b.1638861860.git.quic_vamslank@quicinc.com --- .../devicetree/bindings/clock/qcom,gcc-sdx65.yaml | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml new file mode 100644 index 000000000000..16c4cdc7b4d6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SDX65 + +maintainers: + - Vamsi krishna Lanka + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SDX65 + + See also: + - dt-bindings/clock/qcom,gcc-sdx65.h + +properties: + compatible: + const: qcom,gcc-sdx65 + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + - description: PLL test clock source (Optional clock) + minItems: 5 + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: pcie_pipe_clk + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk + - const: core_bi_pll_test_se # Optional clock + minItems: 5 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,gcc-sdx65"; + reg = <0x100000 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, + <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", + "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... -- cgit From 72a0ca203ca7fae34fe61668906fe483b97d9039 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 7 Dec 2021 17:10:02 +0530 Subject: dt-bindings: clock: Add SM8450 GCC clock bindings Add device tree bindings for global clock controller on SM8450 SoCs. Signed-off-by: Vinod Koul Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211207114003.100693-2-vkoul@kernel.org --- .../devicetree/bindings/clock/qcom,gcc-sm8450.yaml | 85 ++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml new file mode 100644 index 000000000000..58d98a766de6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SM8450 + +maintainers: + - Vinod Koul + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SM8450 + + See also: + - dt-bindings/clock/qcom,gcc-sm8450.h + +properties: + compatible: + const: qcom,gcc-sm8450 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source (Optional clock) + - description: PCIE 1 Pipe clock source (Optional clock) + - description: PCIE 1 Phy Auxillary clock source (Optional clock) + - description: UFS Phy Rx symbol 0 clock source (Optional clock) + - description: UFS Phy Rx symbol 1 clock source (Optional clock) + - description: UFS Phy Tx symbol 0 clock source (Optional clock) + - description: USB3 Phy wrapper pipe clock source (Optional clock) + minItems: 2 + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + - const: pcie_0_pipe_clk # Optional clock + - const: pcie_1_pipe_clk # Optional clock + - const: pcie_1_phy_aux_clk # Optional clock + - const: ufs_phy_rx_symbol_0_clk # Optional clock + - const: ufs_phy_rx_symbol_1_clk # Optional clock + - const: ufs_phy_tx_symbol_0_clk # Optional clock + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock + minItems: 2 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,gcc-sm8450"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... -- cgit From 6d24d9546d6e6c524505e51bb5f76d9a83fac478 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Wed, 8 Dec 2021 10:10:35 +0100 Subject: dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller Document the required properties and firmware clocks for gcc-msm8976 to operate nominally, and add header definitions for referencing the clocks from firmware. Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211208091036.132334-2-marijn.suijten@somainline.org --- .../bindings/clock/qcom,gcc-msm8976.yaml | 97 ++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml new file mode 100644 index 000000000000..f3430b159caa --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for MSM8976 + +maintainers: + - Stephen Boyd + - Taniya Das + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on MSM8976. + + See also: + - dt-bindings/clock/qcom,gcc-msm8976.h + +properties: + compatible: + enum: + - qcom,gcc-msm8976 + - qcom,gcc-msm8976-v1.1 + + clocks: + items: + - description: XO source + - description: Always-on XO source + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY1 + - description: Byte clock from DSI PHY1 + + clock-names: + items: + - const: xo + - const: xo_a + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + + vdd_gfx-supply: + description: + Phandle to voltage regulator providing power to the GX domain. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - vdd_gfx-supply + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-msm8976"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x1800000 0x80000>; + + clocks = <&xo_board>, + <&xo_board>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>; + + clock-names = "xo", + "xo_a", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + + vdd_gfx-supply = <&pm8004_s5>; + }; +... -- cgit From 77624aa1d81f4036d83d9868053199eacf2ae2ed Mon Sep 17 00:00:00 2001 From: David Virag Date: Mon, 6 Dec 2021 16:31:16 +0100 Subject: dt-bindings: clock: Document Exynos7885 CMU bindings Provide dt-schema documentation for Exynos7885 SoC clock controller. Description is modified from Exynos850 clock controller documentation as I couldn't describe it any better, that was written by Sam Protsenko. Signed-off-by: David Virag Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski Reviewed-by: Sam Protsenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211206153124.427102-3-virag.david003@gmail.com --- .../bindings/clock/samsung,exynos7885-clock.yaml | 166 +++++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml new file mode 100644 index 000000000000..7e5a9cac2fd2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos7885 SoC clock controller + +maintainers: + - Dávid Virág + - Chanwoo Choi + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + Exynos7885 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that root tree + is an external clock: OSCCLK (26 MHz). This external clock must be defined + as a fixed-rate clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/exynos7885.h' header. + +properties: + compatible: + enum: + - samsung,exynos7885-cmu-top + - samsung,exynos7885-cmu-core + - samsung,exynos7885-cmu-peri + + clocks: + minItems: 1 + maxItems: 10 + + clock-names: + minItems: 1 + maxItems: 10 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos7885-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7885-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CORE bus clock (from CMU_TOP) + - description: CCI clock (from CMU_TOP) + - description: G3D clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_core_bus + - const: dout_core_cci + - const: dout_core_g3d + + - if: + properties: + compatible: + contains: + const: samsung,exynos7885-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERI bus clock (from CMU_TOP) + - description: SPI0 clock (from CMU_TOP) + - description: SPI1 clock (from CMU_TOP) + - description: UART0 clock (from CMU_TOP) + - description: UART1 clock (from CMU_TOP) + - description: UART2 clock (from CMU_TOP) + - description: USI0 clock (from CMU_TOP) + - description: USI1 clock (from CMU_TOP) + - description: USI2 clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_peri_bus + - const: dout_peri_spi0 + - const: dout_peri_spi1 + - const: dout_peri_uart0 + - const: dout_peri_uart1 + - const: dout_peri_uart2 + - const: dout_peri_usi0 + - const: dout_peri_usi1 + - const: dout_peri_usi2 + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_PERI + - | + #include + + cmu_peri: clock-controller@10010000 { + compatible = "samsung,exynos7885-cmu-peri"; + reg = <0x10010000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_SPI0>, + <&cmu_top CLK_DOUT_PERI_SPI1>, + <&cmu_top CLK_DOUT_PERI_UART0>, + <&cmu_top CLK_DOUT_PERI_UART1>, + <&cmu_top CLK_DOUT_PERI_UART2>, + <&cmu_top CLK_DOUT_PERI_USI0>, + <&cmu_top CLK_DOUT_PERI_USI1>, + <&cmu_top CLK_DOUT_PERI_USI2>; + clock-names = "oscclk", + "dout_peri_bus", + "dout_peri_spi0", + "dout_peri_spi1", + "dout_peri_uart0", + "dout_peri_uart1", + "dout_peri_uart2", + "dout_peri_usi0", + "dout_peri_usi1", + "dout_peri_usi2"; + }; + +... -- cgit