From 20612d2428c3cdd191d45d548e930f41785f62cc Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Mon, 11 Jan 2021 12:21:13 +0100 Subject: fpga: dfl-pci: rectify ReST formatting Commit fa41d10589be ("fpga: dfl-pci: locate DFLs by PCIe vendor specific capability") provides documentation to the FPGA Device Feature List (DFL) Framework Overview, but introduced new documentation warnings: ./Documentation/fpga/dfl.rst: 505: WARNING: Title underline too short. 523: WARNING: Unexpected indentation. 523: WARNING: Blank line required after table. 524: WARNING: Block quote ends without a blank line; unexpected unindent. Rectify ReST formatting in ./Documentation/fpga/dfl.rst. Tested-by: Tom Rix Acked-by: Moritz Fischer Acked-by: Matthew Gerlach Signed-off-by: Lukas Bulwahn Link: https://lore.kernel.org/r/20210111112113.27242-1-lukas.bulwahn@gmail.com Signed-off-by: Greg Kroah-Hartman --- Documentation/fpga/dfl.rst | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/fpga') diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ea8cefc18bdb..c41ac76ffaae 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -502,7 +502,7 @@ FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. Location of DFLs on a PCI Device -=========================== +================================ The original method for finding a DFL on a PCI device assumed the start of the first DFL to offset 0 of bar 0. If the first node of the DFL is an FME, then further DFLs in the port(s) are specified in FME header registers. @@ -514,6 +514,7 @@ data begins with a 4 byte vendor specific register for the number of DFLs follow Offset/BIR vendor specific registers for each DFL. Bits 2:0 of Offset/BIR register indicates the BAR, and bits 31:3 form the 8 byte aligned offset where bits 2:0 are zero. +:: +----------------------------+ |31 Number of DFLS 0| -- cgit