From 7d2078310cbf0fa7fb4323d595fe093c418dcd37 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 4 Jan 2023 18:05:13 +0000 Subject: dt-bindings: arm: move cpu-capacity to a shared loation RISC-V uses the same generic topology code as arm64 & while there currently exists no binding for cpu-capacity on RISC-V, the code paths can be hit if the property is present. Move the documentation of cpu-capacity to a shared location, ahead of defining a binding for capacity-dmips-mhz on RISC-V. Update some references to this document in the process. Signed-off-by: Conor Dooley Reviewed-by: Ley Foon Tan Acked-by: Rob Herring Reviewed-by: Yanteng Si Link: https://lore.kernel.org/r/20230104180513.1379453-2-conor@kernel.org Signed-off-by: Palmer Dabbelt --- Documentation/scheduler/sched-capacity.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/scheduler') diff --git a/Documentation/scheduler/sched-capacity.rst b/Documentation/scheduler/sched-capacity.rst index 805f85f330b5..8e2b8538bc2b 100644 --- a/Documentation/scheduler/sched-capacity.rst +++ b/Documentation/scheduler/sched-capacity.rst @@ -260,7 +260,7 @@ for that purpose. The arm and arm64 architectures directly map this to the arch_topology driver CPU scaling data, which is derived from the capacity-dmips-mhz CPU binding; see -Documentation/devicetree/bindings/arm/cpu-capacity.txt. +Documentation/devicetree/bindings/cpu/cpu-capacity.txt. 3.2 Frequency invariance ------------------------ -- cgit