From 66bd1333abd7fa191f13b929c9119d6cd3df27b0 Mon Sep 17 00:00:00 2001 From: Mike Leach Date: Wed, 17 Nov 2021 16:42:20 +0000 Subject: Documentation: coresight: Fix documentation issue Fix the description of the directories and attributes used in cs_etm as used by perf. Drop the references to the 'configurations' sub-directory which had been removed in an earlier version of the patchset. Fixes: f71cd93d5ea4 ("Documentation: coresight: Add documentation for CoreSight config") Reported-by: German Gomex Signed-off-by: Mike Leach Link: https://lore.kernel.org/r/20211117164220.14883-1-mike.leach@linaro.org Signed-off-by: Mathieu Poirier --- Documentation/trace/coresight/coresight-config.rst | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) (limited to 'Documentation') diff --git a/Documentation/trace/coresight/coresight-config.rst b/Documentation/trace/coresight/coresight-config.rst index a4e3ef295240..6ed13398ca2c 100644 --- a/Documentation/trace/coresight/coresight-config.rst +++ b/Documentation/trace/coresight/coresight-config.rst @@ -211,19 +211,13 @@ also declared in the perf 'cs_etm' event infrastructure so that they can be selected when running trace under perf:: $ ls /sys/devices/cs_etm - configurations format perf_event_mux_interval_ms sinks type - events nr_addr_filters power + cpu0 cpu2 events nr_addr_filters power subsystem uevent + cpu1 cpu3 format perf_event_mux_interval_ms sinks type -Key directories here are 'configurations' - which lists the loaded -configurations, and 'events' - a generic perf directory which allows -selection on the perf command line.:: +The key directory here is 'events' - a generic perf directory which allows +selection on the perf command line. As with the sinks entries, this provides +a hash of the configuration name. - $ ls configurations/ - autofdo - $ cat configurations/autofdo - 0xa7c3dddd - -As with the sinks entries, this provides a hash of the configuration name. The entry in the 'events' directory uses perfs built in syntax generator to substitute the syntax for the name when evaluating the command:: -- cgit From 3b47746cd787d7130dda700e96a4503f7f315cbd Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Thu, 21 Oct 2021 16:10:55 +0530 Subject: dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 SoCs. Signed-off-by: Odelu Kukatla Acked-by: Rob Herring Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/1634812857-10676-2-git-send-email-okukatla@codeaurora.org Signed-off-by: Georgi Djakov --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index e701524ee811..116e434d0daa 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,sc7180-osm-l3 + - qcom,sc7280-epss-l3 - qcom,sc8180x-osm-l3 - qcom,sdm845-osm-l3 - qcom,sm8150-osm-l3 -- cgit From 45c548cc5baa047e59865bec5dfa0bd36b48ff17 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 21 Oct 2021 13:24:25 +0000 Subject: dt-bindings: interconnect: Combine SDM660 bindings into RPM schema SDM660 interconnect bindings are similar to other RPM interconnect providers, and now it shares the same common driver with them, so it is better to combine them into qcom,rpm.yaml. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov #db820c Link: https://lore.kernel.org/r/20211021132329.234942-2-y.oudjana@protonmail.com Signed-off-by: Georgi Djakov --- .../devicetree/bindings/interconnect/qcom,rpm.yaml | 103 +++++++++++- .../bindings/interconnect/qcom,sdm660.yaml | 185 --------------------- 2 files changed, 95 insertions(+), 193 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 983d71fb5399..6c39c0529e36 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -30,19 +30,23 @@ properties: - qcom,qcs404-bimc - qcom,qcs404-pcnoc - qcom,qcs404-snoc + - qcom,sdm660-a2noc + - qcom,sdm660-bimc + - qcom,sdm660-cnoc + - qcom,sdm660-gnoc + - qcom,sdm660-mnoc + - qcom,sdm660-snoc '#interconnect-cells': const: 1 - clock-names: - items: - - const: bus - - const: bus_a - clocks: - items: - - description: Bus Clock - - description: Bus A Clock + minItems: 2 + maxItems: 7 + + clock-names: + minItems: 2 + maxItems: 7 required: - compatible @@ -53,6 +57,89 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8916-bimc + - qcom,msm8916-pcnoc + - qcom,msm8916-snoc + - qcom,msm8939-bimc + - qcom,msm8939-pcnoc + - qcom,msm8939-snoc + - qcom,msm8939-snoc-mm + - qcom,qcs404-bimc + - qcom,qcs404-pcnoc + - qcom,qcs404-snoc + - qcom,sdm660-bimc + - qcom,sdm660-cnoc + - qcom,sdm660-gnoc + - qcom,sdm660-snoc + + then: + properties: + clock-names: + items: + - const: bus + - const: bus_a + + clocks: + items: + - description: Bus Clock + - description: Bus A Clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm660-mnoc + + then: + properties: + clock-names: + items: + - const: bus + - const: bus_a + - const: iface + + clocks: + items: + - description: Bus Clock. + - description: Bus A Clock. + - description: CPU-NoC High-performance Bus Clock. + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm660-a2noc + + then: + properties: + clock-names: + items: + - const: bus + - const: bus_a + - const: ipa + - const: ufs_axi + - const: aggre2_ufs_axi + - const: aggre2_usb3_axi + - const: cfg_noc_usb2_axi + + clocks: + items: + - description: Bus Clock. + - description: Bus A Clock. + - description: IPA Clock. + - description: UFS AXI Clock. + - description: Aggregate2 UFS AXI Clock. + - description: Aggregate2 USB3 AXI Clock. + - description: Config NoC USB2 AXI Clock. + examples: - | #include diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml deleted file mode 100644 index bcd41e491f1d..000000000000 --- a/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml +++ /dev/null @@ -1,185 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SDM660 Network-On-Chip interconnect - -maintainers: - - AngeloGioacchino Del Regno - -description: | - The Qualcomm SDM660 interconnect providers support adjusting the - bandwidth requirements between the various NoC fabrics. - -properties: - reg: - maxItems: 1 - - compatible: - enum: - - qcom,sdm660-a2noc - - qcom,sdm660-bimc - - qcom,sdm660-cnoc - - qcom,sdm660-gnoc - - qcom,sdm660-mnoc - - qcom,sdm660-snoc - - '#interconnect-cells': - const: 1 - - clocks: - minItems: 1 - maxItems: 7 - - clock-names: - minItems: 1 - maxItems: 7 - -required: - - compatible - - reg - - '#interconnect-cells' - - clock-names - - clocks - -additionalProperties: false - -allOf: - - if: - properties: - compatible: - contains: - enum: - - qcom,sdm660-mnoc - then: - properties: - clocks: - items: - - description: Bus Clock. - - description: Bus A Clock. - - description: CPU-NoC High-performance Bus Clock. - clock-names: - items: - - const: bus - - const: bus_a - - const: iface - - - if: - properties: - compatible: - contains: - enum: - - qcom,sdm660-a2noc - then: - properties: - clocks: - items: - - description: Bus Clock. - - description: Bus A Clock. - - description: IPA Clock. - - description: UFS AXI Clock. - - description: Aggregate2 UFS AXI Clock. - - description: Aggregate2 USB3 AXI Clock. - - description: Config NoC USB2 AXI Clock. - clock-names: - items: - - const: bus - - const: bus_a - - const: ipa - - const: ufs_axi - - const: aggre2_ufs_axi - - const: aggre2_usb3_axi - - const: cfg_noc_usb2_axi - - - if: - properties: - compatible: - contains: - enum: - - qcom,sdm660-bimc - - qcom,sdm660-cnoc - - qcom,sdm660-gnoc - - qcom,sdm660-snoc - then: - properties: - clocks: - items: - - description: Bus Clock. - - description: Bus A Clock. - clock-names: - items: - - const: bus - - const: bus_a - -examples: - - | - #include - #include - #include - - bimc: interconnect@1008000 { - compatible = "qcom,sdm660-bimc"; - reg = <0x01008000 0x78000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; - }; - - cnoc: interconnect@1500000 { - compatible = "qcom,sdm660-cnoc"; - reg = <0x01500000 0x10000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_CNOC_CLK>, - <&rpmcc RPM_SMD_CNOC_A_CLK>; - }; - - snoc: interconnect@1626000 { - compatible = "qcom,sdm660-snoc"; - reg = <0x01626000 0x7090>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; - }; - - a2noc: interconnect@1704000 { - compatible = "qcom,sdm660-a2noc"; - reg = <0x01704000 0xc100>; - #interconnect-cells = <1>; - clock-names = "bus", - "bus_a", - "ipa", - "ufs_axi", - "aggre2_ufs_axi", - "aggre2_usb3_axi", - "cfg_noc_usb2_axi"; - clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, - <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, - <&rpmcc RPM_SMD_IPA_CLK>, - <&gcc GCC_UFS_AXI_CLK>, - <&gcc GCC_AGGRE2_UFS_AXI_CLK>, - <&gcc GCC_AGGRE2_USB3_AXI_CLK>, - <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; - }; - - mnoc: interconnect@1745000 { - compatible = "qcom,sdm660-mnoc"; - reg = <0x01745000 0xa010>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a", "iface"; - clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, - <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, - <&mmcc AHB_CLK_SRC>; - }; - - gnoc: interconnect@17900000 { - compatible = "qcom,sdm660-gnoc"; - reg = <0x17900000 0xe000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&xo_board>, <&xo_board>; - }; -- cgit From 3e9fdc6b73ca862e72ea8a563638cecdc11d26e2 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Thu, 21 Oct 2021 13:24:54 +0000 Subject: dt-bindings: interconnect: Add Qualcomm MSM8996 DT bindings Add bindings for interconnects on Qualcomm MSM8996. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov #db820c Link: https://lore.kernel.org/r/20211021132329.234942-4-y.oudjana@protonmail.com Signed-off-by: Georgi Djakov --- .../devicetree/bindings/interconnect/qcom,rpm.yaml | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 6c39c0529e36..e4c3c2818119 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -27,6 +27,14 @@ properties: - qcom,msm8939-pcnoc - qcom,msm8939-snoc - qcom,msm8939-snoc-mm + - qcom,msm8996-a0noc + - qcom,msm8996-a1noc + - qcom,msm8996-a2noc + - qcom,msm8996-bimc + - qcom,msm8996-cnoc + - qcom,msm8996-mnoc + - qcom,msm8996-pnoc + - qcom,msm8996-snoc - qcom,qcs404-bimc - qcom,qcs404-pcnoc - qcom,qcs404-snoc @@ -48,6 +56,9 @@ properties: minItems: 2 maxItems: 7 + power-domains: + maxItems: 1 + required: - compatible - reg @@ -70,6 +81,12 @@ allOf: - qcom,msm8939-pcnoc - qcom,msm8939-snoc - qcom,msm8939-snoc-mm + - qcom,msm8996-a1noc + - qcom,msm8996-a2noc + - qcom,msm8996-bimc + - qcom,msm8996-cnoc + - qcom,msm8996-pnoc + - qcom,msm8996-snoc - qcom,qcs404-bimc - qcom,qcs404-pcnoc - qcom,qcs404-snoc @@ -95,6 +112,7 @@ allOf: compatible: contains: enum: + - qcom,msm8996-mnoc - qcom,sdm660-mnoc then: @@ -111,6 +129,30 @@ allOf: - description: Bus A Clock. - description: CPU-NoC High-performance Bus Clock. + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-a0noc + + then: + properties: + clock-names: + items: + - const: aggre0_snoc_axi + - const: aggre0_cnoc_ahb + - const: aggre0_noc_mpu_cfg + + clocks: + items: + - description: Aggregate0 System NoC AXI Clock. + - description: Aggregate0 Config NoC AHB Clock. + - description: Aggregate0 NoC MPU Clock. + + required: + - power-domains + - if: properties: compatible: -- cgit From 26379667d26f33083484f0df814afec3a955b974 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 3 Nov 2021 16:44:09 -0700 Subject: dt-bindings: phy: Introduce Qualcomm eDP PHY binding Introduce a binding for the eDP PHY hardware block found in several different Qualcomm platforms. Signed-off-by: Bjorn Andersson Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211103234410.1352424-1-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/qcom,edp-phy.yaml | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml new file mode 100644 index 000000000000..9076e19b6417 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm eDP PHY + +maintainers: + - Bjorn Andersson + +description: + The Qualcomm eDP PHY is found in a number of Qualcomm platform and provides + the physical interface for Embedded Display Port. + +properties: + compatible: + const: qcom,sc8180x-edp-phy + + reg: + items: + - description: PHY base register block + - description: tx0 register block + - description: tx1 register block + - description: PLL register block + + clocks: + maxItems: 2 + + clock-names: + items: + - const: aux + - const: cfg_ahb + + "#clock-cells": + const: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@aec2a00 { + compatible = "qcom,sc8180x-edp-phy"; + reg = <0x0aec2a00 0x1c0>, + <0x0aec2200 0xa0>, + <0x0aec2600 0xa0>, + <0x0aec2000 0x19c>; + + clocks = <&dispcc 0>, <&dispcc 1>; + clock-names = "aux", "cfg_ahb"; + + #clock-cells = <1>; + #phy-cells = <0>; + }; +... -- cgit From 3870a48cd10c216213417e9929d9ffa85edb6ed5 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Wed, 20 Oct 2021 21:51:06 +0200 Subject: dt-bindings: phy: Add the Amlogic Meson8 HDMI TX PHY bindings Amlogic Meson8, Meson8b and Meson8m2 all include an identical (or at least very similar) HDMI TX PHY. The PHY registers are part of the HHI register area. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211020195107.1564533-2-martin.blumenstingl@googlemail.com Signed-off-by: Vinod Koul --- .../bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml new file mode 100644 index 000000000000..1f085cdd1c85 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY + +maintainers: + - Martin Blumenstingl + +description: |+ + The HDMI TX PHY node should be the child of a syscon node with the + required property: + + compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" + + Refer to the bindings described in + Documentation/devicetree/bindings/mfd/syscon.yaml + +properties: + $nodename: + pattern: "^hdmi-phy@[0-9a-f]+$" + + compatible: + oneOf: + - items: + - enum: + - amlogic,meson8b-hdmi-tx-phy + - amlogic,meson8m2-hdmi-tx-phy + - const: amlogic,meson8-hdmi-tx-phy + - const: amlogic,meson8-hdmi-tx-phy + + reg: + maxItems: 1 + + clocks: + minItems: 1 + description: + HDMI TMDS clock + + "#phy-cells": + const: 0 + +required: + - compatible + - "#phy-cells" + +additionalProperties: false + +examples: + - | + hdmi-phy@3a0 { + compatible = "amlogic,meson8-hdmi-tx-phy"; + reg = <0x3a0 0xc>; + clocks = <&tmds_clock>; + #phy-cells = <0>; + }; + - | + hdmi-phy@3a0 { + compatible = "amlogic,meson8b-hdmi-tx-phy", "amlogic,meson8-hdmi-tx-phy"; + reg = <0x3a0 0xc>; + clocks = <&tmds_clock>; + #phy-cells = <0>; + }; -- cgit From 5c2ecfce44b28aefeac4053a3680ae3a46e57f39 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 31 Oct 2021 12:32:36 +0100 Subject: dt-bindings: phy: Tegra194 P2U convert to YAML Convert Tegra194 P2U binding to the YAML format. Signed-off-by: David Heidelberg Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211031113236.29712-1-david@ixit.cz Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/phy-tegra194-p2u.txt | 28 -------------- .../devicetree/bindings/phy/phy-tegra194-p2u.yaml | 44 ++++++++++++++++++++++ 2 files changed, 44 insertions(+), 28 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt deleted file mode 100644 index d23ff90baad5..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt +++ /dev/null @@ -1,28 +0,0 @@ -NVIDIA Tegra194 P2U binding - -Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High -Speed) each interfacing with 12 and 8 P2U instances respectively. -A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE -interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe -lane. - -Required properties: -- compatible: For Tegra19x, must contain "nvidia,tegra194-p2u". -- reg: Should be the physical address space and length of respective each P2U - instance. -- reg-names: Must include the entry "ctl". - -Required properties for PHY port node: -- #phy-cells: Defined by generic PHY bindings. Must be 0. - -Refer to phy/phy-bindings.txt for the generic PHY binding properties. - -Example: - -p2u_hsio_0: phy@3e10000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e10000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; -}; diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml new file mode 100644 index 000000000000..9a89d05efbda --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra194 P2U binding + +maintainers: + - Thierry Reding + +description: > + Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High + Speed) each interfacing with 12 and 8 P2U instances respectively. + A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE + interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe + lane. + +properties: + compatible: + const: nvidia,tegra194-p2u + + reg: + maxItems: 1 + description: Should be the physical address space and length of respective each P2U instance. + + reg-names: + items: + - const: ctl + + '#phy-cells': + const: 0 + +additionalProperties: false + +examples: + - | + p2u_hsio_0: phy@3e10000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03e10000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; -- cgit From d0cfb865b363e6de30295348fca20d9c6810a0dc Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Fri, 29 Oct 2021 19:39:00 +0900 Subject: dt-bindings: phy: uniphier-usb3: Add bindings for NX1 SoC Update USB3-PHY binding document for UniPhier NX1 SoC. Add SS-PHY and HS-PHY compatible strings for the SoC to the document. Signed-off-by: Kunihiko Hayashi Acked-by: Rob Herring Link: https://lore.kernel.org/r/1635503947-18250-2-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml | 1 + Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml | 1 + 2 files changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml index a681cbc3b4ef..33946efcac5e 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml @@ -22,6 +22,7 @@ properties: - socionext,uniphier-pxs2-usb3-hsphy - socionext,uniphier-ld20-usb3-hsphy - socionext,uniphier-pxs3-usb3-hsphy + - socionext,uniphier-nx1-usb3-hsphy reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml index 41c0dd68ee25..92d46eb913a3 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml @@ -23,6 +23,7 @@ properties: - socionext,uniphier-pxs2-usb3-ssphy - socionext,uniphier-ld20-usb3-ssphy - socionext,uniphier-pxs3-usb3-ssphy + - socionext,uniphier-nx1-usb3-ssphy reg: maxItems: 1 -- cgit From 21db1010cd80763c622d2e5e3f084e2af8a4b682 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Fri, 29 Oct 2021 19:39:02 +0900 Subject: dt-bindings: phy: uniphier-pcie: Add bindings for NX1 SoC Update PCIe-PHY binding document for UniPhier NX1 SoC. Add a compatible string for the SoC to the document. Signed-off-by: Kunihiko Hayashi Acked-by: Rob Herring Link: https://lore.kernel.org/r/1635503947-18250-4-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml index 3e0566899041..fbb71d6dd531 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml @@ -19,6 +19,7 @@ properties: - socionext,uniphier-pro5-pcie-phy - socionext,uniphier-ld20-pcie-phy - socionext,uniphier-pxs3-pcie-phy + - socionext,uniphier-nx1-pcie-phy reg: maxItems: 1 -- cgit From 34f92b67621fe933ed9a3ed5a6f432541d183851 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Fri, 29 Oct 2021 19:39:06 +0900 Subject: dt-bindings: phy: uniphier-ahci: Add bindings for Pro4 SoC Update AHCI-PHY binding document for UniPhier Pro4 SoC. Add a compatible string, clock and reset lines for the SoC to the document. Pro4 AHCI-PHY needs to control additional GIO clock line and reset lines ("pm", "tx", and "rx"). Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/1635503947-18250-8-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Vinod Koul --- .../bindings/phy/socionext,uniphier-ahci-phy.yaml | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml index 745c525ce6b9..3b400a85b44a 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml @@ -16,6 +16,7 @@ maintainers: properties: compatible: enum: + - socionext,uniphier-pro4-ahci-phy - socionext,uniphier-pxs2-ahci-phy - socionext,uniphier-pxs3-ahci-phy @@ -26,23 +27,35 @@ properties: const: 0 clocks: + minItems: 1 maxItems: 2 clock-names: oneOf: - items: # for PXs2 - const: link + - items: # for Pro4 + - const: link + - const: gio - items: # for others - const: link - const: phy resets: - maxItems: 2 + minItems: 2 + maxItems: 5 reset-names: - items: - - const: link - - const: phy + oneOf: + - items: # for Pro4 + - const: link + - const: gio + - const: pm + - const: tx + - const: rx + - items: # for others + - const: link + - const: phy required: - compatible -- cgit From fd66e57e46a3d1b73912e4a04b1f17d3369f8bfa Mon Sep 17 00:00:00 2001 From: Horatiu Vultur Date: Tue, 16 Nov 2021 11:08:16 +0100 Subject: dt-bindings: phy: Add lan966x-serdes binding Document the lan966x ethernet serdes phy driver bindings. Reviewed-by: Rob Herring Signed-off-by: Horatiu Vultur Link: https://lore.kernel.org/r/20211116100818.1615762-2-horatiu.vultur@microchip.com Signed-off-by: Vinod Koul --- .../bindings/phy/microchip,lan966x-serdes.yaml | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/microchip,lan966x-serdes.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/microchip,lan966x-serdes.yaml b/Documentation/devicetree/bindings/phy/microchip,lan966x-serdes.yaml new file mode 100644 index 000000000000..6e914fbbac56 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/microchip,lan966x-serdes.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/microchip,lan966x-serdes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Lan966x Serdes controller + +maintainers: + - Horatiu Vultur + +description: | + Lan966x has 7 interfaces, consisting of 2 copper transceivers(CU), + 3 SERDES6G and 2 RGMII interfaces. Two of the SERDES6G support QSGMII. + Also it has 8 logical Ethernet ports which can be connected to these + interfaces. The Serdes controller will allow to configure these interfaces + and allows to "mux" the interfaces to different ports. + + For simple selection of the interface that is used with a port, the + following macros are defined CU(X), SERDES6G(X), RGMII(X). Where X is a + number that represents the index of that interface type. For example + CU(1) means use interface copper transceivers 1. SERDES6G(2) means use + interface SerDes 2. + +properties: + $nodename: + pattern: "^serdes@[0-9a-f]+$" + + compatible: + const: microchip,lan966x-serdes + + reg: + items: + - description: HSIO registers + - description: HW_STAT register + + '#phy-cells': + const: 2 + description: | + - Input port to use for a given macro. + - The macro to be used. The macros are defined in + dt-bindings/phy/phy-lan966x-serdes. + +required: + - compatible + - reg + - '#phy-cells' + +additionalProperties: false + +examples: + - | + serdes: serdes@e2004010 { + compatible = "microchip,lan966x-serdes"; + reg = <0xe202c000 0x9c>, <0xe2004010 0x4>; + #phy-cells = <2>; + }; + +... -- cgit From efb6935dd786a9d213ee542ed77d47ece700357c Mon Sep 17 00:00:00 2001 From: Rashmi A Date: Wed, 27 Oct 2021 17:25:15 +0530 Subject: dt-bindings: phy: intel: Add Thunder Bay eMMC PHY bindings Binding description for Intel Thunder Bay eMMC PHY. Added the newly introduced files into MAINTAINERS file-list Signed-off-by: Rashmi A Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211027115516.4475-4-rashmi.a@intel.com Signed-off-by: Vinod Koul --- .../bindings/phy/intel,phy-thunderbay-emmc.yaml | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml b/Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml new file mode 100644 index 000000000000..34bdb5c4cae8 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/intel,phy-thunderbay-emmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Thunder Bay eMMC PHY bindings + +maintainers: + - Srikandan Nandhini + +properties: + compatible: + const: intel,thunderbay-emmc-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: emmcclk + +required: + - "#phy-cells" + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + mmc_phy@80440800 { + #phy-cells = <0x0>; + compatible = "intel,thunderbay-emmc-phy"; + status = "okay"; + reg = <0x80440800 0x100>; + clocks = <&emmc>; + clock-names = "emmcclk"; + }; -- cgit From f9809d56513541ca10f67d9666de02384600f109 Mon Sep 17 00:00:00 2001 From: Mike Leach Date: Wed, 24 Nov 2021 20:00:38 +0000 Subject: Documentation: coresight: Update coresight configuration docs Update the CoreSight System Configuration document to cover the use of loadable modules to add configurations and features to the system. Signed-off-by: Mike Leach Link: https://lore.kernel.org/r/20211124200038.28662-7-mike.leach@linaro.org Signed-off-by: Mathieu Poirier --- Documentation/trace/coresight/coresight-config.rst | 62 ++++++++++++++++++++-- 1 file changed, 59 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/trace/coresight/coresight-config.rst b/Documentation/trace/coresight/coresight-config.rst index 6ed13398ca2c..6d5ffa6f7347 100644 --- a/Documentation/trace/coresight/coresight-config.rst +++ b/Documentation/trace/coresight/coresight-config.rst @@ -155,14 +155,14 @@ follows:: autofdo $ cd autofdo/ $ ls - description preset1 preset3 preset5 preset7 preset9 - feature_refs preset2 preset4 preset6 preset8 + description feature_refs preset1 preset3 preset5 preset7 preset9 + enable preset preset2 preset4 preset6 preset8 $ cat description Setup ETMs with strobing for autofdo $ cat feature_refs strobing -Each preset declared has a preset subdirectory declared. The values for +Each preset declared has a 'preset' subdirectory declared. The values for the preset can be examined:: $ cat preset1/values @@ -170,6 +170,9 @@ the preset can be examined:: $ cat preset2/values strobing.window = 0x1388 strobing.period = 0x4 +The 'enable' and 'preset' files allow the control of a configuration when +using CoreSight with sysfs. + The features referenced by the configuration can be examined in the features directory:: @@ -236,3 +239,56 @@ A preset to override the current parameter values can also be selected:: When configurations are selected in this way, then the trace sink used is automatically selected. + +Using Configurations in sysfs +============================= + +Coresight can be controlled using sysfs. When this is in use then a configuration +can be made active for the devices that are used in the sysfs session. + +In a configuration there are 'enable' and 'preset' files. + +To enable a configuration for use with sysfs:: + + $ cd configurations/autofdo + $ echo 1 > enable + +This will then use any default parameter values in the features - which can be +adjusted as described above. + +To use a preset set of parameter values:: + + $ echo 3 > preset + +This will select preset3 for the configuration. +The valid values for preset are 0 - to deselect presets, and any value of + where a preset sub-directory is present. + +Note that the active sysfs configuration is a global parameter, therefore +only a single configuration can be active for sysfs at any one time. +Attempting to enable a second configuration will result in an error. +Additionally, attempting to disable the configuration while in use will +also result in an error. + +The use of the active configuration by sysfs is independent of the configuration +used in perf. + + +Creating and Loading Custom Configurations +========================================== + +Custom configurations and / or features can be dynamically loaded into the +system by using a loadable module. + +An example of a custom configuration is found in ./samples/coresight. + +This creates a new configuration that uses the existing built in +strobing feature, but provides a different set of presets. + +When the module is loaded, then the configuration appears in the configfs +file system and is selectable in the same way as the built in configuration +described above. + +Configurations can use previously loaded features. The system will ensure +that it is not possible to unload a feature that is currently in use, by +enforcing the unload order as the strict reverse of the load order. -- cgit From 4ba0b2c294fe691921271372f7b59e5cc2ce4b0f Mon Sep 17 00:00:00 2001 From: Russ Weight Date: Thu, 18 Nov 2021 17:55:51 -0800 Subject: fpga: mgr: Use standard dev_release for class driver The FPGA manager class driver data structure is being treated as a managed resource instead of using the standard dev_release call-back function to release the class data structure. This change removes the managed resource code for the freeing of the class data structure and combines the create() and register() functions into a single register() or register_full() function. The register_full() function accepts an info data structure to provide flexibility in passing optional parameters. The register() function supports the current parameter list for users that don't require the use of optional parameters. The devm_fpga_mgr_register() function is retained, and the devm_fpga_mgr_register_full() function is added. Signed-off-by: Russ Weight Reviewed-by: Xu Yilun Acked-by: Xu Yilun Signed-off-by: Moritz Fischer --- Documentation/driver-api/fpga/fpga-mgr.rst | 38 +++++++++++++++++++++++------- 1 file changed, 29 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/driver-api/fpga/fpga-mgr.rst b/Documentation/driver-api/fpga/fpga-mgr.rst index 4d926b452cb3..42c01f396dce 100644 --- a/Documentation/driver-api/fpga/fpga-mgr.rst +++ b/Documentation/driver-api/fpga/fpga-mgr.rst @@ -24,7 +24,7 @@ How to support a new FPGA device -------------------------------- To add another FPGA manager, write a driver that implements a set of ops. The -probe function calls fpga_mgr_register(), such as:: +probe function calls fpga_mgr_register() or fpga_mgr_register_full(), such as:: static const struct fpga_manager_ops socfpga_fpga_ops = { .write_init = socfpga_fpga_ops_configure_init, @@ -49,14 +49,14 @@ probe function calls fpga_mgr_register(), such as:: * them in priv */ - mgr = devm_fpga_mgr_create(dev, "Altera SOCFPGA FPGA Manager", - &socfpga_fpga_ops, priv); - if (!mgr) - return -ENOMEM; + mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager", + &socfpga_fpga_ops, priv); + if (IS_ERR(mgr)) + return PTR_ERR(mgr); platform_set_drvdata(pdev, mgr); - return fpga_mgr_register(mgr); + return 0; } static int socfpga_fpga_remove(struct platform_device *pdev) @@ -68,6 +68,11 @@ probe function calls fpga_mgr_register(), such as:: return 0; } +Alternatively, the probe function could call one of the resource managed +register functions, devm_fpga_mgr_register() or devm_fpga_mgr_register_full(). +When these functions are used, the parameter syntax is the same, but the call +to fpga_mgr_unregister() should be removed. In the above example, the +socfpga_fpga_remove() function would not be required. The ops will implement whatever device specific register writes are needed to do the programming sequence for this particular FPGA. These ops return 0 for @@ -104,8 +109,14 @@ API for implementing a new FPGA Manager driver * ``fpga_mgr_states`` - Values for :c:expr:`fpga_manager->state`. * struct fpga_manager - the FPGA manager struct * struct fpga_manager_ops - Low level FPGA manager driver ops -* devm_fpga_mgr_create() - Allocate and init a manager struct -* fpga_mgr_register() - Register an FPGA manager +* struct fpga_manager_info - Parameter structure for fpga_mgr_register_full() +* fpga_mgr_register_full() - Create and register an FPGA manager using the + fpga_mgr_info structure to provide the full flexibility of options +* fpga_mgr_register() - Create and register an FPGA manager using standard + arguments +* devm_fpga_mgr_register_full() - Resource managed version of + fpga_mgr_register_full() +* devm_fpga_mgr_register() - Resource managed version of fpga_mgr_register() * fpga_mgr_unregister() - Unregister an FPGA manager .. kernel-doc:: include/linux/fpga/fpga-mgr.h @@ -117,11 +128,20 @@ API for implementing a new FPGA Manager driver .. kernel-doc:: include/linux/fpga/fpga-mgr.h :functions: fpga_manager_ops +.. kernel-doc:: include/linux/fpga/fpga-mgr.h + :functions: fpga_manager_info + .. kernel-doc:: drivers/fpga/fpga-mgr.c - :functions: devm_fpga_mgr_create + :functions: fpga_mgr_register_full .. kernel-doc:: drivers/fpga/fpga-mgr.c :functions: fpga_mgr_register +.. kernel-doc:: drivers/fpga/fpga-mgr.c + :functions: devm_fpga_mgr_register_full + +.. kernel-doc:: drivers/fpga/fpga-mgr.c + :functions: devm_fpga_mgr_register + .. kernel-doc:: drivers/fpga/fpga-mgr.c :functions: fpga_mgr_unregister -- cgit From 0d70af3c2530a70f1b2c197feaa63fbd3548ce34 Mon Sep 17 00:00:00 2001 From: Russ Weight Date: Thu, 18 Nov 2021 17:55:52 -0800 Subject: fpga: bridge: Use standard dev_release for class driver The FPGA bridge class driver data structure is being treated as a managed resource instead of using the standard dev_release call-back function to release the class data structure. This change removes the managed resource code and combines the create() and register() functions into a single register() function. Signed-off-by: Russ Weight Reviewed-by: Xu Yilun Acked-by: Xu Yilun Signed-off-by: Moritz Fischer --- Documentation/driver-api/fpga/fpga-bridge.rst | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/driver-api/fpga/fpga-bridge.rst b/Documentation/driver-api/fpga/fpga-bridge.rst index 8d650b4e2ce6..604208534095 100644 --- a/Documentation/driver-api/fpga/fpga-bridge.rst +++ b/Documentation/driver-api/fpga/fpga-bridge.rst @@ -6,8 +6,7 @@ API to implement a new FPGA bridge * struct fpga_bridge - The FPGA Bridge structure * struct fpga_bridge_ops - Low level Bridge driver ops -* devm_fpga_bridge_create() - Allocate and init a bridge struct -* fpga_bridge_register() - Register a bridge +* fpga_bridge_register() - Create and register a bridge * fpga_bridge_unregister() - Unregister a bridge .. kernel-doc:: include/linux/fpga/fpga-bridge.h @@ -16,9 +15,6 @@ API to implement a new FPGA bridge .. kernel-doc:: include/linux/fpga/fpga-bridge.h :functions: fpga_bridge_ops -.. kernel-doc:: drivers/fpga/fpga-bridge.c - :functions: devm_fpga_bridge_create - .. kernel-doc:: drivers/fpga/fpga-bridge.c :functions: fpga_bridge_register -- cgit From 8886a579744fbfa53e69aa453ed10ae3b1f9abac Mon Sep 17 00:00:00 2001 From: Russ Weight Date: Thu, 18 Nov 2021 17:55:53 -0800 Subject: fpga: region: Use standard dev_release for class driver The FPGA region class driver data structure is being treated as a managed resource instead of using the standard dev_release call-back function to release the class data structure. This change removes the managed resource code and combines the create() and register() functions into a single register() or register_full() function. The register_full() function accepts an info data structure to provide flexibility in passing optional parameters. The register() function supports the current parameter list for users that don't require the use of optional parameters. Signed-off-by: Russ Weight Reviewed-by: Xu Yilun Acked-by: Xu Yilun Signed-off-by: Moritz Fischer --- Documentation/driver-api/fpga/fpga-region.rst | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/driver-api/fpga/fpga-region.rst b/Documentation/driver-api/fpga/fpga-region.rst index 2636a27c11b2..dc55d60a0b4a 100644 --- a/Documentation/driver-api/fpga/fpga-region.rst +++ b/Documentation/driver-api/fpga/fpga-region.rst @@ -46,8 +46,11 @@ API to add a new FPGA region ---------------------------- * struct fpga_region - The FPGA region struct -* devm_fpga_region_create() - Allocate and init a region struct -* fpga_region_register() - Register an FPGA region +* struct fpga_region_info - Parameter structure for fpga_region_register_full() +* fpga_region_register_full() - Create and register an FPGA region using the + fpga_region_info structure to provide the full flexibility of options +* fpga_region_register() - Create and register an FPGA region using standard + arguments * fpga_region_unregister() - Unregister an FPGA region The FPGA region's probe function will need to get a reference to the FPGA @@ -75,8 +78,11 @@ following APIs to handle building or tearing down that list. .. kernel-doc:: include/linux/fpga/fpga-region.h :functions: fpga_region +.. kernel-doc:: include/linux/fpga/fpga-region.h + :functions: fpga_region_info + .. kernel-doc:: drivers/fpga/fpga-region.c - :functions: devm_fpga_region_create + :functions: fpga_region_register_full .. kernel-doc:: drivers/fpga/fpga-region.c :functions: fpga_region_register -- cgit From a91f82d944e369c13e62f94f19994e8c915cb028 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Sat, 13 Nov 2021 16:23:15 +0100 Subject: Documentation: dt: iio: st_lsm6dsx: add disable-sensor-hub property Enable/disable internal i2c controller slave autoprobing at bootstrap. Disable sensor-hub is useful if i2c controller clock/data lines are connected through a pull-up with other chip lines (e.g. SDO/SA0). Signed-off-by: Lorenzo Bianconi Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/54287a93922ac839501b776d288cc368aa81f0ab.1636816719.git.lorenzo@kernel.org Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml b/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml index d9b3213318fb..0750f700a143 100644 --- a/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml +++ b/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml @@ -61,6 +61,13 @@ properties: type: boolean description: enable/disable internal i2c controller pullup resistors. + st,disable-sensor-hub: + type: boolean + description: + Enable/disable internal i2c controller slave autoprobing at bootstrap. + Disable sensor-hub is useful if i2c controller clock/data lines are + connected through a pull-up with other chip lines (e.g. SDO/SA0). + drive-open-drain: type: boolean description: -- cgit From fc27e69f4df643e7985752ebee72299d085b0efc Mon Sep 17 00:00:00 2001 From: Evgeny Boger Date: Thu, 18 Nov 2021 17:12:33 +0300 Subject: dt-bindings: iio: adc: document TS voltage in AXP PMICs Most AXPxxx-based reference designs place a 10k NTC thermistor on a TS pin. axp20x IIO driver now report the voltage of this pin via additional IIO channel. Add new "ts_v" channel to the channel description. Signed-off-by: Evgeny Boger Acked-by: Rob Herring Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20211118141233.247907-3-boger@wirenboard.com Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml b/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml index e759a5da708d..d6d3d8590171 100644 --- a/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml @@ -27,6 +27,7 @@ description: | 8 | batt_v 9 | batt_chrg_i 10 | batt_dischrg_i + 11 | ts_v AXP22x ------ @@ -34,6 +35,7 @@ description: | 1 | batt_v 2 | batt_chrg_i 3 | batt_dischrg_i + 4 | ts_v AXP813 ------ @@ -42,6 +44,7 @@ description: | 2 | batt_v 3 | batt_chrg_i 4 | batt_dischrg_i + 5 | ts_v properties: -- cgit From 2cc131ace0d2f47e5d8fcc8a2be12f5e3a20b1f0 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Thu, 25 Nov 2021 17:56:45 +0500 Subject: dt-bindings: iio: light: ltr501: Add proximity-near-level This value inidcates the proximity level that should be considered "close". Signed-off-by: Nikita Travkin Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211125125646.54831-1-nikita@trvn.ru Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/light/liteon,ltr501.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/light/liteon,ltr501.yaml b/Documentation/devicetree/bindings/iio/light/liteon,ltr501.yaml index db0407bc9209..c8074f180a79 100644 --- a/Documentation/devicetree/bindings/iio/light/liteon,ltr501.yaml +++ b/Documentation/devicetree/bindings/iio/light/liteon,ltr501.yaml @@ -9,6 +9,9 @@ title: LiteON LTR501 I2C Proximity and Light sensor maintainers: - Nikita Travkin +allOf: + - $ref: ../common.yaml# + properties: compatible: enum: @@ -25,6 +28,8 @@ properties: interrupts: maxItems: 1 + proximity-near-level: true + additionalProperties: false required: @@ -42,6 +47,8 @@ examples: light-sensor@23 { compatible = "liteon,ltr559"; reg = <0x23>; + proximity-near-level = <75>; + vdd-supply = <&pm8916_l17>; vddio-supply = <&pm8916_l6>; -- cgit From 07cc0fa49bdbe051c69c1497b334b75a18d44a73 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 1 Dec 2021 13:14:54 +0530 Subject: scsi: ufs: dt-bindings: Add SM8450 compatible strings Document "qcom,sm8450-ufshc" compatible string. "qcom,sm8450-ufshc" is for UFS HC found in SM8450 SoC. Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Acked-by: Martin K. Petersen Link: https://lore.kernel.org/r/20211201074456.3969849-2-vkoul@kernel.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index d8fd4df81743..d0fee78e6203 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt @@ -16,6 +16,7 @@ Required properties: "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0" "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0" "qcom,sm8350-ufshc", "qcom,ufshc", "jedec,ufs-2.0" + "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0" - interrupts : - reg : -- cgit From e04121ba1b085af40b3c9ca2516b3577245d078d Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 1 Dec 2021 13:14:55 +0530 Subject: dt-bindings: phy: qcom,qmp: Add SM8450 UFS phy compatible Document the UFS phy compatible for QMP UFS phy found in SM8450 SoC. Signed-off-by: Vinod Koul Reviewed-by: Bjorn Andersson Acked-by: Martin K. Petersen Link: https://lore.kernel.org/r/20211201074456.3969849-3-vkoul@kernel.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 630ceaf915e2..c59bbca9a900 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -50,6 +50,7 @@ properties: - qcom,sm8350-qmp-ufs-phy - qcom,sm8350-qmp-usb3-phy - qcom,sm8350-qmp-usb3-uni-phy + - qcom,sm8450-qmp-ufs-phy - qcom,sdx55-qmp-pcie-phy - qcom,sdx55-qmp-usb3-uni-phy -- cgit From 2ff1f4d8df665316921bb752d28a5ea68c1a9811 Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Thu, 2 Dec 2021 17:08:19 +0200 Subject: dt-bindings:iio:dac: add ad7293 doc Add device tree bindings for the AD7293 Power Amplifier. Signed-off-by: Antoniu Miclaus Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211202150819.24832-2-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/dac/adi,ad7293.yaml | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml new file mode 100644 index 000000000000..5ee80bf6aa11 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad7293.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad7293.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AD7293 12-Bit Power Amplifier Current Controller with ADC, + DACs, Temperature and Current Sensors + +maintainers: + - Antoniu Miclaus + +description: | + Power Amplifier drain current controller containing functionality + for general-purpose monitoring and control of current, voltage, + and temperature, integrated into a single chip solution with an + SPI-compatible interface. + + https://www.analog.com/en/products/ad7293.html + +properties: + compatible: + enum: + - adi,ad7293 + + avdd-supply: true + + vdrive-supply: true + + reset-gpios: + maxItems: 1 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 1000000 + +required: + - compatible + - reg + - avdd-supply + - vdrive-supply + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + ad7293@0 { + compatible = "adi,ad7293"; + reg = <0>; + spi-max-frequency = <1000000>; + avdd-supply = <&avdd>; + vdrive-supply = <&vdrive>; + reset-gpios = <&gpio 10 0>; + }; + }; +... -- cgit From 3cf3cdea6fe3fdb7a1e4ac1372b80408e4f56b73 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 5 Dec 2021 13:40:44 +0200 Subject: dt-bindings: iio: add AD74413R The AD74412R and AD74413R are quad-channel, software configurable, input/output solutions for building and process control applications. They contain functionality for analog output, analog input, digital input, resistance temperature detector, and thermocouple measurements integrated into a single chip solution with an SPI interface. The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide four configurable input/output channels and a suite of diagnostic functions. The AD74413R differentiates itself from the AD74412R by being HART-compatible. Signed-off-by: Cosmin Tanislav Reviewed-by: Rob Herring Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20211205114045.173612-3-cosmin.tanislav@analog.com Signed-off-by: Jonathan Cameron --- .../bindings/iio/addac/adi,ad74413r.yaml | 158 +++++++++++++++++++++ 1 file changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml b/Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml new file mode 100644 index 000000000000..baa65a521bad --- /dev/null +++ b/Documentation/devicetree/bindings/iio/addac/adi,ad74413r.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/addac/adi,ad74413r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD74412R/AD74413R device + +maintainers: + - Cosmin Tanislav + +description: | + The AD74412R and AD74413R are quad-channel software configurable input/output + solutions for building and process control applications. They contain + functionality for analog output, analog input, digital input, resistance + temperature detector, and thermocouple measurements integrated + into a single chip solution with an SPI interface. + The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide + four configurable input/output channels and a suite of diagnostic functions. + The AD74413R differentiates itself from the AD74412R by being HART-compatible. + https://www.analog.com/en/products/ad74412r.html + https://www.analog.com/en/products/ad74413r.html + +properties: + compatible: + enum: + - adi,ad74412r + - adi,ad74413r + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + spi-max-frequency: + maximum: 1000000 + + spi-cpol: true + + interrupts: + maxItems: 1 + + refin-supply: true + + shunt-resistor-micro-ohms: + description: + Shunt (sense) resistor value in micro-Ohms. + default: 100000000 + +required: + - compatible + - reg + - spi-max-frequency + - spi-cpol + - refin-supply + +additionalProperties: false + +patternProperties: + "^channel@[0-3]$": + type: object + description: Represents the external channels which are connected to the device. + + properties: + reg: + description: | + The channel number. It can have up to 4 channels numbered from 0 to 3. + minimum: 0 + maximum: 3 + + adi,ch-func: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Channel function. + HART functions are not supported on AD74412R. + 0 - CH_FUNC_HIGH_IMPEDANCE + 1 - CH_FUNC_VOLTAGE_OUTPUT + 2 - CH_FUNC_CURRENT_OUTPUT + 3 - CH_FUNC_VOLTAGE_INPUT + 4 - CH_FUNC_CURRENT_INPUT_EXT_POWER + 5 - CH_FUNC_CURRENT_INPUT_LOOP_POWER + 6 - CH_FUNC_RESISTANCE_INPUT + 7 - CH_FUNC_DIGITAL_INPUT_LOGIC + 8 - CH_FUNC_DIGITAL_INPUT_LOOP_POWER + 9 - CH_FUNC_CURRENT_INPUT_EXT_POWER_HART + 10 - CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART + minimum: 0 + maximum: 10 + default: 0 + + adi,gpo-comparator: + type: boolean + description: | + Whether to configure GPO as a comparator or not. + When not configured as a comparator, the GPO will be treated as an + output-only GPIO. + + required: + - reg + +examples: + - | + #include + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + status = "okay"; + + ad74413r@0 { + compatible = "adi,ad74413r"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gpio>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + + refin-supply = <&ad74413r_refin>; + + channel@0 { + reg = <0>; + + adi,ch-func = ; + }; + + channel@1 { + reg = <1>; + + adi,ch-func = ; + }; + + channel@2 { + reg = <2>; + + adi,ch-func = ; + adi,gpo-comparator; + }; + + channel@3 { + reg = <3>; + + adi,ch-func = ; + }; + }; + }; +... -- cgit From 1665a92f780ac47c56c47916a9f8c4efbdd794b9 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sat, 4 Dec 2021 16:58:17 +0000 Subject: dt-bindings: iio: dac: adi,ad5755: drop unrelated included. Probably a cut and paste error, but the binding header used in the example is for the wrong device and nothing from it is used. Signed-off-by: Jonathan Cameron Cc: Sean Nyekjaer Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/iio/dac/adi,ad5755.yaml | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5755.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5755.yaml index be419ac46caa..f866b88e1440 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5755.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5755.yaml @@ -125,7 +125,6 @@ oneOf: examples: - | - #include spi { #address-cells = <1>; #size-cells = <0>; -- cgit From 918aaae300a634c4e0e98ad6820c9dc31eba09af Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 13 Dec 2021 09:26:05 +0100 Subject: dt-bindings: phy: qcom,qusb2: Add SM6350 compatible Add devicetree compatible for the usb phy on SM6350 SoC. Signed-off-by: Luca Weiss Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20211213082614.22651-5-luca.weiss@fairphone.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index aa2e409a1a09..e651a63a4be3 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -30,6 +30,7 @@ properties: - enum: - qcom,sc7180-qusb2-phy - qcom,sdm845-qusb2-phy + - qcom,sm6350-qusb2-phy - const: qcom,qusb2-v2-phy reg: maxItems: 1 -- cgit From b3b5516a6fee5a4d39cd04fd84ed0a64b74e7238 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 2 Dec 2021 16:02:32 +0800 Subject: dt-bindings: phy: Add imx8 pcie phy driver support Add dt-binding for the standalone i.MX8 PCIe PHY driver. Signed-off-by: Richard Zhu Tested-by: Marcel Ziswiler Reviewed-by: Tim Harvey Tested-by: Tim Harvey Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/1638432158-4119-3-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml new file mode 100644 index 000000000000..b6421eedece3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8 SoC series PCIe PHY Device Tree Bindings + +maintainers: + - Richard Zhu + +properties: + "#phy-cells": + const: 0 + + compatible: + enum: + - fsl,imx8mm-pcie-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ref + + resets: + maxItems: 1 + + reset-names: + items: + - const: pciephy + + fsl,refclk-pad-mode: + description: | + Specifies the mode of the refclk pad used. It can be UNUSED(PHY + refclock is derived from SoC internal source), INPUT(PHY refclock + is provided externally via the refclk pad) or OUTPUT(PHY refclock + is derived from SoC internal source and provided on the refclk pad). + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants + to be used. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + + fsl,tx-deemph-gen1: + description: Gen1 De-emphasis value (optional). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + fsl,tx-deemph-gen2: + description: Gen2 De-emphasis value (optional). + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + fsl,clkreq-unsupported: + type: boolean + description: A boolean property indicating the CLKREQ# signal is + not supported in the board design (optional) + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + - fsl,refclk-pad-mode + +additionalProperties: false + +examples: + - | + #include + #include + #include + + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mm-pcie-phy"; + reg = <0x32f00000 0x10000>; + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "ref"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + assigned-clock-rates = <100000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>; + resets = <&src IMX8MQ_RESET_PCIEPHY>; + reset-names = "pciephy"; + fsl,refclk-pad-mode = ; + #phy-cells = <0>; + }; +... -- cgit From 0ae8c6252888d487f69b406369c3176172bb2064 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 9 Dec 2021 14:18:41 +0530 Subject: dt-bindings: interconnect: Add Qualcomm SM8450 DT bindings The Qualcomm SM8450 SoC has several bus fabrics that could be controlled and tuned dynamically according to the bandwidth demand Signed-off-by: Vinod Koul Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211209084842.189627-2-vkoul@kernel.org Signed-off-by: Georgi Djakov --- Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index 3fd1a134162d..cbb24f9bb609 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -104,6 +104,17 @@ properties: - qcom,sm8350-mmss-noc - qcom,sm8350-compute-noc - qcom,sm8350-system-noc + - qcom,sm8450-aggre1-noc + - qcom,sm8450-aggre2-noc + - qcom,sm8450-clk-virt + - qcom,sm8450-config-noc + - qcom,sm8450-gem-noc + - qcom,sm8450-lpass-ag-noc + - qcom,sm8450-mc-virt + - qcom,sm8450-mmss-noc + - qcom,sm8450-nsp-noc + - qcom,sm8450-pcie-anoc + - qcom,sm8450-system-noc '#interconnect-cells': enum: [ 1, 2 ] -- cgit From 061dbde2bf3b12d80a4efd4b40db0b272e55b7f5 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 15 Dec 2021 08:23:23 +0800 Subject: dt-bindings: interconnect: Add Qualcomm QCM2290 NoC support Add bindings for Qualcomm QCM2290 Network-On-Chip interconnect devices. Signed-off-by: Shawn Guo Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211215002324.1727-5-shawn.guo@linaro.org Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom,qcm2290.yaml | 137 +++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml new file mode 100644 index 000000000000..f65a2fe846de --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcm2290.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,qcm2290.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCM2290 Network-On-Chip interconnect + +maintainers: + - Shawn Guo + +description: | + The Qualcomm QCM2290 interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +properties: + reg: + maxItems: 1 + + compatible: + enum: + - qcom,qcm2290-bimc + - qcom,qcm2290-cnoc + - qcom,qcm2290-snoc + + '#interconnect-cells': + const: 1 + + clock-names: + items: + - const: bus + - const: bus_a + + clocks: + items: + - description: Bus Clock + - description: Bus A Clock + +# Child node's properties +patternProperties: + '^interconnect-[a-z0-9]+$': + type: object + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + + properties: + compatible: + enum: + - qcom,qcm2290-qup-virt + - qcom,qcm2290-mmrt-virt + - qcom,qcm2290-mmnrt-virt + + '#interconnect-cells': + const: 1 + + clock-names: + items: + - const: bus + - const: bus_a + + clocks: + items: + - description: Bus Clock + - description: Bus A Clock + + required: + - compatible + - '#interconnect-cells' + - clock-names + - clocks + + additionalProperties: false + +required: + - compatible + - reg + - '#interconnect-cells' + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + #include + + snoc: interconnect@1880000 { + compatible = "qcom,qcm2290-snoc"; + reg = <0x01880000 0x60200>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + + qup_virt: interconnect-qup { + compatible = "qcom,qcm2290-qup-virt"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_QUP_CLK>, + <&rpmcc RPM_SMD_QUP_A_CLK>; + }; + + mmnrt_virt: interconnect-mmnrt { + compatible = "qcom,qcm2290-mmnrt-virt"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_MMNRT_CLK>, + <&rpmcc RPM_SMD_MMNRT_A_CLK>; + }; + + mmrt_virt: interconnect-mmrt { + compatible = "qcom,qcm2290-mmrt-virt"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_MMRT_CLK>, + <&rpmcc RPM_SMD_MMRT_A_CLK>; + }; + }; + + cnoc: interconnect@1900000 { + compatible = "qcom,qcm2290-cnoc"; + reg = <0x01900000 0x8200>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + bimc: interconnect@4480000 { + compatible = "qcom,qcm2290-bimc"; + reg = <0x04480000 0x80000>; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; -- cgit From d8f0136919128135b0a7a7e3a05dca5b569eef45 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 13 Dec 2021 18:44:48 +0530 Subject: dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SM8450 Document the compatible string for USB phy found in Qualcomm SM8450 SoC Signed-off-by: Vinod Koul Acked-by: Rob Herring Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213131450.535775-1-vkoul@kernel.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml index 20203a8a9e41..0dfe6914ec87 100644 --- a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml @@ -20,6 +20,7 @@ properties: - qcom,sm8150-usb-hs-phy - qcom,sm8250-usb-hs-phy - qcom,sm8350-usb-hs-phy + - qcom,sm8450-usb-hs-phy - qcom,usb-snps-femto-v2-phy reg: -- cgit From 03eacc3c6523749294d2d0922591c0ad78a0b633 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 13 Dec 2021 18:44:49 +0530 Subject: dt-bindings: phy: qcom,qmp: Add SM8450 USB3 PHY Add compatible string for USB QMP phy in Qualcomm SM8450 SoC Signed-off-by: Vinod Koul Acked-by: Rob Herring Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213131450.535775-2-vkoul@kernel.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index c59bbca9a900..d625a6fe0205 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -51,6 +51,7 @@ properties: - qcom,sm8350-qmp-usb3-phy - qcom,sm8350-qmp-usb3-uni-phy - qcom,sm8450-qmp-ufs-phy + - qcom,sm8450-qmp-usb3-phy - qcom,sdx55-qmp-pcie-phy - qcom,sdx55-qmp-usb3-uni-phy -- cgit From bf75e044ca6b03256faa99590c264251f052eefb Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 7 Dec 2021 17:54:44 +0200 Subject: dt-bindings:iio:filter: add admv8818 doc Add device tree bindings for the ADMV8818 Filter. Signed-off-by: Antoniu Miclaus Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- .../bindings/iio/filter/adi,admv8818.yaml | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml b/Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml new file mode 100644 index 000000000000..b77e855bd594 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/filter/adi,admv8818.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/filter/adi,admv8818.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADMV8818 Digitally Tunable, High-Pass and Low-Pass Filter + +maintainers: + - Antoniu Miclaus + +description: | + Fully monolithic microwave integrated circuit (MMIC) that + features a digitally selectable frequency of operation. + The device features four independently controlled high-pass + filters (HPFs) and four independently controlled low-pass filters + (LPFs) that span the 2 GHz to 18 GHz frequency range. + + https://www.analog.com/en/products/admv8818.html + +properties: + compatible: + enum: + - adi,admv8818 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 10000000 + + clocks: + description: + Definition of the external clock. + minItems: 1 + + clock-names: + items: + - const: rf_in + + clock-output-names: + maxItems: 1 + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + admv8818@0 { + compatible = "adi,admv8818"; + reg = <0>; + spi-max-frequency = <10000000>; + clocks = <&admv8818_rfin>; + clock-names = "rf_in"; + }; + }; +... -- cgit From bf92d87d7c678b29b18e65ae4a97ced4bbe18c06 Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 7 Dec 2021 17:54:45 +0200 Subject: iio:filter:admv8818: Add sysfs ABI documentation Add initial ABI documentation for admv8818 filter sysfs interfaces. Signed-off-by: Antoniu Miclaus Signed-off-by: Jonathan Cameron --- Documentation/ABI/testing/sysfs-bus-iio-filter-admv8818 | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-filter-admv8818 (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-iio-filter-admv8818 b/Documentation/ABI/testing/sysfs-bus-iio-filter-admv8818 new file mode 100644 index 000000000000..f6c035752639 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-filter-admv8818 @@ -0,0 +1,16 @@ +What: /sys/bus/iio/devices/iio:deviceX/filter_mode_available +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Reading this returns the valid values that can be written to the + on_altvoltage0_mode attribute: + + - auto -> Adjust bandpass filter to track changes in input clock rate. + - manual -> disable/unregister the clock rate notifier / input clock tracking. + +What: /sys/bus/iio/devices/iio:deviceX/filter_mode +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + This attribute configures the filter mode. + Reading returns the actual mode. -- cgit From b0a96c5f599ecf263119d092e22a984d3248fd85 Mon Sep 17 00:00:00 2001 From: Mihail Chindris Date: Mon, 13 Dec 2021 11:08:24 +0000 Subject: dt-bindings: iio: dac: Add adi,ad3552r.yaml Add documentation for ad3552r and ad3542r Signed-off-by: Mihail Chindris Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/dac/adi,ad3552r.yaml | 217 +++++++++++++++++++++ 1 file changed, 217 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml new file mode 100644 index 000000000000..501a463e5d88 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml @@ -0,0 +1,217 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad3552r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD2552R DAC device driver + +maintainers: + - Mihail Chindris + +description: | + Bindings for the Analog Devices AD3552R DAC device and similar. + Datasheet can be found here: + https://www.analog.com/media/en/technical-documentation/data-sheets/ad3542r.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad3552r.pdf + +properties: + compatible: + enum: + - adi,ad3542r + - adi,ad3552r + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 30000000 + + reset-gpios: + maxItems: 1 + + ldac-gpios: + description: | + LDAC pin to be used as a hardware trigger to update the DAC channels. + maxItems: 1 + + vref-supply: + description: + The regulator to use as an external reference. If it does not exists the + internal reference will be used. External reference must be 2.5V + + adi,vref-out-en: + description: Vref I/O driven by internal vref to 2.5V. If not set, Vref pin + will be floating. + type: boolean + + adi,sdo-drive-strength: + description: | + Configure SDIO0 and SDIO1 strength levels: + - 0: low SDO drive strength. + - 1: medium low SDO drive strength. + - 2: medium high SDO drive strength. + - 3: high SDO drive strength + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^channel@([0-1])$": + type: object + description: Configurations of the DAC Channels + + additionalProperties: false + + properties: + reg: + description: Channel number + enum: [0, 1] + + adi,output-range-microvolt: true + + custom-output-range-config: + type: object + description: Configuration of custom range when + adi,output-range-microvolt is not present. + The formulas for calculation the output voltages are + Vout_fs = 2.5 + [(GainN + Offset/1024) * 2.5 * Rfbx * 1.03] + Vout_zs = 2.5 - [(GainP + Offset/1024) * 2.5 * Rfbx * 1.03] + + properties: + adi,gain-offset: + description: Gain offset used in the above formula + $ref: /schemas/types.yaml#/definitions/int32 + maximum: 511 + minimum: -511 + + adi,gain-scaling-p-inv-log2: + description: GainP = 1 / ( 2 ^ adi,gain-scaling-p-inv-log2) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + adi,gain-scaling-n-inv-log2: + description: GainN = 1 / ( 2 ^ adi,gain-scaling-n-inv-log2) + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + adi,rfb-ohms: + description: Feedback Resistor + + required: + - adi,gain-offset + - adi,gain-scaling-p-inv-log2 + - adi,gain-scaling-n-inv-log2 + - adi,rfb-ohms + + required: + - reg + + oneOf: + # If adi,output-range-microvolt is missing, + # custom-output-range-config must be used + - required: + - adi,output-range-microvolt + + - required: + - custom-output-range-config + +allOf: + - if: + properties: + compatible: + contains: + const: adi,ad3542r + then: + patternProperties: + "^channel@([0-1])$": + type: object + properties: + adi,output-range-microvolt: + description: | + Voltage output range of the channel as + Required connections: + Rfb1x for: 0 to 2.5 V; 0 to 3V; 0 to 5 V; + Rfb2x for: 0 to 10 V; 2.5 to 7.5V; -5 to 5 V; + oneOf: + - items: + - const: 0 + - enum: [2500000, 3000000, 5000000, 10000000] + - items: + - const: -2500000 + - const: 7500000 + - items: + - const: -5000000 + - const: 5000000 + + required: + - adi,output-range-microvolt + + - if: + properties: + compatible: + contains: + const: adi,ad3552r + then: + patternProperties: + "^channel@([0-1])$": + type: object + properties: + adi,output-range-microvolt: + description: | + Voltage output range of the channel as + Required connections: + Rfb1x for: 0 to 2.5 V; 0 to 5 V; + Rfb2x for: 0 to 10 V; -5 to 5 V; + Rfb4x for: -10 to 10V + oneOf: + - items: + - const: 0 + - enum: [2500000, 5000000, 10000000] + - items: + - const: -5000000 + - const: 5000000 + - items: + - const: -10000000 + - const: 10000000 + +required: + - compatible + - reg + - spi-max-frequency + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + ad3552r@0 { + compatible = "adi,ad3552r"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + adi,output-range-microvolt = <0 10000000>; + }; + channel@1 { + reg = <1>; + custom-output-range-config { + adi,gain-offset = <5>; + adi,gain-scaling-p-inv-log2 = <1>; + adi,gain-scaling-n-inv-log2 = <2>; + adi,rfb-ohms = <1>; + }; + }; + }; + }; +... -- cgit From ef8261dce39503cddf1fe1f44578815df8ee4b2e Mon Sep 17 00:00:00 2001 From: James Lo Date: Thu, 16 Dec 2021 11:08:08 -0800 Subject: dt-bindings: spmi: remove the constraint of reg property 'reg' is controller specific so we shouldn't even be specifying it here. Just remove it. Link: https://lore.kernel.org/r/20211119034613.32489-2-james.lo@mediatek.com Reviewed-by: Rob Herring Signed-off-by: James Lo Signed-off-by: Hsin-Hsiung Wang Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20211216190812.1574801-3-sboyd@kernel.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/spmi/spmi.yaml | 3 --- 1 file changed, 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spmi/spmi.yaml b/Documentation/devicetree/bindings/spmi/spmi.yaml index 1d243faef2f8..c1b06fa5c631 100644 --- a/Documentation/devicetree/bindings/spmi/spmi.yaml +++ b/Documentation/devicetree/bindings/spmi/spmi.yaml @@ -24,9 +24,6 @@ properties: $nodename: pattern: "^spmi@.*" - reg: - maxItems: 1 - "#address-cells": const: 2 -- cgit From 312644352f53a22f6f11f16481a4f23694650aba Mon Sep 17 00:00:00 2001 From: James Lo Date: Thu, 16 Dec 2021 11:08:09 -0800 Subject: dt-bindings: spmi: document binding for the Mediatek SPMI controller This adds documentation for the SPMI controller found on Mediatek SoCs. Link: https://lore.kernel.org/r/20211119034613.32489-3-james.lo@mediatek.com Reviewed-by: Rob Herring Signed-off-by: James Lo Signed-off-by: Hsin-Hsiung Wang Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20211216190812.1574801-4-sboyd@kernel.org Signed-off-by: Greg Kroah-Hartman --- .../bindings/spmi/mtk,spmi-mtk-pmif.yaml | 76 ++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml new file mode 100644 index 000000000000..2445c5e0b0ef --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek SPMI Controller Device Tree Bindings + +maintainers: + - Hsin-Hsiung Wang + +description: |+ + On MediaTek SoCs the PMIC is connected via SPMI and the controller allows + for multiple SoCs to control a single SPMI master. + +allOf: + - $ref: "spmi.yaml" + +properties: + compatible: + enum: + - mediatek,mt6873-spmi + - mediatek,mt8195-spmi + + reg: + maxItems: 2 + + reg-names: + items: + - const: pmif + - const: spmimst + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: pmif_sys_ck + - const: pmif_tmr_ck + - const: spmimst_clk_mux + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + spmi: spmi@10027000 { + compatible = "mediatek,mt6873-spmi"; + reg = <0x10027000 0xe00>, + <0x10029000 0x100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; +... -- cgit From 9710b162c8b93cda554146520cddbc68c95dc6a6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 15 Dec 2021 01:58:38 +0300 Subject: dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings There are two different PCIe PHYs on SM8450, one having one lane and another with two lanes. Add DT bindings for the first one. Support for second PCIe host and PHY will be submitted separately. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211214225846.2043361-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index d625a6fe0205..5887b046c640 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -50,6 +50,7 @@ properties: - qcom,sm8350-qmp-ufs-phy - qcom,sm8350-qmp-usb3-phy - qcom,sm8350-qmp-usb3-uni-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-ufs-phy - qcom,sm8450-qmp-usb3-phy - qcom,sdx55-qmp-pcie-phy @@ -334,6 +335,7 @@ allOf: - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy then: properties: clocks: -- cgit From ae807879e6be321308ee4196275bfb8408858ba7 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Thu, 9 Dec 2021 17:42:32 +0000 Subject: dt-bindings: nvmem: mediatek: add support bits property Add support bits property, will satisfy more consumers. Acked-by: Rob Herring Signed-off-by: Chunfeng Yun Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20211209174235.14049-2-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/mtk-efuse.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt index b6791702bcfc..ec70c5b7a340 100644 --- a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt +++ b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt @@ -10,6 +10,7 @@ Required properties: "mediatek,mt8192-efuse", "mediatek,efuse": for MT8192 "mediatek,mt8516-efuse", "mediatek,efuse": for MT8516 - reg: Should contain registers location and length +- bits: contain the bits range by offset and size = Data cells = Are child nodes of MTK-EFUSE, bindings of which as described in -- cgit From 9d87b0ac80e3949b372108eb6b7ae172dc71ec5c Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Thu, 9 Dec 2021 17:42:33 +0000 Subject: dt-bindings: nvmem: mediatek: add support for mt8195 Add compatible for mt8195 Acked-by: Rob Herring Signed-off-by: Chunfeng Yun Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20211209174235.14049-3-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/mtk-efuse.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt index ec70c5b7a340..39d529599444 100644 --- a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt +++ b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt @@ -8,6 +8,7 @@ Required properties: "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623 "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173 "mediatek,mt8192-efuse", "mediatek,efuse": for MT8192 + "mediatek,mt8195-efuse", "mediatek,efuse": for MT8195 "mediatek,mt8516-efuse", "mediatek,efuse": for MT8516 - reg: Should contain registers location and length - bits: contain the bits range by offset and size -- cgit From 15c00b681760b4e0c0127439ab18cdce73ae1f0b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 9 Dec 2021 17:42:35 +0000 Subject: dt-bindings: nvmem: Add missing 'reg' property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With 'unevaluatedProperties' support implemented, the following warnings are generated in the nvmem examples: Documentation/devicetree/bindings/nvmem/st,stm32-romem.example.dt.yaml: efuse@1fff7800: Unevaluated properties are not allowed ('reg' was unexpected) Documentation/devicetree/bindings/nvmem/rmem.example.dt.yaml: nvram@10000000: Unevaluated properties are not allowed ('reg' was unexpected) Documentation/devicetree/bindings/nvmem/brcm,nvram.example.dt.yaml: nvram@1eff0000: Unevaluated properties are not allowed ('reg' was unexpected) Add the missing 'reg' property definition. Cc: Srinivas Kandagatla Cc: Maxime Coquelin Cc: Alexandre Torgue Cc: Rafał Miłecki Cc: Saenz Julienne Cc: Fabrice Gasnier Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-arm-kernel@lists.infradead.org Reviewed-by: Fabrice Gasnier Reviewed-by: Thierry Reding Signed-off-by: Rob Herring Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20211209174235.14049-5-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml | 3 +++ Documentation/devicetree/bindings/nvmem/rmem.yaml | 3 +++ Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml | 3 +++ 3 files changed, 9 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml b/Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml index 58ff6b0bdb1a..8c3f0cd22821 100644 --- a/Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml +++ b/Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml @@ -24,6 +24,9 @@ properties: compatible: const: brcm,nvram + reg: + maxItems: 1 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/nvmem/rmem.yaml b/Documentation/devicetree/bindings/nvmem/rmem.yaml index 1d85a0a30846..a4a755dcfc43 100644 --- a/Documentation/devicetree/bindings/nvmem/rmem.yaml +++ b/Documentation/devicetree/bindings/nvmem/rmem.yaml @@ -19,6 +19,9 @@ properties: - raspberrypi,bootloader-config - const: nvmem-rmem + reg: + maxItems: 1 + no-map: $ref: /schemas/types.yaml#/definitions/flag description: diff --git a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml index a48c8fa56bce..448a2678dc62 100644 --- a/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml +++ b/Documentation/devicetree/bindings/nvmem/st,stm32-romem.yaml @@ -24,6 +24,9 @@ properties: - st,stm32f4-otp - st,stm32mp15-bsec + reg: + maxItems: 1 + patternProperties: "^.*@[0-9a-f]+$": type: object -- cgit From 39dd2d1e251d3ad7910aadac1d723e93e201dafa Mon Sep 17 00:00:00 2001 From: Anand Ashok Dumbre Date: Fri, 3 Dec 2021 21:23:57 +0000 Subject: dt-bindings: iio: adc: Add Xilinx AMS binding documentation Xilinx AMS have several ADC channels that can be used for measurement of different voltages and temperatures. Document the same in the bindings. Signed-off-by: Anand Ashok Dumbre Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211203212358.31444-5-anand.ashok.dumbre@xilinx.com Signed-off-by: Jonathan Cameron --- .../bindings/iio/adc/xlnx,zynqmp-ams.yaml | 227 +++++++++++++++++++++ 1 file changed, 227 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml new file mode 100644 index 000000000000..87992db389b2 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml @@ -0,0 +1,227 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/xlnx,zynqmp-ams.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynq Ultrascale AMS controller + +maintainers: + - Anand Ashok Dumbre + +description: | + The AMS (Analog Monitoring System) includes an ADC as well as on-chip sensors + that can be used to sample external voltages and monitor on-die operating + conditions, such as temperature and supply voltage levels. + The AMS has two SYSMON blocks which are PL (Programmable Logic) SYSMON and + PS (Processing System) SYSMON. + All designs should have AMS registers, but PS and PL are optional. The + AMS controller can work with only PS, only PL and both PS and PL + configurations. Please specify registers according to your design. Devicetree + should always have AMS module property. Providing PS & PL module is optional. + + AMS Channel Details + ``````````````````` + Sysmon Block |Channel| Details |Measurement + |Number | |Type + --------------------------------------------------------------------------------------------------------- + AMS CTRL |0 |System PLLs voltage measurement, VCC_PSPLL. |Voltage + |1 |Battery voltage measurement, VCC_PSBATT. |Voltage + |2 |PL Internal voltage measurement, VCCINT. |Voltage + |3 |Block RAM voltage measurement, VCCBRAM. |Voltage + |4 |PL Aux voltage measurement, VCCAUX. |Voltage + |5 |Voltage measurement for six DDR I/O PLLs, VCC_PSDDR_PLL. |Voltage + |6 |VCC_PSINTFP_DDR voltage measurement. |Voltage + --------------------------------------------------------------------------------------------------------- + PS Sysmon |7 |LPD temperature measurement. |Temperature + |8 |FPD temperature measurement (REMOTE). |Temperature + |9 |VCC PS LPD voltage measurement (supply1). |Voltage + |10 |VCC PS FPD voltage measurement (supply2). |Voltage + |11 |PS Aux voltage reference (supply3). |Voltage + |12 |DDR I/O VCC voltage measurement. |Voltage + |13 |PS IO Bank 503 voltage measurement (supply5). |Voltage + |14 |PS IO Bank 500 voltage measurement (supply6). |Voltage + |15 |VCCO_PSIO1 voltage measurement. |Voltage + |16 |VCCO_PSIO2 voltage measurement. |Voltage + |17 |VCC_PS_GTR voltage measurement (VPS_MGTRAVCC). |Voltage + |18 |VTT_PS_GTR voltage measurement (VPS_MGTRAVTT). |Voltage + |19 |VCC_PSADC voltage measurement. |Voltage + --------------------------------------------------------------------------------------------------------- + PL Sysmon |20 |PL temperature measurement. |Temperature + |21 |PL Internal voltage measurement, VCCINT. |Voltage + |22 |PL Auxiliary voltage measurement, VCCAUX. |Voltage + |23 |ADC Reference P+ voltage measurement. |Voltage + |24 |ADC Reference N- voltage measurement. |Voltage + |25 |PL Block RAM voltage measurement, VCCBRAM. |Voltage + |26 |LPD Internal voltage measurement, VCC_PSINTLP (supply4). |Voltage + |27 |FPD Internal voltage measurement, VCC_PSINTFP (supply5). |Voltage + |28 |PS Auxiliary voltage measurement (supply6). |Voltage + |29 |PL VCCADC voltage measurement (vccams). |Voltage + |30 |Differential analog input signal voltage measurment. |Voltage + |31 |VUser0 voltage measurement (supply7). |Voltage + |32 |VUser1 voltage measurement (supply8). |Voltage + |33 |VUser2 voltage measurement (supply9). |Voltage + |34 |VUser3 voltage measurement (supply10). |Voltage + |35 |Auxiliary ch 0 voltage measurement (VAux0). |Voltage + |36 |Auxiliary ch 1 voltage measurement (VAux1). |Voltage + |37 |Auxiliary ch 2 voltage measurement (VAux2). |Voltage + |38 |Auxiliary ch 3 voltage measurement (VAux3). |Voltage + |39 |Auxiliary ch 4 voltage measurement (VAux4). |Voltage + |40 |Auxiliary ch 5 voltage measurement (VAux5). |Voltage + |41 |Auxiliary ch 6 voltage measurement (VAux6). |Voltage + |42 |Auxiliary ch 7 voltage measurement (VAux7). |Voltage + |43 |Auxiliary ch 8 voltage measurement (VAux8). |Voltage + |44 |Auxiliary ch 9 voltage measurement (VAux9). |Voltage + |45 |Auxiliary ch 10 voltage measurement (VAux10). |Voltage + |46 |Auxiliary ch 11 voltage measurement (VAux11). |Voltage + |47 |Auxiliary ch 12 voltage measurement (VAux12). |Voltage + |48 |Auxiliary ch 13 voltage measurement (VAux13). |Voltage + |49 |Auxiliary ch 14 voltage measurement (VAux14). |Voltage + |50 |Auxiliary ch 15 voltage measurement (VAux15). |Voltage + -------------------------------------------------------------------------------------------------------- + +properties: + compatible: + enum: + - xlnx,zynqmp-ams + + interrupts: + maxItems: 1 + + reg: + description: AMS Controller register space + maxItems: 1 + + ranges: + description: + Maps the child address space for PS and/or PL. + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + '#io-channel-cells': + const: 1 + + ams-ps@0: + type: object + description: | + PS (Processing System) SYSMON is memory mapped to PS. This block has + built-in alarm generation logic that is used to interrupt the processor + based on condition set. + + properties: + compatible: + enum: + - xlnx,zynqmp-ams-ps + + reg: + description: Register Space for PS-SYSMON + maxItems: 1 + + required: + - compatible + - reg + + additionalProperties: false + + ams-pl@400: + type: object + description: + PL-SYSMON is capable of monitoring off chip voltage and temperature. + PL-SYSMON block has DRP, JTAG and I2C interface to enable monitoring + from external master. Out of this interface currently only DRP is + supported. This block has alarm generation logic that is used to + interrupt the processor based on condition set. + + properties: + compatible: + items: + - enum: + - xlnx,zynqmp-ams-pl + + reg: + description: Register Space for PL-SYSMON. + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + "^channel@([2-4][0-9]|50)$": + type: object + description: + Describes the external channels connected. + + properties: + reg: + description: + Pair of pins the channel is connected to. This value is + same as Channel Number for a particular channel. + minimum: 20 + maximum: 50 + + xlnx,bipolar: + $ref: /schemas/types.yaml#/definitions/flag + type: boolean + description: + If the set channel is used in bipolar mode. + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - ranges + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + xilinx_ams: ams@ffa50000 { + compatible = "xlnx,zynqmp-ams"; + interrupt-parent = <&gic>; + interrupts = <0 56 4>; + reg = <0x0 0xffa50000 0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + #io-channel-cells = <1>; + ranges = <0 0 0xffa50800 0x800>; + + ams_ps: ams-ps@0 { + compatible = "xlnx,zynqmp-ams-ps"; + reg = <0 0x400>; + }; + + ams_pl: ams-pl@400 { + compatible = "xlnx,zynqmp-ams-pl"; + reg = <0x400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + channel@30 { + reg = <30>; + xlnx,bipolar; + }; + channel@31 { + reg = <31>; + }; + channel@38 { + reg = <38>; + xlnx,bipolar; + }; + }; + }; + }; -- cgit From 8eff5b99042dd2fe6494e82ab1dc39bcdd5b976c Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Wed, 15 Dec 2021 16:02:46 -0500 Subject: dt-bindings: phy: phy-rockchip-inno-usb2: add rk3568 documentation The rk3568 usb2phy node is a standalone node with a single muxed interrupt. Add documentation for it to phy-rockchip-inno-usb2. Signed-off-by: Peter Geis Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211215210252.120923-3-pgwipeout@gmail.com Signed-off-by: Vinod Koul --- .../bindings/phy/phy-rockchip-inno-usb2.yaml | 44 ++++++++++++++++++++-- 1 file changed, 40 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml index 5bebd86bf8b6..4b75289735eb 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml @@ -18,6 +18,7 @@ properties: - rockchip,rk3328-usb2phy - rockchip,rk3366-usb2phy - rockchip,rk3399-usb2phy + - rockchip,rk3568-usb2phy - rockchip,rv1108-usb2phy reg: @@ -50,6 +51,10 @@ properties: description: Phandle to the extcon device providing the cable state for the otg phy. + interrupts: + description: Muxed interrupt for both ports + maxItems: 1 + rockchip,usbgrf: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -67,6 +72,7 @@ properties: interrupts: description: host linestate interrupt + maxItems: 1 interrupt-names: const: linestate @@ -78,8 +84,6 @@ properties: required: - "#phy-cells" - - interrupts - - interrupt-names otg-port: type: object @@ -109,8 +113,6 @@ properties: required: - "#phy-cells" - - interrupts - - interrupt-names required: - compatible @@ -120,6 +122,40 @@ required: - host-port - otg-port +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-usb2phy + + then: + properties: + host-port: + properties: + interrupts: false + + otg-port: + properties: + interrupts: false + + required: + - interrupts + + else: + properties: + interrupts: false + + host-port: + required: + - interrupts + - interrupt-names + + otg-port: + required: + - interrupts + - interrupt-names + additionalProperties: false examples: -- cgit From ce6d7056cc806099acff8cd89d95bdc6f53593db Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 21 Dec 2021 13:22:05 +0200 Subject: dt-bindings: iio: frequency: add admv1013 doc Add device tree bindings for the ADMV1013 Upconverter. Signed-off-by: Antoniu Miclaus Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211221112206.97066-2-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron --- .../bindings/iio/frequency/adi,admv1013.yaml | 91 ++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,admv1013.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,admv1013.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,admv1013.yaml new file mode 100644 index 000000000000..23f1f3b55abb --- /dev/null +++ b/Documentation/devicetree/bindings/iio/frequency/adi,admv1013.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,admv1013.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADMV1013 Microwave Upconverter + +maintainers: + - Antoniu Miclaus + +description: | + Wideband, microwave upconverter optimized for point to point microwave + radio designs operating in the 24 GHz to 44 GHz frequency range. + + https://www.analog.com/en/products/admv1013.html + +properties: + compatible: + enum: + - adi,admv1013 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 1000000 + + clocks: + description: + Definition of the external clock. + minItems: 1 + + clock-names: + items: + - const: lo_in + + vcm-supply: + description: + Analog voltage regulator. + + adi,detector-enable: + description: + Enable the Envelope Detector available at output pins VENV_P and + VENV_N. Disable to reduce power consumption. + type: boolean + + adi,input-mode: + description: + Select the input mode. + iq - in-phase quadrature (I/Q) input + if - complex intermediate frequency (IF) input + enum: [iq, if] + + adi,quad-se-mode: + description: + Switch the LO path from differential to single-ended operation. + se-neg - Single-Ended Mode, Negative Side Disabled. + se-pos - Single-Ended Mode, Positive Side Disabled. + diff - Differential Mode. + enum: [se-neg, se-pos, diff] + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - vcm-supply + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + admv1013@0{ + compatible = "adi,admv1013"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&admv1013_lo>; + clock-names = "lo_in"; + vcm-supply = <&vcm>; + adi,quad-se-mode = "diff"; + adi,detector-enable; + }; + }; +... -- cgit From f407c2374af64202c7b278580d22f81eec6f33c0 Mon Sep 17 00:00:00 2001 From: Antoniu Miclaus Date: Tue, 21 Dec 2021 13:22:06 +0200 Subject: Documentation:ABI:testing:admv1013: add ABI docs Add documentation for the use of the Local Oscillator Feedthrough Offset calibration. Signed-off-by: Antoniu Miclaus Link: https://lore.kernel.org/r/20211221112206.97066-3-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron --- .../ABI/testing/sysfs-bus-iio-frequency-admv1013 | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1013 (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1013 b/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1013 new file mode 100644 index 000000000000..de1e323e5d47 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1013 @@ -0,0 +1,38 @@ +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-1_i_calibphase +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Read/write unscaled value for the Local Oscillatior path quadrature I phase shift. + +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-1_q_calibphase +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Read/write unscaled value for the Local Oscillatior path quadrature Q phase shift. + +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_i_calibbias +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Read/write value for the Local Oscillatior Feedthrough Offset Calibration I Positive + side. + +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_q_calibbias +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Read/write value for the Local Oscillatior Feedthrough Offset Calibration Q Positive side. + +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage1_i_calibbias +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Read/write raw value for the Local Oscillatior Feedthrough Offset Calibration I Negative + side. + +What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage1_q_calibbias +KernelVersion: +Contact: linux-iio@vger.kernel.org +Description: + Read/write raw value for the Local Oscillatior Feedthrough Offset Calibration Q Negative + side. -- cgit From 088879292a0a3672a6acc9215174fbc355ed3daa Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 21 Dec 2021 15:50:00 +0800 Subject: dt-bindings:iio:adc: update the maintainer of vf610-adc Drop Fugang Duan as the vf610-adc maintainer, and add my self as the maintainer. Signed-off-by: Haibo Chen Acked-by: Rob Herring Link: https://lore.kernel.org/r/1640073000-32629-2-git-send-email-haibo.chen@nxp.com Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml b/Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml index 1ca571056ea9..925f355cc21f 100644 --- a/Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ADC found on Freescale vf610 and similar SoCs maintainers: - - Fugang Duan + - Haibo Chen description: ADCs found on vf610/i.MX6slx and upward SoCs from Freescale. -- cgit From 3ba4c0a8f4c91dc4c274bea7a8766463356d6704 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 18 Dec 2021 17:17:54 +0300 Subject: dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings There are two different PCIe PHYs on SM8450, one having one lane and another with two lanes. Add support for second (gen4, two lanes) PHY. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211218141754.503661-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 5887b046c640..e417cd667997 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -51,6 +51,7 @@ properties: - qcom,sm8350-qmp-usb3-phy - qcom,sm8350-qmp-usb3-uni-phy - qcom,sm8450-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen4x2-pcie-phy - qcom,sm8450-qmp-ufs-phy - qcom,sm8450-qmp-usb3-phy - qcom,sdx55-qmp-pcie-phy @@ -336,6 +337,7 @@ allOf: - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen4x2-pcie-phy then: properties: clocks: -- cgit From c6d92a287ae718c3207dddea3f36ea1689ac59a8 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Sat, 18 Dec 2021 16:27:58 +0800 Subject: dt-bindings: phy: mediatek: tphy: support software efuse load Add optional property nvmem-cells and nvmem-cell-names to support software efuse load, this helps to fix the efuse bit shift issue on mt8195 etc. Acked-by: Rob Herring Signed-off-by: Chunfeng Yun Link: https://lore.kernel.org/r/20211218082802.5256-1-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/mediatek,tphy.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 9e6c0f43f1c6..05ee274b4b71 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -160,6 +160,24 @@ patternProperties: - PHY_TYPE_PCIE - PHY_TYPE_SATA + nvmem-cells: + items: + - description: internal R efuse for U2 PHY or U3/PCIe PHY + - description: rx_imp_sel efuse for U3/PCIe PHY + - description: tx_imp_sel efuse for U3/PCIe PHY + description: | + Phandles to nvmem cell that contains the efuse data; + Available only for U2 PHY or U3/PCIe PHY of version 2/3, these + three items should be provided at the same time for U3/PCIe PHY, + when use software to load efuse; + If unspecified, will use hardware auto-load efuse. + + nvmem-cell-names: + items: + - const: intr + - const: rx_imp + - const: tx_imp + # The following optional vendor properties are only for debug or HQA test mediatek,eye-src: description: -- cgit From 3eb7754ff43827294bebcb2760969e9dc2283027 Mon Sep 17 00:00:00 2001 From: Ofir Bitton Date: Tue, 12 Oct 2021 20:52:46 +0300 Subject: habanalabs: debugfs support for larger I2C transactions I2C debugfs support is limited to 1 byte. We extend functionality to more than 1 byte by using one of the pad fields as a length. No backward compatibility issues as new F/W versions will treat 0 length as a 1 byte length transaction. Signed-off-by: Ofir Bitton Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- Documentation/ABI/testing/debugfs-driver-habanalabs | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/debugfs-driver-habanalabs b/Documentation/ABI/testing/debugfs-driver-habanalabs index 63c46d9d538f..6085ee506135 100644 --- a/Documentation/ABI/testing/debugfs-driver-habanalabs +++ b/Documentation/ABI/testing/debugfs-driver-habanalabs @@ -155,6 +155,13 @@ Description: Triggers an I2C transaction that is generated by the device's CPU. Writing to this file generates a write transaction while reading from the file generates a read transaction +What: /sys/kernel/debug/habanalabs/hl/i2c_len +Date: Dec 2021 +KernelVersion: 5.17 +Contact: obitton@habana.ai +Description: Sets I2C length in bytes for I2C transaction that is generated by + the device's CPU + What: /sys/kernel/debug/habanalabs/hl/i2c_reg Date: Jan 2019 KernelVersion: 5.1 -- cgit From a9ecddb9e30af1485c8f41afb0264ec53ae6f5ed Mon Sep 17 00:00:00 2001 From: Tomer Tayar Date: Sun, 14 Nov 2021 09:29:48 +0200 Subject: habanalabs: align debugfs documentation to alphabetical order Move an entry in the debugfs documentation to align with the alphabetical order which is kept this file. Signed-off-by: Tomer Tayar Reviewed-by: Oded Gabbay Signed-off-by: Oded Gabbay --- Documentation/ABI/testing/debugfs-driver-habanalabs | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/debugfs-driver-habanalabs b/Documentation/ABI/testing/debugfs-driver-habanalabs index 6085ee506135..2667cbf940f3 100644 --- a/Documentation/ABI/testing/debugfs-driver-habanalabs +++ b/Documentation/ABI/testing/debugfs-driver-habanalabs @@ -21,11 +21,11 @@ Description: Allow the root user to disable/enable in runtime the clock a different engine to disable/enable its clock gating feature. The bitmask is composed of 20 bits: - ======= ============ + ======= ============ 0 - 7 DMA channels 8 - 11 MME engines 12 - 19 TPC engines - ======= ============ + ======= ============ The bit's location of a specific engine can be determined using (1 << GAUDI_ENGINE_ID_*). GAUDI_ENGINE_ID_* values @@ -233,12 +233,6 @@ Description: Gets the state dump occurring on a CS timeout or failure. Writing an integer X discards X state dumps, so that the next read would return X+1-st newest state dump. -What: /sys/kernel/debug/habanalabs/hl/timeout_locked -Date: Sep 2021 -KernelVersion: 5.16 -Contact: obitton@habana.ai -Description: Sets the command submission timeout value in seconds. - What: /sys/kernel/debug/habanalabs/hl/stop_on_err Date: Mar 2020 KernelVersion: 5.6 @@ -246,6 +240,12 @@ Contact: ogabbay@kernel.org Description: Sets the stop-on_error option for the device engines. Value of "0" is for disable, otherwise enable. +What: /sys/kernel/debug/habanalabs/hl/timeout_locked +Date: Sep 2021 +KernelVersion: 5.16 +Contact: obitton@habana.ai +Description: Sets the command submission timeout value in seconds. + What: /sys/kernel/debug/habanalabs/hl/userptr Date: Jan 2019 KernelVersion: 5.1 -- cgit From 253f06c7b1c1729b50e7ec52638e046239327bb1 Mon Sep 17 00:00:00 2001 From: Swapnil Jakhade Date: Thu, 23 Dec 2021 07:01:25 +0100 Subject: dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names Rename SSC macros to use generic names instead of PHY specific names, so that they can be used to specify SSC modes for both Torrent and Sierra. Renaming the macros should not affect the things as these are not being used in any DTS file yet. Signed-off-by: Swapnil Jakhade Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211223060137.9252-4-sjakhade@cadence.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index bd9ae11c9994..2fec9e54ad0e 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -202,7 +202,7 @@ examples: #phy-cells = <0>; cdns,phy-type = ; cdns,num-lanes = <2>; - cdns,ssc-mode = ; + cdns,ssc-mode = ; }; phy@2 { @@ -211,7 +211,7 @@ examples: #phy-cells = <0>; cdns,phy-type = ; cdns,num-lanes = <1>; - cdns,ssc-mode = ; + cdns,ssc-mode = ; }; }; }; -- cgit From 262303b92945f4d05bec78ead17f5c7c0d098d54 Mon Sep 17 00:00:00 2001 From: Swapnil Jakhade Date: Thu, 23 Dec 2021 07:01:26 +0100 Subject: dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Add binding to specify Spread Spectrum Clocking mode used. Signed-off-by: Swapnil Jakhade Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211223060137.9252-5-sjakhade@cadence.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml index e71b32c9c0d1..a9e227d8b076 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml @@ -113,6 +113,15 @@ patternProperties: minimum: 1 maximum: 16 + cdns,ssc-mode: + description: + Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC, + EXTERNAL_SSC or INTERNAL_SSC. + Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 1 + required: - reg - resets -- cgit From 98644726044e7f08322ccfb683773514810744e8 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 30 Dec 2021 16:02:51 +0100 Subject: counter: Update documentation for new counter registration functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to replace the counter registration API also update the documentation to the new way. Reviewed-by: Jonathan Cameron Acked-by: William Breathitt Gray Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20211230150300.72196-15-u.kleine-koenig@pengutronix.de Signed-off-by: Greg Kroah-Hartman --- Documentation/driver-api/generic-counter.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/driver-api/generic-counter.rst b/Documentation/driver-api/generic-counter.rst index 1b487a331467..71ccc30e586b 100644 --- a/Documentation/driver-api/generic-counter.rst +++ b/Documentation/driver-api/generic-counter.rst @@ -262,11 +262,11 @@ order to communicate with the device: to read and write various Signals and Counts, and to set and get the "action mode" and "function mode" for various Synapses and Counts respectively. -A defined counter_device structure may be registered to the system by -passing it to the counter_register function, and unregistered by passing -it to the counter_unregister function. Similarly, the -devm_counter_register function may be used if device memory-managed -registration is desired. +A counter_device structure is allocated using counter_alloc() and then +registered to the system by passing it to the counter_add() function, and +unregistered by passing it to the counter_unregister function. There are +device managed variants of these functions: devm_counter_alloc() and +devm_counter_add(). The struct counter_comp structure is used to define counter extensions for Signals, Synapses, and Counts. -- cgit From 8f2cade5da97713e77ca5be576438f194b8873d7 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Sun, 2 Jan 2022 23:38:18 +0100 Subject: dt-bindings: mux: Document mux-states property In some cases, it is required to provide the state to which the mux controller has to be set to, from the consumer device tree node. Document the property mux-states that can be used for adding this support. Signed-off-by: Aswath Govindraju Reviewed-by: Rob Herring Signed-off-by: Peter Rosin Link: https://lore.kernel.org/r/f4d02ac8-23ee-d891-4056-75c672cc59c9@axentia.se Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/mux/gpio-mux.yaml | 11 +++++++-- .../devicetree/bindings/mux/mux-consumer.yaml | 21 +++++++++++++++++ .../devicetree/bindings/mux/mux-controller.yaml | 26 +++++++++++++++++++++- 3 files changed, 55 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mux/gpio-mux.yaml b/Documentation/devicetree/bindings/mux/gpio-mux.yaml index 0a7c8d64981a..ee4de9fbaf4d 100644 --- a/Documentation/devicetree/bindings/mux/gpio-mux.yaml +++ b/Documentation/devicetree/bindings/mux/gpio-mux.yaml @@ -26,7 +26,10 @@ properties: List of gpios used to control the multiplexer, least significant bit first. '#mux-control-cells': - const: 0 + enum: [ 0, 1 ] + + '#mux-state-cells': + enum: [ 1, 2 ] idle-state: default: -1 @@ -34,7 +37,11 @@ properties: required: - compatible - mux-gpios - - "#mux-control-cells" +anyOf: + - required: + - "#mux-control-cells" + - required: + - "#mux-state-cells" additionalProperties: false diff --git a/Documentation/devicetree/bindings/mux/mux-consumer.yaml b/Documentation/devicetree/bindings/mux/mux-consumer.yaml index 7af93298ab5c..d3d854967359 100644 --- a/Documentation/devicetree/bindings/mux/mux-consumer.yaml +++ b/Documentation/devicetree/bindings/mux/mux-consumer.yaml @@ -25,6 +25,17 @@ description: | strings to label each of the mux controllers listed in the "mux-controls" property. + If it is required to provide the state that the mux controller needs to + be set to, the property "mux-states" must be used. An optional property + "mux-state-names" can be used to provide a list of strings, to label + each of the multiplixer states listed in the "mux-states" property. + + Properties "mux-controls" and "mux-states" can be used depending on how + the consumers want to control the mux controller. If the consumer needs + needs to set multiple states in a mux controller, then property + "mux-controls" can be used. If the consumer needs to set the mux + controller to a given state then property "mux-states" can be used. + mux-ctrl-specifier typically encodes the chip-relative mux controller number. If the mux controller chip only provides a single mux controller, the mux-ctrl-specifier can typically be left out. @@ -35,12 +46,22 @@ properties: mux-controls: $ref: /schemas/types.yaml#/definitions/phandle-array + mux-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + mux-control-names: description: Devices that use more than a single mux controller can use the "mux-control-names" property to map the name of the requested mux controller to an index into the list given by the "mux-controls" property. + mux-state-names: + description: + Devices that use more than a single multiplexer state can use the + "mux-state-names" property to map the name of the requested mux + controller to an index into the list given by the "mux-states" + property. + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/mux/mux-controller.yaml b/Documentation/devicetree/bindings/mux/mux-controller.yaml index 736a84c3b6a5..c855fbad3884 100644 --- a/Documentation/devicetree/bindings/mux/mux-controller.yaml +++ b/Documentation/devicetree/bindings/mux/mux-controller.yaml @@ -25,7 +25,9 @@ description: | -------------------- Mux controller nodes must specify the number of cells used for the - specifier using the '#mux-control-cells' property. + specifier using the '#mux-control-cells' or '#mux-state-cells' property. + The value of '#mux-state-cells' will always be one greater than the value + of '#mux-control-cells'. Optionally, mux controller nodes can also specify the state the mux should have when it is idle. The idle-state property is used for this. If the @@ -67,6 +69,8 @@ select: pattern: '^mux-controller' - required: - '#mux-control-cells' + - required: + - '#mux-state-cells' properties: $nodename: @@ -75,6 +79,9 @@ properties: '#mux-control-cells': enum: [ 0, 1 ] + '#mux-state-cells': + enum: [ 1, 2 ] + idle-state: $ref: /schemas/types.yaml#/definitions/int32 minimum: -2 @@ -179,4 +186,21 @@ examples: }; }; }; + + - | + #include + + mux1: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; + }; + + transceiver4: can-phy4 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>; + mux-states = <&mux1 1>; + }; ... -- cgit