From 3ddfa03d8162264b32b95b26eccb902ed4e07f3f Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 30 Mar 2022 11:05:44 +1300 Subject: dt-bindings: mmc: xenon: Convert to JSON schema Convert the marvell,xenon-sdhci binding to JSON schema. Currently the in-tree dts files don't validate because they use sdhci@ instead of mmc@ as required by the generic mmc-controller schema. The compatible "marvell,sdhci-xenon" was not documented in the old binding but it accompanies the of "marvell,armada-3700-sdhci" in the armada-37xx SoC dtsi so this combination is added to the new binding document. Signed-off-by: Chris Packham Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220329220544.2132135-3-chris.packham@alliedtelesis.co.nz Signed-off-by: Ulf Hansson --- .../bindings/mmc/marvell,xenon-sdhci.txt | 173 ------------- .../bindings/mmc/marvell,xenon-sdhci.yaml | 275 +++++++++++++++++++++ 2 files changed, 275 insertions(+), 173 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt deleted file mode 100644 index c51a62d751dc..000000000000 --- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt +++ /dev/null @@ -1,173 +0,0 @@ -Marvell Xenon SDHCI Controller device tree bindings -This file documents differences between the core mmc properties -described by mmc.txt and the properties used by the Xenon implementation. - -Multiple SDHCs might be put into a single Xenon IP, to save size and cost. -Each SDHC is independent and owns independent resources, such as register sets, -clock and PHY. -Each SDHC should have an independent device tree node. - -Required Properties: -- compatible: should be one of the following - - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC. - Must provide a second register area and marvell,pad-type. - - "marvell,armada-ap806-sdhci": For controllers on Armada AP806. - - "marvell,armada-ap807-sdhci": For controllers on Armada AP807. - - "marvell,armada-cp110-sdhci": For controllers on Armada CP110. - -- clocks: - Array of clocks required for SDHC. - Require at least input clock for Xenon IP core. For Armada AP806 and - CP110, the AXI clock is also mandatory. - -- clock-names: - Array of names corresponding to clocks property. - The input clock for Xenon IP core should be named as "core". - The input clock for the AXI bus must be named as "axi". - -- reg: - * For "marvell,armada-3700-sdhci", two register areas. - The first one for Xenon IP register. The second one for the Armada 3700 SoC - PHY PAD Voltage Control register. - Please follow the examples with compatible "marvell,armada-3700-sdhci" - in below. - Please also check property marvell,pad-type in below. - - * For other compatible strings, one register area for Xenon IP. - -Optional Properties: -- marvell,xenon-sdhc-id: - Indicate the corresponding bit index of current SDHC in - SDHC System Operation Control Register Bit[7:0]. - Set/clear the corresponding bit to enable/disable current SDHC. - If Xenon IP contains only one SDHC, this property is optional. - -- marvell,xenon-phy-type: - Xenon support multiple types of PHYs. - To select eMMC 5.1 PHY, set: - marvell,xenon-phy-type = "emmc 5.1 phy" - eMMC 5.1 PHY is the default choice if this property is not provided. - To select eMMC 5.0 PHY, set: - marvell,xenon-phy-type = "emmc 5.0 phy" - - All those types of PHYs can support eMMC, SD and SDIO. - Please note that this property only presents the type of PHY. - It doesn't stand for the entire SDHC type or property. - For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only - supports eMMC 5.1. - -- marvell,xenon-phy-znr: - Set PHY ZNR value. - Only available for eMMC PHY. - Valid range = [0:0x1F]. - ZNR is set as 0xF by default if this property is not provided. - -- marvell,xenon-phy-zpr: - Set PHY ZPR value. - Only available for eMMC PHY. - Valid range = [0:0x1F]. - ZPR is set as 0xF by default if this property is not provided. - -- marvell,xenon-phy-nr-success-tun: - Set the number of required consecutive successful sampling points - used to identify a valid sampling window, in tuning process. - Valid range = [1:7]. - Set as 0x4 by default if this property is not provided. - -- marvell,xenon-phy-tun-step-divider: - Set the divider for calculating TUN_STEP. - Set as 64 by default if this property is not provided. - -- marvell,xenon-phy-slow-mode: - If this property is selected, transfers will bypass PHY. - Only available when bus frequency lower than 55MHz in SDR mode. - Disabled by default. Please only try this property if timing issues - always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25, - SD Default Speed and HS mode and eMMC legacy speed mode. - -- marvell,xenon-tun-count: - Xenon SDHC SoC usually doesn't provide re-tuning counter in - Capabilities Register 3 Bit[11:8]. - This property provides the re-tuning counter. - If this property is not set, default re-tuning counter will - be set as 0x9 in driver. - -- marvell,pad-type: - Type of Armada 3700 SoC PHY PAD Voltage Controller register. - Only valid when "marvell,armada-3700-sdhci" is selected. - Two types: "sd" and "fixed-1-8v". - If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning and is - switched to 1.8V when later in higher speed mode. - If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC. - Please follow the examples with compatible "marvell,armada-3700-sdhci" - in below. - -Example: -- For eMMC: - - sdhci@aa0000 { - compatible = "marvell,armada-ap806-sdhci"; - reg = <0xaa0000 0x1000>; - interrupts = - clocks = <&emmc_clk>,<&axi_clk>; - clock-names = "core", "axi"; - bus-width = <4>; - marvell,xenon-phy-slow-mode; - marvell,xenon-tun-count = <11>; - non-removable; - no-sd; - no-sdio; - - /* Vmmc and Vqmmc are both fixed */ - }; - -- For SD/SDIO: - - sdhci@ab0000 { - compatible = "marvell,armada-cp110-sdhci"; - reg = <0xab0000 0x1000>; - interrupts = - vqmmc-supply = <&sd_vqmmc_regulator>; - vmmc-supply = <&sd_vmmc_regulator>; - clocks = <&sdclk>, <&axi_clk>; - clock-names = "core", "axi"; - bus-width = <4>; - marvell,xenon-tun-count = <9>; - }; - -- For eMMC with compatible "marvell,armada-3700-sdhci": - - sdhci@aa0000 { - compatible = "marvell,armada-3700-sdhci"; - reg = <0xaa0000 0x1000>, - ; - interrupts = - clocks = <&emmcclk>; - clock-names = "core"; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - non-removable; - no-sd; - no-sdio; - - /* Vmmc and Vqmmc are both fixed */ - - marvell,pad-type = "fixed-1-8v"; - }; - -- For SD/SDIO with compatible "marvell,armada-3700-sdhci": - - sdhci@ab0000 { - compatible = "marvell,armada-3700-sdhci"; - reg = <0xab0000 0x1000>, - ; - interrupts = - vqmmc-supply = <&sd_regulator>; - /* Vmmc is fixed */ - clocks = <&sdclk>; - clock-names = "core"; - bus-width = <4>; - - marvell,pad-type = "sd"; - }; diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml new file mode 100644 index 000000000000..c79639e9027e --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml @@ -0,0 +1,275 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Xenon SDHCI Controller + +description: | + This file documents differences between the core MMC properties described by + mmc-controller.yaml and the properties used by the Xenon implementation. + + Multiple SDHCs might be put into a single Xenon IP, to save size and cost. + Each SDHC is independent and owns independent resources, such as register + sets, clock and PHY. + + Each SDHC should have an independent device tree node. + +maintainers: + - Ulf Hansson + +properties: + compatible: + oneOf: + - enum: + - marvell,armada-cp110-sdhci + - marvell,armada-ap806-sdhci + + - items: + - const: marvell,armada-ap807-sdhci + - const: marvell,armada-ap806-sdhci + + - items: + - const: marvell,armada-3700-sdhci + - const: marvell,sdhci-xenon + + reg: + minItems: 1 + maxItems: 2 + description: | + For "marvell,armada-3700-sdhci", two register areas. The first one + for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD + Voltage Control register. Please follow the examples with compatible + "marvell,armada-3700-sdhci" in below. + Please also check property marvell,pad-type in below. + + For other compatible strings, one register area for Xenon IP. + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: core + - const: axi + + marvell,xenon-sdhc-id: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + description: | + Indicate the corresponding bit index of current SDHC in SDHC System + Operation Control Register Bit[7:0]. Set/clear the corresponding bit to + enable/disable current SDHC. + + marvell,xenon-phy-type: + $ref: /schemas/types.yaml#/definitions/string + enum: + - "emmc 5.1 phy" + - "emmc 5.0 phy" + description: | + Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set: + marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default + choice if this property is not provided. To select eMMC 5.0 PHY, set: + marvell,xenon-phy-type = "emmc 5.0 phy" + + All those types of PHYs can support eMMC, SD and SDIO. Please note that + this property only presents the type of PHY. It doesn't stand for the + entire SDHC type or property. For example, "emmc 5.1 phy" doesn't mean + that this Xenon SDHC only supports eMMC 5.1. + + marvell,xenon-phy-znr: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 0x1f + default: 0xf + description: | + Set PHY ZNR value. + Only available for eMMC PHY. + + marvell,xenon-phy-zpr: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 0x1f + default: 0xf + description: | + Set PHY ZPR value. + Only available for eMMC PHY. + + marvell,xenon-phy-nr-success-tun: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 7 + default: 0x4 + description: | + Set the number of required consecutive successful sampling points + used to identify a valid sampling window, in tuning process. + + marvell,xenon-phy-tun-step-divider: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 64 + description: | + Set the divider for calculating TUN_STEP. + + marvell,xenon-phy-slow-mode: + type: boolean + description: | + If this property is selected, transfers will bypass PHY. + Only available when bus frequency lower than 55MHz in SDR mode. + Disabled by default. Please only try this property if timing issues + always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25, + SD Default Speed and HS mode and eMMC legacy speed mode. + + marvell,xenon-tun-count: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x9 + description: | + Xenon SDHC SoC usually doesn't provide re-tuning counter in + Capabilities Register 3 Bit[11:8]. + This property provides the re-tuning counter. + +allOf: + - $ref: mmc-controller.yaml# + - if: + properties: + compatible: + contains: + const: marvell,armada-3700-sdhci + + then: + properties: + reg: + items: + - description: Xenon IP registers + - description: Armada 3700 SoC PHY PAD Voltage Control register + minItems: 2 + + marvell,pad-type: + $ref: /schemas/types.yaml#/definitions/string + enum: + - sd + - fixed-1-8v + description: | + Type of Armada 3700 SoC PHY PAD Voltage Controller register. + If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning + and is switched to 1.8V when later in higher speed mode. + If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for + eMMC. + Please follow the examples with compatible + "marvell,armada-3700-sdhci" in below. + + required: + - marvell,pad-type + + - if: + properties: + compatible: + contains: + enum: + - marvell,armada-cp110-sdhci + - marvell,armada-ap807-sdhci + - marvell,armada-ap806-sdhci + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: core + - const: axi + + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + // For eMMC + #include + #include + + mmc@aa0000 { + compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci"; + reg = <0xaa0000 0x1000>; + interrupts = ; + clocks = <&emmc_clk 0>, <&axi_clk 0>; + clock-names = "core", "axi"; + bus-width = <4>; + marvell,xenon-phy-slow-mode; + marvell,xenon-tun-count = <11>; + non-removable; + no-sd; + no-sdio; + + /* Vmmc and Vqmmc are both fixed */ + }; + + - | + // For SD/SDIO + #include + #include + + mmc@ab0000 { + compatible = "marvell,armada-cp110-sdhci"; + reg = <0xab0000 0x1000>; + interrupts = ; + vqmmc-supply = <&sd_vqmmc_regulator>; + vmmc-supply = <&sd_vmmc_regulator>; + clocks = <&sdclk 0>, <&axi_clk 0>; + clock-names = "core", "axi"; + bus-width = <4>; + marvell,xenon-tun-count = <9>; + }; + + - | + // For eMMC with compatible "marvell,armada-3700-sdhci": + #include + #include + + mmc@aa0000 { + compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon"; + reg = <0xaa0000 0x1000>, + <0x17808 0x4>; + interrupts = ; + clocks = <&emmcclk 0>; + clock-names = "core"; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + non-removable; + no-sd; + no-sdio; + + /* Vmmc and Vqmmc are both fixed */ + + marvell,pad-type = "fixed-1-8v"; + }; + + - | + // For SD/SDIO with compatible "marvell,armada-3700-sdhci": + #include + #include + + mmc@ab0000 { + compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon"; + reg = <0xab0000 0x1000>, + <0x17808 0x4>; + interrupts = ; + vqmmc-supply = <&sd_regulator>; + /* Vmmc is fixed */ + clocks = <&sdclk 0>; + clock-names = "core"; + bus-width = <4>; + + marvell,pad-type = "sd"; + }; -- cgit From 7792fdf626c20aa4e0d2b0daacf4e30df3ff9583 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Wed, 30 Mar 2022 17:45:31 +0800 Subject: dt-bindings: mmc: mtk-sd: increase reg items MediaTek has a new version of mmc IP since mt8183. Some IO registers are moved to top to improve hardware design and named as "host top registers". Add host top register in the reg binding description for mt8183 and successors. Signed-off-by: Wenbin Mei Signed-off-by: Tinghan Shen Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220330094532.21721-2-tinghan.shen@mediatek.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 297ada03e3de..2a2e9fa8c188 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -40,7 +40,10 @@ properties: - const: mediatek,mt8183-mmc reg: - maxItems: 1 + minItems: 1 + items: + - description: base register (required). + - description: top base register (required for MT8183). clocks: description: @@ -168,6 +171,16 @@ required: - vmmc-supply - vqmmc-supply +if: + properties: + compatible: + contains: + const: mediatek,mt8183-mmc +then: + properties: + reg: + minItems: 2 + unevaluatedProperties: false examples: -- cgit From 6c1757be927ab1800754b14df01ad56da795339a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 10 Apr 2022 14:35:41 -0500 Subject: dt-bindings: mmc: imx-esdhc: Update compatible fallbacks The SDHC controller in the imx8mn and imx8mp have the same controller as the imx8mm which is slightly different than that of the imx7d. Using the fallback of the imx8mm enables the controllers to support HS400-ES which is not available on the imx7d. After discussion with NXP, it turns out that the imx8qm should fall back to the imx8qxp, because those have some additional flags not present in the imx8mm. Mark the current state of the fallbacks as deprecated, and add the proper fallbacks so in the future, the deprecated combination can be removed and prevent any future devices from using the wrong fallback. Suggested-by: haibo.chen@nxp.com Signed-off-by: Adam Ford Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220410193544.1745684-1-aford173@gmail.com Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 30 +++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml index 7dbbcae9485c..58447095f000 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml @@ -34,22 +34,46 @@ properties: - fsl,imx6ull-usdhc - fsl,imx7d-usdhc - fsl,imx7ulp-usdhc + - fsl,imx8mm-usdhc - fsl,imxrt1050-usdhc - nxp,s32g2-usdhc + - items: + - enum: + - fsl,imx8mq-usdhc + - const: fsl,imx7d-usdhc + - items: + - enum: + - fsl,imx8mn-usdhc + - fsl,imx8mp-usdhc + - fsl,imx93-usdhc + - fsl,imx8ulp-usdhc + - const: fsl,imx8mm-usdhc + - items: + - enum: + - fsl,imx8qm-usdhc + - const: fsl,imx8qxp-usdhc - items: - enum: - fsl,imx8mm-usdhc - fsl,imx8mn-usdhc - fsl,imx8mp-usdhc - - fsl,imx8mq-usdhc - fsl,imx8qm-usdhc - fsl,imx8qxp-usdhc - const: fsl,imx7d-usdhc + deprecated: true - items: - enum: - - fsl,imx93-usdhc - - fsl,imx8ulp-usdhc + - fsl,imx8mn-usdhc + - fsl,imx8mp-usdhc - const: fsl,imx8mm-usdhc + - const: fsl,imx7d-usdhc + deprecated: true + - items: + - enum: + - fsl,imx8qm-usdhc + - const: fsl,imx8qxp-usdhc + - const: fsl,imx7d-usdhc + deprecated: true reg: maxItems: 1 -- cgit From de6e855b28f4c54eb04582cd468c6fa17577c8cc Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 17 Apr 2022 16:42:23 +0200 Subject: dt-bindings: mmc: Add small binding note on level shifters The VQMMC is often provided by a level shifter, so drop a small note in the bindings that this can be the case and how that is done. It is helpful information since this is pretty common. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20220417144223.649201-1-linus.walleij@linaro.org Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mmc-controller.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml index 513f3c8758aa..ff5ce89e5111 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -298,7 +298,10 @@ properties: vqmmc-supply: description: - Supply for the bus IO line power + Supply for the bus IO line power, such as a level shifter. + If the level shifter is controlled by a GPIO line, this shall + be modeled as a "regulator-fixed" with a GPIO line for + switching the level shifter on/off. mmc-pwrseq: $ref: /schemas/types.yaml#/definitions/phandle -- cgit From a778dbd9a8ef30c07eaa7f46292d88f0a3b51e23 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Tue, 19 Apr 2022 14:46:10 +1200 Subject: dt-bindings: mmc: convert orion-sdio to JSON schema Convert the orion-sdio binding to JSON schema. Signed-off-by: Chris Packham Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20220419024611.1327525-4-chris.packham@alliedtelesis.co.nz Signed-off-by: Ulf Hansson --- .../bindings/mmc/marvell,orion-sdio.yaml | 44 ++++++++++++++++++++++ .../devicetree/bindings/mmc/orion-sdio.txt | 16 -------- 2 files changed, 44 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/marvell,orion-sdio.yaml delete mode 100644 Documentation/devicetree/bindings/mmc/orion-sdio.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/marvell,orion-sdio.yaml b/Documentation/devicetree/bindings/mmc/marvell,orion-sdio.yaml new file mode 100644 index 000000000000..8a97ded15aed --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/marvell,orion-sdio.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/marvell,orion-sdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell orion-sdio controller + +maintainers: + - Nicolas Pitre + - Ulf Hansson + +allOf: + - $ref: mmc-controller.yaml# + +properties: + compatible: + const: marvell,orion-sdio + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + mmc@d00d4000 { + compatible = "marvell,orion-sdio"; + reg = <0xd00d4000 0x200>; + interrupts = <54>; + clocks = <&gateclk 17>; + }; diff --git a/Documentation/devicetree/bindings/mmc/orion-sdio.txt b/Documentation/devicetree/bindings/mmc/orion-sdio.txt deleted file mode 100644 index 10f0818a34c5..000000000000 --- a/Documentation/devicetree/bindings/mmc/orion-sdio.txt +++ /dev/null @@ -1,16 +0,0 @@ -* Marvell orion-sdio controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the orion-sdio driver. - -- compatible: Should be "marvell,orion-sdio" -- clocks: reference to the clock of the SDIO interface - -Example: - - mvsdio@d00d4000 { - compatible = "marvell,orion-sdio"; - reg = <0xd00d4000 0x200>; - interrupts = <54>; - clocks = <&gateclk 17>; - }; -- cgit From a18f3e46537434537bc3c11d33ef529c52370815 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Tue, 19 Apr 2022 14:46:11 +1200 Subject: dt-bindings: mmc: convert sdhci-dove to JSON schema Convert the sdhci-dove binding to JSON schema. The optional clocks property was not in the original binding document but has been in the dove.dtsi since commit 5b03df9ace68 ("ARM: dove: switch to DT clock providers"). Signed-off-by: Chris Packham Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20220419024611.1327525-5-chris.packham@alliedtelesis.co.nz Signed-off-by: Ulf Hansson --- .../bindings/mmc/marvell,dove-sdhci.yaml | 44 ++++++++++++++++++++++ .../devicetree/bindings/mmc/sdhci-dove.txt | 14 ------- 2 files changed, 44 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/marvell,dove-sdhci.yaml delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-dove.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/marvell,dove-sdhci.yaml b/Documentation/devicetree/bindings/mmc/marvell,dove-sdhci.yaml new file mode 100644 index 000000000000..7c9c652ad59c --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/marvell,dove-sdhci.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/marvell,dove-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell sdhci-dove controller + +maintainers: + - Adrian Hunter + - Ulf Hansson + +allOf: + - $ref: mmc-controller.yaml# + +properties: + compatible: + const: marvell,dove-sdhci + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + sdio0: mmc@92000 { + compatible = "marvell,dove-sdhci"; + reg = <0x92000 0x100>; + interrupts = <35>; + clocks = <&gate_clk 9>; + }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-dove.txt b/Documentation/devicetree/bindings/mmc/sdhci-dove.txt deleted file mode 100644 index ae9aab9abcd7..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-dove.txt +++ /dev/null @@ -1,14 +0,0 @@ -* Marvell sdhci-dove controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers. - -- compatible: Should be "marvell,dove-sdhci". - -Example: - -sdio0: sdio@92000 { - compatible = "marvell,dove-sdhci"; - reg = <0x92000 0x100>; - interrupts = <35>; -}; -- cgit From cfb646613649c013591a9d5a4dc8f5db3e7ac25b Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 19 Apr 2022 14:35:12 +0300 Subject: dt-bindings: mmc: imx-esdhc: Add i.MX8DXL compatible string Add i.MX8DXL compatible string. It also needs "fsl,imx8qm-fec" compatible. Signed-off-by: Abel Vesa Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220419113516.1827863-10-abel.vesa@nxp.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml index 58447095f000..29339d0196ec 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml @@ -54,6 +54,7 @@ properties: - const: fsl,imx8qxp-usdhc - items: - enum: + - fsl,imx8dxl-usdhc - fsl,imx8mm-usdhc - fsl,imx8mn-usdhc - fsl,imx8mp-usdhc -- cgit From 7a0587496a6233b9ffa8441573d38f8844751066 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Mon, 25 Apr 2022 12:01:19 +0530 Subject: dt-bindings: mmc: sdhci-am654: Add flag to force setting of TESTCD bit The ARASAN MMC controller on Keystone 3 class of devices needs the SDCD line to be connected for proper functioning. Similar to the issue pointed out in sdhci-of-arasan.c driver, commit 3794c542641f ("mmc: sdhci-of-arasan: Set controller to test mode when no CD bit"). In cases where SDCD line is not connected, adding "ti,fails-without-test-cd" in the DT node helps to indicate the controller, that the SDCD line has been pulled down, using the TESTCD bit. Signed-off-by: Aswath Govindraju Link: https://lore.kernel.org/r/20220425063120.10135-2-a-govindraju@ti.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-am654.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml index 0566493c4def..0ab07759b472 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml @@ -186,6 +186,13 @@ properties: description: Clock Delay Buffer Select $ref: "/schemas/types.yaml#/definitions/uint32" + ti,fails-without-test-cd: + $ref: /schemas/types.yaml#/definitions/flag + description: + When present, indicates that the CD line is not connected + and the controller is required to be forced into Test mode + to set the TESTCD bit. + required: - compatible - reg -- cgit From bbbd8872825310b14bc6e04250d2cb5edcd55edb Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Fri, 22 Apr 2022 19:09:08 +0200 Subject: dt-bindings: mmc: sdhci-of-dwcmhsc: Add rk3588 Add compatible value for the Rockchip rk3588 dwcmshc controller. Signed-off-by: Sebastian Reichel Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220422170920.401914-8-sebastian.reichel@collabora.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index f300ced4cdf3..71f8e726d641 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - rockchip,rk3568-dwcmshc + - rockchip,rk3588-dwcmshc - snps,dwcmshc-sdhci reg: -- cgit From b16ebda6d00361095c539d27b21b50488b71cec2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 28 Apr 2022 10:18:16 +0200 Subject: dt-bindings: mmc: brcm,sdhci-brcmstb: correct number of reg entries The binding should not allow infinite number of 'reg' entries, so add strict limit. Signed-off-by: Krzysztof Kozlowski Acked-by: Florian Fainelli Link: https://lore.kernel.org/r/20220428081817.35382-1-krzysztof.kozlowski@linaro.org Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index dccd5ad96981..54a0edab5f8c 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -31,7 +31,7 @@ properties: - const: brcm,sdhci-brcmstb reg: - minItems: 2 + maxItems: 2 reg-names: items: -- cgit From 0a70c5d289b050fe1d2b3de91c837763a3c347f5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 28 Apr 2022 10:18:17 +0200 Subject: dt-bindings: mmc: brcm,sdhci-brcmstb: cleanup example Cleanup indentation and order of entries in example DTS. The most important when reading the DTS are compatible and reg. By convention they are usually to first entries. No functional change. Signed-off-by: Krzysztof Kozlowski Acked-by: Florian Fainelli Link: https://lore.kernel.org/r/20220428081817.35382-2-krzysztof.kozlowski@linaro.org Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index 54a0edab5f8c..b672202fff4e 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -65,15 +65,15 @@ unevaluatedProperties: false examples: - | mmc@84b0000 { - sd-uhs-sdr50; - sd-uhs-ddr50; - sd-uhs-sdr104; - sdhci,auto-cmd12; compatible = "brcm,bcm7216-sdhci", "brcm,bcm7445-sdhci", "brcm,sdhci-brcmstb"; reg = <0x84b0000 0x260>, <0x84b0300 0x200>; reg-names = "host", "cfg"; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + sdhci,auto-cmd12; interrupts = <0x0 0x26 0x4>; interrupt-names = "sdio0_0"; clocks = <&scmi_clk 245>; @@ -81,6 +81,11 @@ examples: }; mmc@84b1000 { + compatible = "brcm,bcm7216-sdhci", + "brcm,bcm7445-sdhci", + "brcm,sdhci-brcmstb"; + reg = <0x84b1000 0x260>, <0x84b1300 0x200>; + reg-names = "host", "cfg"; mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; @@ -88,11 +93,6 @@ examples: supports-cqe; non-removable; bus-width = <0x8>; - compatible = "brcm,bcm7216-sdhci", - "brcm,bcm7445-sdhci", - "brcm,sdhci-brcmstb"; - reg = <0x84b1000 0x260>, <0x84b1300 0x200>; - reg-names = "host", "cfg"; interrupts = <0x0 0x27 0x4>; interrupt-names = "sdio1_0"; clocks = <&scmi_clk 245>; -- cgit From a45537723f4b87fa2c97ae01ac08a3a9ddec0a10 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 30 Apr 2022 03:38:30 +0530 Subject: dt-bindings: mmc: sdhci-msm: Convert bindings to yaml Convert Qualcomm sdhci-msm devicetree binding to YAML. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20220429220833.873672-2-bhupesh.sharma@linaro.org Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/sdhci-msm.txt | 123 ------------- .../devicetree/bindings/mmc/sdhci-msm.yaml | 192 +++++++++++++++++++++ 2 files changed, 192 insertions(+), 123 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-msm.txt create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-msm.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt deleted file mode 100644 index 6216ed777343..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ /dev/null @@ -1,123 +0,0 @@ -* Qualcomm SDHCI controller (sdhci-msm) - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-msm driver. - -Required properties: -- compatible: Should contain a SoC-specific string and a IP version string: - version strings: - "qcom,sdhci-msm-v4" for sdcc versions less than 5.0 - "qcom,sdhci-msm-v5" for sdcc version 5.0 - For SDCC version 5.0.0, MCI registers are removed from SDCC - interface and some registers are moved to HC. New compatible - string is added to support this change - "qcom,sdhci-msm-v5". - full compatible strings with SoC and version: - "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4" - "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5" - "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; - "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; - "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5" - "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; - "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5" - NOTE that some old device tree files may be floating around that only - have the string "qcom,sdhci-msm-v4" without the SoC compatible string - but doing that should be considered a deprecated practice. - -- reg: Base address and length of the register in the following order: - - Host controller register map (required) - - SD Core register map (required for controllers earlier than msm-v5) - - CQE register map (Optional, CQE support is present on SDHC instance meant - for eMMC and version v4.2 and above) - - Inline Crypto Engine register map (optional) -- reg-names: When CQE register map is supplied, below reg-names are required - - "hc" for Host controller register map - - "core" for SD core register map - - "cqhci" for CQE register map - - "ice" for Inline Crypto Engine register map (optional) -- interrupts: Should contain an interrupt-specifiers for the interrupts: - - Host controller interrupt (required) -- pinctrl-names: Should contain only one value - "default". -- pinctrl-0: Should specify pin control groups used for this controller. -- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names. -- clock-names: Should contain the following: - "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required) - "core" - SDC MMC clock (MCLK) (required) - "bus" - SDCC bus voter clock (optional) - "xo" - TCXO clock (optional) - "cal" - reference clock for RCLK delay calibration (optional) - "sleep" - sleep clock for RCLK delay calibration (optional) - "ice" - clock for Inline Crypto Engine (optional) - -- qcom,ddr-config: Certain chipsets and platforms require particular settings - for the DDR_CONFIG register. Use this field to specify the register - value as per the Hardware Programming Guide. - -- qcom,dll-config: Chipset and Platform specific value. Use this field to - specify the DLL_CONFIG register value as per Hardware Programming Guide. - -Optional Properties: -* Following bus parameters are required for interconnect bandwidth scaling: -- interconnects: Pairs of phandles and interconnect provider specifier - to denote the edge source and destination ports of - the interconnect path. - -- interconnect-names: For sdhc, we have two main paths. - 1. Data path : sdhc to ddr - 2. Config path : cpu to sdhc - For Data interconnect path the name supposed to be - is "sdhc-ddr" and for config interconnect path it is - "cpu-sdhc". - Please refer to Documentation/devicetree/bindings/ - interconnect/ for more details. - -Example: - - sdhc_1: sdhci@f9824900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - interrupts = <0 123 0>; - bus-width = <8>; - non-removable; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>; - - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; - interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>, - <&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>; - interconnect-names = "sdhc-ddr","cpu-sdhc"; - - qcom,dll-config = <0x000f642c>; - qcom,ddr-config = <0x80040868>; - }; - - sdhc_2: sdhci@f98a4900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - interrupts = <0 125 0>; - bus-width = <4>; - cd-gpios = <&msmgpio 62 0x1>; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>; - - clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; - - qcom,dll-config = <0x0007642c>; - qcom,ddr-config = <0x80040868>; - }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml new file mode 100644 index 000000000000..3b7defd9ee4d --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -0,0 +1,192 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm SDHCI controller (sdhci-msm) + +maintainers: + - Bhupesh Sharma + +description: + Secure Digital Host Controller Interface (SDHCI) present on + Qualcomm SOCs supports SD/MMC/SDIO devices. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,apq8084-sdhci + - qcom,msm8226-sdhci + - qcom,msm8953-sdhci + - qcom,msm8974-sdhci + - qcom,msm8916-sdhci + - qcom,msm8992-sdhci + - qcom,msm8994-sdhci + - qcom,msm8996-sdhci + - qcom,qcs404-sdhci + - qcom,sc7180-sdhci + - qcom,sc7280-sdhci + - qcom,sdm630-sdhci + - qcom,sdm845-sdhci + - qcom,sdx55-sdhci + - qcom,sm6125-sdhci + - qcom,sm6350-sdhci + - qcom,sm8250-sdhci + - enum: + - qcom,sdhci-msm-v4 # for sdcc versions less than 5.0 + - qcom,sdhci-msm-v5 # for sdcc version 5.0 + - items: + - const: qcom,sdhci-msm-v4 # Deprecated (only for backward compatibility) + # for sdcc versions less than 5.0 + + reg: + minItems: 1 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + + clocks: + minItems: 3 + items: + - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock + - description: SDC MMC clock, MCLK + - description: TCXO clock + - description: clock for Inline Crypto Engine + - description: SDCC bus voter clock + - description: reference clock for RCLK delay calibration + - description: sleep clock for RCLK delay calibration + + clock-names: + minItems: 2 + items: + - const: iface + - const: core + - const: xo + - const: ice + - const: bus + - const: cal + - const: sleep + + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: hc_irq + - const: pwr_irq + + pinctrl-names: + minItems: 1 + items: + - const: default + - const: sleep + + pinctrl-0: + description: + Should specify pin control groups used for this controller. + + qcom,ddr-config: + $ref: /schemas/types.yaml#/definitions/uint32 + description: platform specific settings for DDR_CONFIG reg. + + qcom,dll-config: + $ref: /schemas/types.yaml#/definitions/uint32 + description: platform specific settings for DLL_CONFIG reg. + + iommus: + minItems: 1 + maxItems: 8 + description: | + phandle to apps_smmu node with sid mask. + + interconnects: + items: + - description: data path, sdhc to ddr + - description: config path, cpu to sdhc + + interconnect-names: + items: + - const: sdhc-ddr + - const: cpu-sdhc + + power-domains: + description: A phandle to sdhci power domain node + maxItems: 1 + +patternProperties: + '^opp-table(-[a-z0-9]+)?$': + if: + properties: + compatible: + const: operating-points-v2 + then: + patternProperties: + '^opp-?[0-9]+$': + required: + - required-opps + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: true + +examples: + - | + #include + #include + #include + #include + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x4a0 0x0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd SM8250_CX>; + + operating-points-v2 = <&sdhc2_opp_table>; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; -- cgit From 17a9f73d45ea74b2beb009c29ad38569990c3453 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 30 Apr 2022 03:38:32 +0530 Subject: dt-bindings: mmc: sdhci-msm: Add compatible string for sm8150 Add sm8150 SoC specific compatible strings for qcom-sdhci controller. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20220429220833.873672-4-bhupesh.sharma@linaro.org Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 3b7defd9ee4d..da42a88aabb3 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -35,6 +35,7 @@ properties: - qcom,sdx55-sdhci - qcom,sm6125-sdhci - qcom,sm6350-sdhci + - qcom,sm8150-sdhci - qcom,sm8250-sdhci - enum: - qcom,sdhci-msm-v4 # for sdcc versions less than 5.0 -- cgit From 210deba2d9b73082625a7f67a406c396bf0e9b84 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 2 May 2022 14:07:42 +0530 Subject: dt-bindings: mmc: sdhci-msm: Document the SDX65 compatible The SDHCI controller on SDX65 is based on MSM SDHCI v5 IP. Hence, document the compatible with "qcom,sdhci-msm-v5" as the fallback. Signed-off-by: Rohit Agarwal Acked-by: Rob Herring Link: https://lore.kernel.org/r/1651480665-14978-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index da42a88aabb3..e4236334e748 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -33,6 +33,7 @@ properties: - qcom,sdm630-sdhci - qcom,sdm845-sdhci - qcom,sdx55-sdhci + - qcom,sdx65-sdhci - qcom,sm6125-sdhci - qcom,sm6350-sdhci - qcom,sm8150-sdhci -- cgit