From 55f36df9ec4f6c53b6a06acfc4195e99bd9355fa Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 2 Sep 2021 17:57:48 -0500 Subject: dt-bindings: watchdog: sunxi: Add compatibles for R329 On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M) divided by 750. However, starting with R329, LOSC (OSC32k) is added as an alternative clock source, with a bit to switch between them. Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the cycle counts to keep the timeouts independent of the clock source. This keeps the programming interface backward-compatible. Furthermore, the R329 has two watchdogs: one for use by the ARM CPUs at 0x20000a0, and a second one for use by the DSPs at 0x7020400. The first of these adds two more new registers, to allow software to immediately assert the SoC reset signal. Add an additional "-reset" suffix to signify the presence of this feature. Signed-off-by: Samuel Holland Acked-by: Maxime Ripard Reviewed-by: Rob Herring Acked-by: Guenter Roeck Link: https://lore.kernel.org/r/20210902225750.29313-2-samuel@sholland.org Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- .../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 42 +++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 9aa3c313c49f..877f47759814 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -24,6 +24,8 @@ properties: - allwinner,sun50i-a100-wdt - allwinner,sun50i-h6-wdt - allwinner,sun50i-h616-wdt + - allwinner,sun50i-r329-wdt + - allwinner,sun50i-r329-wdt-reset - const: allwinner,sun6i-a31-wdt - items: - const: allwinner,suniv-f1c100s-wdt @@ -33,7 +35,18 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + items: + - description: High-frequency oscillator input, divided internally + - description: Low-frequency oscillator input, only found on some variants + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: hosc + - const: losc interrupts: maxItems: 1 @@ -44,6 +57,33 @@ required: - clocks - interrupts +if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-r329-wdt + - allwinner,sun50i-r329-wdt-reset + +then: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + required: + - clock-names + +else: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + unevaluatedProperties: false examples: -- cgit From 601db217916de339ddebeb3b6f024f09a275562a Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 2 Sep 2021 17:57:49 -0500 Subject: dt-bindings: watchdog: sunxi: Add compatibles for D1 D1 keeps the same register layout and clock sources as the R329, but it adds a key field which must be set to update the watchdog's "CFG" and "MODE" registers. Therefore it is not backward-compatible. Similarly to the R329, the D1 has three watchdog instances, and only one of them has the "soft reset" registers. So that instance needs an extra compatible string. Signed-off-by: Samuel Holland Acked-by: Maxime Ripard Acked-by: Guenter Roeck Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210902225750.29313-3-samuel@sholland.org Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- .../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 877f47759814..44cad9427ae6 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -30,6 +30,10 @@ properties: - items: - const: allwinner,suniv-f1c100s-wdt - const: allwinner,sun4i-a10-wdt + - const: allwinner,sun20i-d1-wdt + - items: + - const: allwinner,sun20i-d1-wdt-reset + - const: allwinner,sun20i-d1-wdt reg: maxItems: 1 @@ -62,6 +66,8 @@ if: compatible: contains: enum: + - allwinner,sun20i-d1-wdt + - allwinner,sun20i-d1-wdt-reset - allwinner,sun50i-r329-wdt - allwinner,sun50i-r329-wdt-reset -- cgit From eed09878923ef2cd69b832b8ac84f8dfa674f353 Mon Sep 17 00:00:00 2001 From: Fengquan Chen Date: Tue, 14 Sep 2021 20:34:53 +0800 Subject: dt-bindings: watchdog: mtk-wdt: add disable_wdt_extrst support This patch add a description and example of disable_wdt_extrst element for watchdog on MTK Socs Signed-off-by: Fengquan Chen Acked-by: Rob Herring Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20210914123454.32603-2-Fengquan.Chen@mediatek.com Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index a4e31ce96e0e..0114871f887a 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -22,6 +22,7 @@ Required properties: - reg : Specifies base physical address and size of the registers. Optional properties: +- mediatek,disable-extrst: disable send output reset signal - interrupts: Watchdog pre-timeout (bark) interrupt. - timeout-sec: contains the watchdog timeout in seconds. - #reset-cells: Should be 1. @@ -31,6 +32,7 @@ Example: watchdog: watchdog@10007000 { compatible = "mediatek,mt8183-wdt", "mediatek,mt6589-wdt"; + mediatek,disable-extrst; reg = <0 0x10007000 0 0x100>; interrupts = ; timeout-sec = <10>; -- cgit