From 1f6ccfff6314672743ad7252160654709e997a2a Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 13 May 2013 18:30:41 +0530 Subject: ARCv2: Support for ARCv2 ISA and HS38x cores The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta --- arch/arc/include/asm/irqflags-compact.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arc/include/asm/irqflags-compact.h') diff --git a/arch/arc/include/asm/irqflags-compact.h b/arch/arc/include/asm/irqflags-compact.h index 18f3634ac347..aa805575c320 100644 --- a/arch/arc/include/asm/irqflags-compact.h +++ b/arch/arc/include/asm/irqflags-compact.h @@ -39,6 +39,8 @@ #define AUX_ITRIGGER 0x40d #define AUX_IPULSE 0x415 +#define ISA_INIT_STATUS_BITS STATUS_IE_MASK + #ifndef __ASSEMBLY__ /****************************************************************** -- cgit