From 292a3546b9eb20bf5a292f4e55dd1a027424669f Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 17 Mar 2015 17:33:54 +0100 Subject: ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level For L2 cache controller node, cache-level property is mandatory. Let's add it to Armada 370 and Armada XP device tree. Signed-off-by: Gregory CLEMENT Reviewed-by: Thomas Petazzoni --- arch/arm/boot/dts/armada-xp.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts/armada-xp.dtsi') diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 448af3352175..013d63f69e36 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -79,6 +79,7 @@ compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-level = <2>; cache-unified; wt-override; }; -- cgit