From da41645f11bb58eae3dda87dc459495a094f1935 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Fri, 3 Jun 2022 09:37:05 +0200 Subject: ARM: dts: aspeed: ast2600-evb: Enable Quad SPI RX tranfers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that the pinctrl definitions of the ast2600 SoC have been fixed, see commit 925fbe1f7eb6 ("dt-bindings: pinctrl: aspeed-g6: add FWQSPI function/group"), it is safe to activate QSPI on the ast2600 evb. Cc: Chin-Ting Kuo Tested-by: Jae Hyun Yoo Signed-off-by: Cédric Le Goater Link: https://lore.kernel.org/r/20220603073705.1624351-1-clg@kaod.org Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts/aspeed-ast2600-evb.dts') diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 14dbeaee7ee3..5c6eacb43c03 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -182,6 +182,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; + spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #include "openbmc-flash-layout-64.dtsi" }; @@ -196,6 +197,7 @@ status = "okay"; m25p,fast-read; label = "pnor"; + spi-rx-bus-width = <4>; spi-max-frequency = <100000000>; }; }; -- cgit