From 018e4feb7584971b3dbda6daa6a8fef310cafbcb Mon Sep 17 00:00:00 2001 From: Yendapally Reddy Dhananjaya Reddy Date: Fri, 4 Dec 2015 12:12:42 -0500 Subject: ARM: dts: enable GPIO-a for Broadcom NSP This enables the GPIO-a support for Broadcom NSP SoC Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts/bcm-nsp.dtsi') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 10bdef557ba0..49f9376d0d12 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -169,6 +169,18 @@ #address-cells = <1>; #size-cells = <1>; + gpioa: gpio@0020 { + compatible = "brcm,nsp-gpio-a"; + reg = <0x0020 0x70>, + <0x3f1c4 0x1c>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <32>; + interrupt-controller; + interrupts = ; + gpio-ranges = <&pinctrl 0 0 32>; + }; + uart0: serial@0300 { compatible = "ns16550a"; reg = <0x0300 0x100>; -- cgit From 522199029fdcc3a8b507779d59d1d78d4fa14460 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 5 Feb 2016 17:43:20 -0500 Subject: ARM: dts: NSP: Fix PCIE DT issue Adding the ranges value is preventing the PCI nodes from working. Pulling them out outside makes them work again (and makes it similar to the NS2 device tree). Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 144 ++++++++++++++++++++--------------------- 1 file changed, 72 insertions(+), 72 deletions(-) (limited to 'arch/arm/boot/dts/bcm-nsp.dtsi') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 49f9376d0d12..3b8c2c09286f 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -197,78 +197,6 @@ status = "disabled"; }; - pcie0: pcie@12000 { - compatible = "brcm,iproc-pcie"; - reg = <0x12000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; - - status = "disabled"; - }; - - pcie1: pcie@13000 { - compatible = "brcm,iproc-pcie"; - reg = <0x13000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>; - - linux,pci-domain = <1>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; - - status = "disabled"; - }; - - pcie2: pcie@14000 { - compatible = "brcm,iproc-pcie"; - reg = <0x14000 0x1000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>; - - linux,pci-domain = <2>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - - /* Note: The HW does not support I/O resources. So, - * only the memory resource range is being specified. - */ - ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; - - status = "disabled"; - }; - nand: nand@26000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x026000 0x600>, @@ -318,4 +246,76 @@ <0x3f408 0x04>; }; }; + + pcie0: pcie@18012000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18012000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; + + status = "disabled"; + }; + + pcie1: pcie@18013000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18013000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>; + + linux,pci-domain = <1>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; + + status = "disabled"; + }; + + pcie2: pcie@18014000 { + compatible = "brcm,iproc-pcie"; + reg = <0x18014000 0x1000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>; + + linux,pci-domain = <2>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + + /* Note: The HW does not support I/O resources. So, + * only the memory resource range is being specified. + */ + ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; + + status = "disabled"; + }; }; -- cgit From 5a6c7b52d09baa7dcf37657b232ee8dfcc55d734 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 5 Feb 2016 17:43:21 -0500 Subject: ARM: dts: NSP: Fix CPU DT issue There is a double definition of the CPUs present in the device tree. Remove unnecessary cpu device tree definition. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'arch/arm/boot/dts/bcm-nsp.dtsi') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 3b8c2c09286f..834862b52b52 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -68,18 +68,6 @@ #address-cells = <1>; #size-cells = <1>; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - }; - }; - a9pll: arm_clk@00000 { #clock-cells = <0>; compatible = "brcm,nsp-armpll"; -- cgit From 9d57f60c219832dc74954c7479675e07abb86f9a Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 5 Feb 2016 17:43:22 -0500 Subject: ARM: dts: NSP: Add PMU Support to DT Add support for the ARM Performance Monitor Unit to the Northstar Plus device tree. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts/bcm-nsp.dtsi') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 834862b52b52..a984bafee208 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -45,14 +45,14 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; @@ -62,6 +62,13 @@ }; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + mpcore { compatible = "simple-bus"; ranges = <0x00000000 0x19000000 0x00023000>; -- cgit From a0efb0d28b77e481704b67a419d36a789e16beaa Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Sat, 6 Feb 2016 12:53:39 -0500 Subject: ARM: dts: NSP: Add SP804 Support to DT Add support for the ARM SP804 timer to the Northstar Plus device tree. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/boot/dts/bcm-nsp.dtsi') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index a984bafee208..bed67017f9d0 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -206,6 +206,24 @@ brcm,nand-has-wp; }; + ccbtimer0: timer@34000 { + compatible = "arm,sp804"; + reg = <0x34000 0x1000>; + interrupts = , + ; + clocks = <&iprocslow>; + clock-names = "apb_pclk"; + }; + + ccbtimer1: timer@35000 { + compatible = "arm,sp804"; + reg = <0x35000 0x1000>; + interrupts = , + ; + clocks = <&iprocslow>; + clock-names = "apb_pclk"; + }; + i2c0: i2c@38000 { compatible = "brcm,iproc-i2c"; reg = <0x38000 0x50>; -- cgit From 7c3fe8a1f6d1d2287de5dc8cbfc901a0a2d71838 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 5 Feb 2016 17:43:23 -0500 Subject: ARM: dts: NSP: Add SP805 Support to DT Add support for the ARM SP805 Watchdog timer to the Northstar Plus device tree. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts/bcm-nsp.dtsi') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index bed67017f9d0..def9e783b5c6 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -233,6 +233,14 @@ clock-frequency = <100000>; }; + watchdog@39000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x39000 0x1000>; + interrupts = ; + clocks = <&iprocslow>, <&iprocslow>; + clock-names = "wdogclk", "apb_pclk"; + }; + lcpll0: lcpll0@3f100 { #clock-cells = <1>; compatible = "brcm,nsp-lcpll0"; -- cgit