From 0da65870413630339399eb691162eef5c27272de Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Sat, 24 Jan 2015 13:16:15 +0900 Subject: ARM: dts: convert to generic power domain bindings for exynos DT This patch replaces all custom samsung,power-domain dt properties with generic power domain bindings and updates documentation Samsung's devices referring to old binding. Suggested-by: Kevin Hilman Signed-off-by: Marek Szyprowski Reviewed-by: Javier Martinez Canillas [javier.martinez@collabora.co.uk: tested on the Exynos5800 Peach Pi Chromebook] Tested-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 517e50f6760b..03ef2481c640 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -178,7 +178,7 @@ interrupts = <0 96 0>; clocks = <&clock CLK_MFC>; clock-names = "mfc"; - samsung,power-domain = <&mfc_pd>; + power-domains = <&mfc_pd>; }; mmc_0: mmc@12200000 { @@ -250,11 +250,13 @@ gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; + #power-domain-cells = <0>; }; isp_pd: power-domain@10044020 { compatible = "samsung,exynos4210-pd"; reg = <0x10044020 0x20>; + #power-domain-cells = <0>; }; mfc_pd: power-domain@10044060 { @@ -263,11 +265,13 @@ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, <&clock CLK_MOUT_USER_ACLK333>; clock-names = "oscclk", "pclk0", "clk0"; + #power-domain-cells = <0>; }; msc_pd: power-domain@10044120 { compatible = "samsung,exynos4210-pd"; reg = <0x10044120 0x20>; + #power-domain-cells = <0>; }; pinctrl_0: pinctrl@13400000 { @@ -730,7 +734,7 @@ interrupts = <0 85 0>; clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; - samsung,power-domain = <&gsc_pd>; + power-domains = <&gsc_pd>; }; gsc_1: video-scaler@13e10000 { @@ -739,7 +743,7 @@ interrupts = <0 86 0>; clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; - samsung,power-domain = <&gsc_pd>; + power-domains = <&gsc_pd>; }; pmu_system_controller: system-controller@10040000 { -- cgit From ea08de16eb1ba2052ce2db4b58b62a2ec33357a3 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sat, 24 Jan 2015 13:25:35 +0900 Subject: ARM: dts: Add DISP1 power domain for exynos5420 The DISP1 power domain on Exynos5420 SoC includes the FIMD1, MIXER and HDMI modules. Add a device node for this power domain and mark these modules as consumer of the DISP1 power domain. When a power domain is powered on and off, the input clocks of the devices attached to it are reparented. So a reference to the input and parent clocks of the devices are needed to manage that. Signed-off-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 03ef2481c640..a0a3b2829208 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -274,6 +274,20 @@ #power-domain-cells = <0>; }; + disp_pd: power-domain@100440C0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440C0 0x20>; + #power-domain-cells = <0>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>, + <&clock CLK_MOUT_USER_ACLK200_DISP1>, + <&clock CLK_MOUT_SW_ACLK300>, + <&clock CLK_MOUT_USER_ACLK300_DISP1>, + <&clock CLK_MOUT_SW_ACLK400>, + <&clock CLK_MOUT_USER_ACLK400_DISP1>; + clock-names = "oscclk", "pclk0", "clk0", + "pclk1", "clk1", "pclk2", "clk2"; + }; + pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13400000 0x1000>; @@ -541,6 +555,7 @@ fimd: fimd@14400000 { clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; + power-domains = <&disp_pd>; }; adc: adc@12D10000 { @@ -714,6 +729,7 @@ phy = <&hdmiphy>; samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; + power-domains = <&disp_pd>; }; hdmiphy: hdmiphy@145D0000 { @@ -726,6 +742,7 @@ interrupts = <0 94 0>; clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "sclk_hdmi"; + power-domains = <&disp_pd>; }; gsc_0: video-scaler@13e00000 { -- cgit