From 2125212785c96c053a0b803b9605398e014e3a29 Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Mon, 17 Jun 2019 18:14:32 +0200 Subject: ARM: dts: imx6qdl-kontron-samx6i: add Kontron SMARC SoM Support The patch adds the following interfaces according the SMARC Spec 1.1 [1] and provided schematics: - SMARC SPI0/1 Note: Since Kontron still uses silicon revisions below 1.3 they have add a spi-nor to implement Workaround #1 of erratum ERR006282. - SMARC SDIO - SMARC LCD - SMARC HDMI - SMARC Management pins Note: Kontron don't route all of these pins to the i.MX6, some are routed to the SoM CPLD. - SMARC GPIO - SMARC CSI Camera Note: As specified in [1] the data lanes are shared to cover the csi and the parallel case. The case depends on the baseboard so muxing the data lanes is not part of this patch. - SMARC I2S - SMARC Watchdog Note: The watchdog output pin is routed to the CPLD and the SMARC header. The CPLD performs a reset after a 30s timeout so we need to enable the watchdog per default. - SMARC module eeprom Due to the lack of hardware not all of these interfaces are tesetd. [1] https://sget.org/standards/smarc Signed-off-by: Michael Grzeschik Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi | 36 +++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi (limited to 'arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi') diff --git a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi new file mode 100644 index 000000000000..2618eccfe50d --- /dev/null +++ b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Copyright 2019 (C) Pengutronix, Marco Felsch + */ + +#include "imx6q.dtsi" +#include "imx6qdl-kontron-samx6i.dtsi" +#include + +/ { + model = "Kontron SMARC sAMX6i Quad/Dual"; + compatible = "kontron,imx6q-samx6i", "fsl,imx6q"; +}; + +/* Quad/Dual SoMs have 3 chip-select signals */ +&ecspi4 { + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>, + <&gpio3 29 GPIO_ACTIVE_HIGH>, + <&gpio3 25 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl_ecspi4 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + + /* SPI4_IMX_CS2# - connected to internal flash */ + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 + /* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + /* SPI4_CS3# - connected to SMARC SPI0_CS1# */ + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0 + >; +}; -- cgit