From 833f2cbf7091099baee28136dc68678e974c0ac5 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Sat, 10 Oct 2015 18:15:07 +0800 Subject: ARM: dts: imx6: change the core clock of spdif The correct core clock of spdif is SPDIF_GCLK, which is added to clock tree. So the dts also need to be updated. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm/boot/dts/imx6sl.dtsi') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index ebe8670f3ae6..d8ba99f1d87b 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -135,8 +135,24 @@ ranges; spdif: spdif@02004000 { + compatible = "fsl,imx6sl-spdif", + "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 14 18 0>, + <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, + <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "dma"; + status = "disabled"; }; ecspi1: ecspi@02008000 { -- cgit