From fa28d8212ede9c533ae87a737571a9d3b3eebb29 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 10 Jul 2020 07:19:37 +0200 Subject: ARM: dts: imx: default to #pwm-cells = <3> in the SoC dtsi files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The imx-pwm driver supports 3 cells and this is the more flexible setting. So use it by default and overwrite it back to two for the files that reference the PWMs with just 2 cells to minimize changes. This allows to drop explicit setting to 3 cells for the boards that already depend on this. The boards that are now using 2 cells explicitly can be converted to 3 individually. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/boot/dts/imx6sl.dtsi') diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index eb8aeaa5ccab..1c7180f28539 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -334,7 +334,7 @@ }; pwm1: pwm@2080000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; @@ -344,7 +344,7 @@ }; pwm2: pwm@2084000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; @@ -354,7 +354,7 @@ }; pwm3: pwm@2088000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; @@ -364,7 +364,7 @@ }; pwm4: pwm@208c000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; -- cgit