From 5d2ea79c7f73c8d57ccbc46e97ff400afd9bfe9b Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Wed, 1 Apr 2015 14:41:06 +0200 Subject: ARM: dts: lpc18xx: add ssp nodes Add nodes for the ARM SSP controllers on lpc18xx. Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc18xx.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm/boot/dts/lpc18xx.dtsi') diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 60dc929568b3..920cdb26743c 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -123,6 +123,17 @@ status = "disabled"; }; + ssp0: spi@40083000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x40083000 0x1000>; + interrupts = <22>; + clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>; + clock-names = "sspclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer0: timer@40084000 { compatible = "nxp,lpc3220-timer"; reg = <0x40084000 0x1000>; @@ -181,6 +192,17 @@ clock-names = "timerclk"; }; + ssp1: spi@400c5000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x400c5000 0x1000>; + interrupts = <23>; + clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>; + clock-names = "sspclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpio: gpio@400f4000 { compatible = "nxp,lpc1850-gpio"; reg = <0x400f4000 0x4000>; -- cgit