From 572cf7d7b07d3d61b82024bccb2a45366d58710e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 2 Jul 2018 23:57:20 -0700 Subject: ARM: dts: Improve omap l4per idling with wlcore edge sensitive interrupt The wl1835mod.pdf data sheet says this pretty clearly for WL_IRQ line: "WLAN SDIO out-of-band interrupt line. Set to rising edge (active high) by default." And it seems this interrupt can be optionally configured to use falling edge too since commit bd763482c82e ("wl18xx: wlan_irq: support platform dependent interrupt types"). On omap4, if the wlcore interrupt is configured as level instead of edge, L4PER will stop doing hardware based idling after ifconfig wlan0 down is done and the WL_EN line is pulled down. The symptoms show up with L4PER status registers no longer showing the IDLEST bits as 2 but as 0 for all the active GPIO banks and for L4PER_CLKCTRL. Also the l4per_pwrdm RET count stops increasing in the /sys/kernel/debug/pm_debug/count. While there is also probably a GPIO related issue that needs to be still fixed, this change gets us to the point where we can have L4PER idling. I'm guessing wlcore was at some point configured to use level interrupts because of edge handling issues in gpio-omap. However, with the recent fixes to gpio-omap the edge interrupts seem to be working just fine. Let's change it for all omap boards with wlcore interrupt set as level. Cc: Dave Gerlach Cc: Eyal Reizer Cc: Grygorii Strashko Cc: Kalle Valo Cc: Nishanth Menon Cc: Tero Kristo [tony@atomide.com updated comments a bit for gpio issue] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-droid4-xt894.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/omap4-droid4-xt894.dts') diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index bdf73cbcec3a..4f00559015a4 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -372,7 +372,7 @@ compatible = "ti,wl1285", "ti,wl1283"; reg = <2>; interrupt-parent = <&gpio4>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; /* gpio100 */ + interrupts = <4 IRQ_TYPE_EDGE_RISING>; /* gpio100 */ ref-clock-frequency = <26000000>; tcxo-clock-frequency = <26000000>; }; -- cgit From e40c7f75c9bc81a19c3f927769e42fd974fccaa2 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 2 Jul 2018 23:57:42 -0700 Subject: ARM: dts: omap4-droid4: Use software debounce for gpio-keys The default value of 5ms will use GPIO hardware based debounce clocks that will keep L4PER from idling consuming about extra 30mW. Use a value of 10ms that is above the hardware debounce maximum of 7.95ms forcing software based debouncing. This allows droid4 to enter PER retention during idle as long as UARTs are idled and USB modules unloaded or unbound. Note that there seems to be a pending issue with having droid 4 enter core retention during idle where GPIO bank 1 needs to be reset late after init for some reason to not block core retention. In addition to that, we are also missing GPIO related PM runtime calls for omap4 that will be posted separately. Cc: Marcel Partap Cc: Merlijn Wajer Cc: Michael Scott Cc: NeKit Cc: Pavel Machek Cc: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-droid4-xt894.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/omap4-droid4-xt894.dts') diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 4f00559015a4..63105ca92e9c 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -128,6 +128,8 @@ gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ linux,code = ; linux,can-disable; + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; }; slider { @@ -136,7 +138,8 @@ linux,input-type = ; linux,code = ; linux,can-disable; - + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; }; }; -- cgit