From ba08220aa81e757491a3665c28df7eaa954128dc Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@codeaurora.org>
Date: Wed, 28 May 2014 12:01:29 -0500
Subject: ARM: dts: qcom: Update msm8974/apq8074 device trees

* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-apq8074-dragonboard.dts)
* Move spi pinctrl into board file
* Cleanup cpu node to match binding spec, enable-method and compatible
  should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
  binding spec
* Move timer node out of SoC container

Signed-off-by: Kumar Gala <galak@codeaurora.org>
---
 arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 +++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

(limited to 'arch/arm/boot/dts/qcom-apq8074-dragonboard.dts')

diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index 92320c4a7668..b4dfb01fe6fb 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -4,7 +4,11 @@
 	model = "Qualcomm APQ8074 Dragonboard";
 	compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
 
-	soc: soc {
+	soc {
+		serial@f991e000 {
+			status = "ok";
+		};
+
 		sdhci@f9824900 {
 			bus-width = <8>;
 			non-removable;
@@ -15,5 +19,27 @@
 			cd-gpios = <&msmgpio 62 0x1>;
 			bus-width = <4>;
 		};
+
+
+		pinctrl@fd510000 {
+			spi8_default: spi8_default {
+				mosi {
+					pins = "gpio45";
+					function = "blsp_spi8";
+				};
+				miso {
+					pins = "gpio46";
+					function = "blsp_spi8";
+				};
+				cs {
+					pins = "gpio47";
+					function = "blsp_spi8";
+				};
+				clk {
+					pins = "gpio48";
+					function = "blsp_spi8";
+				};
+			};
+		};
 	};
 };
-- 
cgit