From 6bfe03ddcd670e34a3fd8d3e573fd70580645ee1 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Fri, 7 Jul 2017 16:57:10 +0200 Subject: ARM: dts: qcom: add pseudo random number generator on the IPQ4019 This architecture has a pseudo random number generator supported by the existing "qcom,prng" binding. rngtest: bits received from input: 5795960032 rngtest: FIPS 140-2 successes: 289591 rngtest: FIPS 140-2 failures: 207 rngtest: FIPS 140-2(2001-10-10) Monobit: 25 rngtest: FIPS 140-2(2001-10-10) Poker: 28 rngtest: FIPS 140-2(2001-10-10) Runs: 91 rngtest: FIPS 140-2(2001-10-10) Long run: 67 rngtest: FIPS 140-2(2001-10-10) Continuous run: 0 rngtest: input channel speed: (min=244; avg=46122; max=3906250)Kibits/s rngtest: FIPS tests speed: (min=1.327; avg=20.966; max=26.345)Mibits/s rngtest: Program run time: 386965827 microseconds Signed-off-by: Christian Lamparter Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts/qcom-ipq4019.dtsi') diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index bd4b3c52d868..069243bc161c 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -134,6 +134,14 @@ reg = <0x1800000 0x60000>; }; + rng@22000 { + compatible = "qcom,prng"; + reg = <0x22000 0x140>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq4019-pinctrl"; reg = <0x01000000 0x300000>; -- cgit