From 2e1aa605faddb810b2bd5dac7ed418d898268e40 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 22 Mar 2017 00:05:16 +0100 Subject: ARM: dts: rockchip: fix PPI misconfiguration on Cortex-A9 socs According to [0] pointed out by Marc Zyngier in a report about a similar error message, PPIs 11 and 13 are edge triggered on Cortex-A9 socs including the rk3066 and rk3188 which currently mark them as level triggered. Until some time ago the gic did not care but commit 992345a58e0c ("irqchip/gic: WARN if setting the interrupt type for a PPI fails") introduced a warning for that case. Fix the warning on these socs by describing the interrupts correctly and also using the binding constants for easier reading in the future. [0] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407f/CCHEIGIC.html Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3xxx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts/rk3xxx.dtsi') diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 233513cdd279..c5b8592af73c 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -132,14 +132,14 @@ global_timer: global-timer@1013c200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x1013c200 0x20>; - interrupts = ; + interrupts = ; clocks = <&cru CORE_PERI>; }; local_timer: local-timer@1013c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x1013c600 0x20>; - interrupts = ; + interrupts = ; clocks = <&cru CORE_PERI>; }; -- cgit