From 59d94d2ed45d598211feb52566e6a806d17f8a3f Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 25 Jan 2017 10:01:28 -0600 Subject: ARM: dts: watchdog0 cannot reliably trigger reset On the Arria10, because of hardware bug, watchdog0 cannot reliably trigger a reset to the CPU. The workaround would be to use watchdog1 instead. Also for watchdog1, there is a dependency on the bootloader to enable the boot_clk source to be from the cb_intosc_hs_clk/2, versus from EOSC1. This corresponds to the (SWCTRLBTCLKEN & SWCTRLBTCLKSEL) bits enabled in the control register in the clock manager module of Arria10. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/socfpga_arria10_socdk.dtsi') diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 4c99c99d1752..c57e6cea0d83 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -160,6 +160,6 @@ status = "okay"; }; -&watchdog0 { +&watchdog1 { status = "okay"; }; -- cgit