From 3599a8af1cce1143eb01208df27250cd5937246c Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Thu, 15 Mar 2018 08:18:00 +0100 Subject: ARM: dts: stm32: Enable stm32mp1 clock driver on stm32mp157c This patch enables stm32mp1 clock driver. Signed-off-by: Gabriel Fernandez Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 48 +++++++++++++------------------------- 1 file changed, 16 insertions(+), 32 deletions(-) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 9e17e42b02b2..bc3eddc3eda6 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -4,6 +4,7 @@ * Author: Ludovic Barre for STMicroelectronics. */ #include +#include / { #address-cells = <1>; @@ -71,12 +72,6 @@ clock-frequency = <24000000>; }; - clk_pll_per: clk-pll-per { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - clk_hsi: clk-hsi { #clock-cells = <0>; compatible = "fixed-clock"; @@ -100,24 +95,6 @@ compatible = "fixed-clock"; clock-frequency = <4000000>; }; - - clk_pclk1: clk-pclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <86000000>; - }; - - clk_pll3_p: clk-pll3_p { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <172000000>; - }; - - clk_pll2_p: clk-pll2_p { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <264000000>; - }; }; soc { @@ -131,7 +108,7 @@ compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>; interrupts = ; - clocks = <&clk_pclk1>; + clocks = <&rcc USART2_K>; status = "disabled"; }; @@ -139,7 +116,7 @@ compatible = "st,stm32h7-uart"; reg = <0x4000f000 0x400>; interrupts = ; - clocks = <&clk_pclk1>; + clocks = <&rcc USART3_K>; status = "disabled"; }; @@ -147,7 +124,7 @@ compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; interrupts = ; - clocks = <&clk_pclk1>; + clocks = <&rcc UART4_K>; status = "disabled"; }; @@ -155,7 +132,7 @@ compatible = "st,stm32h7-uart"; reg = <0x40011000 0x400>; interrupts = ; - clocks = <&clk_pclk1>; + clocks = <&rcc UART5_K>; status = "disabled"; }; @@ -163,7 +140,7 @@ compatible = "st,stm32h7-uart"; reg = <0x40018000 0x400>; interrupts = ; - clocks = <&clk_pclk1>; + clocks = <&rcc UART7_K>; status = "disabled"; }; @@ -171,7 +148,7 @@ compatible = "st,stm32h7-uart"; reg = <0x40019000 0x400>; interrupts = ; - clocks = <&clk_pclk1>; + clocks = <&rcc UART8_K>; status = "disabled"; }; @@ -179,15 +156,22 @@ compatible = "st,stm32h7-uart"; reg = <0x44003000 0x400>; interrupts = ; - clocks = <&clk_pclk1>; + clocks = <&rcc USART6_K>; status = "disabled"; }; + rcc: rcc@50000000 { + compatible = "st,stm32mp1-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + usart1: serial@5c000000 { compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; interrupts = ; - clocks = <&clk_pclk1>; + clocks = <&rcc USART1_K>; status = "disabled"; }; }; -- cgit From 61fc211c484d1c5dfec077bed8ebcd10696ad087 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Tue, 17 Apr 2018 15:45:00 +0200 Subject: ARM: dts: stm32: add timers support to stm32mp157c Add PWM and trigger support to stm32mp157c. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 283 +++++++++++++++++++++++++++++++++++++ 1 file changed, 283 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index bc3eddc3eda6..115ec7335d34 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -104,6 +104,185 @@ interrupt-parent = <&intc>; ranges; + timers2: timer@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + clocks = <&rcc TIM2_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32h7-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + }; + + timers3: timer@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + clocks = <&rcc TIM3_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32h7-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + timers4: timer@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + clocks = <&rcc TIM4_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32h7-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + }; + + timers5: timer@40003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40003000 0x400>; + clocks = <&rcc TIM5_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32h7-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + }; + + timers6: timer@40004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40004000 0x400>; + clocks = <&rcc TIM6_K>; + clock-names = "int"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32h7-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + + timers7: timer@40005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40005000 0x400>; + clocks = <&rcc TIM7_K>; + clock-names = "int"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32h7-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + timers12: timer@40006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40006000 0x400>; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timer@40007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40007000 0x400>; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; + }; + + timers14: timer@40008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40008000 0x400>; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; + }; + usart2: serial@4000e000 { compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>; @@ -152,6 +331,48 @@ status = "disabled"; }; + timers1: timer@44000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44000000 0x400>; + clocks = <&rcc TIM1_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32h7-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + }; + + timers8: timer@44001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44001000 0x400>; + clocks = <&rcc TIM8_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32h7-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + }; + usart6: serial@44003000 { compatible = "st,stm32h7-uart"; reg = <0x44003000 0x400>; @@ -160,6 +381,68 @@ status = "disabled"; }; + timers15: timer@44006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44006000 0x400>; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; + }; + + timers16: timer@44007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44007000 0x400>; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; + + timers17: timer@44008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44008000 0x400>; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; -- cgit From 9f790afbdd54d49b04116c7bdae655ede21846d7 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 18 Apr 2018 09:47:00 +0200 Subject: ARM: dts: stm32: Add vrefbuf support to stm32mp157c stm32mp157c has vrefbuf regulator that can provide analog reference voltage from 1500mV to 2500mV. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 115ec7335d34..c81f7edf4954 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -450,6 +450,15 @@ #reset-cells = <1>; }; + vrefbuf: vrefbuf@50025000 { + compatible = "st,stm32-vrefbuf"; + reg = <0x50025000 0x8>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + clocks = <&rcc VREF>; + status = "disabled"; + }; + usart1: serial@5c000000 { compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; -- cgit From 966ed8785f15064a55915ffae723354dd7467653 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 2 May 2018 13:53:38 +0200 Subject: ARM: dts: stm32: Add LPtimer support to stm32mp157c Add LPtimer definitions, depending on features they provide: - lptimer1 & 2 can act as PWM, trigger and encoder/counter - lptimer3 can act as PWM and trigger - lptimer4 & 5 can act as PWM Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 104 +++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index c81f7edf4954..509347cb5ba5 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -283,6 +283,33 @@ }; }; + lptimer1: timer@40009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40009000 0x400>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + usart2: serial@4000e000 { compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>; @@ -450,6 +477,83 @@ #reset-cells = <1>; }; + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + lptimer5: timer@50024000 { + compatible = "st,stm32-lptimer"; + reg = <0x50024000 0x400>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + vrefbuf: vrefbuf@50025000 { compatible = "st,stm32-vrefbuf"; reg = <0x50025000 0x8>; -- cgit From bde22824dc2e22f3b9c01f81eda66ff3308a4c30 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Wed, 2 May 2018 14:14:44 +0200 Subject: ARM: dts: stm32: add reset binding on stm32mp157c This patch adds reset binding file. Signed-off-by: Gabriel Fernandez Reviewed-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 509347cb5ba5..ee3e44032dd2 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -5,6 +5,7 @@ */ #include #include +#include / { #address-cells = <1>; -- cgit From da6cddc7e8a40e6e8617deaae905c3e7bfcfdf94 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 18 Apr 2018 17:46:00 +0200 Subject: ARM: dts: stm32: Add DAC support to stm32mp157c Add support for DAC (Digital to Analog Converter) to STM32MP157C. STM32MP157C DAC has two output channels. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index ee3e44032dd2..9c1a6c48d318 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -343,6 +343,30 @@ status = "disabled"; }; + dac: dac@40017000 { + compatible = "st,stm32h7-dac-core"; + reg = <0x40017000 0x400>; + clocks = <&rcc DAC12>; + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dac1: dac@1 { + compatible = "st,stm32-dac"; + #io-channels-cells = <1>; + reg = <1>; + status = "disabled"; + }; + + dac2: dac@2 { + compatible = "st,stm32-dac"; + #io-channels-cells = <1>; + reg = <2>; + status = "disabled"; + }; + }; + uart7: serial@40018000 { compatible = "st,stm32h7-uart"; reg = <0x40018000 0x400>; -- cgit From ea1c404e8e2feb54ab3d13624477d013c1c9408c Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Fri, 20 Apr 2018 11:14:00 +0200 Subject: ARM: dts: stm32: Add DMAv2 support on STM32MP157C Activate DMAv2 for STM32MP157C Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 9c1a6c48d318..af8bdeeed44e 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -495,6 +495,38 @@ }; }; + dma1: dma@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&rcc DMA1>; + #dma-cells = <4>; + st,mem2mem; + }; + + dma2: dma@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&rcc DMA2>; + #dma-cells = <4>; + st,mem2mem; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; -- cgit From 1cffb560fda4fc9379bcb0f6b3fb545921dfd5e5 Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Fri, 20 Apr 2018 11:14:00 +0200 Subject: ARM: dts: stm32: Add DMAMUX support on STM32MP157C Activate DMAMUX for STM32MP157C Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index af8bdeeed44e..ca213cebdc91 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -509,6 +509,7 @@ clocks = <&rcc DMA1>; #dma-cells = <4>; st,mem2mem; + dma-requests = <8>; }; dma2: dma@48001000 { @@ -525,6 +526,17 @@ clocks = <&rcc DMA2>; #dma-cells = <4>; st,mem2mem; + dma-requests = <8>; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; + reg = <0x48002000 0x1c>; + #dma-cells = <3>; + dma-requests = <128>; + dma-masters = <&dma1 &dma2>; + dma-channels = <16>; + clocks = <&rcc DMAMUX>; }; rcc: rcc@50000000 { -- cgit From 8ecf910a4de806e9e3c7205310e6c59bd667ebab Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Fri, 20 Apr 2018 11:15:00 +0200 Subject: ARM: dts: stm32: Add MDMA support on STM32MP157C Activate MDMA for STM32MP157C Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index ca213cebdc91..d66106ab81b4 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -632,6 +632,16 @@ status = "disabled"; }; + mdma1: dma@58000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x58000000 0x1000>; + interrupts = ; + clocks = <&rcc MDMA>; + #dma-cells = <5>; + dma-channels = <32>; + dma-requests = <48>; + }; + usart1: serial@5c000000 { compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; -- cgit From 6973f0a0c7040363c7b62d8834cba855f6cc4914 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Mon, 23 Apr 2018 17:19:00 +0200 Subject: ARM: dts: stm32: Add RNG support on stm32mp157c This patch add RNG instance of the stm32mp157c SoC Signed-off-by: Lionel Debieve Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index d66106ab81b4..c598904395cb 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -632,6 +632,14 @@ status = "disabled"; }; + rng1: rng@54003000 { + compatible = "st,stm32-rng"; + reg = <0x54003000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; + status = "disabled"; + }; + mdma1: dma@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; -- cgit From fc9962c98abc0daa54c9081cd6ea540395e5ae97 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Mon, 23 Apr 2018 17:19:00 +0200 Subject: ARM: dts: stm32: Add CRYP support on stm32mp157c This patch add CRYP instance of the stm32mp157c SoC Signed-off-by: Lionel Debieve Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index c598904395cb..c26431589051 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -632,6 +632,15 @@ status = "disabled"; }; + cryp1: cryp@54001000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54001000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; + }; + rng1: rng@54003000 { compatible = "st,stm32-rng"; reg = <0x54003000 0x400>; -- cgit From 8b2820abec543ea83fae96d6313bd9d0a06f35c9 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Mon, 23 Apr 2018 17:19:00 +0200 Subject: ARM: dts: stm32: Add CRC support on stm32mp157c This patch add CRC instance of the stm32mp157c SoC Signed-off-by: Lionel Debieve Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index c26431589051..068632f179f7 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -659,6 +659,13 @@ dma-requests = <48>; }; + crc1: crc@58009000 { + compatible = "st,stm32f7-crc"; + reg = <0x58009000 0x400>; + clocks = <&rcc CRC1>; + status = "disabled"; + }; + usart1: serial@5c000000 { compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; -- cgit From d126e86f403f6187ac4be7b5f883c54173330b4e Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Mon, 23 Apr 2018 11:48:00 +0200 Subject: ARM: dts: stm32: Add STM32F7 I2C support for STM32MP157C SoC This patch adds all STM32F7 I2C instances for STM32MP157C SoC. Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 78 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 068632f179f7..e7162f551aa6 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -343,6 +343,58 @@ status = "disabled"; }; + i2c1: i2c@40012000 { + compatible = "st,stm32f7-i2c"; + reg = <0x40012000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C1_K>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@40013000 { + compatible = "st,stm32f7-i2c"; + reg = <0x40013000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C2_K>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@40014000 { + compatible = "st,stm32f7-i2c"; + reg = <0x40014000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@40015000 { + compatible = "st,stm32f7-i2c"; + reg = <0x40015000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dac: dac@40017000 { compatible = "st,stm32h7-dac-core"; reg = <0x40017000 0x400>; @@ -673,5 +725,31 @@ clocks = <&rcc USART1_K>; status = "disabled"; }; + + i2c4: i2c@5c002000 { + compatible = "st,stm32f7-i2c"; + reg = <0x5c002000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@5c009000 { + compatible = "st,stm32f7-i2c"; + reg = <0x5c009000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C6_K>; + resets = <&rcc I2C6_R>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; -- cgit From 570cae638120bd698a10493adeedd9743ac0061a Mon Sep 17 00:00:00 2001 From: yannick fertre Date: Tue, 24 Apr 2018 09:54:00 +0200 Subject: ARM: dts: stm32: add ltdc support on stm32mp157c Add support for the display controller ltdc. Signed-off-by: yannick fertre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index e7162f551aa6..861cfa7babe8 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -718,6 +718,17 @@ status = "disabled"; }; + ltdc: display-controller@5a001000 { + compatible = "st,stm32-ltdc"; + reg = <0x5a001000 0x400>; + interrupts = , + ; + clocks = <&rcc LTDC_PX>; + clock-names = "lcd"; + resets = <&rcc LTDC_R>; + status = "disabled"; + }; + usart1: serial@5c000000 { compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; -- cgit From 9d603e44c1935568d92f0e1e96b4b1e0376c24e1 Mon Sep 17 00:00:00 2001 From: yannick fertre Date: Tue, 24 Apr 2018 09:54:00 +0200 Subject: ARM: dts: stm32: add dsi support on stm32mp157c Add dsi support on stm32mp157c Signed-off-by: yannick fertre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 861cfa7babe8..8b3c27c112cc 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -718,6 +718,16 @@ status = "disabled"; }; + dsi: dsi@5a000000 { + compatible = "st,stm32-dsi"; + reg = <0x5a000000 0x800>; + clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clock-names = "pclk", "ref", "px_clk"; + resets = <&rcc DSI_R>; + reset-names = "apb"; + status = "disabled"; + }; + ltdc: display-controller@5a001000 { compatible = "st,stm32-ltdc"; reg = <0x5a001000 0x400>; -- cgit From 3c00436fdb20304d4af0e004055a4ea8ea1cb634 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 24 Apr 2018 11:41:00 +0200 Subject: ARM: dts: stm32: add USBPHYC support to stm32mp157c Add support for USBPHYC (USB PHY Controller) to STM32MP157C SoC. It manages two usb2 ports. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 8b3c27c112cc..319788cd78a0 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -739,6 +739,26 @@ status = "disabled"; }; + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + usart1: serial@5c000000 { compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; -- cgit From 949a0c0dec8596385a3162ee8141224533c517b3 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 24 Apr 2018 13:24:00 +0200 Subject: ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c Add support for USBH (USB Host) to STM32MP157C SoC. USBH is a USB Host controller supporting the standard registers used for full- and low-speed (OHCI controller) and high-speed (EHCI controller). Signed-off-by: Amelie Delaunay --- arch/arm/boot/dts/stm32mp157c.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 319788cd78a0..ab5e1d75417b 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -718,6 +718,25 @@ status = "disabled"; }; + usbh_ohci: usbh-ohci@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + status = "disabled"; + }; + + usbh_ehci: usbh-ehci@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + companion = <&usbh_ohci>; + status = "disabled"; + }; + dsi: dsi@5a000000 { compatible = "st,stm32-dsi"; reg = <0x5a000000 0x800>; -- cgit From 066f371b80ccef8cf7fdb6a665b423eb72a0be56 Mon Sep 17 00:00:00 2001 From: yannick fertre Date: Tue, 24 Apr 2018 09:54:00 +0200 Subject: ARM: dts: stm32: add cec support on stm32mp157c Add cec support on stm32mp157c Signed-off-by: yannick fertre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index ab5e1d75417b..5ef6495fc2da 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -395,6 +395,15 @@ status = "disabled"; }; + cec: cec@40016000 { + compatible = "st,stm32-cec"; + reg = <0x40016000 0x400>; + interrupts = ; + clocks = <&rcc CEC_K>, <&clk_lse>; + clock-names = "cec", "hdmi-cec"; + status = "disabled"; + }; + dac: dac@40017000 { compatible = "st,stm32h7-dac-core"; reg = <0x40017000 0x400>; -- cgit From c38928d638f16611ea0534374d212b205976c37a Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Mon, 30 Apr 2018 09:11:00 +0200 Subject: ARM: dts: stm32: add qspi support for stm32mp157c This patch adds qspi support on stm32mp157c, read in memory mapped, write in indirect mode. Signed-off-by: Ludovic Barre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 5ef6495fc2da..203fa972895f 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -720,6 +720,16 @@ dma-requests = <48>; }; + qspi: qspi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = ; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + status = "disabled"; + }; + crc1: crc@58009000 { compatible = "st,stm32f7-crc"; reg = <0x58009000 0x400>; -- cgit From 2ff04d0f537fcb8ff033b4ae97e5e0751e21de5e Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 3 May 2018 15:28:28 +0200 Subject: ARM: dts: stm32: Fix IRQ_TYPE_NONE warnings on stm32mp157c Since commit 83a86fbb5b56 ("irqchip/gic: Loudly complain about the use of IRQ_TYPE_NONE"), a warning is raised if IRQ_TYPE_NONE is used. So we use IRQ_TYPE_LEVEL_HIGH for usart nodes instead of IRQ_TYPE_NONE. Signed-off-by: Alexandre Torgue Tested-by: Fabrice Gasnier --- arch/arm/boot/dts/stm32mp157c.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm/boot/dts/stm32mp157c.dtsi') diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 203fa972895f..b66f673b5038 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -314,7 +314,7 @@ usart2: serial@4000e000 { compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>; - interrupts = ; + interrupts = ; clocks = <&rcc USART2_K>; status = "disabled"; }; @@ -322,7 +322,7 @@ usart3: serial@4000f000 { compatible = "st,stm32h7-uart"; reg = <0x4000f000 0x400>; - interrupts = ; + interrupts = ; clocks = <&rcc USART3_K>; status = "disabled"; }; @@ -330,7 +330,7 @@ uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; - interrupts = ; + interrupts = ; clocks = <&rcc UART4_K>; status = "disabled"; }; @@ -338,7 +338,7 @@ uart5: serial@40011000 { compatible = "st,stm32h7-uart"; reg = <0x40011000 0x400>; - interrupts = ; + interrupts = ; clocks = <&rcc UART5_K>; status = "disabled"; }; @@ -431,7 +431,7 @@ uart7: serial@40018000 { compatible = "st,stm32h7-uart"; reg = <0x40018000 0x400>; - interrupts = ; + interrupts = ; clocks = <&rcc UART7_K>; status = "disabled"; }; @@ -439,7 +439,7 @@ uart8: serial@40019000 { compatible = "st,stm32h7-uart"; reg = <0x40019000 0x400>; - interrupts = ; + interrupts = ; clocks = <&rcc UART8_K>; status = "disabled"; }; @@ -489,7 +489,7 @@ usart6: serial@44003000 { compatible = "st,stm32h7-uart"; reg = <0x44003000 0x400>; - interrupts = ; + interrupts = ; clocks = <&rcc USART6_K>; status = "disabled"; }; @@ -800,7 +800,7 @@ usart1: serial@5c000000 { compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; - interrupts = ; + interrupts = ; clocks = <&rcc USART1_K>; status = "disabled"; }; -- cgit