From 7145570159fb20654b507026a8e388f739fffa5c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Dec 2014 22:59:54 +0100 Subject: ARM: sunxi: DT: Convert to device tree includes Prepare the device trees to use the C preprocessor. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 494714f67b57..90d0450850e9 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -47,7 +47,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "skeleton64.dtsi" +#include "skeleton64.dtsi" / { interrupt-parent = <&gic>; -- cgit From 092a0c3b18ce8f2207591846dad5c9071ed2f832 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Dec 2014 22:59:57 +0100 Subject: ARM: sunxi: DT: Convert the DTs to use a header for the pinctrl nodes The pinctrl nodes require some extra opaque arguments for the pull up and drive strength values. Introduce a new header file and convert the device trees to replace these opaque numbers by defines. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 90d0450850e9..de31b210e2c1 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -49,6 +49,8 @@ #include "skeleton64.dtsi" +#include + / { interrupt-parent = <&gic>; @@ -355,22 +357,22 @@ i2c3_pins_a: i2c3@0 { allwinner,pins = "PG10", "PG11"; allwinner,function = "i2c3"; - allwinner,drive = <0>; - allwinner,pull = <0>; + allwinner,drive = ; + allwinner,pull = ; }; uart0_pins_a: uart0@0 { allwinner,pins = "PH12", "PH13"; allwinner,function = "uart0"; - allwinner,drive = <0>; - allwinner,pull = <0>; + allwinner,drive = ; + allwinner,pull = ; }; uart4_pins_a: uart4@0 { allwinner,pins = "PG12", "PG13", "PG14", "PG15"; allwinner,function = "uart4"; - allwinner,drive = <0>; - allwinner,pull = <0>; + allwinner,drive = ; + allwinner,pull = ; }; }; -- cgit From 19882b84d7d9b1888b03f35b2430de550b61e49d Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Dec 2014 22:59:58 +0100 Subject: ARM: sunxi: DT: Convert the DTs to use the GIC headers The GIC requires some extra opaque arguments to set the IRQ type and flags. Convert the DTs to using the common defines. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 52 +++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 25 deletions(-) (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index de31b210e2c1..4b584cb9c2f0 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -49,6 +49,8 @@ #include "skeleton64.dtsi" +#include + #include / { @@ -293,7 +295,7 @@ <0x01c46000 0x2000>; interrupt-controller; #interrupt-cells = <3>; - interrupts = <1 9 0xf04>; + interrupts = ; }; ahb0_resets: reset@060005a0 { @@ -329,12 +331,12 @@ timer@06000c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x06000c00 0xa0>; - interrupts = <0 18 4>, - <0 19 4>, - <0 20 4>, - <0 21 4>, - <0 22 4>, - <0 23 4>; + interrupts = , + , + , + , + , + ; clocks = <&osc24M>; }; @@ -342,11 +344,11 @@ pio: pinctrl@06000800 { compatible = "allwinner,sun9i-a80-pinctrl"; reg = <0x06000800 0x400>; - interrupts = <0 11 4>, - <0 15 4>, - <0 16 4>, - <0 17 4>, - <0 120 4>; + interrupts = , + , + , + , + ; clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; @@ -379,7 +381,7 @@ uart0: serial@07000000 { compatible = "snps,dw-apb-uart"; reg = <0x07000000 0x400>; - interrupts = <0 0 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 16>; @@ -390,7 +392,7 @@ uart1: serial@07000400 { compatible = "snps,dw-apb-uart"; reg = <0x07000400 0x400>; - interrupts = <0 1 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 17>; @@ -401,7 +403,7 @@ uart2: serial@07000800 { compatible = "snps,dw-apb-uart"; reg = <0x07000800 0x400>; - interrupts = <0 2 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 18>; @@ -412,7 +414,7 @@ uart3: serial@07000c00 { compatible = "snps,dw-apb-uart"; reg = <0x07000c00 0x400>; - interrupts = <0 3 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 19>; @@ -423,7 +425,7 @@ uart4: serial@07001000 { compatible = "snps,dw-apb-uart"; reg = <0x07001000 0x400>; - interrupts = <0 4 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 20>; @@ -434,7 +436,7 @@ uart5: serial@07001400 { compatible = "snps,dw-apb-uart"; reg = <0x07001400 0x400>; - interrupts = <0 5 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&apb1_gates 21>; @@ -445,7 +447,7 @@ i2c0: i2c@07002800 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07002800 0x400>; - interrupts = <0 6 4>; + interrupts = ; clocks = <&apb1_gates 0>; resets = <&apb1_resets 0>; status = "disabled"; @@ -456,7 +458,7 @@ i2c1: i2c@07002c00 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07002c00 0x400>; - interrupts = <0 7 4>; + interrupts = ; clocks = <&apb1_gates 1>; resets = <&apb1_resets 1>; status = "disabled"; @@ -467,7 +469,7 @@ i2c2: i2c@07003000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07003000 0x400>; - interrupts = <0 8 4>; + interrupts = ; clocks = <&apb1_gates 2>; resets = <&apb1_resets 2>; status = "disabled"; @@ -478,7 +480,7 @@ i2c3: i2c@07003400 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07003400 0x400>; - interrupts = <0 9 4>; + interrupts = ; clocks = <&apb1_gates 3>; resets = <&apb1_resets 3>; status = "disabled"; @@ -489,7 +491,7 @@ i2c4: i2c@07003800 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07003800 0x400>; - interrupts = <0 10 4>; + interrupts = ; clocks = <&apb1_gates 4>; resets = <&apb1_resets 4>; status = "disabled"; @@ -500,13 +502,13 @@ r_wdt: watchdog@08001000 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x08001000 0x20>; - interrupts = <0 36 4>; + interrupts = ; }; r_uart: serial@08002800 { compatible = "snps,dw-apb-uart"; reg = <0x08002800 0x400>; - interrupts = <0 38 4>; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; clocks = <&osc24M>; -- cgit From d2aa6f540022f3308fc959d9192dae5cc409ac3e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 13 Jan 2015 09:37:25 +0800 Subject: ARM: dts: sun9i: Add mmc module clock nodes for A80 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mmc module clocks are A80 specific module 0 (storage) type clocks. Signed-off-by: Chen-Yu Tsai Signed-off-by: Andreas Färber Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 4b584cb9c2f0..ddc34676987d 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -219,6 +219,42 @@ clock-output-names = "cci400"; }; + mmc0_clk: clk@06000410 { + #clock-cells = <1>; + compatible = "allwinner,sun9i-a80-mmc-clk"; + reg = <0x06000410 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "mmc0", "mmc0_output", + "mmc0_sample"; + }; + + mmc1_clk: clk@06000414 { + #clock-cells = <1>; + compatible = "allwinner,sun9i-a80-mmc-clk"; + reg = <0x06000414 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "mmc1", "mmc1_output", + "mmc1_sample"; + }; + + mmc2_clk: clk@06000418 { + #clock-cells = <1>; + compatible = "allwinner,sun9i-a80-mmc-clk"; + reg = <0x06000418 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "mmc2", "mmc2_output", + "mmc2_sample"; + }; + + mmc3_clk: clk@0600041c { + #clock-cells = <1>; + compatible = "allwinner,sun9i-a80-mmc-clk"; + reg = <0x0600041c 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "mmc3", "mmc3_output", + "mmc3_sample"; + }; + ahb0_gates: clk@06000580 { #clock-cells = <1>; compatible = "allwinner,sun9i-a80-ahb0-gates-clk"; -- cgit From 203c6883b8b4754eb833d50935338556685b8a93 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 13 Jan 2015 09:37:27 +0800 Subject: ARM: dts: sun9i: Add clock-indices property for bus gate clocks of_clk_get_parent_name() uses the clock-indices property to resolve clock phandle arguments in case that the argument index does not match the clock-output-names sequence. This is the case on sunxi, where we use the actual bit index as the argument to the phandle. Add the clock-indices property so that of_clk_get_parent_name() resolves the names correctly. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index ddc34676987d..9d0a66c14caf 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -260,6 +260,9 @@ compatible = "allwinner,sun9i-a80-ahb0-gates-clk"; reg = <0x06000580 0x4>; clocks = <&ahb0>; + clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>, + <14>, <15>, <16>, <18>, <20>, <21>, + <22>, <23>; clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu", "ahb0_ss", "ahb0_sd", "ahb0_nand1", "ahb0_nand0", "ahb0_sdram", @@ -273,6 +276,7 @@ compatible = "allwinner,sun9i-a80-ahb1-gates-clk"; reg = <0x06000584 0x4>; clocks = <&ahb1>; + clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>; clock-output-names = "ahb1_usbotg", "ahb1_usbhci", "ahb1_gmac", "ahb1_msgbox", "ahb1_spinlock", "ahb1_hstimer", @@ -284,6 +288,8 @@ compatible = "allwinner,sun9i-a80-ahb2-gates-clk"; reg = <0x06000588 0x4>; clocks = <&ahb2>; + clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>, + <11>; clock-output-names = "ahb2_lcd0", "ahb2_lcd1", "ahb2_edp", "ahb2_csi", "ahb2_hdmi", "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi"; @@ -294,6 +300,8 @@ compatible = "allwinner,sun9i-a80-apb0-gates-clk"; reg = <0x06000590 0x4>; clocks = <&apb0>; + clock-indices = <1>, <5>, <11>, <12>, <13>, <15>, + <17>, <18>, <19>; clock-output-names = "apb0_spdif", "apb0_pio", "apb0_ac97", "apb0_i2s0", "apb0_i2s1", "apb0_lradc", "apb0_gpadc", "apb0_twd", @@ -305,6 +313,8 @@ compatible = "allwinner,sun9i-a80-apb1-gates-clk"; reg = <0x06000594 0x4>; clocks = <&apb1>; + clock-indices = <0>, <1>, <2>, <3>, <4>, + <16>, <17>, <18>, <19>, <20>, <21>; clock-output-names = "apb1_i2c0", "apb1_i2c1", "apb1_i2c2", "apb1_i2c3", "apb1_i2c4", "apb1_uart0", "apb1_uart1", -- cgit From cd23e2e5ce874cef5c1adc469ca93c9a373b3804 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 13 Jan 2015 09:37:31 +0800 Subject: ARM: dts: sun9i: Add pinmux setting for mmc0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mmc0 is only available on port F, and is always used with a 4 bit wide bus for the onboard micro-sd slot. Signed-off-by: Chen-Yu Tsai Signed-off-by: Andreas Färber Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 9d0a66c14caf..820b4c5995f3 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -409,6 +409,14 @@ allwinner,pull = ; }; + mmc0_pins: mmc0 { + allwinner,pins = "PF0", "PF1" ,"PF2", "PF3", + "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = ; + allwinner,pull = ; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PH12", "PH13"; allwinner,function = "uart0"; -- cgit From 9c56f3f39a60292d785f3a72a7fb09997570abe0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 17 Jan 2015 13:19:29 +0800 Subject: ARM: dts: sun9i: Add mmc config clock nodes Add the device tree nodes for the mmc config clock nodes. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 820b4c5995f3..1925c89ee701 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -333,6 +333,19 @@ */ ranges = <0 0 0 0x20000000>; + mmc_config_clk: clk@01c13000 { + compatible = "allwinner,sun9i-a80-mmc-config-clk"; + reg = <0x01c13000 0x10>; + clocks = <&ahb0_gates 8>; + clock-names = "ahb"; + resets = <&ahb0_resets 8>; + reset-names = "ahb"; + #clock-cells = <1>; + #reset-cells = <1>; + clock-output-names = "mmc0_config", "mmc1_config", + "mmc2_config", "mmc3_config"; + }; + gic: interrupt-controller@01c41000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c41000 0x1000>, -- cgit From 2f6941cd2923c37ea93ec27a6f7ae2a7f0f8332a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 17 Jan 2015 13:19:30 +0800 Subject: ARM: dts: sun9i: Add mmc controller nodes to the A80 dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The A80 has 4 mmc controllers. Signed-off-by: Chen-Yu Tsai Signed-off-by: Andreas Färber Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 1925c89ee701..7387fb2a5111 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -333,6 +333,54 @@ */ ranges = <0 0 0 0x20000000>; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>, + <&mmc0_clk 1>, <&mmc0_clk 2>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&mmc_config_clk 0>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>, + <&mmc1_clk 1>, <&mmc1_clk 2>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&mmc_config_clk 1>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>, + <&mmc2_clk 1>, <&mmc2_clk 2>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&mmc_config_clk 2>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + }; + + mmc3: mmc@01c12000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>, + <&mmc3_clk 1>, <&mmc3_clk 2>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&mmc_config_clk 3>; + reset-names = "ahb"; + interrupts = ; + status = "disabled"; + }; + mmc_config_clk: clk@01c13000 { compatible = "allwinner,sun9i-a80-mmc-config-clk"; reg = <0x01c13000 0x10>; -- cgit From 23a602b665d6ab6b82378f866475d8b657e84729 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 17 Jan 2015 13:19:33 +0800 Subject: ARM: dts: sun9i: Add 8 bit mmc pinmux setting for mmc2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mmc2 is available on port C. Add a pinmux setting for 8 bit wide eMMC. Signed-off-by: Chen-Yu Tsai Signed-off-by: Andreas Färber Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/boot/dts/sun9i-a80.dtsi') diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 7387fb2a5111..9e28ffc6dd90 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -478,6 +478,15 @@ allwinner,pull = ; }; + mmc2_8bit_pins: mmc2_8bit { + allwinner,pins = "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", + "PC13", "PC14", "PC15"; + allwinner,function = "mmc2"; + allwinner,drive = ; + allwinner,pull = ; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PH12", "PH13"; allwinner,function = "uart0"; -- cgit