From bb034cb5eb7fa6596c40d405e31cef02de21ad30 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 9 Aug 2013 16:49:28 +0200 Subject: ARM: tegra: Enable PCIe controller on Beaver PCIe lane 0 is connected to an onboard Gigabit Ethernet (RTL8168evl) and lane 4 is routed to the board's miniPCIe slot. Signed-off-by: Thierry Reding Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-beaver.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/boot/dts/tegra30-beaver.dts') diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 1de4ff6ada88..21660da2ec59 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -10,6 +10,27 @@ reg = <0x80000000 0x7ff00000>; }; + pcie-controller { + status = "okay"; + pex-clk-supply = <&sys_3v3_pexs_reg>; + vdd-supply = <&ldo1_reg>; + avdd-supply = <&ldo2_reg>; + + pci@1,0 { + status = "okay"; + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + status = "okay"; + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + nvidia,num-lanes = <1>; + }; + }; + host1x { hdmi { status = "okay"; -- cgit